Power-on reset circuit and method

Abstract

The embodiment of the invention provides a power-on reset circuit and method, and relates to the technical field of circuit testing. The power-on reset circuit comprises a starting module which is used for outputting a first voltage at a first node according to a power supply voltage provided by a power supply voltage end; the trigger module comprises at least two divider resistors; the trigger module is used for outputting a power-on reset enable signal at the second node under the condition that the first voltage reaches a trigger threshold value; and compensating the trigger threshold according to the resistance values of the at least two divider resistors, and the anti-phase time delay module is used for responding to the power-on reset enable signal and outputting the equivalent voltage of the power supply voltage in a delayed manner after overturning the equivalent voltage of the power supply voltage. According to the embodiment of the invention, the POR voltage starting points at different temperatures can be ensured to be consistent, so that the zero-temperature characteristic of the power-on reset circuit in the full-temperature range can be effectively realized.

Description

Technical Field

[0001] The present application belongs to the technical field of circuit testing, and in particular, relates to a power-on reset circuit and method. Background Art

[0002] With the rapid development of electronic technology, more and more electronic products are widely used in various scenarios. There are many different circuit systems in different electronic products, and there are many different component circuits in different circuit systems.

[0003] The power-on reset circuit (POR circuit for short) is widely used in various circuit systems, such as electronic cigarette product systems. The power-on reset circuit usually starts the chip in the control system. However, when the external environment, such as temperature conditions, changes, the POR power-on reset voltage output by the power-on reset circuit often becomes abnormal, which is likely to have a serious impact on the stability of the chip. Summary of the invention

[0004] The embodiments of the present application provide a power-on reset circuit and method, which can ensure that the POR voltage starting point is consistent at different temperatures, thereby effectively realizing the full temperature range zero temperature characteristic of the power-on reset circuit.

[0005] In a first aspect, an embodiment of the present application provides a power-on reset circuit, the power-on reset circuit comprising:

[0006] A startup module, wherein a first terminal of the startup module is electrically connected to the power supply voltage terminal, a second terminal of the startup module is grounded, and the startup module includes a first node; the startup module is used to output a first voltage at the first node according to a power supply voltage provided by the power supply voltage terminal;

[0007] A trigger module, wherein a first end of the trigger module is electrically connected to a power supply voltage end, and a second end of the reset trigger module is grounded; the trigger module comprises a second node; and the trigger module comprises at least two voltage-dividing resistors;

[0008] The trigger module is used to output a power-on reset enable signal at the second node when the first voltage reaches the trigger threshold; and compensate the trigger threshold according to the resistance values ​​of at least two voltage-dividing resistors;

[0009] The inverting delay module has a first end electrically connected to the power supply voltage end and a second end grounded; the inverting delay module is used to respond to a power-on reset enable signal, flip the equivalent voltage of the power supply voltage and then delay the output.

[0010] In a possible implementation of the first aspect, the trigger module includes a first switch unit, a second switch unit, a third switch unit, a first resistor, and a second resistor;

[0011] A first end of the first resistor is electrically connected to the power supply voltage end, and a second end of the first resistor is electrically connected to the second end of the first switch module;

[0012] The control end of the first switch unit is electrically connected to the second node, and the first end of the first switch unit is electrically connected to the first end of the second resistor;

[0013] The control end of the second switch unit is electrically connected to the first node, the first end of the second switch unit is electrically connected to the second end of the second resistor, and the second end of the second switch unit is grounded;

[0014] A control end of the third switch unit is electrically connected to the first node, a first end of the third switch unit is electrically connected to the second node, and a second end of the third switch unit is electrically connected to the first end of the second resistor;

[0015] The first switch unit, the second switch unit and the third switch unit are turned on in sequence as the first voltage increases; when the first voltage increases to reach a trigger threshold, the third switch unit is turned on to reduce the node potential of the second node to output a power-on reset enable signal;

[0016] The trigger threshold is associated with a target voltage value, and the target voltage value is the sum of a turn-on threshold voltage of the third switch unit and a voltage difference across the second resistor;

[0017] When the turn-on threshold voltage of the third switch unit changes, the trigger threshold is compensated by adjusting the voltage difference across the second resistor.

[0018] In a possible implementation manner of the first aspect, the trigger module further includes a fourth switch unit, a fifth switch unit, and a sixth switch unit;

[0019] The control end of the fourth switch unit is electrically connected to the second node, the first end of the fourth switch unit is electrically connected to the second end of the fifth switch unit, and the second end of the fourth switch unit is grounded;

[0020] The control terminal of the fifth switch unit is electrically connected to the first node, and the first terminal of the fifth switch unit is electrically connected to the power supply voltage terminal;

[0021] The control end of the sixth switch unit is electrically connected to the first node, the first end of the sixth switch unit is electrically connected to the second end of the fifth switch unit, and the second end of the sixth switch unit is electrically connected to the second node;

[0022] When the first voltage does not reach the trigger threshold, the fifth switch unit and the sixth switch unit are turned on to pull up the node potential of the second node to output a power-on reset disabling signal;

[0023] The inverting delay module is used to respond to the power-on reset non-enable signal, invert the ground voltage and then delay the output.

[0024] In a possible implementation of the first aspect, the first switch unit includes a first NMOS transistor, the second switch unit includes a second NMOS transistor, and the third switch unit includes a third NMOS transistor; the fourth switch unit includes a first PMOS transistor, the fifth switch unit includes a second PMOS transistor, and the sixth switch unit includes a third PMOS transistor;

[0025] The control end of the first NMOS transistor is electrically connected to the second node, the first end of the first NMOS transistor is electrically connected to the first end of the second resistor, and the second end of the first NMOS transistor is electrically connected to the second end of the first resistor;

[0026] The control end of the second NMOS transistor is electrically connected to the first node, the first end of the second NMOS transistor is electrically connected to the second end of the second resistor, and the second end of the second NMOS transistor is grounded;

[0027] The control end of the third NMOS transistor is electrically connected to the first node, the first end of the third NMOS transistor is electrically connected to the second node, and the second end of the third NMOS transistor is electrically connected to the first end of the second resistor;

[0028] The control end of the first PMOS tube is electrically connected to the second node, the first end of the first PMOS tube is electrically connected to the second end of the second PMOS tube, and the second end of the first PMOS tube is grounded;

[0029] The control end of the second PMOS tube is electrically connected to the first node, and the first end of the second PMOS tube is electrically connected to the power supply voltage end;

[0030] The control end of the third PMOS tube is electrically connected to the first node, the first end of the third PMOS tube is electrically connected to the second end of the second PMOS tube, and the second end of the third PMOS tube is electrically connected to the second node.

[0031] In a possible implementation manner of the first aspect, the startup module includes a primary compensation unit, a seventh switch unit, and a first storage unit;

[0032] A first terminal of the primary compensation unit is electrically connected to the power supply voltage terminal, and a second terminal of the initial compensation unit is electrically connected to a first terminal of the seventh switch unit;

[0033] The control terminal and the second terminal of the seventh switch unit are both electrically connected to the first node;

[0034] A first electrode of the first storage cell is electrically connected to the first node, and a second electrode of the first storage cell is grounded.

[0035] In a possible implementation of the first aspect, the primary compensation unit includes a positive temperature characteristic compensation resistor, the seventh switch unit includes a fourth PMOS tube, and the first storage unit includes a first capacitor;

[0036] A first end of the positive temperature characteristic compensation resistor is electrically connected to the power supply voltage terminal, and a second end of the compensation resistor is electrically connected to a first end of the fourth PMOS tube;

[0037] The control terminal and the second terminal of the fourth PMOS tube are both electrically connected to the first node;

[0038] A first electrode of the first capacitor is electrically connected to the first node, and a second electrode of the first capacitor is grounded.

[0039] In a possible implementation of the first aspect, the trigger module further includes a power-on reset maintaining unit;

[0040] The control end of the power-on reset maintaining unit is electrically connected to the third node, the first end of the power-on reset maintaining unit is electrically connected to the power supply voltage end, and the second end of the power-on reset maintaining unit is electrically connected to the first node;

[0041] The power-on reset maintaining unit is used to transmit the power supply voltage provided by the power supply voltage terminal to the first node in response to the conduction level of the third node; wherein, when the node voltage of the second node is a power-on reset enable signal, the third node provides a conduction level.

[0042] In a possible implementation of the first aspect, the inversion delay module includes an inverter unit and a delay unit; the delay unit includes an even number of inverters; the inverter unit includes an odd number of inverters;

[0043] The first end of the delay unit is electrically connected to the power supply voltage end, and the second end of the delay unit is grounded; the delay unit is used to respond to the power-on reset enable signal of the second node and delay the output of the ground voltage to the inverter unit;

[0044] The first end of the inverter unit is electrically connected to the power supply voltage end, and the second end of the inverter unit is grounded; the inverter unit is used to flip the ground voltage an odd number of times to generate a voltage equivalent to the power supply voltage and output the voltage equivalent to the power supply voltage.

[0045] In a possible implementation manner of the first aspect, the delay unit includes a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube and a fifth NMOS tube; the inverter unit includes a seventh PMOS tube and a sixth NMOS tube;

[0046] The control end of the fifth PMOS tube is electrically connected to the second node, the first end of the fifth PMOS tube is electrically connected to the power supply voltage end, and the second end of the fifth PMOS tube is electrically connected to the first end of the fourth NMOS tube;

[0047] The control end of the fourth NMOS tube is electrically connected to the second node, and the second end of the fourth NMOS tube is grounded;

[0048] The control end of the sixth PMOS tube is electrically connected to the first end of the fourth NMOS tube, the first end of the sixth PMOS tube is electrically connected to the power supply voltage end, and the second end of the sixth PMOS tube is electrically connected to the third node;

[0049] The control end of the fifth NMOS tube is electrically connected to the first end of the fourth NMOS tube, the first end of the fifth NMOS tube is electrically connected to the third node, and the second end of the fifth NMOS tube is grounded;

[0050] The control end of the seventh PMOS tube is electrically connected to the third node, the first end of the seventh PMOS tube is electrically connected to the power supply voltage end, and the second end of the seventh PMOS tube is electrically connected to the power-on reset signal output end;

[0051] The control end of the sixth NMOS tube is electrically connected to the third node, the first end of the sixth NMOS tube is electrically connected to the power-on reset signal output end, and the second end of the sixth NMOS tube is grounded;

[0052] The power-on reset signal output terminal is used to output a voltage equivalent to the power supply voltage.

[0053] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a power-on reset method, which is applied to a power-on reset circuit provided by any embodiment of the first aspect of the present application; the power-on reset method comprises:

[0054] The trigger threshold is compensated by controlling the resistance values ​​of at least two voltage-dividing resistors in the trigger module.

[0055] A power-on reset circuit and method provided by an embodiment of the present application, the power-on reset circuit includes a startup module, a trigger module and an inverting reset module, the startup module is used to output a first voltage at a first node according to a power supply voltage provided by a power supply voltage terminal; the trigger module can be used to output a power-on reset enable signal at a second node when the first voltage reaches a trigger threshold; and the trigger threshold is compensated according to the resistance value of at least two voltage-dividing resistors; the inverting delay module is used to respond to the power-on reset enable signal, and the equivalent voltage of the power supply voltage is reversed and then output with a delay. A power-on reset circuit and method of an embodiment of the present application, under different external temperature environments, can compensate for the trigger threshold by introducing at least two voltage-dividing resistors in the trigger module, so that the trigger threshold can be flexibly adjusted with the temperature, and the trigger threshold will directly affect the starting value of the equivalent voltage of the power supply voltage output by the inverting delay module in response to the power-on reset enable signal, so that the POR voltage starting point is effectively guaranteed to be consistent at different temperatures, or fluctuate only within a small range, thereby fully realizing the full temperature range zero temperature characteristics of the power-on reset circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0057] Figure 1 It is a structural schematic diagram of a power-on reset circuit provided in an embodiment of the present application;

[0058] Figure 2 is a structural schematic diagram of another power-on reset circuit provided in an embodiment of the present application;

[0059] Figure 3 It is a structural schematic diagram of another power-on reset circuit provided in an embodiment of the present application;

[0060] Figure 4 It is a signal waveform diagram of a power-on reset circuit provided in an embodiment of the present application;

[0061] Figure 5 is a signal waveform diagram of another power-on reset circuit provided in an embodiment of the present application;

[0062] Figure 6 It is a schematic diagram of a temperature characteristic curve provided in an embodiment of the present application. DETAILED DESCRIPTION

[0063] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0064] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0065] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0066] It should be noted that the transistor in the embodiment of the present application can be an N-type transistor or a P-type transistor. For an N-type transistor, the on-level is a high level and the off-level is a low level. That is, when the gate of the N-type transistor is at a high level, the first and second poles thereof are connected, and when the gate of the N-type transistor is at a low level, the first and second poles thereof are disconnected. For a P-type transistor, the on-level is a low level and the off-level is a high level. That is, when the control pole of the P-type transistor is at a low level, the first and second poles thereof are connected, and when the control terminal of the P-type transistor is at a high level, the first and second poles thereof are disconnected. In a specific implementation, the gate of each of the above-mentioned transistors is used as its control pole, and, according to the signal of the gate of each transistor and its type, the first pole thereof can be used as the source and the second pole as the drain, or the first pole thereof can be used as the drain and the second pole as the source, and no distinction is made here. In addition, the on-level and the off-level in the embodiment of the present invention are both general terms, and the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / turn off the transistor.

[0067] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0068] In the embodiment of the present application, the first node, the second node and the third node are only defined for the convenience of describing the circuit structure, and the first node, the second node and the third node are not actual circuit units.

[0069] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0070] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0071] As mentioned above, the inventors of this application have discovered that in the related art, when the external temperature environment changes, the internal device characteristics of the power-on reset circuit are affected by the temperature and change, thereby causing the POR voltage output by the power-on reset circuit to be abnormal, which is likely to have a serious impact on the stability of the chip operation.

[0072] The inventor of the present application has further studied and found that the means used in the prior art to solve this problem are usually: using a positive temperature characteristic resistor to replace the transistor device in the original power-on reset circuit. Although this can bring a certain compensation effect to the POR voltage, the POR voltage temperature characteristic that this solution can achieve is heavily dependent on the process, and it is difficult to find a resistor that can fully fit and realize the zero temperature characteristic of the POR voltage. Therefore, the industry is still in urgent need of a new power-on reset circuit that can achieve a precise compensation effect to achieve zero temperature characteristics over the entire temperature range.

[0073] In view of the above, in order to solve the problems in the prior art, the embodiments of the present application provide a power-on reset circuit and method. It should be noted that the embodiments provided in the present application are not intended to limit the scope of the present application.

[0074] The following first introduces the power-on reset circuit provided in the embodiment of the present application.

[0075] Figure 1 1 is a schematic diagram of a power-on reset circuit provided in an embodiment of the present application. The power-on reset circuit includes a start-up module 10 , a trigger module 20 and an inversion delay module 30 .

[0076] Specifically, the first terminal of the startup module 10 is electrically connected to the power supply voltage terminal, the second terminal of the startup module 10 is grounded, and the startup module 10 includes a first node N1. The startup module 10 can be used to output a first voltage V1 at the first node N1 according to the power supply voltage VCC provided by the power supply voltage terminal.

[0077] It should be noted that during the power-on reset process, the power supply voltage VCC provided by the power supply voltage terminal may change over time. For example, the power supply voltage may increase linearly over time.

[0078] Based on this, when the startup module 10 outputs the first voltage V1 at the first node N1 according to the power voltage VCC provided by the power voltage terminal, the voltage value of the output first voltage V1 will also gradually increase.

[0079] The first terminal of the trigger module 20 is electrically connected to the power supply voltage terminal, and the second terminal of the reset trigger module 20 is grounded. The trigger module 20 includes a second node N2, and the trigger module 20 includes at least two voltage-dividing resistors.

[0080] During the operation of the specific power-on reset circuit, the trigger module 20 can be used to output the power-on reset enable signal at the second node N2 when the first voltage V1 reaches the trigger threshold; and compensate the trigger threshold according to the resistance values ​​of at least two voltage-dividing resistors.

[0081] During the operation of the specific power-on reset circuit, the first voltage V1 gradually increases. When the first voltage V1 increases to reach the trigger threshold, in response to the first voltage V1, the second voltage V2 at the second node N2 becomes the power-on reset enable signal. The trigger module 20 outputs the power-on reset enable signal at the second node N2.

[0082] Furthermore, the trigger module 20 includes at least two voltage-dividing resistors, and the trigger threshold can be flexibly compensated and adjusted at different temperatures according to the resistance values ​​of the at least two voltage-dividing resistors, so that the starting voltage value of the final output POR voltage remains unchanged, or fluctuates only within a small range.

[0083] For example, if the external temperature environment decreases, the devices in the power-on reset circuit, such as transistors, will accordingly exhibit negative temperature characteristics. If the circuit is not compensated accordingly at this time, the above-mentioned trigger threshold will be affected and change significantly, so that the starting voltage value of the final output POR voltage cannot be kept consistent with that in the normal temperature environment.

[0084] In this embodiment, at least two voltage-dividing resistors are set in the trigger module 20. In this way, when the external temperature environment changes, the trigger threshold can be flexibly compensated at the current temperature by flexibly adjusting the resistance value of the voltage-dividing resistor, thereby effectively ensuring that the POR voltage starting point is consistent at different temperatures, thereby fully realizing the full temperature range zero temperature characteristics of the power-on reset circuit of the present application.

[0085] The first end of the inverting delay module 30 is electrically connected to the power supply voltage end, and the second end of the inverting delay module 30 is grounded; the inverting delay module 30 is used to respond to the power-on reset enable signal, invert the equivalent voltage of the power supply voltage VCC and then delay the output.

[0086] It should be understood that when the first voltage V1 reaches the trigger threshold, the second node N2 starts to provide a power-on reset enable signal. In this case, the inverting delay module 30 will respond to the power-on reset enable signal, invert the equivalent voltage of the power supply voltage VCC and then delay the output, that is, realize the output of the POR voltage.

[0087] An embodiment of the present application provides a power-on reset circuit, which includes a startup module 10, a trigger module 20 and an inverting delay module 30. The startup module 10 is used to output a first voltage V1 at a first node N1 according to a power supply voltage VCC provided by a power supply voltage terminal; the trigger module 20 can be used to output a power-on reset enable signal at a second node N2 when the first voltage V1 reaches a trigger threshold; and compensate the trigger threshold according to the resistance values ​​of at least two voltage-dividing resistors; the inverting delay module 30 is used to respond to the power-on reset enable signal, flip the equivalent voltage of the power supply voltage VCC and output it after delay.

[0088] A power-on reset circuit in an embodiment of the present application can compensate for the trigger threshold by introducing at least two voltage-dividing resistors in the trigger module 20 under different external temperature environments, so that the trigger threshold can be flexibly adjusted with the temperature, and the trigger threshold will directly affect the starting value of the equivalent voltage of the power supply voltage VCC output by the inverting delay module 30 in response to the power-on reset enable signal. In this way, it is effectively ensured that the POR voltage starting point is consistent at different temperatures, or fluctuates only within a small range, thereby fully realizing the full temperature range zero temperature characteristics of the power-on reset circuit.

[0089] Please refer to the following for details Figure 2 , Figure 2 Schematic diagram of another power-on reset circuit provided in an embodiment of the present application. Figure 2 As shown, in some more specific implementations, in order to more reasonably implement the function of the startup module 10 so as to subsequently effectively output the required POR voltage value, optionally, the startup module 10 includes a primary compensation unit, a seventh switch unit and a first storage unit.

[0090] Specifically, the first end of the primary compensation unit is electrically connected to the power supply voltage end, and the second end of the initial compensation unit is electrically connected to the first end of the seventh switch unit.

[0091] The control terminal and the second terminal of the seventh switch unit are both electrically connected to the first node N1.

[0092] A first electrode of the first storage unit is electrically connected to the first node N1, and a second electrode of the first storage unit is grounded.

[0093] Please continue to see Figure 2 In some more specific embodiments, such as Figure 2 As shown, in order to more reasonably realize compensation for the trigger threshold based on the voltage-dividing resistor, optionally, the trigger module 20 may specifically include a first switch unit, a second switch unit, a third switch unit, a first resistor R1 and a second resistor R2.

[0094] A first end of the first resistor R1 is electrically connected to the power supply voltage end, and a second end of the first resistor R1 is electrically connected to the second end of the first switch module.

[0095] The control end of the first switch unit is electrically connected to the second node N2, and the first end of the first switch unit is electrically connected to the first end of the second resistor R2.

[0096] The control end of the second switch unit is electrically connected to the first node N1 , the first end of the second switch unit is electrically connected to the second end of the second resistor R2 , and the second end of the second switch unit is grounded.

[0097] The control end of the third switch unit is electrically connected to the first node N1 , the first end of the third switch unit is electrically connected to the second node N2 , and the second end of the third switch unit is electrically connected to the first end of the second resistor R2 .

[0098] The first switch unit, the second switch unit and the third switch unit are turned on in sequence as the first voltage V1 increases. Specifically, as the first voltage V1 increases, the first switch unit is turned on first, and after a period of time, the second switch unit is turned on.

[0099] After the second switch unit is turned on, the first voltage continues to increase gradually. When the first voltage V1 increases to reach the trigger threshold, the third switch unit is turned on to pull down the node potential of the second node N2, that is, the second voltage V2 at the second node N2 is reduced, and a power-on reset enable signal is provided.

[0100] The trigger threshold is associated with a target voltage value, which is the sum of a turn-on threshold voltage of the third switch unit and a voltage difference across the second resistor R2.

[0101] When the external temperature environment changes, the device characteristics of the third switch unit change under the influence of temperature, and its on-threshold voltage changes accordingly. When the on-threshold voltage of the third switch unit changes, the present application compensates the trigger threshold by adjusting the voltage difference across the second resistor R2.

[0102] When specifically compensating, the voltage difference across the second resistor R2 may be adjusted by adjusting the resistance value of the first resistor R1 or by adjusting the resistance value of the second resistor R2, thereby compensating for the trigger threshold.

[0103] Of course, in some other feasible implementations, the resistance values ​​of the first resistor R1 and the second resistor R2 may be adjusted to change the voltage difference across the second resistor R2 by means of resistance voltage division, and the present application does not impose any specific restrictions on this.

[0104] Please continue to see Figure 2In some more specific implementations, in order to further ensure that the power-on reset circuit can reasonably output the required POR voltage, optionally, as Figure 2 As shown, the trigger module 20 further includes a fourth switch unit, a fifth switch unit and a sixth switch unit.

[0105] Specifically, the control end of the fourth switch unit is electrically connected to the second node N2, the first end of the fourth switch unit is electrically connected to the second end of the fifth switch unit, and the second end of the fourth switch unit is grounded.

[0106] A control terminal of the fifth switch unit is electrically connected to the first node N1, and a first terminal of the fifth switch unit is electrically connected to the power supply voltage terminal.

[0107] A control end of the sixth switch unit is electrically connected to the first node N1 , a first end of the sixth switch unit is electrically connected to the second end of the fifth switch unit, and a second end of the sixth switch unit is electrically connected to the second node N2 .

[0108] When the first voltage V1 does not reach the trigger threshold, the fifth switch unit and the sixth switch unit are in the on state, the node potential of the second node N2 is pulled up, and the value of the second voltage V2 at the second node N2 is approximately the voltage value of the power supply voltage VCC. In this case, the second voltage V2 can be regarded as a power-on reset disabling signal.

[0109] In this case, the inverting delay module 30 can be used to respond to the power-on reset disable signal, flip the ground voltage GND and then delay the output. Specifically, when the second voltage V2 is the power-on reset disable signal, Figure 2 The POR output terminal in the circuit outputs a ground voltage of 0V, which is equivalent to no output.

[0110] Please continue to see Figure 2 In some more specific embodiments, optionally, Figure 2 As shown, in order to maintain a stable output of the POR voltage, the trigger module 20 may further include a power-on reset maintaining unit.

[0111] Specifically, the control end of the power-on reset maintaining unit is electrically connected to the third node N3, the first end of the power-on reset maintaining unit is electrically connected to the power supply voltage end, and the second end of the power-on reset maintaining unit is electrically connected to the first node N1.

[0112] The power-on reset maintaining unit is used to transmit the power supply voltage VCC provided by the power supply voltage terminal to the first node N1 in response to the conduction level of the third node N3. When the node voltage of the second node N2 is a power-on reset enable signal, the third node N3 provides a conduction level.

[0113] Continue as Figure 2As shown, in some more specific implementations, optionally, in order to more reasonably respond to the node potential of the second node N2 for POR voltage output, the above-mentioned inversion delay module 30 may specifically include an inverter unit and a delay unit.

[0114] In specific implementation, the first end of the delay unit is electrically connected to the power supply voltage end, and the second end of the delay unit is grounded. The delay unit can be used to delay the output of the ground voltage GND to the inverter unit in response to the power-on reset enable signal of the second node N2.

[0115] The first end of the inverter unit is electrically connected to the power supply voltage end, and the second end of the inverter unit is grounded. The inverter unit is used to flip the ground voltage GND an odd number of times to generate a voltage equivalent to the power supply voltage VCC and output the voltage equivalent to the power supply voltage VCC.

[0116] The delay unit includes an even number of inverters, and the specific number of inverters can be set according to the delay requirements in the actual circuit. The output level of the delay unit is consistent with the level of the node potential of the second node N2. When the second node N2 is at a low potential, the delay unit outputs a low level.

[0117] The inverter unit can be used to flip a low potential to a high potential, or flip a high potential to a low potential. The inverter unit can specifically include an odd number of inverters, and the number of inverters in the inverter unit can be determined according to actual circuit requirements, etc., and this application does not impose specific restrictions on this.

[0118] In addition, it should be added that, considering that the input signal from the second node N2 may fluctuate, multiple inverter structures are provided in the delay unit and the inverter unit in this embodiment. In this way, multiple signal flips are performed through multiple inverter structures, so that the anti-interference effect of the fluctuation of the input signal from the second node N2 can be achieved, so that the final output POR voltage is more stable.

[0119] It is necessary to add that, Figure 2 As shown, the delay unit and the inverter unit can be electrically connected through a third node N3, and the node voltage of the third node N3 is a third voltage V3. When the second node N2 outputs a power-on reset enable signal, the third voltage V3 is a ground voltage GND. The third node N3 can be electrically connected to the control end of the power-on reset maintenance unit to provide a conduction level for the control end of the power-on reset maintenance unit when the node voltage of the second node N2 is a power-on reset enable signal.

[0120] In order to more intuitively reflect the structural design of the power-on reset circuit in the present application, some specific application embodiments are described below.

[0121] See below Figure 3 , Figure 3 is a schematic diagram of the structure of another power-on reset circuit provided in an embodiment of the present application. Figure 3 As shown, in some more specific embodiments, the above-mentioned first switch unit may include a first NMOS tube MN1, the second switch unit may include a second NMOS tube MN2, and the third switch unit may include a third NMOS tube MN3; the fourth switch unit may include a first PMOS tube MP1, the fifth switch unit may include a second PMOS tube MP2, and the sixth switch unit may include a third PMOS tube MP3.

[0122] Specifically, the control end of the first NMOS transistor MN1 is electrically connected to the second node N2, the first end of the first NMOS transistor MN1 is electrically connected to the first end of the second resistor R2, and the second end of the first NMOS transistor MN1 is electrically connected to the second end of the first resistor R1.

[0123] The control end of the second NMOS transistor MN2 is electrically connected to the first node N1 , the first end of the second NMOS transistor MN2 is electrically connected to the second end of the second resistor R2 , and the second end of the second NMOS transistor MN2 is grounded.

[0124] The control end of the third NMOS transistor MN3 is electrically connected to the first node N1, the first end of the third NMOS transistor MN3 is electrically connected to the second node N2, and the second end of the third NMOS transistor MN3 is electrically connected to the first end of the second resistor R2.

[0125] The control end of the first PMOS transistor MP1 is electrically connected to the second node N2 , the first end of the first PMOS transistor MP1 is electrically connected to the second end of the second PMOS transistor MP2 , and the second end of the first PMOS transistor MP1 is grounded.

[0126] The control end of the second PMOS transistor MP2 is electrically connected to the first node N1 , and the first end of the second PMOS transistor MP2 is electrically connected to the power supply voltage end.

[0127] The control end of the third PMOS transistor MP3 is electrically connected to the first node N1 , the first end of the third PMOS transistor MP3 is electrically connected to the second end of the second PMOS transistor MP2 , and the second end of the third PMOS transistor MP3 is electrically connected to the second node N2 .

[0128] Please continue to see Figure 3 In some more specific implementations, optionally, the primary compensation unit may include a positive temperature characteristic compensation resistor R0, the seventh switch unit may include a fourth PMOS tube MP4, and the first storage unit may include a first capacitor C1.

[0129] Specifically, a first end of the positive temperature characteristic compensation resistor R0 is electrically connected to the power supply voltage terminal, and a second end of the compensation resistor R0 is electrically connected to a first end of the fourth PMOS transistor MP4.

[0130] The control terminal and the second terminal of the fourth PMOS transistor MP4 may both be electrically connected to the first node N1. In the actual working process, the fourth PMOS transistor MP4 may be equivalent to a diode.

[0131] A first electrode of the first capacitor C1 is electrically connected to the first node N1 , and a second electrode of the first capacitor C1 is grounded.

[0132] Continue as Figure 3 As shown, in some more specific implementations, the delay unit may specifically include a fifth PMOS tube MP5, a sixth PMOS tube MP6, a fourth NMOS tube MN4 and a fifth NMOS tube. The inverter unit may include a seventh PMOS tube MP7 and a sixth NMOS tube MN6.

[0133] Specifically, the control end of the fifth PMOS transistor MP5 is electrically connected to the second node N2, the first end of the fifth PMOS transistor MP5 is electrically connected to the power supply voltage end, and the second end of the fifth PMOS transistor MP5 is electrically connected to the first end of the fourth NMOS transistor MN4.

[0134] A control end of the fourth NMOS transistor MN4 is electrically connected to the second node N2, and a second end of the fourth NMOS transistor MN4 is grounded.

[0135] The control end of the sixth PMOS transistor MP6 is electrically connected to the first end of the fourth NMOS transistor MN4 , the first end of the sixth PMOS transistor MP6 is electrically connected to the power supply voltage end, and the second end of the sixth PMOS transistor MP6 is electrically connected to the third node N3 .

[0136] The control end of the fifth NMOS tube is electrically connected to the first end of the fourth NMOS tube MN4, the first end of the fifth NMOS tube is electrically connected to the third node N3, and the second end of the fifth NMOS tube is grounded.

[0137] The control end of the seventh PMOS tube MP7 is electrically connected to the third node N3, the first end of the seventh PMOS tube MP7 is electrically connected to the power supply voltage end, and the second end of the seventh PMOS tube MP7 is electrically connected to the power-on reset signal output end.

[0138] The control end of the sixth NMOS transistor MN6 is electrically connected to the third node N3, the first end of the sixth NMOS transistor MN6 is electrically connected to the power-on reset signal output end, and the second end of the sixth NMOS transistor MN6 is grounded; wherein the power-on reset signal output end is used to output a voltage equivalent to the power supply voltage VCC.

[0139] It should be noted that, in addition to the transistors listed above, the power-on reset circuit of the present application may also include other transistors or other capacitors, resistors and other devices, and the present application does not impose strict restrictions on this.

[0140] For ease of understanding Figure 3 The working process of the power-on reset circuit is shown below. Figure 4 and Figure 5 . Figure 4 is a signal waveform diagram of a power-on reset circuit provided in an embodiment of the present application, Figure 5 It is a signal waveform diagram of another power-on reset circuit provided in an embodiment of the present application. Figure 4 and Figure 5 The signal waveform diagrams shown are consistent with Figure 3 The circuit shown corresponds to

[0141] Combine the following Figure 4 and Figure 5 The signal waveform diagram shown is Figure 3 The specific working process of the power-on reset circuit shown is introduced.

[0142] like Figure 4 As shown, in the actual power-on reset process, the power supply terminal starts to power on first, and the power supply voltage VCC provided by the power supply voltage terminal gradually increases linearly over time.

[0143] The first stage: at the initial stage of power-on, the first voltage V1 and the second voltage V2 are both 0V.

[0144] The second stage: after the power supply voltage VCC is greater than Vth (MP4), the node potential at the first node N1, that is, the first voltage V1, gradually increases. At this time, both MP2 and MP3 are in the on state, the second voltage V2 at the second node N2 is approximately equal to the power supply voltage VCC, and the MP1 tube is cut off. The gate potential and drain potential of the MN1 tube are basically equal, and the MN1 tube is cut off.

[0145] The third stage: When the power supply voltage VCC rises to Vth(MN1), the second voltage V2 rises accordingly, turning on the MN1 tube. At this time, under the action of the charging of C1, since the first voltage V1 at the first node N1 rises slowly, the MN2 tube is still in the cut-off state, and the drain potential of the MN2 tube is approximately VCC-Vth(MN1).

[0146] Fourth stage: Due to the difference in potential between MN2 and MN3 (substrate bias effect), when the first voltage V1 continues to rise to Vth(MN2), MN2 is turned on, MN3 is turned off, and the drain potential of MN2 decreases. Ignoring the voltage drop of MN2, the source potential of MN3 can be approximated to VR2 (the voltage difference across the second resistor R2).

[0147] Phase 5: As the power supply voltage VCC rises, the first voltage V1 at the first node N1 continues to rise. When the first voltage V1 reaches the trigger threshold (ignoring the voltage drop of MN2): Vth(MN3)+VR2, the MN3 transistor is turned on. The power supply voltage VCC at this time can be called VCCon, that is, the starting voltage value of the POR voltage output.

[0148] At this stage, when the MN3 tube is turned on, the second voltage V2 at the second node N2 decreases rapidly. In response to the potential change of the second voltage V2, in the first inverter composed of MP5 and MN4, MP5 is turned on, and the power supply voltage VCC is transmitted to the second inverter (composed of MP6 and MN5). In response to the high level provided by the power supply voltage VCC, the MN5 tube in the second inverter is turned on, and the MN5 tube transmits the low level of the ground voltage GND to the third node N3. In response to the low level of the third node N3, MN6 in the third inverter (composed of MP7 and MN6) is turned on, and finally the equivalent voltage of the power supply voltage VCC is output, that is, the POR voltage output is powered on; MP8 is turned on, and under the action of the turned-on MP8 tube, the power supply voltage VCC provided by the power supply voltage terminal is transmitted to the first node N1, and the first voltage V1 point is pulled up to the same value as the power supply voltage VCC, so that the conduction of the MN2 and MN3 tubes can be better maintained, so that the second node N2 can be maintained at a low potential.

[0149] From the above power-on working process and principle, we can know that if we ignore the conduction voltage drop of MN2 tube, we can get the following expression:

[0150] VCCon=VR0+Vth(MP4)+Vth(MN3)+VR2.

[0151] Trigger threshold: Vth(MN3)+VR2.

[0152] Among them, VR0 is the voltage difference across the positive temperature characteristic compensation resistor.

[0153] In this embodiment, when the external ambient temperature changes and causes the transistor characteristics of MP4 and MN3, especially the threshold voltage, to change, the primary temperature compensation can be achieved through the positive temperature characteristics of the resistor R0 itself (the primary compensation depends on the process and it is difficult to achieve accurate compensation). In addition, VR2 can be further controlled by adjusting the resistance value of the first resistor R1 and / or the second resistor R2 to achieve compensation for the trigger threshold through VR2, thereby achieving accurate compensation for the secondary temperature. In this way, the value of the VCCon is controllable and can be as unaffected by the external temperature as possible, thereby effectively achieving the full temperature range zero temperature characteristics of the power-on reset circuit.

[0154] In order to more intuitively reflect the full temperature range zero temperature characteristics achieved by the power-on reset circuit of this application, please refer to the following Figure 6 , Figure 6 It is a schematic diagram of a temperature characteristic curve provided in an embodiment of the present application. Figure 6 In the coordinate axis shown, the ordinate indicates the starting voltage value of the POR voltage, and the abscissa indicates the external environment temperature value.

[0155] like Figure 6 As shown, Figure 6 Line 1 in the figure is the temperature characteristic curve corresponding to the power-on reset circuit in the prior art: the temperature characteristic compensation is not performed or the compensation capability is insufficient. As can be seen from the figure, when the temperature gradually decreases (for example, from summer to winter), the starting voltage value of the POR voltage output by the circuit will gradually increase as the temperature decreases. That is, the lower the external environment temperature, the more difficult it is for the power-on reset circuit to start powering on.

[0156] Thus, when the power-on reset circuit is applied to a circuit system, since its starting voltage point is greatly affected by temperature, it is not conducive to starting the chip initialization work in time.

[0157] Figure 6 Line 2 in FIG. 1 is a temperature characteristic curve corresponding to a power-on reset circuit provided in an embodiment of the present application. As can be seen from the figure, when the temperature gradually decreases, the starting voltage value of the POR voltage output by the circuit is always only within a small range of waveforms.

[0158] That is to say, the power-on reset circuit provided by the embodiment of the present application can basically effectively realize the zero temperature characteristic of the power-on reset circuit in the full temperature range. In this way, no matter what changes occur in the external ambient temperature, the power-on reset circuit can respond to the output POR voltage in time, which is conducive to the rapid start of the chip initialization work in the actual circuit system.

[0159] It should be added that, in some other possible implementations, the primary compensation unit may not be implemented by the positive temperature characteristic compensation resistor R0, but may specifically include a PMOS tube. The control end of the PMOS tube is grounded, the first end is electrically connected to the power supply voltage end, and the second end is electrically connected to the first end of the fourth PMOS tube MP4. In actual circuit operation, the PMOS tube may be equivalent to a linear resistor.

[0160] And, in some other possible implementations, in order to further increase the delay effect of the delay unit, the delay unit may further include a second capacitor, the first electrode of the second capacitor may be electrically connected to the third node N3, and the second electrode of the second capacitor may be grounded. In this way, based on the storage function of the second capacitor, the delay of the POR voltage output is further achieved.

[0161] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a power-on reset method, which is applied to a power-on reset circuit provided by any embodiment of the first aspect of the present application; the power-on reset method comprises:

[0162] The trigger threshold is compensated by controlling the resistance values ​​of at least two voltage-dividing resistors in the trigger module.

[0163] A power-on reset method provided in an embodiment of the present application can compensate for a trigger threshold by controlling at least two voltage-dividing resistors in a trigger module under different external temperature environments, so that the trigger threshold can be flexibly adjusted with the temperature. The trigger threshold directly affects the starting value of the equivalent voltage of the power supply voltage output by the power-on reset circuit. Therefore, the power-on reset method can effectively ensure that the POR voltage starting point is consistent at different temperatures, thereby fully realizing the full temperature range zero temperature characteristics of the power-on reset circuit.

[0164] It should be understood that the specific structures of the circuits provided in the drawings of the embodiments of the present application are merely examples and are not intended to limit the present application. In addition, the above embodiments provided in the present application may be combined with each other if there is no contradiction.

[0165] It should be clear that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. According to the embodiments described above in this application, these embodiments do not describe all the details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the application, so that technicians in the relevant technical field can make good use of the application and the modified use based on the application. The application is only limited by the claims and their full scope and equivalents.

[0166] Those skilled in the art should understand that the above embodiments are exemplary rather than restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on the study of the drawings, the specification and the claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity involves "one" but does not exclude multiple; the terms "first" and "second" are used to indicate names rather than to indicate any specific order. Any figure marks in the claims should not be understood as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A power-on reset circuit, characterized in that: include: A startup module, wherein a first terminal of the startup module is electrically connected to a power supply voltage terminal, a second terminal of the startup module is grounded, and the startup module includes a first node; The startup module is used to output a first voltage at the first node according to the power supply voltage provided by the power supply voltage terminal; A trigger module, wherein a first end of the trigger module is electrically connected to the power supply voltage end, and a second end of the reset trigger module is grounded; the trigger module comprises a second node; and the trigger module comprises at least two voltage-dividing resistors; The trigger module is used for outputting a power-on reset enable signal at the second node when the first voltage reaches a trigger threshold; and, compensating the trigger threshold according to the resistance values ​​of the at least two voltage-dividing resistors; An inverting delay module, wherein the first end of the inverting delay module is electrically connected to the power supply voltage end, and the second end of the inverting delay module is grounded; the inverting delay module is used to respond to the power-on reset enable signal, flip the equivalent voltage of the power supply voltage and then delay the output.

2. The circuit according to claim 1, characterized in that The trigger module includes a first switch unit, a second switch unit, a third switch unit, a first resistor and a second resistor; A first end of the first resistor is electrically connected to the power supply voltage end, and a second end of the first resistor is electrically connected to a second end of the first switch module; The control end of the first switch unit is electrically connected to the second node, and the first end of the first switch unit is electrically connected to the first end of the second resistor; The control end of the second switch unit is electrically connected to the first node, the first end of the second switch unit is electrically connected to the second end of the second resistor, and the second end of the second switch unit is grounded; The control end of the third switch unit is electrically connected to the first node, the first end of the third switch unit is electrically connected to the second node, and the second end of the third switch unit is electrically connected to the first end of the second resistor; The first switch unit, the second switch unit and the third switch unit are turned on in sequence as the first voltage increases; when the first voltage increases to reach the trigger threshold, the third switch unit is turned on to reduce the node potential of the second node to output the power-on reset enable signal; The trigger threshold is associated with a target voltage value, and the target voltage value is the sum of a turn-on threshold voltage of the third switch unit and a voltage difference across the second resistor; When the turn-on threshold voltage of the third switch unit changes, the trigger threshold is compensated by adjusting the voltage difference across the second resistor.

3. The circuit according to claim 2, characterized in that The trigger module further includes a fourth switch unit, a fifth switch unit and a sixth switch unit; The control end of the fourth switch unit is electrically connected to the second node, the first end of the fourth switch unit is electrically connected to the second end of the fifth switch unit, and the second end of the fourth switch unit is grounded; The control end of the fifth switch unit is electrically connected to the first node, and the first end of the fifth switch unit is electrically connected to the power supply voltage end; The control end of the sixth switch unit is electrically connected to the first node, the first end of the sixth switch unit is electrically connected to the second end of the fifth switch unit, and the second end of the sixth switch unit is electrically connected to the second node; When the first voltage does not reach the trigger threshold, the fifth switch unit and the sixth switch unit are turned on to pull up the node potential of the second node to output a power-on reset disabling signal; The inversion delay module is used to respond to the power-on reset disable signal, invert the ground voltage and then output it with a delay.

4. The circuit according to claim 3, characterized in that The first switch unit includes a first NMOS transistor, the second switch unit includes a second NMOS transistor, and the third switch unit includes a third NMOS transistor; the fourth switch unit includes a first PMOS transistor, the fifth switch unit includes a second PMOS transistor, and the sixth switch unit includes a third PMOS transistor; The control end of the first NMOS transistor is electrically connected to the second node, the first end of the first NMOS transistor is electrically connected to the first end of the second resistor, and the second end of the first NMOS transistor is electrically connected to the second end of the first resistor; The control end of the second NMOS transistor is electrically connected to the first node, the first end of the second NMOS transistor is electrically connected to the second end of the second resistor, and the second end of the second NMOS transistor is grounded; The control end of the third NMOS transistor is electrically connected to the first node, the first end of the third NMOS transistor is electrically connected to the second node, and the second end of the third NMOS transistor is electrically connected to the first end of the second resistor; The control end of the first PMOS tube is electrically connected to the second node, the first end of the first PMOS tube is electrically connected to the second end of the second PMOS tube, and the second end of the first PMOS tube is grounded; The control end of the second PMOS tube is electrically connected to the first node, and the first end of the second PMOS tube is electrically connected to the power supply voltage end; The control end of the third PMOS tube is electrically connected to the first node, the first end of the third PMOS tube is electrically connected to the second end of the second PMOS tube, and the second end of the third PMOS tube is electrically connected to the second node.

5. The circuit according to claim 1, characterized in that The startup module includes a primary compensation unit, a seventh switch unit and a first storage unit; The first end of the primary compensation unit is electrically connected to the power supply voltage end, and the second end of the initial compensation unit is electrically connected to the first end of the seventh switch unit; The control terminal and the second terminal of the seventh switch unit are both electrically connected to the first node; A first electrode of the first storage unit is electrically connected to the first node, and a second electrode of the first storage unit is grounded.

6. The circuit according to claim 5, characterized in that The primary compensation unit includes a positive temperature characteristic compensation resistor, the seventh switch unit includes a fourth PMOS tube, and the first storage unit includes a first capacitor; The first end of the positive temperature characteristic compensation resistor is electrically connected to the power supply voltage terminal, and the second end of the compensation resistor is electrically connected to the first end of the fourth PMOS tube; The control end and the second end of the fourth PMOS tube are both electrically connected to the first node; A first electrode of the first capacitor is electrically connected to the first node, and a second electrode of the first capacitor is grounded.

7. The circuit according to claim 1, characterized in that The trigger module also includes a power-on reset maintaining unit; The control end of the power-on reset maintaining unit is electrically connected to the third node, the first end of the power-on reset maintaining unit is electrically connected to the power supply voltage end, and the second end of the power-on reset maintaining unit is electrically connected to the first node; The power-on reset maintaining unit is used to transmit the power supply voltage provided by the power supply voltage terminal to the first node in response to the conduction level of the third node; wherein, when the node voltage of the second node is the power-on reset enable signal, the third node provides a conduction level.

8. The circuit according to claim 1, characterized in that The inversion delay module includes an inverter unit and a delay unit; the delay unit includes an even number of inverters; the inverter unit includes an odd number of inverters; The first end of the delay unit is electrically connected to the power supply voltage end, and the second end of the delay unit is grounded; the delay unit is used to delay the output of the ground voltage to the inverter unit in response to the power-on reset enable signal of the second node; The first end of the inverter unit is electrically connected to the power supply voltage end, and the second end of the inverter unit is grounded; The inverter unit is used to flip the ground voltage an odd number of times to generate a voltage equivalent to the power supply voltage, and output the voltage equivalent to the power supply voltage.

9. The circuit according to claim 1, characterized in that The delay unit includes a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube and a fifth NMOS tube; the inverter unit includes a seventh PMOS tube and a sixth NMOS tube; The control end of the fifth PMOS tube is electrically connected to the second node, the first end of the fifth PMOS tube is electrically connected to the power supply voltage end, and the second end of the fifth PMOS tube is electrically connected to the first end of the fourth NMOS tube; The control end of the fourth NMOS transistor is electrically connected to the second node, and the second end of the fourth NMOS transistor is grounded; The control end of the sixth PMOS tube is electrically connected to the first end of the fourth NMOS tube, the first end of the sixth PMOS tube is electrically connected to the power supply voltage end, and the second end of the sixth PMOS tube is electrically connected to the third node; The control end of the fifth NMOS tube is electrically connected to the first end of the fourth NMOS tube, the first end of the fifth NMOS tube is electrically connected to the third node, and the second end of the fifth NMOS tube is grounded; The control end of the seventh PMOS tube is electrically connected to the third node, the first end of the seventh PMOS tube is electrically connected to the power supply voltage end, and the second end of the seventh PMOS tube is electrically connected to the power-on reset signal output end; The control end of the sixth NMOS tube is electrically connected to the third node, the first end of the sixth NMOS tube is electrically connected to the power-on reset signal output end, and the second end of the sixth NMOS tube is grounded; Wherein, the power-on reset signal output terminal is used to output a voltage equivalent to the power supply voltage.

10. A power-on reset method, characterized in that: Applicable to the power-on reset circuit according to any one of claims 1 to 9; the power-on reset method comprises: The trigger threshold is compensated by controlling the resistance values ​​of at least two voltage-dividing resistors in the trigger module.

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