Injection locking phase-locked loop clock system and electronic chip

Abstract

The invention relates to the technical field of integrated circuits, and discloses an injection-locked phase-locked loop clock system and an electronic chip. The system comprises a first phase-locked loop circuit and a second phase-locked loop circuit which are cascaded, a first time sequence self-calibrator of a first phase-locked loop circuit processes a first injection clock signal and an intermediate clock signal output by a first signal pulse generator to obtain a first delay control voltage; the first phase-locked loop main loop processes the reference clock signal and the first injection clock signal based on the first delay control voltage to obtain an intermediate clock signal; a second time sequence self-calibrator of a second phase-locked loop circuit processes a second injection clock signal and an output clock signal output by a second signal pulse generator to obtain a second delay control voltage; and the second phase-locked loop main loop processes the reference clock signal and the second injection clock signal based on the second delay control voltage to obtain an output clock signal. The time sequence calibration can be automatically completed, and the reliability of the system is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to an injection locked phase locked loop clock system and an electronic chip. Background Art

[0002] As digital circuits become larger and larger and clock speeds become faster and faster, the phase-locked loop system is used to provide a clean, low-jitter, and reliable high-speed clock to the high-speed clock chip as much as possible.

[0003] However, as the requirements for power consumption and noise continue to increase, various improved PLL structures have emerged, such as charge pump phase-locked loop (CPPLL), all-digital phase-locked loop (ADPLL), sub-sampling phase-locked loop (SSPLL), and injection-locked phase-locked loop (ILPLL).

[0004] The injection-locked phase-locked loop (ILPLL) is based on the traditional charge pump phase-locked loop (CPPLL). It injects a clean pulse V into the oscillator VCO at the frequency of a low-frequency clock such as the reference clock REF. inj , the output clock CLK of the oscillator VCO is periodically retimed. This structure can simultaneously reduce the in-band and out-of-band phase noise in the phase-locked loop without significantly increasing the power consumption of the phase-locked loop, thereby achieving low jitter and low power consumption at the same time.

[0005] Since the essence of the injection-locked phase-locked loop (ILPLL) is to inject a low-frequency clean pulse into the oscillator based on the traditional charge pump (CPPPLL), it is important to align the edge and timing of the additional low-frequency pulse with the edge and timing injected by the charge pump (CP, Charge Pump) in the main loop. In CPPLL, the phase frequency detector (PFD, Phase Frequency Detector) helps the reference clock and the divided clock to align the frequency and phase. If the alignment cannot be achieved or the alignment is insufficient, reference spurious spikes will be generated around the spectrum of the output clock at the reference frequency of positive and negative N positive integer multiples. This spike is generated when the CP is injected; while in the injection-locked phase-locked loop (ILPLL), the charge pump CP injects and additionally injects a low-frequency clock into the oscillator. If the timing edge is not aligned, reference spurious will naturally be generated in the same way; and the higher the frequency of the phase-locked loop, the higher the requirements for timing and edge alignment will be. If the timing edge cannot be aligned, the reference spurious will be significantly deteriorated in the high-frequency ILPLL. Summary of the invention

[0006] In view of this, the embodiments of the present application provide an injection-locked phase-locked loop clock system and an electronic chip, which can effectively solve the injection-locked phase-locked loop reference spurious problem, etc.

[0007] In a first aspect, an embodiment of the present application provides an injection-locked phase-locked loop clock system, comprising: a first phase-locked loop circuit and a second phase-locked loop circuit connected in cascade;

[0008] The first phase-locked loop circuit includes a first signal pulse generator, a first phase-locked loop main loop and a first timing self-calibrator; the first signal pulse generator is used to process the input reference clock signal to obtain a first injection clock signal; the first timing self-calibrator is used to perform timing processing on the first injection clock signal and the intermediate clock signal to obtain a first delay control voltage; the first phase-locked loop main loop is used to process the reference clock signal and the first injection clock signal under the action of the first delay control voltage to obtain the intermediate clock signal;

[0009] The second phase-locked loop circuit includes a second signal pulse generator, a second phase-locked loop main loop and a second timing self-calibrator; the second signal pulse generator is used to process the intermediate clock signal output by the first phase-locked loop main loop to obtain a second injection clock signal; the second timing self-calibrator is used to perform timing processing on the second injection clock signal and the output clock signal to obtain a second delay control voltage; the second phase-locked loop main loop is used to process the reference clock signal and the second injection clock signal under the action of the second delay control voltage to obtain the output clock signal.

[0010] In some embodiments, the first timing self-calibrator and the second timing self-calibrator have the same structure;

[0011] The first timing self-calibrator includes a frequency division module, a control module, a switch module and an output module;

[0012] The input of the frequency division module is connected to the intermediate clock signal, and the frequency division module is used to perform frequency division processing on the intermediate clock signal to obtain a positive phase frequency division signal and a negative phase frequency division signal;

[0013] The input of the control module is connected to the output end of the frequency division module, and the control module is used to receive the positive phase frequency division signal and the negative phase frequency division signal, and perform control according to the positive phase frequency division signal and the negative phase frequency division signal to output a first voltage and a second voltage;

[0014] The input end of the output module is connected to the output end of the control module via the switch module. When the switch module is closed, the output module uses the first voltage and the second voltage as the third voltage and the fourth voltage input to the output module respectively, and obtains the first delay control voltage according to the third voltage and the fourth voltage.

[0015] In some embodiments, when the first injection clock signal is at a high level, the switch module is in a closed state so that the third voltage follows the first voltage change and the fourth voltage follows the second voltage change; when the first injection clock is at a low level and the edges of the first injection clock signal and the intermediate clock signal are aligned, the switch module switches to an open state so that the injection-locked phase-locked loop clock system is locked to the same third voltage and the fourth voltage.

[0016] In some embodiments, the frequency division module includes a two-frequency divider, a first buffer, and a second buffer;

[0017] The clock input end of the frequency divider is connected to the intermediate clock signal, and the data input end of the frequency divider is connected to the second output end of the frequency divider; the frequency divider is used to perform frequency division processing on the intermediate clock signal to obtain a frequency division signal;

[0018] The input end of the first buffer is connected to the first output end of the binary frequency divider, and the first buffer is used to buffer the frequency-divided signal to obtain a positive-phase frequency-divided signal;

[0019] The input end of the second buffer is connected to the first output end of the binary frequency divider. The second buffer has a built-in inverter. The second buffer is used to perform inverting buffering on the frequency-divided signal to obtain an inverted frequency-divided signal.

[0020] In some embodiments, the control module includes a first set of current sources and a second set of current sources;

[0021] The input end of the first group of current sources is connected to the output end of the first buffer and the output end of the second buffer, and the first group of current sources is used to obtain the first voltage according to the positive phase frequency division signal and the negative phase frequency division signal;

[0022] The input end of the second current source group is connected to the output end of the first buffer and the output end of the second buffer, and the second current source group is used to obtain the second voltage according to the positive phase frequency division signal and the negative phase frequency division signal;

[0023] The second voltage is opposite to the first voltage in direction.

[0024] In some embodiments, the first phase-locked loop main loop is specifically used for:

[0025] Under the action of the first delay control voltage, delay processing is performed on the reference clock signal to obtain a first delayed reference clock;

[0026] The intermediate clock signal is obtained according to the first delayed reference clock, the first injected clock signal and the first frequency-divided clock signal of the first phase-locked loop main loop.

[0027] In some embodiments, the first phase-locked loop main loop includes a first adjustable delay module, a first phase frequency detector / charge pump, a first voltage-controlled oscillator, and a first frequency divider;

[0028] The first adjustable delay module is connected to the reference clock signal and the first delay control voltage, and the first adjustable delay module is used to delay the reference clock signal under the action of the first delay control voltage to obtain a first delayed reference clock;

[0029] The input end of the first phase frequency detector / charge pump is connected to the output end of the first adjustable delay module and the output end of the first frequency divider; the first phase frequency detector / charge pump is used to process the phase difference between the first delay reference clock and the first frequency-divided clock signal output by the first frequency divider to obtain a first control voltage;

[0030] The input end of the first voltage-controlled oscillator is connected to the output end of the first phase frequency detector / charge pump, and the output end of the first voltage-controlled oscillator is connected to the input end of the first phase frequency detector / charge pump via the first frequency divider; the first voltage-controlled oscillator is used to process the first control voltage and the first injected clock signal to obtain the intermediate clock signal.

[0031] In some embodiments, the second phase-locked loop main loop is specifically used for:

[0032] Under the action of the second delay control voltage, the reference clock signal is delayed and controlled to obtain a second delayed reference clock;

[0033] The output clock signal is obtained according to the second delayed reference clock, the second injected clock signal and the second frequency-divided clock signal of the second phase-locked loop main loop.

[0034] In some embodiments, the second phase-locked loop main loop includes a second adjustable delay module, a second phase frequency detector / charge pump, a second voltage-controlled oscillator, and a second frequency divider;

[0035] The second adjustable delay module is connected to the intermediate clock signal and the second delay control voltage. Under the action of the second delay control voltage, the second adjustable delay module performs delay processing on the intermediate clock signal to obtain a second delayed reference clock;

[0036] The input end of the second phase frequency detector / charge pump is connected to the output end of the second adjustable delay module and the output end of the second frequency divider; the second phase frequency detector / charge pump is used to process the phase difference between the second delayed reference clock and the second frequency-divided clock signal output by the second frequency divider to obtain a second control voltage;

[0037] The input end of the second voltage-controlled oscillator is connected to the output end of the second phase frequency detector / charge pump, and the output end of the second voltage-controlled oscillator is connected to the input end of the second phase frequency detector / charge pump via the second frequency divider; the second voltage-controlled oscillator is used to obtain the output clock signal according to the second control voltage and the second injection clock signal.

[0038] In a second aspect, an embodiment of the present application provides an electronic chip, wherein the electronic chip includes a clock circuit, and the clock circuit is the above-mentioned injection-locked phase-locked loop clock system.

[0039] The embodiments of the present application have the following beneficial effects:

[0040] The first phase-locked loop circuit in the injection-locked clock system of the present application performs a first-stage frequency multiplication, and the second phase-locked loop circuit performs a second-stage frequency multiplication. The first phase-locked loop circuit and the second phase-locked loop circuit are cascaded to achieve a smaller frequency multiplication, thereby achieving a larger frequency multiplication result for the entire injection-locked clock system. Each phase-locked loop circuit has a smaller frequency multiplication, which can ensure low noise and low jitter; and under the action of the timing self-calibrator, the output signal of the phase-locked loop circuit and the injected clock signal can be edge-aligned, thereby reducing the deterioration of reference spurs and even avoiding the occurrence of reference spurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 A schematic diagram of the principle structure of an injection locked phase locked loop clock system in an embodiment of the present application is shown;

[0043] Figure 2 A schematic diagram of the timing of each signal node in the injection-locked phase-locked loop clock system according to an embodiment of the present application is shown;

[0044] Figure 3 A partial signal schematic diagram of a voltage-controlled oscillator in a main loop of a phase-locked loop according to an embodiment of the present application is shown;

[0045] Figure 4 A schematic diagram showing synthesis of different current vectors during the locking process of an embodiment of the present application is shown;

[0046] Figure 5 The schematic structure diagram of the first timing self-calibrator according to the embodiment of the present application is shown;

[0047] Figure 6 A timing diagram of each signal node in the first timing self-calibrator according to an embodiment of the present application is shown.

[0048] Description of main component symbols:

[0049] 10-first phase-locked loop circuit; 11-first signal pulse generator; 12-first phase-locked loop main loop; 20-second phase-locked loop circuit; 21-second signal pulse generator; 22-second phase-locked loop main loop; 30-frequency division module; 40-control module; 41-first group of current sources; 42-second group of current sources; 50 switch module; 60-output module. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0051] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0052] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.

[0053] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0054] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0055] The injection-locked phase-locked loop clock system injects a clean low-frequency clock and periodically resets the output clock signal of the voltage-controlled oscillator to simultaneously reduce the in-band and out-of-band phase noise within the phase-locked loop. However, the frequency of the injected low-frequency clock ω in For the frequency ω of the output clock signal of the voltage controlled oscillator out The size of the multiple N between the two has a greater impact on the effect of reducing noise. The larger N is, the worse the effect of reducing phase noise is. Therefore, the current injection-locked phase-locked loop clock system using a single phase-locked loop is not suitable for using a large division ratio, that is, the ratio of the frequency of the output clock to the frequency of the injected clock signal; and the timing of the injected clock signal and the output clock of the locked main loop needs to be accurately aligned, otherwise the misaligned part will produce sufficiently large reference spurs at the reference frequency of positive and negative N positive integer multiples around the main frequency point of the phase-locked loop, further deteriorating the performance of the output clock; in response to the above-mentioned problems, the present application proposes to use two injection phase-locked loops and cascade the two injection phase-locked loops, so as to achieve a larger division ratio, while ensuring a better noise reduction effect, and the timing calibration can be automatically completed through the timing self-calibrator in the system; that is, the present application proposes a low-power, low-jitter injection-locked phase-locked loop clock system.

[0056] The injection locked phase locked loop clock system is described below in conjunction with some specific embodiments.

[0057] Figure 1 A structural schematic diagram of an injection-locked phase-locked loop clock system of an embodiment of the present application is shown. Exemplarily, the injection-locked phase-locked loop clock system includes a first phase-locked loop circuit 10 and a second phase-locked loop circuit 20; the first phase-locked loop circuit 10 and the second phase-locked loop circuit 20 are cascaded, and the first phase-locked loop circuit 10 and the second phase-locked loop circuit 20 have a signal pulse generator (11, 21), a phase-locked loop main loop (12, 22) and a timing self-calibrator (auto-Calib1, auto-Calib2) of the same structure.

[0058] In order to more clearly describe the injection-locked phase-locked loop clock system and the signal processing change process, the first phase-locked loop circuit 10 and the second phase-locked loop circuit 20 have the same structure of signal pulse generator (11, 21), phase-locked loop main loop (12, 22) and timing self-calibrator (auto-Calib1, auto-Calib2) as follows: the first phase-locked loop circuit 10 includes a first signal pulse generator 11, a first phase-locked loop main loop 12 and a first timing self-calibrator auto-Calib1; the second phase-locked loop circuit 20 includes a second signal pulse generator 21, a second phase-locked loop main loop 22 and a second timing self-calibrator auto-Calib2.

[0059] In the first phase-locked loop circuit 10, the input end of the first signal pulse generator 11 is connected to the reference clock signal REF, and the first signal pulse generator 11 delays the reference clock signal REF and then outputs the first injection clock signal V inj1 The first input terminal of the first timing self-calibrator auto-Calib1 is connected to the output terminal of the first signal pulse generator for receiving the first injection clock signal V inj1 The second input terminal of the first timing self-calibrator auto-Calib1 is connected to the output terminal of the first phase-locked loop main loop 12 for receiving the intermediate clock signal CLKN; the first timing self-calibrator auto-Calib1 injects the clock signal V inj1 The first delay control voltage V is obtained by performing edge alignment processing on the intermediate clock signal CLKN. tc1 The reference input terminal of the first phase-locked loop main loop 12 is connected to the reference clock signal REF; the injection input terminal of the first phase-locked loop main loop 12 is connected to the output terminal of the first signal pulse generator 11 for receiving the first injection clock signal V inj1 The control end of the first phase-locked loop main loop 12 is connected to the output end of the first timing self-calibrator auto-Calib1, which is used to receive the first delay control voltage V tc1 The first phase-locked loop main loop 12 is in the first delay control voltage V tc1 Under the action of the reference clock signal REF and the first injected clock signal V inj1 The intermediate clock signal CLKN is obtained by processing.

[0060] In one embodiment of the present application, the first signal pulse generator 11 is mainly used to generate a first injection clock signal V inj1The first signal pulse generator 11 includes a first delay module △T11, a first inverter and a first AND gate; the input end of the first delay module △T11 is connected to the reference clock signal REF, and the output end of the first delay module △T11 is connected to the first input end of the first AND gate via the first inverter; the second input end of the first AND gate is connected to the reference clock signal, and the output end of the first AND gate is the output end of the first signal pulse generator 11, forming a pulse signal generator that only generates a first set width (200ps) at the rising edge of the reference clock signal, that is, the first injection clock signal V output by the first signal pulse generator 11 inj1 The pulse width is the first set width (200ps), and the first injected clock signal V inj1 Directly output to the first phase-locked loop circuit 10.

[0061] The first delay module △T11 in this application is used to define the first injection clock signal V inj1 The bandwidth of the first signal pulse generator 11 is directly equal to the frequency of the first injected clock signal, which can break through the limitation that the bandwidth of the locked main loop needs to be the ratio of the frequency of the reference clock signal, thereby achieving faster and more precise phase offset adjustment.

[0062] In one embodiment of the present application, the first phase-locked loop main loop 12 is in a state where the first delay control voltage V tc1 Under the action of, the reference clock signal REF is delayed to obtain a first delayed reference clock ref d1 ; and according to the first delayed reference clock ref d1 , the first injected clock signal V inj1 The intermediate clock signal CLKN is obtained by combining the first divided clock signal div1 of the first phase-locked loop main loop 12.

[0063] Specifically, the first phase-locked loop main loop 12 includes a first adjustable delay module △T1, a first phase frequency detector / charge pump PFD1 / CP1, a first voltage-controlled oscillator VCO1 and a first frequency divider DIV1; the first adjustable delay module △T1 is connected to the reference clock signal REF and the first delay control voltage V tc1 The first adjustable delay module △T1 is at the first delay control voltage V tc1 Under the action of, the reference clock signal REF is delayed to obtain a first delayed reference clock ref d1 The input end of the first phase frequency detector / charge pump PFD1 / CP1 is connected to the output end of the first adjustable delay module △T1 and the output end of the first frequency divider DIV1; the first phase frequency detector / charge pump PFD1 / CP1 is connected to the first delay reference clock ref d1The first control voltage vc1 is obtained by processing the phase difference of the first divided clock signal div1 output by the first frequency divider DIV1; the input end of the first voltage controlled oscillator VCO1 is connected to the output end of the first phase frequency detector / charge pump PFD1 / CP1, and the output end of the first voltage controlled oscillator VCO1 is connected to the input end of the first phase frequency detector / charge pump PFD1 / CP1 through the first frequency divider DIV1; the first voltage controlled oscillator VCO1 generates an input signal according to the first control voltage vc1 and the first injected clock signal V inj1 The intermediate clock signal CLKN is obtained.

[0064] In another embodiment of the present application, the first phase-locked loop main loop 12 further includes a first low-pass filter LPF1, which is connected between the output end of the first phase frequency detector / charge pump PFD1 / CP1 and the input end of the first voltage-controlled oscillator VCO1, and is used to filter the first control voltage vc1 output by the first phase frequency detector / charge pump PFD1 / CP1 and then input it into the first voltage-controlled oscillator VCO1. Exemplarily, the first low-pass filter LPF1 includes a first branch and a second branch, the first branch and the second branch are connected in parallel, the first branch includes a capacitor and a resistor, and the second branch includes a resistor.

[0065] In the second phase-locked loop circuit 20, the input end of the second signal pulse generator 21 is connected to the output end of the first phase-locked loop circuit 10. The second signal pulse generator 21 uses the intermediate clock signal CLKN as its reference clock signal, delays the intermediate clock signal CLKN, and then outputs the second injection clock signal V inj2 The first input terminal of the second timing self-calibrator auto-Calib2 is connected to the output terminal of the second signal pulse generator 21, and is used to receive the second injection clock signal V inj2 The second input terminal of the second timing self-calibrator auto-Calib2 is connected to the output terminal of the second phase-locked loop main loop 22 for receiving the output clock signal CLKO; the second timing self-calibrator auto-Calib2 is connected to the second injection clock signal V inj2 The second delay control voltage V is obtained by performing edge alignment processing on the output clock signal CLKO tc2 The reference input terminal of the second phase-locked loop main loop 22 is connected to the reference clock signal REF; the injection input terminal of the second phase-locked loop main loop 22 is connected to the output terminal of the second signal pulse generator 21 for receiving the second injection clock signal V inj2 The control end of the second phase-locked loop main loop 22 is connected to the output end of the second timing self-calibrator auto-Calib2, for receiving the second delay control voltage V tc2 The second phase-locked loop main loop 22 at the second delay control voltage V tc2Under the action of the reference clock signal REF and the second injected clock signal V inj2 The output clock signal CLKO is obtained by processing.

[0066] In one embodiment of the present application, the second signal pulse generator 21 is mainly used to generate a second injection clock signal V inj2 The second signal pulse generator 21 includes a second delay module △T21, a second inverter and a second AND gate; the input end of the second delay module △T21 is connected to the reference clock signal REF, and the output end of the second delay module △T21 is connected to the first input end of the second AND gate via the second inverter; the second input end of the second AND gate is connected to the reference clock signal, and the output end of the second AND gate is the output end of the second signal pulse generator 21, forming a pulse signal generator that only generates a second set width (50ps) at the rising edge of the reference clock signal, that is, the second injection clock signal V output by the second signal pulse generator 21 inj2 The pulse width is the second set width (50ps), and the generated second injection clock signal V inj2 The signal is directly output to the second phase-locked loop circuit 20 .

[0067] The second delay module △T21 in this application is used to define the second injection clock signal V inj2 The width of the second signal pulse generator 21 is directly equal to the frequency of the second injected clock signal, which can break through the ratio limitation that the locked main loop bandwidth needs to be the frequency of the reference clock signal, thereby achieving faster and more precise phase offset adjustment.

[0068] In one embodiment of the present application, the second phase-locked loop main loop 22 is controlled by the second delay control voltage V tc2 Under the action of, the reference clock signal REF is delayed to obtain a second delayed reference clock ref d1 ; and according to the second delayed reference clock ref d1 , the second injected clock signal V inj2 The output clock signal CLKO is obtained by combining the second divided clock signal div of the second phase-locked loop main loop 22.

[0069] Specifically, the second phase-locked loop main loop 22 includes a second adjustable delay module △T2, a second phase frequency detector / charge pump PFD2 / CP2, a second voltage-controlled oscillator VCO2 and a second frequency divider DIV2; the second adjustable delay module △T2 is connected to the intermediate clock signal CLKN and the second delay control voltage V tc2 The second adjustable delay module △T2 is at the second delay control voltage V tc2 Under the action of , the intermediate clock signal CLKN is delayed to obtain the second delayed reference clock ref d2The input end of the second phase frequency detector / charge pump PFD2 / CP2 is connected to the output end of the second adjustable delay module △T2 and the output end of the second frequency divider DIV2; the second phase frequency detector / charge pump PFD2 / CP2 is connected to the second delay reference clock ref d2 The second control voltage vc2 is obtained by processing the phase difference of the second divided clock signal div2 output by the second frequency divider DIV2; the input end of the second voltage controlled oscillator VCO2 is connected to the output end of the second phase frequency detector / charge pump PFD2 / CP2, and the output end of the second voltage controlled oscillator VCO2 is connected to the input end of the second phase frequency detector / charge pump PFD2 / CP2 via the second frequency divider DIV2; the second voltage controlled oscillator VCO2 generates an output signal according to the second control voltage vc2 and the second injected clock signal V inj2 The output clock signal CLKO is obtained.

[0070] In another embodiment of the present application, the second phase-locked loop main loop 22 further includes a second low-pass filter LPF2, which is connected between the output end of the second phase frequency detector / charge pump PFD2 / CP2 and the input end of the second voltage-controlled oscillator VCO2, and is used to filter the second control voltage vc2 output by the second phase frequency detector / charge pump PFD2 / CP2 and then input it into the second voltage-controlled oscillator VCO2. Exemplarily, the structure of the second low-pass filter LPF2 is the same as that of the first low-pass filter LPF1.

[0071] Based on the above description of the cascaded first injection-locked phase-locked loop clock circuit and the second injection-locked phase-locked loop clock circuit, it can be seen that if there is no first injection-locked phase-locked loop clock circuit, the frequency of the injected clock source can only be 500MHz, and the frequency ratio of the output clock to the injected clock is 20. If the frequency ratio is too large, it will lead to poor noise optimization effect; and the entire injection-locked phase-locked loop clock system of the present application is divided into two parts, the multiplication ratio of the first injection-locked phase-locked loop clock circuit is N1, and the multiplication ratio of the second injection-locked phase-locked loop clock circuit is N2. For example, Figure 2 As shown, the first injection-locked phase-locked loop clock circuit multiplies the 500MHz reference clock signal REF to 2.5GHz. At this time, N1=5, and the first injection clock signal V inj1 and the pulse width of the intermediate clock signal CLKN is 200ps; then the 2.5GHz intermediate clock signal with a pulse width of 200ps is used as the injection clock source of the second signal pulse generator in the second injection-locked phase-locked loop clock circuit, and the second injection-locked phase-locked loop clock circuit multiplies the 2.5GHz injection clock source (intermediate clock signal) to the output clock signal CLKO of 10GHz. At this time, N2=4, and the second injection clock signal V inj2The pulse width of the output clock signal CLKO is 50ps; after two levels of frequency division, it is realized by 20 times, but in fact, the frequency ratio of the 10GHz output clock signal CLKO of the second injection-locked phase-locked loop clock circuit and the 2.5GHz injection clock source (intermediate clock signal CLKN) is

[0072] Taking into account that the phase noise within the locked frequency range decreases with the increase of the ratio of the output clock signal to the injected clock signal, it essentially means that when the injected clock responsible for periodically resetting the output clock phase deviation, if the frequency of the injected clock signal becomes smaller and smaller relative to the frequency of the output clock signal, the compensation effect on the phase deviation will become worse and worse, and when the frequency ratio is less than 5, a good phase noise optimization effect can still be achieved; therefore, the present application uses a cascade structure to achieve a ratio of the frequency of the output clock signal to the frequency of the injected clock signal to 4, while maintaining a good phase noise optimization effect, it can actually achieve a 20-fold clock multiplication effect.

[0073] Combination Figure 3 and Figure 4 Analyze the locking process of the injection phase-locked loop. Figure 3 This is a simplified schematic diagram of locking the main loop and the signal pulse generator in the voltage-controlled oscillator VCO to jointly control the output clock signal frequency. The resonant circuit in the dotted box indicates the voltage-controlled oscillator, and the current flowing through the entire voltage-controlled oscillator is represented by I T , respectively, by the control current I after passing through the low-pass filter OSC The injection current I of the injection pulse signal output by the signal pulse generator inj Since these three have a phase relationship, the sum of the two is a vector sum, as shown in the vector diagram Figure 4 As shown in Figure 1.1, the delay module of the signal pulse generator is fixed. inj is the horizontal axis, in fact, I T and I OSC The direction of the signal is changing. Assuming that at a certain moment, the signal obtained is as shown in the right figure, the I obtained by combining the two T in I inj The direction is 0, only I inj The vertical component of the ideal state is that each subsequent adjustment, I inj and I OSC In the horizontal direction, it is 0, and I T The value changes only in the vertical direction. Based on this special case as the boundary, two regions can be obtained in the vector diagram, one is the α angle region on the right, and the other is the β angle region on the left. The phase noise performance of the entire injection phase-locked loop in the two regions is completely different.

[0074] When the locking performance in the α angle area, when the locking situation enters the α angle area, then no matter at a certain moment, I T The components in the horizontal direction are all positive, so the next time I OSC A positive vector component will be added to the horizontal axis, and the cycle operation will be adjusted multiple times, and finally I OSC Will get closer to I inj , and every time I get close, T The absolute value of the component in the vertical direction will decrease, and finally when it is stable, I inj and I OSC It will oscillate within a very small angle. At this time, this very small angle is the jitter of the final output clock, so the jitter is very low.

[0075] When the locking performance in the β angle area, when the locking situation enters the β angle area, then no matter at a certain moment, I T The components in the horizontal direction are all negative, so the next time I OSC A negative vector component will be added to the horizontal axis, so I OSC Gradually approaching the negative direction of the horizontal axis, because there is inevitably a lag in adjustment, it will definitely exceed the horizontal axis and enter the lower half of the β angle area. At this time, it is equivalent to jumping into the next cycle. At this time, after maintaining a certain excess amount, continue to make similar reciprocating adjustments in the opposite direction, so I OSC It will be adjusted repeatedly in the β angle area, and the phase noise of the output clock will continue to change. The closer it is to the horizontal axis, the greater the phase deviation. Therefore, in this locked area, the jitter of the clock output by the overall phase-locked loop system will be very large.

[0076] Based on the above analysis of the locking process of the injection phase-locked loop, it is necessary to avoid entering the β angle area, so timing alignment and self-calibration are particularly important; the timing self-calibrator of the present application is introduced below. The structure of the first timing self-calibrator and the second timing self-calibrator is the same. In this application, the first timing self-calibrator is mainly taken as an example to introduce the structure of the timing self-calibrator in detail.

[0077] like Figure 5 As shown, the first timing self-calibrator includes a frequency division module 30 , a control module 40 , a switch module 50 and an output module 60 .

[0078] The input of the frequency division module 30 of the present application is connected to the intermediate clock signal CLKN, and performs frequency division processing on the intermediate clock signal CLKN to obtain a positive phase frequency division signal and a negative phase frequency division signal.

[0079] In some embodiments, the frequency division module 30 includes a binary frequency divider, a first buffer and a second buffer; the clock input terminal Clk of the binary frequency divider is connected to the intermediate clock signal, and the data input terminal D of the binary frequency divider is connected to the second output terminal Q` of the binary frequency divider; the binary frequency divider divides the intermediate clock signal CLKN to obtain a frequency division signal clk1; the input terminal of the first buffer is connected to the first output terminal Q of the binary frequency divider, and the first buffer is used to buffer the frequency division signal to obtain a positive phase frequency division signal; the input terminal of the second buffer is connected to the first output terminal Q of the binary frequency divider, and the second buffer has a built-in inverter, and the second buffer is used to invert the frequency division signal to obtain an inverted phase frequency division signal.

[0080] The input of the control module 40 of the present application is connected to the output end of the frequency division module 30. The control module 40 is used to receive the positive phase frequency division signal and the negative phase frequency division signal, and perform control according to the positive phase frequency division signal and the negative phase frequency division signal to output a first voltage V1 and a second voltage V2.

[0081] In some embodiments, the control module 40 includes a first group of current sources 41 and a second group of current sources 42; the input end of the first group of current sources 41 is connected to the output end of the first buffer and the output end of the second buffer, and the first group of current sources 41 is used to process the positive phase frequency division signal and the negative phase frequency division signal to obtain a first voltage V1; the input end of the second group of current sources 42 is connected to the output end of the first buffer and the output end of the second buffer, and the second group of current sources 42 is used to process the positive phase frequency division signal and the negative phase frequency division signal to obtain a second voltage V2; wherein the second voltage V2 is opposite to the direction of the first voltage V1.

[0082] More specifically, the first group of current sources 41 includes a first current source I1 and a second current source I2; the control end of the first current source I1 is connected to the output end of the first buffer, the control end of the second current source I2 is connected to the output end of the second buffer, the positive pole of the first current source I1 is connected to the power supply, the negative pole of the first current source I1 is connected to the positive pole of the second current source I2, and the negative pole of the second current source I2 is grounded; the connection point between the first current source I1 and the second current source I2 is the output end of the first group of current sources 41, which outputs a first voltage V1.

[0083] More specifically, the second group of current sources 42 includes a third current source I3 and a fourth current source I4; the control end of the third current source I3 is connected to the output end of the second buffer, the control end of the fourth current source I4 is connected to the output end of the first buffer, the positive pole of the third current source I3 is connected to the power supply, the negative pole of the third current source I3 is connected to the positive pole of the fourth current source I4, and the negative pole of the fourth current source I4 is grounded; the connection point between the third current source I3 and the fourth current source I4 is the output end of the second group of current sources 42, and the first voltage V2 is output.

[0084] The input end of the output module 60 of the present application is connected to the output end of the control module 40 via the switch module 50. When the switch module 50 is closed, the output module 60 uses the first voltage V1 as the third voltage V3 of the input end of the output module 60 and the second voltage V2 as the fourth voltage V4 of the input end of the output module 60; and obtains the first delay control voltage V according to the third voltage V3 and the fourth voltage V4. tc1 ; This process is actually based on the first injection clock signal V inj1 The phase difference information of the intermediate clock signal CLK generates a first delay control voltage V tc1 .

[0085] In some embodiments, the switch module 50 includes a first switch and a second switch, wherein the first end of the first switch is connected to the output end of the first group of current sources 41, and the second end of the first switch is connected to the first input end of the output module; the first end of the second switch is connected to the output end of the second group of current sources 42, and the second end of the second switch is connected to the second input end of the output module.

[0086] In some embodiments, the output module includes a fifth current source I5 and a sixth current source I6, the control end of the fifth current source I5 is the first input end of the output module, and is used to control the fifth current source I5 according to the third voltage V3; the control end of the sixth current source I6 is the second input end of the output module, and is used to control the sixth current source I6 according to the fourth voltage V4; the positive pole of the fifth current source I5 is connected to the power supply, the negative pole of the fifth current source I5 is connected to the positive pole of the sixth current source I6, and the negative pole of the sixth current source I6 is grounded.

[0087] Specifically, when the first injected clock signal V inj1 When the first injection clock signal V inj1 is switched low and the first injected clock signal V inj1 When the edge of the intermediate clock signal CLKN is aligned, the switch module 50 is switched to an off state, so that the injection-locked phase-locked loop clock system is locked to the third voltage V3 and the fourth voltage V4 being the same.

[0088] The specific working process of the first timing calibrator is as follows: Figure 6As shown, the intermediate clock signal CLKN first passes through a two-way frequency divider to obtain a frequency division signal clk1, then passes through a buffer to output a positive frequency division signal, and passes through a buffer with a built-in inverter to output an inverted frequency division signal. The positive frequency division signal and the inverted frequency division signal simultaneously control the first group of current sources and the second group of current sources. When the intermediate clock signal is an odd cycle, the first group of current sources are controlled to output a first voltage V1 that is a linearly rising triangular wave; when the intermediate clock signal is an even cycle, the first group of current sources are controlled to output a second voltage V2 that is a linearly falling triangular wave; the first voltage V1 and the second voltage V2 are completely opposite triangular waves. If the first injected clock signal V inj1 The clock edge of the intermediate clock signal CLKN is aligned, that is, the first injected clock signal V inj1 The falling edge of the intermediate clock signal CLKN must be the falling edge of the intermediate clock signal CLKN. inj1 As the sampling clock, the obtained third voltage V3 must be at the midpoint sample of the first voltage V1 and the second voltage V2. Since the first voltage V1 and the second voltage V2 are a set of triangle waves that are symmetrical up and down, the voltages of the midpoint sample of the first voltage V1 and the second voltage V2 must be the same. Therefore, the upper and lower currents of the fifth current source I5 and the sixth current source I6 controlled by the obtained third voltage V3 and the fourth voltage V4 are also the same. Then the first delay control voltage V tc1 It will not change at this moment, and this is the first time the clock signal V is injected. inj1 The moment when the intermediate clock signal CLKN is aligned with the edge of the intermediate clock signal CLKN. inj1 , sample the first injected clock signal V inj1 The obtained third voltage V3 must be less than the fourth voltage V4; then the first delay control voltage will be reduced by the current draw, and the delay of the first adjustable delay module will increase, so that the output intermediate clock signal will increase the delay appropriately, thereby compensating for the advanced phase difference; if the intermediate clock signal CLKN lags behind the first injected clock signal V inj1 , sample the first injected clock signal V inj1 The obtained third voltage V3 must be greater than the fourth voltage V4; then the first delay control voltage will be increased by the injection current, and the delay of the first adjustable delay module will be reduced, so that the output intermediate clock signal will appropriately reduce the delay, thereby compensating for the advanced phase difference.

[0089] The structure and principle of the second timing calibrator are the same as those of the first timing calibrator, except that the input of the frequency division module in the second timing calibrator is connected to the intermediate clock signal CLKN, and the switch module is connected to the second injected clock signal.

[0090] The present application cascades the first injection-locked phase-locked loop clock circuit and the second injection-locked phase-locked loop clock circuit, and while ensuring that the injection phase-locked loop has the advantage of low phase noise, it can also achieve a higher frequency division ratio to meet most application scenarios, and compared with the prior art, in order to solve the problem of injection-locked phase-locked loop self-calibration, a complex digital circuit is introduced for calibration, resulting in a complex phase-locked loop system. The present application only needs to use a simple timing self-calibrator to align the timing, that is, self-calibrate the injected clock signal and the working output clock, thereby reducing the complexity of the circuit. Therefore, the injection-locked phase-locked loop system of the present application not only achieves low jitter and high-frequency clock effects well, can meet the needs of common frequency multiplication scenarios, but also maintains low power consumption and low area requirements.

[0091] The present application also provides an electronic chip. Exemplarily, the electronic chip includes the above-mentioned injection-locked phase-locked loop clock system, and the output clock signal of the injection-locked phase-locked loop clock system generates a stable clock signal for the electronic chip.

[0092] It can be understood that the clock circuit of this embodiment corresponds to the injection-locked phase-locked loop clock system of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described repeatedly here.

[0093] In several embodiments provided in the present application, it should be understood that the disclosed system can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0094] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0095] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application.

[0096] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. An injection locked phase locked loop clock system, characterized in that: include: A first phase-locked loop circuit and a second phase-locked loop circuit connected in cascade; The first phase-locked loop circuit includes a first signal pulse generator, a first phase-locked loop main loop and a first timing self-calibrator; The first signal pulse generator is used to process the input reference clock signal to obtain a first injection clock signal; the first timing self-calibrator is used to perform timing processing on the first injection clock signal and the intermediate clock signal to obtain a first delay control voltage; The first phase-locked loop main loop is used for processing the reference clock signal and the first injected clock signal to obtain the intermediate clock signal under the action of the first delay control voltage; The second phase-locked loop circuit includes a second signal pulse generator, a second phase-locked loop main loop and a second timing self-calibrator; the second signal pulse generator is used to process the intermediate clock signal output by the first phase-locked loop main loop to obtain a second injection clock signal; the second timing self-calibrator is used to perform timing processing on the second injection clock signal and the output clock signal to obtain a second delay control voltage; the second phase-locked loop main loop is used to process the reference clock signal and the second injection clock signal under the action of the second delay control voltage to obtain the output clock signal.

2. The injection-locked phase-locked loop clock system according to claim 1, characterized in that: The first timing self-calibrator and the second timing self-calibrator have the same structure; The first timing self-calibrator includes a frequency division module, a control module, a switch module and an output module; The input of the frequency division module is connected to the intermediate clock signal, and the frequency division module is used to perform frequency division processing on the intermediate clock signal to obtain a positive phase frequency division signal and a negative phase frequency division signal; The input of the control module is connected to the output end of the frequency division module, and the control module is used to receive the positive phase frequency division signal and the negative phase frequency division signal, and perform control according to the positive phase frequency division signal and the negative phase frequency division signal to output a first voltage and a second voltage; The input end of the output module is connected to the output end of the control module via the switch module. When the switch module is closed, the first voltage and the second voltage are used as the third voltage and the fourth voltage input to the output module respectively, and the first delay control voltage is obtained according to the third voltage and the fourth voltage.

3. The injection-locked phase-locked loop clock system according to claim 2, characterized in that: When the first injection clock signal is at a high level, the switch module is in a closed state, so that the third voltage changes with the first voltage, and the fourth voltage changes with the second voltage; When the first injection clock is at a low level and the edges of the first injection clock signal and the intermediate clock signal are aligned, the switch module is switched to an off state so that the injection-locked phase-locked loop clock system is locked to the third voltage being the same as the fourth voltage.

4. The injection-locked phase-locked loop clock system according to claim 2, characterized in that: The frequency division module includes a two-frequency divider, a first buffer and a second buffer; The clock input end of the frequency divider is connected to the intermediate clock signal, and the data input end of the frequency divider is connected to the second output end of the frequency divider; the frequency divider is used to perform frequency division processing on the intermediate clock signal to obtain a frequency division signal; The input end of the first buffer is connected to the first output end of the binary frequency divider, and the first buffer is used to buffer the frequency-divided signal to obtain a positive-phase frequency-divided signal; The input end of the second buffer is connected to the first output end of the binary frequency divider. The second buffer has a built-in inverter. The second buffer is used to perform inverting buffering on the frequency-divided signal to obtain an inverted frequency-divided signal.

5. The injection-locked phase-locked loop clock system according to claim 4, characterized in that: The control module includes a first group of current sources and a second group of current sources; The input end of the first group of current sources is connected to the output end of the first buffer and the output end of the second buffer, and the first group of current sources is used to obtain the first voltage according to the positive phase frequency division signal and the negative phase frequency division signal; The input end of the second current source group is connected to the output end of the first buffer and the output end of the second buffer, and the second current source group is used to obtain the second voltage according to the positive phase frequency division signal and the negative phase frequency division signal; The second voltage is opposite to the first voltage in direction.

6. The injection-locked phase-locked loop clock system according to claim 1, characterized in that: The first phase-locked loop main loop is specifically used for: Under the action of the first delay control voltage, delay processing is performed on the reference clock signal to obtain a first delayed reference clock; The intermediate clock signal is obtained according to the first delayed reference clock, the first injected clock signal and the first frequency-divided clock signal of the first phase-locked loop main loop.

7. The injection-locked phase-locked loop clock system according to claim 6, characterized in that: The first phase-locked loop main loop includes a first adjustable delay module, a first phase frequency detector / charge pump, a first voltage-controlled oscillator and a first frequency divider; The first adjustable delay module is connected to the reference clock signal and the first delay control voltage, and the first adjustable delay module is used to delay the reference clock signal under the action of the first delay control voltage to obtain a first delayed reference clock; The input end of the first phase frequency detector / charge pump is connected to the output end of the first adjustable delay module and the output end of the first frequency divider; the first phase frequency detector / charge pump is used to process the phase difference between the first delay reference clock and the first frequency-divided clock signal output by the first frequency divider to obtain a first control voltage; The input end of the first voltage-controlled oscillator is connected to the output end of the first phase frequency detector / charge pump, and the output end of the first voltage-controlled oscillator is connected to the input end of the first phase frequency detector / charge pump via the first frequency divider; the first voltage-controlled oscillator is used to process the first control voltage and the first injected clock signal to obtain the intermediate clock signal.

8. The injection-locked phase-locked loop clock system according to claim 1, characterized in that: The second phase-locked loop main loop is specifically used for: Under the action of the second delay control voltage, the reference clock signal is delayed and controlled to obtain a second delayed reference clock; The output clock signal is obtained according to the second delayed reference clock, the second injected clock signal and the second frequency-divided clock signal of the second phase-locked loop main loop.

9. The injection-locked phase-locked loop clock system according to claim 8, characterized in that: The second phase-locked loop main loop includes a second adjustable delay module, a second phase frequency detector / charge pump, a second voltage-controlled oscillator and a second frequency divider; The second adjustable delay module is connected to the intermediate clock signal and the second delay control voltage. Under the action of the second delay control voltage, the second adjustable delay module performs delay processing on the intermediate clock signal to obtain a second delayed reference clock; The input end of the second phase frequency detector / charge pump is connected to the output end of the second adjustable delay module and the output end of the second frequency divider; the second phase frequency detector / charge pump is used to process the phase difference between the second delayed reference clock and the second frequency-divided clock signal output by the second frequency divider to obtain a second control voltage; The input end of the second voltage-controlled oscillator is connected to the output end of the second phase frequency detector / charge pump, and the output end of the second voltage-controlled oscillator is connected to the input end of the second phase frequency detector / charge pump via the second frequency divider; the second voltage-controlled oscillator is used to obtain the output clock signal according to the second control voltage and the second injection clock signal.

10. An electronic chip, characterized in that: The electronic chip comprises a clock circuit, and the clock circuit is an injection-locked phase-locked loop clock system according to any one of claims 1-9.

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