Passive adder circuit applied to Sigma-Delta modulator

Abstract

The invention discloses a passive adder circuit applied to a Sigma-Delta modulator, and relates to the technical field of integrated circuits, the passive adder circuit comprises a switched capacitor circuit, a pre-amplification circuit and a comparator circuit, the switched capacitor circuit is used for summing multiple paths of signals; the pre-amplification circuit is used for amplifying the signal output by the adder; the comparator circuit completes a comparison function of an input signal and a reference voltage and realizes quantification; according to the passive adder circuit applied to the Sigma-Delta modulator, multi-path summation of input signals is achieved through the novel passive adder circuit, the problems of circuit complexity and large power consumption of a traditional passive adder are solved, the passive adder has the advantages of being simple in structure and low in power consumption, and the passive adder circuit can be applied to the Sigma-Delta modulator. And the performance of the Sigma-Delta modulator circuit is improved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to a passive adder circuit applied to a Sigma-Delta modulator. Background Art

[0002] Sigma-Delta modulator is the core part of an analog-to-digital converter commonly used in the fields of communications, audio processing, medical and power amplifiers. Its core principle is to use oversampling and noise shaping technology to convert analog signals into digital signals. Compared with traditional Nyquist modulators, Sigma-Delta modulators have higher resolution, better anti-interference ability and lower power consumption, so they have gradually become the first choice for analog-to-digital converters used in digital signal processing systems.

[0003] The passive adder is an important component of the Sigma-Delta modulator circuit. It is used to sum the analog signals from different channels, and perform corresponding weighted processing and signal synthesis on the signals. The passive adder is a passive circuit. Its design needs to consider the accuracy of signal summation, power consumption, and anti-interference ability, so as to ensure that the input signal can be accurately processed and the output result can be output. In the Sigma-Delta modulator, the performance of the passive adder will directly affect the signal shaping effect of the entire modulator, and then affect the signal transmission quality. The passive adder uses the resistor and capacitor network in the circuit to sum the signal, which has certain defects. The resistor and capacitor will introduce additional power consumption and noise, causing signal distortion and system performance degradation. In addition, the complex circuit structure and the difficulty of adjusting parameters limit the improvement of system performance and the expansion of application scope. Therefore, a passive adder circuit for Sigma-Delta modulator is proposed. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a passive adder circuit applied to a Sigma-Delta modulator, which solves the problems raised in the above background technology.

[0005] To achieve the above object, the present invention is implemented through the following technical scheme: a passive adder circuit applied to a Sigma-Delta modulator, comprising a switched capacitor circuit, a large prevention circuit and a comparator circuit, wherein the switched capacitor circuit is used to sum multiple signals; the large prevention circuit is used to amplify the signal output by the adder; the comparator circuit performs the comparison function between the input signal and the reference voltage to achieve quantization; The switch capacitor circuit includes switches: S1, S2, S3, S4, S5, S6; capacitors: C1, C2, C3; input ports: Vin1n, Vin2n, Vin3n; reference voltage Vcm, reference voltage Vthn, and one end of the switch S1 is connected to the input port Vin1n.

[0006] Optionally, the other end of the switch S1 is connected to the left end of the capacitor C1, one end of the switch S2 is connected to the input port Vin2n, and the other end of the switch S2 is connected to the left end of the capacitor C2; one end of the switch S3 is connected to the input port Vin3n, and the other end of the switch S3 is connected to the left end of the capacitor C3; one end of the switch S7 is connected to the left end of the capacitor C1, and the other end of the switch S7 is connected to the reference voltage Vcm; one end of the switch S8 is connected to the left end of the capacitor C2, and the other end of the switch S8 is connected to the reference voltage Vcm; one end of the switch S9 is connected to the left end of the capacitor C3, and the other end of the switch S9 is connected to the reference voltage Vthn.

[0007] Optionally, the large prevention circuit includes MOS tubes M1, M2, M3, M4, M5, and M6, one end of the MOS tube M1 is connected to the MOS tube M4, one end of the MOS tube M4 is connected to the MOS tube M3, the other end of the MOS tube M1 is connected to the MOS tube M2, one end of the MOS tube M0 is connected to the MOS tube M1 and the MOS tube M2, one end of the MOS tube M2 is connected to the MOS tube M5, one end of the MOS tube M5 is connected to the MOS tube M6, and one end of the capacitor C1 is connected to the MOS tube M1.

[0008] Optionally, the comparator circuit includes MOS tubes: M7, M8, M9, M10, M11, M12, M13, M14, M15, M16 and an SR latch, one end of the MOS tube M7 is connected to the MOS tube M8, one end of the MOS tube M8 is connected to the MOS tube M9 and the MOS tube M10, one end of the MOS tube M9 is connected to the MOS tube M11, one end of the MOS tube M10 is connected to the MOS tube M12, one end of the MOS tube M11 is connected to the MOS tube M15 and the MOS tube M16, one end of the MOS tube M12 is connected to the MOS tube M13 and the MOS tube M14, the other end of the MOS tube M7 is connected to Vbn1, and the SR latch is connected to the MOS tube M13, the MOS tube M14, the MOS tube M15 and the MOS tube M16.

[0009] Optionally, the working process of the passive adder is that the output of the passive adder is input into the comparator through the pre-amplification circuit, and the result finally generated by the comparator is latched by the SR latch.

[0010] Optionally, the result obtained by the passive adder is output to a large prevention circuit, and the large prevention circuit adopts a differential operational amplifier structure with a cross-coupling structure as a load.

[0011] Optionally, the large output of the prevention is used as the input of the comparator. The comparator adopts the StrongARM structure. The cross-coupled pair composed of M11, M12, M14 and M15 can respond quickly to the current changes of Ids9 and Ids10. Finally, the cross-coupled circuit makes S connected to the SR latch high and R low, or the opposite result.

[0012] The present invention provides a passive adder circuit applied to a Sigma-Delta modulator, which has the following beneficial effects: The passive adder circuit applied to the Sigma-Delta modulator realizes multi-path summation of input signals through the novel passive adder circuit proposed by the present invention, solves the problems of circuit complexity and high power consumption of the traditional passive adder, and the passive adder proposed by the present invention has the advantages of simple structure and low power consumption, thereby improving the performance of the Sigma-Delta modulator circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The passive adder and comparator circuit diagram of the present invention; Figure 2 This is the p2 phase equivalent circuit diagram of the present invention; Figure 3 This is the equivalent circuit diagram of phase p1 of the present invention; Figure 4 This is a test waveform diagram of the present invention. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0015] See also Figures 1 to 4 The present invention provides a technical solution: a passive adder circuit applied to a Sigma-Delta modulator, comprising a switched capacitor circuit, a large prevention circuit and a comparator circuit, wherein the switched capacitor circuit is used to sum multiple signals; the large prevention circuit is used to amplify the signal output by the adder; the comparator circuit completes the comparison function between the input signal and the reference voltage to realize quantization; The switch capacitor circuit includes switches: S1, S2, S3, S4, S5, S6; capacitors: C1, C2, C3; input ports: Vin1n, Vin2n, Vin3n; reference voltage Vcm, reference voltage Vthn, one end of switch S1 is connected to the input port Vin1n, and the other end of switch S1 is connected to the left end of capacitor C1, one end of switch S2 is connected to the input port Vin2n, and the other end of switch S2 is connected to the left end of capacitor C2; one end of switch S3 is connected to the input port Vin3n, and the other end of switch S3 is connected to the left end of capacitor C3; one end of switch S7 is connected to the left end of capacitor C1, and the other end of switch S7 is connected to the reference voltage Vcm; one end of switch S8 is connected to the left end of capacitor C2, and the other end of switch S8 is connected to the reference voltage Vcm; one end of switch S9 is connected to the left end of capacitor C3, and the other end of switch S9 is connected to the reference voltage Vthn.

[0016] Among them, the prevention circuit includes MOS tubes M1, M2, M3, M4, M5, and M6. One end of the MOS tube M1 is connected to the MOS tube M4, one end of the MOS tube M4 is connected to the MOS tube M3, the other end of the MOS tube M1 is connected to the MOS tube M2, one end of the MOS tube M0 is connected to the MOS tube M1 and the MOS tube M2, one end of the MOS tube M2 is connected to the MOS tube M5, one end of the MOS tube M5 is connected to the MOS tube M6, and one end of the capacitor C1 is connected to the MOS tube M1.

[0017] Wherein, the comparator circuit includes MOS tubes: M7, M8, M9, M10, M11, M12, M13, M14, M15, M16 and an SR latch, one end of the MOS tube M7 is connected to the MOS tube M8, one end of the MOS tube M8 is connected to the MOS tube M9 and the MOS tube M10, one end of the MOS tube M9 is connected to the MOS tube M11, one end of the MOS tube M10 is connected to the MOS tube M12, one end of the MOS tube M11 is connected to the MOS tube M15 and the MOS tube M16, one end of the MOS tube M12 is connected to the MOS tube M13 and the MOS tube M14, the other end of the MOS tube M7 is connected to Vbn1, and the SR latch is connected to the MOS tube M13, the MOS tube M14, the MOS tube M15 and the MOS tube M16.

[0018] The working process of the passive adder is that the output of the passive adder is input into the comparator through the pre-amplification circuit, and the result finally generated by the comparator is latched by the SR latch.

[0019] Among them, the result obtained by the passive adder is output to the prevention large circuit. The prevention large circuit adopts a differential operational amplifier structure with a cross-coupling structure as the load. The cross-coupling of M3~M6 tubes can quickly establish the prevention large output.

[0020] Among them, the large output is used as the input of the comparator. The comparator adopts the StrongARM structure. The cross-coupled pair composed of M11, M12, M14 and M15 can respond quickly to the current changes of Ids9 and Ids10. Finally, the cross-coupled circuit makes S connected to the SR latch high and R low, or the opposite result.

[0021] The specific circuit implementation is as follows Figure 1 As shown, the left dotted box is a passive adder circuit, which is used to sum the input signal. The specific working steps are as follows: p1 and p2 are generated by two non-overlapping clock circuits. When the p2 phase is high, switches S7, S8, S9, S10, S11, and S12 are closed, and switches S1, S2, S3, S4, S5, and S6 are open. The charges on capacitors C1, C2, and C3 are controlled by the reference level. The phase equivalent circuit is shown in the figure below. Figure 2 When the p1 phase is at a low level, switches S1, S2, S3, S4, S5, and S6 are closed, and switches S7, S8, S9, S10, S11, and S12 are open. The equivalent circuit of this phase is shown in Figure 3 As shown. According to the values ​​of input signals Vin1n, Vin1p, Vin2n, Vin2p, Vin3n, Vin3p and capacitors C1, C2, C3, the law of charge conservation can be used to derive: (1) (2) Subtracting the above two equations, we can get: (3) in, The first three items are to sum the input signals, realizing the passive adder summing function, and the last item is to make a difference with the reference level, so as to realize the comparison function with the reference level.

[0022] Circuit simulation experiment: Circuit simulation results are as follows Figure 4 As shown, the capacitance ratio in this circuit is C1:C2:C3=1:2:1. Vin1n, Vin1p, Vin2n, Vin2p are connected to the common mode signal Vcm, Vin3p and Vin3n are connected to the DC level of 1.3V and 1.1V respectively, and the comparison starts when EN1 rises. The above theory derives: (4) from Figure 4 It can be seen that the simulation results are consistent with the theoretical results.

[0023] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A passive adder circuit for Sigma-Delta modulator, characterized in that: It includes a switched capacitor circuit, a prevention circuit and a comparator circuit. The switched capacitor circuit is used to sum multiple signals; the prevention circuit is used to amplify the signal output by the adder; the comparator circuit completes the comparison function between the input signal and the reference voltage to achieve quantization; The switch capacitor circuit includes switches: S1, S2, S3, S4, S5, S6; capacitors: C1, C2, C3; input ports: Vin1n, Vin2n, Vin3n; reference voltage Vcm, reference voltage Vthn, and one end of the switch S1 is connected to the input port Vin1n.

2. A passive adder circuit for Sigma-Delta modulator according to claim 1, characterized in that: The other end of the switch S1 is connected to the left end of the capacitor C1, one end of the switch S2 is connected to the input port Vin2n, and the other end of the switch S2 is connected to the left end of the capacitor C2; one end of the switch S3 is connected to the input port Vin3n, and the other end of the switch S3 is connected to the left end of the capacitor C3; one end of the switch S7 is connected to the left end of the capacitor C1, and the other end of the switch S7 is connected to the reference voltage Vcm; one end of the switch S8 is connected to the left end of the capacitor C2, and the other end of the switch S8 is connected to the reference voltage Vcm; one end of the switch S9 is connected to the left end of the capacitor C3, and the other end of the switch S9 is connected to the reference voltage Vthn.

3. A passive adder circuit for Sigma-Delta modulator according to claim 1, characterized in that: The prevention circuit includes MOS tubes M1, M2, M3, M4, M5, and M6. One end of the MOS tube M1 is connected to the MOS tube M4, one end of the MOS tube M4 is connected to the MOS tube M3, the other end of the MOS tube M1 is connected to the MOS tube M2, one end of the MOS tube M0 is connected to the MOS tube M1 and the MOS tube M2, one end of the MOS tube M2 is connected to the MOS tube M5, one end of the MOS tube M5 is connected to the MOS tube M6, and one end of the capacitor C1 is connected to the MOS tube M1.

4. A passive adder circuit for Sigma-Delta modulator according to claim 1, characterized in that: The comparator circuit includes MOS tubes: M7, M8, M9, M10, M11, M12, M13, M14, M15, M16 and an SR latch, one end of the MOS tube M7 is connected to the MOS tube M8, one end of the MOS tube M8 is connected to the MOS tube M9 and the MOS tube M10, one end of the MOS tube M9 is connected to the MOS tube M11, one end of the MOS tube M10 is connected to the MOS tube M12, one end of the MOS tube M11 is connected to the MOS tube M15 and the MOS tube M16, one end of the MOS tube M12 is connected to the MOS tube M13 and the MOS tube M14, the other end of the MOS tube M7 is connected to Vbn1, and the SR latch is connected to the MOS tube M13, the MOS tube M14, the MOS tube M15 and the MOS tube M16.

5. A passive adder circuit for Sigma-Delta modulator according to claim 1, characterized in that: The working process of the passive adder is that the output of the passive adder is input into the comparator through the pre-amplification circuit, and the result finally generated by the comparator is latched by the SR latch.

6. A passive adder circuit for Sigma-Delta modulator according to claim 1, characterized in that: The result obtained by the passive adder is output to a large prevention circuit, which uses a differential operational amplifier structure with a cross-coupling structure as a load.

7. The passive adder circuit for Sigma-Delta modulator according to claim 1, characterized in that: The output of the pre-amplifier is used as the input of the comparator. The comparator adopts the StrongARM structure. The cross-coupled pair composed of M11, M12, M14 and M15 can respond quickly to the current changes of Ids9 and Ids10. Finally, the cross-coupled circuit makes S connected to the SR latch high and R low, or the opposite result.

Images