Dual-redundancy FC data link IP core

Abstract

The invention discloses a dual-redundancy FC (Fiber Channel) data link IP (Internet Protocol) core, which comprises an FC sending framing engine, an FC dual-redundancy interface and an FC receiving dual-redundancy transmission engine, the FC sending framing engine is used for receiving the FC data message transmitted by the DMA module and converting the FC data message into a standard FC frame following an FC protocol; the FC dual-redundancy interface is used for sending or receiving an FC frame by adopting an active-active full-symmetric data competition dual-redundancy mode, and the FC dual-redundancy interface is compatible with a non-dual-redundancy mode and a main / standby switching dual-redundancy mode at the same time; and the FC receiving dual-redundancy transmission engine is used for considering the condition that a plurality of FC sequences are received at the same time, and selecting DMA transmission or discarding for the FC frame after redundancy judgment. According to the dual-redundancy FC data link IP core provided by the invention, an active-active holosymmetric data competition dual-redundancy strategy is adopted, redundancy processing is carried out in a receiving node, the redundancy time is only the time difference of transmission of two same FC frames, and compared with other dual-redundancy strategies, higher performance is obtained through consumption of hardware logic resources.

Description

Technical Field

[0001] The invention belongs to the field of network technology and FPGA technology, and specifically relates to a dual-redundancy FC data link IP core. Background Art

[0002] FC (Fibre Channel, FC for short) protocol is a high-speed serial communication protocol proposed by the American National Standards Institute in 1988. It can realize long-distance, high-bandwidth, low-latency data transmission, provide a complete error handling and flow control mechanism, have a flexible topology, support SCSI, IPv4 and other upper layer protocols, and is mainly used in high-performance network storage and avionics communication fields. FC protocol is similar to Ethernet protocol, both adopt a layered structure, including physical layer (FC-0), coding layer (FC-1), protocol layer (FC-2), service layer (FC-3) and mapping layer (FC-4), among which FC-2 layer is the most complex layer, which mainly stipulates the rules of data transmission in FC network system. Most FC network systems offload the functions of FC-2 layer to hardware, and use the high concurrency and low latency characteristics of FPGA to complete the conversion between other protocol data and standard FC frames, greatly improving the conversion efficiency and reducing the CPU load.

[0003] With the continuous development of technology, the transmission rate of FC network systems currently used in the market has been continuously improved from the initial 1.0625Gbps to 2.125Gbps, 4.25Gbps, 8.5Gbps, and 16Gbps. The latest FC protocol standard supports a maximum transmission rate of 256Gbps. In high-speed digital systems, data transmission can easily become unstable due to slight interference. In order to build a high-speed and reliable network, a dual redundant structure is a solution. However, the existing dual redundant structure has poor performance. Summary of the invention

[0004] The present invention provides a dual redundant FC data link IP core to solve the above mentioned technical problems, and specifically adopts the following technical solutions:

[0005] A dual-redundant FC data link IP core, comprising: an FC sending framing engine, an FC dual-redundant interface, and an FC receiving dual-redundant transmission engine;

[0006] The FC transmission framing engine is used to receive the FC data message transmitted by the DMA module and convert the FC data message into a standard FC frame that complies with the FC protocol;

[0007] The FC dual redundant interface is used to send or receive FC frames in a dual-active fully symmetric data competition dual redundant mode, and the FC dual redundant interface is compatible with both a non-dual redundant mode and an active-standby switching dual redundant mode;

[0008] The FC receiving dual redundant transmission engine is used to consider the situation where multiple FC sequences are received simultaneously, and select DMA transmission or discard of FC frames after performing redundancy judgment.

[0009] Furthermore, the FC sending framing engine comprises: a fragmentation module, a framing module and a verification module;

[0010] The fragmentation module is used to extract the frame start delimiter and header of the FC data message and write them into the header FIFO, and to fragment the payload and write them into the payload FIFO, while using a frame information FIFO to record the information required for framing each payload fragment;

[0011] The framing module reads the frame start delimiter and header from the header FIFO and temporarily stores them in the register, modifies part of the header information according to different payload slices, and writes them into the frame data FIFO after splicing with the payload slices read from the payload FIFO;

[0012] The check module replaces the 4-byte payload following the header of the non-start frame, and adds a cyclic redundancy check code and a frame termination delimiter at the end of the FC frame to complete the transmission of the standard FC frame.

[0013] Furthermore, the slicing module slices the payload into 2048-byte units and writes them into the payload FIFO; the information required for framing each payload slice includes the payload length, data message type flag, start frame flag, end frame flag and short frame flag.

[0014] Furthermore, the framing module uses two state machines to work together when framing, the main state machine is responsible for the transmission of the header, payload and information, and the sub-state machine is responsible for the reading, temporary storage and updating of the header.

[0015] Further, the FC dual redundant interface includes an FC sending dual redundant interface and an FC receiving dual redundant interface;

[0016] The FC sending dual redundant interface duplicates the FC frame in dual-active fully symmetric data competition dual redundant mode and sends it to two FC nodes, sends the FC frame only from FC node 1 in non-dual redundant mode, and can selectively send the FC frame from FC node 1 or FC node 2 in active-standby switching dual redundant mode;

[0017] The FC receiving dual redundant interface is used to alternately receive FC frames from two FC nodes and merge them into one channel without judging the specific content of the FC frame, allowing the two channels of FC frames to be different from each other, or there to be only one channel of FC frame.

[0018] Furthermore, the FC sending dual redundant interface uses the first software register mode_sel to perform mode selection.

[0019] Furthermore, the FC sending dual redundant interface controls sending FC frames from FC node 1 or FC node 2 through the second software register port_sel in the active / standby switching dual redundant mode.

[0020] Furthermore, the FC receiving dual redundant transmission engine considers the situation of receiving multiple FC sequences simultaneously, uses a sequence management BRAM to record the transmission status of each FC sequence, performs redundancy judgment based on the information provided by the sequence management BRAM, selects to transmit or discard the current FC frame, and updates the information in time for the redundancy judgment of subsequent FC frames.

[0021] Furthermore, the FC receiving dual redundant transmission engine performs hash calculation on the S_ID and SEQ_ID of each FC sequence to obtain a unique identification flow_id as the address of the sequence management BRAM.

[0022] Furthermore, the sequence management BRAM includes a frame check correct flag, a frame existence flag, a sequence existence flag, a timeout flag, a start frame valid flag, an end frame valid flag, a total number of frames to be transmitted, and a total number of frames currently received.

[0023] The benefit of the present invention lies in that the dual-redundant FC data link IP core provided adds a dual-redundant structure to the design of the FC-2 layer data link to improve the reliability of data transmission, and adopts a dual-active fully symmetric data competition dual-redundant strategy to perform redundant processing inside the receiving node. The redundant time is only the time difference between the transmissions of two identical FC frames. Compared with other dual-redundant strategies, higher performance is obtained through the consumption of hardware logic resources.

[0024] The present invention is also beneficial in that the dual redundant FC data link IP core provided offloads the function of converting protocol data and standard FC frames to hardware, reduces the number of DMA read and write times and the occupancy of storage space, and utilizes the high concurrency and low latency characteristics of FPGA to greatly improve the conversion efficiency, reduce the CPU load, and help to give full play to the high-speed transmission performance of the FC network.

[0025] The invention is also beneficial in that the provided dual-redundant FC data link IP core not only supports dual-redundant data transmission, but can also be switched to a non-dual-redundant transmission mode simply by setting a software register, and has strong versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0027] Figure 1 It is a schematic diagram of the hardware system structure of the dual-redundant FC data link IP core of the present invention;

[0028] Figure 2 It is a schematic diagram of the structure of the FC sending framing engine of the dual redundant FC data link IP core of the present invention;

[0029] Figure 3 It is a schematic diagram of the slicing of the slicing module of the dual-redundant FC data link IP core of the present invention;

[0030] Figure 4 It is a schematic diagram of the framing situation of the framing module of the dual-redundant FC data link IP core of the present invention;

[0031] Figure 5 It is a schematic diagram of the verification process of the verification module of the dual-redundant FC data link IP core of the present invention;

[0032] Figure 6 It is a schematic diagram of the FC node sending state of the dual redundant FC data link IP core of the present invention;

[0033] Figure 7 It is a schematic diagram of the FC dual redundant interface structure of the dual redundant FC data link IP core of the present invention;

[0034] Figure 8 It is a schematic diagram of the content definition of the sequence management BRAM unit of the dual redundant FC data link IP core of the present invention;

[0035] Fig. 9 It is a schematic diagram of the FC node frame reception situation of the dual redundant FC data link IP core of the present invention. DETAILED DESCRIPTION

[0036] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0037] The "FC data message" described in this application refers to a group of non-standardized data consisting of a frame start delimiter (SOF, 4 bytes), a header (24 bytes for ELS message, 40 bytes for ASM message), a payload, a cyclic redundancy check code (CRC, 4 bytes) and a frame end delimiter (EOF, 4 bytes), with a total length of 4 bytes aligned.

[0038] The "FC frame" described in this application is an FC data message with a payload length not exceeding 2048 bytes and data content that complies with the standard FC protocol.

[0039] The "FC sequence" described in this application refers to a set consisting of all FC frames with the same S_ID and SEQ_ID.

[0040] The "dual redundancy" described in this application refers to the active-active fully symmetric data competition dual redundancy strategy unless otherwise specified.

[0041] It should be noted that the dual-redundant FC data link IP core of the present application uses a 64-bit wide data bus.

[0042] Figure 1 The figure shows a hardware structure diagram of a dual-redundant FC data link IP core of the present application. The dual-redundant FC data link IP core complies with the standard FC protocol, takes the FC frame as the basic unit of data transmission, connects the DMA module on one side, interacts with the upper-layer software and memory, and connects the FC node on the other side, interacts with other devices in the FC network. The dual-redundant FC data link IP core includes: an FC sending framing engine, an FC dual-redundant interface, and an FC receiving dual-redundant transmission engine. Specifically, the FC sending framing engine is used to receive FC data messages transmitted by the DMA module, and convert the FC data messages into standard FC frames that comply with the FC protocol. The FC dual-redundant interface is used to send or receive FC frames in a dual-active fully symmetric data competition dual-redundant mode. The FC dual-redundant interface is compatible with both non-dual-redundant mode and active-standby switching dual-redundant mode. The FC receiving dual-redundant transmission engine is used to consider the situation where multiple FC sequences are received at the same time, and select DMA transmission or discard of the FC frame after redundancy judgment.

[0043] like Figure 2 As shown, as a preferred implementation, the FC sending framing engine includes: a fragmentation module, a framing module and a checking module.

[0044] Among them, the fragmentation module is used to extract the frame start delimiter and header of the FC data message and write them into the header FIFO, and to fragment the payload and write them into the payload FIFO, while using a frame information FIFO to record the information required for framing each payload fragment. The framing module reads the frame start delimiter and header from the header FIFO and temporarily stores them in the register, modifies part of the header information according to different payload fragments, and writes them into the frame data FIFO after splicing with the payload fragments read out from the payload FIFO. The check module replaces the 4-byte payload following the header of the non-start frame, and adds a cyclic redundancy check code and a frame end delimiter at the end of the FC frame to complete the transmission of the standard FC frame. As a preferred embodiment, the fragmentation module fragments the payload in units of 2048 bytes and writes them into the payload FIFO.

[0045] Specifically, if Figure 3 As shown in the figure, the fragmentation module extracts the SOF and header of the FC data message and writes them into the header FIFO. Since the data width is 64 bits, the 4-byte payload following the header will be written into the header FIFO together, and the remaining payload will be written into the payload FIFO in fragments of 2048 bytes each. The length of the last payload fragment may be less than 2048 bytes. Figure 3 a is the case where the total length of the FC data message is aligned to 8 bytes, and CRC and EOF are all discarded. Figure 3 b is the case where the total length of the FC data message is aligned to 4 bytes. The CRC will be written into the payload FIFO together with the last payload fragment. When this payload fragment is used later, the last 4 bytes of data need to be ignored.

[0046] After the fragmentation module obtains the separated header and payload, the subsequent framing module needs to reassemble the FC frame. Therefore, in addition to the header FIFO and payload FIFO, a frame information FIFO is also needed to record the information required for each payload fragment framing, including payload length, data message type flag, start frame flag, end frame flag and short frame flag (the payload fragment length is 0, and the payload FIFO is not written).

[0047] like Figure 4 As shown in the figure, only one header is reserved for each FC data message during fragmentation, and this header needs to be used when each payload fragment is framed, so it needs to be temporarily stored in the register after being read from the header FIFO. The headers of different payload fragments are slightly different, such as SOFi3 is used for the start frame, SOFn is used for non-start frames, F_CTRL of the end frame should be set to 1, and SEQ_CNT of each frame should be incremented.

[0048] Two state machines are used to work together when framing. The main state machine is responsible for the transmission of headers, payloads, and information. The sub-state machine is responsible for reading, temporarily storing, and updating headers. The sub-state machine reads and temporarily stores a header when the header FIFO is not empty. The main state machine then reads the frame information FIFO and initiates a handshake. The sub-state machine updates the header and passes it to the main state machine in turn. The main state machine writes the header to the frame data FIFO. After the header is passed, the sub-state machine ends the handshake. The main state machine continues to read the payload from the payload FIFO and write it to the frame data FIFO. The sub-state machine performs different operations based on the end frame flag. If the flag is valid, it returns to the initial state to prepare to read the next header, otherwise it waits for the main state machine to initiate a handshake again.

[0049] The framing module outputs a non-standard FC frame consisting of a SOF, a header, and a payload of up to 2052 bytes. The maximum payload length is 2052 bytes because in the previous fragmentation process, in addition to the 2048-byte fragmentation payload, there is also a 4-byte payload following the header. The check module is responsible for processing the extra 4-byte payload and adding CRC and EOF, and outputting a standard FC frame.

[0050] Figure 5 This is a schematic diagram of the verification flow of the verification module of the dual-redundant FC data link IP core of this application. For a non-end frame of an FC sequence, the upper 4 bytes are written into a register when the last beat of the payload is transmitted. When the next frame is transmitted, the 4-byte payload in the register is used to replace the 4-byte payload following the header, thereby ensuring that the 4-byte payload will not be transmitted repeatedly, and the payload length of the non-end frame is 2048 bytes. At the same time, CRC and EOF are spliced ​​after the last beat of the payload. When no verification is required, CRC is 0. EOFn is used for the EOF of the non-end frame, and EOFt is used for the EOF of the end frame. It should be noted that the number of valid bits of the last beat of data of the FC frame with a total length of 8 bytes aligned and the FC frame with a total length of 4 bytes aligned is different, and two valid signals are used to distinguish them. 2'b11 means 8 bytes are valid, and 2'b01 means 4 bytes are valid.

[0051] As a preferred implementation, the FC dual redundant interface includes a FC sending dual redundant interface and a FC receiving dual redundant interface.

[0052] The FC sending dual redundant interface copies the FC frame in duplicate and sends it to two FC nodes in the active-active fully symmetric data competition dual redundant mode. In the non-dual redundant mode, FC frames are sent only from FC node 1. In the active-standby switching dual redundant mode, FC frames can be sent selectively from FC node 1 or FC node 2.

[0053] Specifically, the FC sending dual redundant interface copies all FC frames in duplicate and sends them to FC node 1 and FC node 2 respectively, according to the different sending states that may appear when the FC frames arrive at the two FC nodes. Figure 6 As shown in the figure, the processing methods are as follows:

[0054] 1. Both FC nodes are in a normal state, as shown in Figure 6 Figure a. After the FC frame is written into the pre-transmission data FIFO, it is directly read out and transmitted to the two FC nodes.

[0055] 2. There is a cache problem with FC node 2. After the Tfifo_full time, the pre-transmission data FIFO is filled. After another T1 time, FC node 2 returns to normal, and the timeout threshold Ttime_out > T1, as shown in Figure 6 Figure b. After the pre-transmission data FIFO is filled, timing starts and the FC transmission framing engine is back-pressured. Before the timeout, FC node 2 returns to normal, and the pre-transmission data FIFO will be gradually emptied. At this time, stopping the back-pressure will return to the first case.

[0056] 3. There is a cache problem with FC node 1. After the Tfifo_full time, the pre-transmission data FIFO is filled. After another T2 time, FC node 1 returns to normal, and the timeout threshold Ttime_out < T2, as shown in Figure 6 Figure c. After the pre-transmission data FIFO is filled, timing starts and the FC transmission framing engine is back-pressured. After the timeout, FC node 1 still cannot transmit. At this time, the back-pressure will be stopped, and only FC node 2 will transmit until FC node 1 returns to normal.

[0057] 4. There are cache problems with both FC nodes, as shown in Figure 6 Figure d. In this case, directly back-pressure until a certain FC node returns to normal.

[0058] The FC transmission dual-redundancy interface of the dual-redundancy FC data link IP core of the present application is compatible with the non-dual-redundancy mode and the primary-backup switching dual-redundancy mode, and is controlled by the software register mode_sel. When the value of mode_sel is 2'b00, the non-dual-redundancy mode is used, and the FC frame is only sent from FC node 1. When the value of mode_sel is 2'b01, the primary-backup switching dual-redundancy mode is used, and the software register port_sel is used to control whether to send the FC frame from FC node 1 or FC node 2. When the value of mode_sel is 2'b10, the dual-active fully symmetric data competition dual-redundancy mode is used.

[0059] The FC reception dual-redundancy interface is used to alternately receive the FC frames of the two FC nodes and merge them into one path, without judging the specific content of the FC frames, allowing the two paths of FC frames to be not completely the same, or only one path of FC frames.

[0060] The FC receiving dual redundant interface receives FC frames from two FC nodes and merges them into one channel. The two FC frames are written into the pre-send data FIFO_1 and the pre-send data FIFO_2 respectively. When FIFO_1 is not empty and FIFO_2 is empty, one frame is read from FIFO_1. When FIFO_2 is not empty and FIFO_1 is empty, one frame is read from FIFO_2. When both FIFOs are not empty, one frame is read from FIFO_1 first and then from FIFO_2. This ensures that the FC frame is the basic unit of data transmission and the two FC frames are transmitted alternately.

[0061] The FC receiving dual redundant interface of the dual redundant FC data link IP core of the present application is compatible with non-dual redundant mode and active-standby switching dual redundant mode. For these two modes, even if the two FC frames mentioned above are not completely the same, or there is only one FC frame, they can be received according to the same principle.

[0062] Due to the similarity between the FC sending dual redundant interface and the FC receiving dual redundant interface, they are integrated into the same module during hardware design. Figure 7 shown.

[0063] As a preferred implementation, the FC receiving dual redundant transmission engine considers the situation of receiving multiple FC sequences simultaneously, and uses a sequence management BRAM to record the transmission status of each FC sequence. The unit content of the BRAM is defined as follows: Figure 8 As shown. The FC receiving dual redundant transmission engine performs hash calculation on the S_ID and SEQ_ID of each FC sequence to obtain a unique identification flow_id as the address of the sequence management BRAM. Redundancy judgment is performed based on the information provided by the sequence management BRAM, and the current FC frame is selected for transmission or discarding, and the information is updated in time for the redundancy judgment of subsequent FC frames.

[0064] for Fig. 9 , frames 1 to N do not necessarily belong to the same FC sequence. When they belong to different FC sequences, they only need to be processed by opening another BRAM storage unit. For the convenience of description, it is assumed that these frames belong to the same FC sequence. At the same time, considering the disorder of FC frames within the same FC sequence, the definition of frame i is the FC frame with SEQ_CNT i-1, rather than the i-th FC frame that arrives. Therefore, frame 1 is the starting frame and frame N is the ending frame. For two identical FC frames, (1) means the first arrival and (2) means the second arrival.

[0065] like Fig. 9 As shown in the figure, according to the different frame reception conditions of the two FC nodes, the FC receiving dual redundant transmission engine processes the frame as follows:

[0066] 1. Two FC nodes transmit FC frames alternately and the CRC check is correct, such as Fig. 9As shown in a. First, frame 1 (1) is received, the sequence management BRAM is accessed, and frame_exist_mk[0] is read as invalid, indicating that the FC frame is received for the first time and the CRC check is correct. Frame_exist_mk[0] and frame_right_mk[0] are set, and the FC frame is transmitted. Then frame 1 (2) is received, the sequence management BRAM is accessed, and frame_exist_mk[0] and frame_right_mk[0] are read as valid, indicating that the FC frame is received for the second time and the first reception is normal. The FC frame is discarded, and frame_exist_mk[0] and frame_right_mk[0] are cleared. For the subsequent FC frames, since no abnormality occurs, frame i (1) is transmitted and frame i (2) is discarded. Regarding the use of other unit contents in the sequence management BRAM, seq_exist_mk is set to 1 when the first FC frame in the sequence is received, first_seq_valid is set to 1 when frame No. 1 (1) is received, last_seq_valid is set to 1 when frame No. N (1) is received, total_frame_cnt is assigned to its SEQ_CNT+1 when frame No. N (1) is received, and cur_frame_cnt is increased by 1 for each received frame. When cur_frame_cnt is twice total_frame_cnt, all unit contents are cleared, indicating that the dual redundant transmission of an FC sequence is completed.

[0067] 2. FC node 2 is delayed and the FC sequence is out of order, e.g. Fig. 9 b. For the first six FC frames, the value of frame_exist_mk[2:0] is updated as follows: 3'b000 (initial value) → 3'b001 (transmit frame 1 (1)) → 3'b101 (transmit frame 3 (1)) → 3'b001 (discard frame 3 (2)) → 3'b011 (transmit frame 2 (1)) → 3'b010 (discard frame 1 (2)) → 3'b000 (discard frame 2 (2)). For the subsequent FC frames, the processing method is the same as case 1.

[0068] 3. The CRC check of frame 3 of FC node 1 is wrong, such as Fig. 9 c. When receiving frame 3 (1), the CRC check fails, frame_exist_mk[2] is set, and the FC frame is discarded. When receiving frame 3 (2), frame_exist_mk[2] is read as valid and frame_right_mk[2] is invalid, indicating that the FC frame is received for the second time and the first reception is abnormal. No check is required and the FC frame is transmitted directly.

[0069] 4. Frame 3 of FC node 1 is lost. Fig. 9d. Because of frame loss, cur_frame_cnt will not accumulate to twice total_frame_cnt. If no processing is done, the BRAM address will be occupied all the time, and problems will occur when receiving non-redundant FC sequences with the same flow_id. Therefore, the FC receiving dual redundant transmission engine is equipped with a timeout mechanism. The core of timeout management is a timer and a timeout BRAM. The value of the timer is increased by 1 in each clock cycle. The timeout BRAM uses flow_id as the write address to store the arrival time of the last frame that has arrived in each FC sequence. The read address of the timeout BRAM is increased by 1 in each clock cycle, and the output of the timeout BRAM is compared with the value of the current timer to calculate the difference. If it exceeds the set threshold time, it is determined to be a timeout. After the timeout is triggered, the time_out_mk bit of the corresponding address in the sequence management BRAM is set, indicating that the storage unit at this address can continue to be used.

[0070] 5. FC node 1 is abnormal, and the system works with a single link, such as Fig. 9 When the system works in a single link, there is no redundant data transmission, which is equivalent to the loss of all frames (2) of number i. The processing method is the same as that of case 4.

[0071] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solution obtained by equivalent replacement or equivalent transformation falls within the protection scope of the present invention.

Claims

1. A dual redundant FC data link IP core, characterized in that: Contains: FC send framing engine, FC dual redundant interface and FC receive dual redundant transmission engine; The FC transmission framing engine is used to receive the FC data message transmitted by the DMA module and convert the FC data message into a standard FC frame that complies with the FC protocol; The FC dual redundant interface is used to send or receive FC frames in a dual-active fully symmetric data competition dual redundant mode, and the FC dual redundant interface is compatible with both a non-dual redundant mode and an active-standby switching dual redundant mode; The FC receiving dual redundant transmission engine is used to consider the situation where multiple FC sequences are received simultaneously, and select DMA transmission or discard of FC frames after performing redundancy judgment.

2. The dual redundant FC data link IP core according to claim 1, characterized in that: The FC sending framing engine comprises: a fragmentation module, a framing module and a verification module; The fragmentation module is used to extract the frame start delimiter and header of the FC data message and write them into the header FIFO, and to fragment the payload and write them into the payload FIFO, while using a frame information FIFO to record the information required for framing each payload fragment; The framing module reads the frame start delimiter and header from the header FIFO and temporarily stores them in the register, modifies part of the header information according to different payload slices, and writes them into the frame data FIFO after splicing with the payload slices read from the payload FIFO; The check module replaces the 4-byte payload following the header of the non-start frame, and adds a cyclic redundancy check code and a frame termination delimiter at the end of the FC frame to complete the transmission of the standard FC frame.

3. The dual redundant FC data link IP core according to claim 2, characterized in that: The slicing module slices the payload into 2048-byte units and writes them into the payload FIFO; The information required for framing each payload fragment includes payload length, data message type flag, start frame flag, end frame flag, and short frame flag.

4. The dual redundant FC data link IP core according to claim 2, characterized in that: The framing module uses two state machines to work together when framing. The main state machine is responsible for the transmission of the header, payload and information, and the sub-state machine is responsible for the reading, temporary storage and updating of the header.

5. The dual redundant FC data link IP core according to claim 1, characterized in that: The FC dual redundant interface comprises an FC sending dual redundant interface and an FC receiving dual redundant interface; The FC sending dual redundant interface duplicates the FC frame in dual-active fully symmetric data competition dual redundant mode and sends it to two FC nodes, sends the FC frame only from FC node 1 in non-dual redundant mode, and can selectively send the FC frame from FC node 1 or FC node 2 in active-standby switching dual redundant mode; The FC receiving dual redundant interface is used to alternately receive FC frames from two FC nodes and merge them into one channel without judging the specific content of the FC frame, allowing the two channels of FC frames to be different from each other, or there to be only one channel of FC frame.

6. The dual redundant FC data link IP core according to claim 5, characterized in that: The FC sending dual redundant interface uses the first software register mode_sel to perform mode selection.

7. The dual redundant FC data link IP core according to claim 5, characterized in that: The FC sending dual redundant interface controls sending FC frames from FC node 1 or FC node 2 through the second software register port_sel in the active / standby switching dual redundant mode.

8. The dual redundant FC data link IP core according to claim 1, characterized in that: The FC receiving dual redundant transmission engine considers the situation of receiving multiple FC sequences simultaneously, uses a sequence management BRAM to record the transmission status of each FC sequence, performs redundancy judgment based on the information provided by the sequence management BRAM, selects to transmit or discard the current FC frame, and updates the information in time for the redundancy judgment of subsequent FC frames.

9. The dual redundant FC data link IP core according to claim 8, characterized in that: The FC receiving dual redundant transmission engine performs hash calculation on the S_ID and SEQ_ID of each FC sequence to obtain a unique identification flow_id as the address of the sequence management BRAM.

10. The dual redundant FC data link IP core according to claim 9, characterized in that: The sequence management BRAM includes a frame check correct flag, a frame existence flag, a sequence existence flag, a timeout flag, a start frame valid flag, an end frame valid flag, a total number of frames to be transmitted, and a total number of frames currently received.

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