Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a storage region and a logic region; the memory gate structures are located on the memory region, are separated from each other and exist in pairs, first openings are formed between the memory gate structures in pairs, and each memory gate structure comprises a floating gate located on the substrate, a control gate dielectric layer located on the floating gate and a control gate located on the control gate dielectric layer; the first opening exposes at least part of the side wall surface of the floating gate; the ion doping region is located in the floating gate, and the first opening is exposed out of the ion doping region; the tunneling dielectric layer is positioned on the surface of the floating gate and the surface of the control gate exposed by the first opening; and the gate oxide layer is positioned on the surface of the logic region. According to the semiconductor structure and the forming method thereof, the influence of an oxidation process of a logic operation device on a flash memory device is reduced, the structural defects are reduced, and the performance stability of the flash memory device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Embedded flash memory (flash) is a non-volatile memory widely used in the automotive, consumer and other fields. With the rapid increase in market demand for new energy vehicles in recent years, the demand for chip storage and processing performance and cost has also increased rapidly. At the same time, the demand for high-voltage devices has also increased. Therefore, various microcontroller and flash memory integration design solutions have emerged. Various research institutions focus on the layout and development of flash memory and BCD (Bipolar, CMOS, DMOS) process compatible process platforms, integrating memory, power devices and logic operation devices on the same wafer.

[0003] In the prior art, in order to maintain the reliability of the performance of the logic operation device, it is usually chosen to first form the device structure of the flash memory area, and then carry out the process preparation of the logic operation device. In the process of forming the logic operation device, due to the existence of a long oxidation process, the structure of the flash memory device is inevitably affected, so that it introduces structural defects due to excessive oxidation, resulting in the erasure efficiency of the flash memory being affected and the device performance being reduced. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which reduces the influence of the oxidation process of the logic operation device on the flash memory device, reduces structural defects, and improves the performance stability of the flash memory device.

[0005] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate including a storage area and a logic area; separate and paired storage gate structures located on the storage area, a first opening is provided between the paired storage gate structures, each storage gate structure includes a floating gate located on the substrate, a control gate dielectric layer located on the floating gate and a control gate located on the control gate dielectric layer, the first opening exposes at least a portion of the side wall surface of the floating gate; an ion-doped region located in the floating gate, the first opening exposes the ion-doped region; a tunneling dielectric layer located on the floating gate surface and the control gate surface exposed by the first opening; and a gate oxide layer located on the surface of the logic area.

[0006] Optionally, the floating gate has a floating gate protrusion protruding from a side wall of the control gate exposed by the first opening, the ion-doped region is located in the floating gate protrusion, and the ion-doped region is exposed on a surface of the floating gate protrusion.

[0007] Optionally, the doping ions in the ion-doped region include nitrogen ions.

[0008] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a storage area and a logic area; forming a floating gate material layer on the surface of the substrate; forming initial storage gate structures that are separate and exist in pairs on the surface of the floating gate material layer on the storage area, wherein an initial first opening is provided between the paired initial storage gate structures, the initial first opening exposing the top surface of the floating gate material layer, each initial storage gate structure comprising a control gate dielectric layer located on the floating gate material layer and a control gate located on the control gate dielectric layer; performing ion doping on the exposed floating gate material layer to form an initial ion doping region in the floating gate material layer; and performing ion doping on the exposed floating gate material layer to form an initial ion doping region in the floating gate material layer. After the ion doping treatment, the floating gate material layer is etched to form separate and paired storage gate structures on the storage area, with a first opening between the paired storage gate structures, each storage gate structure comprising a floating gate located on the substrate, a control gate dielectric layer located on the floating gate, and a control gate located on the control gate dielectric layer, the first opening exposing at least a portion of the sidewall surface of the floating gate, the floating gate having an ion doping region, the first opening exposing the ion doping region; a tunneling dielectric layer is formed on the floating gate surface and the control gate surface exposed by the first opening; after the storage gate structure is formed, an oxidation process is used to form a gate oxide layer on the surface of the logic area.

[0009] Optionally, the floating gate has a floating gate protrusion protruding from a side wall of the control gate exposed by the first opening, the ion-doped region is located in the floating gate protrusion, and the ion-doped region is exposed on a surface of the floating gate protrusion.

[0010] Optionally, the doping ions in the ion-doped region include nitrogen ions.

[0011] Optionally, the process of performing ion doping treatment on the floating gate material layer includes an ion implantation process, a microwave plasma treatment process or an annealing process.

[0012] Optionally, the parameters of the ion implantation process include: an ion implantation energy of 0 to 50 keV; an ion implantation dose of 1E12 ions / cm 2 ~1E16 ions / cm 2 .

[0013] Optionally, the gas used in the annealing process includes nitric oxide or nitrogen dioxide.

[0014] Optionally, there is a floating gate dielectric layer between the floating gate material layer and the substrate; the control gate sidewall and the control gate dielectric layer sidewall surface also have a sidewall structure; the sidewall structure is formed after forming the control gate dielectric layer and the control gate, and the sidewall structure is formed before etching the floating gate material layer.

[0015] Optionally, the sidewall structure includes a first sidewall and a second sidewall, the first sidewall is located on the sidewalls on both sides of the control gate and the sidewall surfaces on both sides of the control gate dielectric layer, and the second sidewall is located on the first sidewall surface of the control gate sidewall and the control gate dielectric layer sidewall surface exposed by the first opening.

[0016] Optionally, the method for forming the sidewall structure, the ion-doped region and the floating gate includes: forming a sidewall structure on the control gate sidewall and the control gate dielectric layer sidewall surface; using the sidewall structure as a mask, etching the floating gate material layer until the floating gate dielectric layer surface is exposed, thereby forming a floating gate and an ion-doped region within the floating gate, the floating gate having a floating gate protrusion protruding from the control gate sidewall exposed by the first opening.

[0017] Optionally, the method for forming the initial storage gate structure includes: forming a control gate dielectric material layer and a control gate material layer on the floating gate material layer; forming a mask layer on the control gate material layer, the mask layer exposing a portion of the surface of the control gate material layer on the storage area; using the mask layer as a mask, etching the control gate material layer and the control gate dielectric material layer until the surface of the floating gate material layer is exposed to form a control gate and a control gate dielectric layer.

[0018] Optionally, after forming the floating gate and the ion-doped region, a gate oxide layer is formed on the surface of the logic region.

[0019] Optionally, the method further includes: after forming the tunnel dielectric layer, forming an erase gate in the first opening.

[0020] Optionally, the method further includes: forming a gate on the gate oxide layer.

[0021] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0022] In the semiconductor structure provided by the technical solution of the present invention, the first opening exposes the ion-doped region in the floating gate. By selecting suitable doping ions, the doped ions can be bonded with the ions in the floating gate to form a stronger chemical bond, which is not easy to break. Therefore, the existence of the ion-doped region prevents the diffusion of oxygen atoms introduced in subsequent processes in the floating gate, reduces the morphological defects caused by oxidation of the floating gate surface, and thus improves the stability of the memory erase efficiency.

[0023] In the method for forming a semiconductor structure provided by the technical solution of the present invention, before forming a gate oxide layer, an ion-doped region is first formed in the floating gate exposed by the first opening. By selecting suitable doping ions, the doped ions can be bonded with the ions in the floating gate to form a stronger chemical bond, which is not easy to break. Therefore, in the subsequent process of forming a gate oxide layer in the logic area, the existence of the ion-doped region prevents the diffusion of oxygen atoms introduced in the subsequent process in the floating gate, reduces the morphological defects caused by oxidation of the floating gate surface, and thus improves the stability of the memory erase efficiency.

[0024] Furthermore, by performing ion doping on the floating gate material layer through an ion implantation process, the thickness of the ion doped region can be controlled by means of the energy and dose of the ion implantation, thereby adjusting the protective effect of the ion doped region on the floating gate according to design requirements, and the process is more controllable. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 and Figure 2 is a cross-sectional schematic diagram of a method for forming a semiconductor structure;

[0026] Figures 3 to 12 It is a schematic cross-sectional structural diagram of a formation process of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] As described in the background technology, in order to integrate memory, power devices and logic operation devices on the same wafer, it is necessary to use a process platform that is compatible with the memory process and the BCD process. In the prior art, in order to maintain the reliability of the performance of the logic operation device, it is usually chosen to first form the device structure of the storage area, and then perform the process preparation of the logic operation device. In the process of forming the logic operation device, due to the long oxidation process, the structure of the memory device is inevitably affected, so that it introduces structural defects due to excessive oxidation, resulting in the erasure efficiency of the memory being affected, and the device performance is reduced.

[0028] Figure 1 and Figure 2 The invention is a cross-sectional schematic diagram of a method for forming a semiconductor structure.

[0029] Please refer to Figure 1, providing a substrate 100, the substrate 100 comprising a storage area I and a logic area II; forming two separate storage gate structures (not shown) in the storage area II, with a first opening (not shown) between the two storage gate structures, each storage gate structure comprising a floating gate dielectric layer 101, a floating gate 103, a control gate dielectric layer 113 and a control gate 120 located on the control gate dielectric layer 113, the control gate 120 comprising a first sidewall and a second sidewall opposite to each other, the first sidewall facing the first opening 140, the floating gate 103 having a floating gate protrusion protruding relative to the first sidewall (such as Figure 1 A tunnel dielectric layer 126 is deposited on the surface of the floating gate 103 and the first sidewall surface exposed by the first opening 140 .

[0030] Please refer to Figure 2 , a gate oxide layer 102 is formed in the logic region II.

[0031] In the process of forming the gate oxide layer 102, it is inevitable to affect the device structure already formed on the storage area I, especially the floating gate protrusion (such as Figure 2 The corners formed by the top and sidewall surfaces are more easily over-oxidized under the action of the oxidation process, thereby rounding the corners and introducing structural defects, resulting in reduced erase efficiency of the memory.

[0032] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, wherein, in the formation method, an ion-doped region is first formed in the floating gate exposed by the first opening, and by selecting suitable doping ions, the doped ions can be bonded with the ions in the floating gate to form a stronger chemical bond, which is not easy to break. Therefore, in the subsequent process of forming a gate oxide layer in the logic area, the presence of the ion-doped region prevents the diffusion of oxygen atoms introduced in the subsequent process in the floating gate, reduces the morphological defects caused by oxidation of the floating gate surface, and thus improves the stability of the memory erase efficiency.

[0033] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figures 3 to 12 It is a schematic cross-sectional structural diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0035] Please refer to Figure 3 , a substrate 200 is provided, wherein the substrate 200 includes a storage area I and a logic area II.

[0036] In this embodiment, the storage area I provides a platform for a flash memory device formed subsequently, and the logic area II provides a platform for a logic device formed subsequently.

[0037] The material of the substrate 200 includes silicon, silicon germanium, silicon carbide, silicon on insulator (SOI), germanium on insulator (GOI), etc. Specifically, in this embodiment, the material of the substrate 200 is silicon.

[0038] Please refer to Figure 4 , a floating gate dielectric layer 201 is formed on the storage area I and the logic area II.

[0039] In this embodiment, the material of the floating gate dielectric layer 201 includes silicon oxide.

[0040] Please refer to Figure 5 , a floating gate material layer 203 is formed on the floating gate dielectric layer 201; initial storage gate structures (not shown) that are separate and exist in pairs are formed on the surface of the floating gate material layer 203 on the storage area I, and an initial first opening 223 is provided between the paired initial storage gate structures, and the initial first opening exposes the top surface of the floating gate material layer 203, and each initial storage gate structure includes a control gate dielectric layer 213 located on the floating gate material layer 203 and a control gate 220 located on the control gate dielectric layer 213.

[0041] It should be noted that, in the present embodiment, at least one pair of initial storage gate structures is formed on the storage region I, and the initial storage gate structures existing in pairs include two initial storage gate structures.

[0042] For ease of understanding, in this embodiment, a pair of initial storage gate structures is formed in the storage area I, that is, two initial storage gate structures are formed in the storage area I. In other embodiments, multiple pairs of initial storage gate structures may be formed in the storage area, and the number of pairs of the initial storage gate structures is greater than or equal to 2.

[0043] In this embodiment, the initial first opening 223 exposes the sidewall of the control gate 220 , the sidewall of the control gate dielectric layer 213 , and the surface of the floating gate material layer 203 .

[0044] In this embodiment, the floating gate material layer 203 provides raw materials for a floating gate formed subsequently.

[0045] In this embodiment, the floating gate material layer 203 is made of polysilicon.

[0046] In this embodiment, the initial first opening 223 provides space for an erase gate to be formed subsequently.

[0047] In this embodiment, the method for forming the control gate dielectric layer 213 and the control gate 220 includes: forming a control gate dielectric material layer (not shown) and a control gate material layer (not shown) on the floating gate material layer 203; forming a mask layer 225 on the control gate material layer, the mask layer 225 exposing a portion of the control gate material layer surface on the storage area I; using the mask layer 225 as a mask, etching the control gate material layer and the control gate dielectric material layer until the surface of the floating gate material layer 203 is exposed to form the control gate 220 and the control gate dielectric layer 213.

[0048] In this embodiment, the material of the control gate 220 includes polysilicon.

[0049] In this embodiment, the control gate dielectric layer 213 includes: a first silicon oxide layer 210 located on the floating gate material layer 203 , a silicon nitride layer 211 located on the surface of the first silicon oxide layer 210 , and a second silicon oxide layer 212 located on the surface of the silicon nitride layer 211 .

[0050] Next, a first spacer 221 is formed on the sidewalls of the control gate 220 and the sidewalls of the control gate dielectric layer 213. The first spacer 221 is located on the sidewalls of the control gate 220 and the sidewalls of the control gate dielectric layer 213.

[0051] Please refer to Figure 6 , performing ion doping treatment on the exposed floating gate material layer 203 to form an initial ion doping region 209 in the floating gate material layer 203 .

[0052] In this embodiment, the ions are doped using the initial storage gate structure as a mask, so the ion doping region 226 is located in other regions of the floating gate material layer 203 except the region covered by the initial storage gate structure.

[0053] In this embodiment, the process of performing ion doping on the floating gate material layer 203 includes an ion implantation process. The doping ions in the initial ion doping region 209 include nitrogen ions, and the nitrogen in the initial ion doping region 209 can form a stronger silicon-nitrogen chemical bond with the silicon in the floating gate material layer 203, and the chemical bond is not easily broken, thereby preventing the diffusion of oxygen atoms introduced in subsequent processes.

[0054] In other embodiments, the doping ions in the initial ion doping region may also be carbon, sulfur, and other particles that can form strong chemical bonds with silicon.

[0055] In this embodiment, the floating gate material layer 203 is ion doped by an ion implantation process, and the thickness of the subsequently formed ion doped region can be controlled by means of the energy and dose of the ion implantation, thereby regulating the protection effect of the ion doped region on the subsequently formed floating gate according to design requirements, and the process is more controllable.

[0056] Specifically, in this embodiment, the parameters of the ion implantation process include: the energy of the ion implantation is 0-50 keV; the ion implantation dose is 1E12 ions / cm 2 ~1E16 ions / cm 2 .

[0057] In another embodiment, the process of performing ion doping treatment on the floating gate material layer includes a microwave plasma treatment process.

[0058] In another embodiment, the process of performing ion doping on the floating gate material layer includes an annealing process, wherein the gas used in the annealing process includes nitrogen monoxide or nitrogen dioxide.

[0059] Please refer to Figure 7 A second sidewall spacer 222 is formed on the surface of the first sidewall spacer 221 on the sidewalls of both sides of the control gate 220 and the sidewalls of both sides of the control gate dielectric layer 213 .

[0060] The material of the second sidewall spacer 222 includes silicon oxide.

[0061] In this embodiment, the second spacer 222 is used to adjust the morphology of the subsequently formed floating gate 204. The second spacer 222 is located on the surface of the initial ion doping region 209 in the floating gate material layer 203.

[0062] Please refer to Figure 8 A mask structure 205 is formed on the surface of the initial storage gate structure and the initial ion doping area 209, and the mask structure 205 exposes part of the surface of the initial ion doping area 209 on both sides of the initial storage gate structure; using the mask structure 205 as a mask, ion implantation is performed on the storage area I, thereby forming word line doping areas (not shown) in the storage area I on both sides of the initial storage gate structure.

[0063] Please refer to Fig. 9 , remove the pair of second side walls 222 farthest from each other on the side wall surface of the initial storage gate structure, and the remaining second side walls 222 are located on the side walls of the control gate 220 exposed by the initial first opening 223 and the surface of the first side wall 221 on the side wall surface of the control gate dielectric layer 213.

[0064] After removing the pair of second side walls 222 that are farthest apart, the first side walls 221 and the remaining second side walls 222 together form a side wall structure (not marked).

[0065] Since the sidewalls of the control gate 220 and the sidewall surfaces of the control gate dielectric layer 213 exposed by the initial first opening 223 have the first sidewall 221 and the second sidewall 222, and the sidewall surfaces on the other side of the control gate 220 and the control gate dielectric layer 213 only have the first sidewall 221, the thickness of the sidewall structure of the sidewalls of the control gate 220 and the sidewall surfaces of the control gate dielectric layer 213 exposed by the initial first opening 223 is greater than the thickness of the sidewall structure of the sidewall surface on the other side of the control gate 220 and the control gate dielectric layer 213.

[0066] In another embodiment, it is not necessary to remove the pair of second side walls farthest from each other on the side wall surface of the initial storage gate structure, and the thickness of the side wall structure of the control gate side wall and the side wall surface of the control gate dielectric layer exposed by the initial first opening is equal to the thickness of the side wall structure of the control gate and the side wall surface on the other side of the control gate dielectric layer.

[0067] Please refer to Fig.10 , using the sidewall structure as a mask, the floating gate material layer 203 is etched until the surface of the floating gate dielectric layer 201 is exposed, thereby forming a floating gate 204 and an ion-doped region 226 in the floating gate 204 .

[0068] After etching the floating gate material layer 203, separate and paired storage gate structures (not shown) are formed on the storage area I, and a first opening 228 is provided between the paired storage gate structures. Each storage gate structure includes a floating gate 204 located on the substrate 200, a control gate dielectric layer 213 located on the floating gate 204, and a control gate 220 located on the control gate dielectric layer 213. The first opening 228 exposes at least a portion of the side wall surface of the floating gate 204. The floating gate 204 has an ion-doped region 226, and the first opening exposes the ion-doped region 226.

[0069] In this embodiment, after etching the floating gate material layer 203, the formed floating gate 204 has a floating gate protrusion B protruding from the side wall of the control gate 220 exposed by the first opening 228. The floating gate 204 also has a second floating gate protrusion located on the other side, and the second floating gate protrusion is below the first sidewall 221 on the sidewall surface of the control gate 220 and the control gate dielectric layer 213 on the other side. Since the thickness of the sidewall structure of the sidewall of the control gate 220 and the sidewall surface of the control gate dielectric layer 213 exposed by the initial first opening 223 is greater than the thickness of the sidewall structure of the sidewall surface of the control gate 220 and the control gate dielectric layer 213 on the other side, and the thickness of the sidewall structure determines the size of the floating gate protrusion, after forming the floating gate 204, the size of the floating gate protrusion B exposed by the first opening 228 is greater than the size of the second floating gate protrusion on the other side of the storage gate structure. The size is the size of the floating gate protrusion in the direction parallel to the surface of the substrate 200.

[0070] Among them, since the floating gate protrusion B exposed by the first opening 228 is larger in size, after the erase gate is subsequently formed in the first opening 228, during the erase operation of the erase gate, the electric field at the protruding corner of the floating gate protrusion B is more concentrated, which is beneficial for the electrons in the floating gate 204 to tunnel into the erase gate through the floating gate protrusion B, thereby obtaining a higher erasing efficiency and improving the performance of the device and the yield of the chip.

[0071] In this embodiment, the ion-doped region 226 is located in the floating gate protrusion B exposed by the first opening 228, the ion-doped region 226 is exposed on the surface of the floating gate protrusion B, and the ion-doped region 226 covers the protrusion angle formed by the top and sidewall surfaces of the floating gate protrusion B. The nitrogen in the ion-doped region 226 is bonded with the silicon in the floating gate 204 to form a stronger silicon-nitrogen chemical bond, which is not easy to break. Therefore, the existence of the ion-doped region 226 prevents the diffusion of oxygen atoms introduced in the subsequent process in the floating gate 204, reduces the morphological defects caused by the oxidation of the floating gate protrusion B, and thus improves the stability of the memory erase efficiency.

[0072] In addition, the ion doped region 226 is only located in the floating gate protrusion B exposed by the first opening 229 , and does not affect other device structures of the storage gate structure, thereby maintaining device stability.

[0073] Specifically, the sidewall surface of the floating gate protrusion B is perpendicular to the surface of the substrate 200 ; and the top surface of the floating gate protrusion B is parallel to the surface of the substrate 200 .

[0074] Please refer to Fig.11A tunneling dielectric layer 230 is formed on the surface of the floating gate 204 , the surface of the ion-doped region 226 , the surface of the control gate 220 , and the surface of the control gate dielectric layer 213 exposed by the first opening 228 .

[0075] In this embodiment, the material of the tunnel dielectric layer 230 includes silicon oxide.

[0076] In this embodiment, the thickness of the tunnel dielectric layer 230 is in the range of 80 angstroms to 130 angstroms.

[0077] In this embodiment, the tunneling dielectric layer 230 is also located on the sidewall of the storage gate structure away from the first opening 228 ; the tunneling dielectric layer 230 is also located on the surface of the floating gate dielectric layer 201 .

[0078] Please refer to Fig.12 , remove the floating gate dielectric layer 201 and the tunnel dielectric layer 230 on the surface of the logic region II; and use an oxidation process to form a gate oxide layer 250 on the surface of the logic region II.

[0079] In this embodiment, the gate oxide layer 250 is used in a high voltage MOS device.

[0080] Specifically, the method for forming the gate oxide layer 250 includes: one of a thermal oxidation process and a diffusion process or a combination of the two. A relatively thick gate oxide layer 250 can be formed by a relatively long thermal oxidation process or a diffusion process, thereby ensuring that it can meet the gate voltage requirements of the high-voltage MOS device.

[0081] In the process of forming the gate oxide layer 250 using an oxidation process, the ion-doped region 226 is located in the floating gate protrusion B exposed by the first opening 228, and covers the protrusion angle formed by the top and side wall surfaces of the floating gate protrusion B. Since the nitrogen in the ion-doped region 226 bonds with the silicon in the floating gate 204 to form a stronger silicon-nitrogen chemical bond, which is not easy to break, the existence of the ion-doped region 226 prevents the diffusion of oxygen atoms introduced during the oxidation process in the floating gate 204, reduces the morphological defects caused by the oxidation of the floating gate protrusion B, and thus improves the stability of the memory erase efficiency.

[0082] In addition, in the process of adjusting the parameters of the oxidation process, it is only necessary to focus on the morphology and thickness of the gate oxide layer 250 on the logic area II to adjust the parameters of the oxidation process without considering its impact on the device structure that has been formed in the storage area I. This makes the process window larger and the effect and efficiency of process control higher.

[0083] Next, an erase gate (not shown) is formed in the first opening 228; a gate (not shown) and a source and drain (not shown) located in the logic area II on both sides of the gate are formed on the gate oxide layer 250, so that the storage area I and the logic area II can perform corresponding device functions.

[0084] In this embodiment, the device structure formed on the storage area I is suitable for a Nor Flash device.

[0085] In this embodiment, the method for forming the device structure on the storage area I and the device structure on the logic area II is applicable to technology platform nodes including 28nm, 40nm, 55nm and 70nm.

[0086] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by adopting the above method.

[0087] Please continue to refer to Fig.12 The semiconductor structure includes: a substrate 200, wherein the substrate 200 includes a storage area I and a logic area II; separate and paired storage gate structures located on the storage area I, wherein a first opening 288 is provided between the paired storage gate structures, wherein each storage gate structure includes a floating gate 204 located on the substrate 200, a control gate dielectric layer 213 located on the floating gate 204, and a control gate 220 located on the control gate dielectric layer 213, wherein the first opening 228 exposes at least a portion of the sidewall surface of the floating gate 204; an ion-doped area 226 located in the floating gate 204, wherein the first opening 228 exposes the ion-doped area 226; a tunneling dielectric layer 230 located on the surface of the floating gate 204 and the surface of the control gate 220 exposed by the first opening 228; and a gate oxide layer 250 located on the surface of the logic area II.

[0088] In this embodiment, the floating gate 204 has a floating gate protrusion B protruding from the sidewall of the control gate 220 exposed by the first opening 228 . The ion doped region 226 is located in the floating gate protrusion B, and the surface of the floating gate protrusion B exposes the ion doped region 226 .

[0089] Among them, the first opening 228 exposes the ion-doped region 226 in the floating gate 204. By selecting suitable doping ions, the doped ions can be bonded with the ions in the floating gate 204 to form a stronger chemical bond, and the chemical bond is not easy to break. Therefore, the existence of the ion-doped region 226 prevents the diffusion of oxygen atoms introduced in the oxidation process of forming the gate oxide layer 250 in the floating gate 204, reduces the morphological defects caused by oxidation on the surface of the floating gate 204, and thus improves the stability of the memory erase efficiency.

[0090] In this embodiment, the doping ions in the ion doping region 226 include nitrogen ions.

[0091] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a storage area and a logic area; Separate and paired memory gate structures located on the memory area, with a first opening between the paired memory gate structures, each memory gate structure comprising a floating gate located on a substrate, a control gate dielectric layer located on the floating gate, and a control gate located on the control gate dielectric layer, the first opening exposing at least a portion of a sidewall surface of the floating gate; an ion-doped region located in the floating gate, the first opening exposing the ion-doped region; A tunneling dielectric layer located on the floating gate surface and the control gate surface exposed by the first opening; A gate oxide layer is located on the surface of the logic area.

2. The semiconductor structure according to claim 1, wherein: The floating gate has a floating gate protrusion protruding from the control gate sidewall exposed by the first opening, the ion doping region is located in the floating gate protrusion, and the surface of the floating gate protrusion exposes the ion doping region.

3. The semiconductor structure according to claim 2, wherein: The doping ions in the ion-doped region include nitrogen ions.

4. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a storage area and a logic area; forming a floating gate material layer on the surface of the substrate; Separate and paired initial storage gate structures are formed on the surface of the floating gate material layer on the storage area, an initial first opening is provided between the paired initial storage gate structures, the initial first opening exposes the top surface of the floating gate material layer, and each initial storage gate structure includes a control gate dielectric layer located on the floating gate material layer and a control gate located on the control gate dielectric layer; Performing ion doping treatment on the exposed floating gate material layer to form an initial ion doping region in the floating gate material layer; After the ion doping treatment is performed, the floating gate material layer is etched to form separate and paired storage gate structures on the storage area, wherein a first opening is provided between the paired storage gate structures, each storage gate structure comprises a floating gate located on the substrate, a control gate dielectric layer located on the floating gate, and a control gate located on the control gate dielectric layer, wherein the first opening exposes at least a portion of the sidewall surface of the floating gate, and the floating gate has an ion doping region in it, and the first opening exposes the ion doping region; forming a tunneling dielectric layer on the floating gate surface and the control gate surface exposed by the first opening; After forming the storage gate structure, an oxidation process is used to form a gate oxide layer on the surface of the logic region.

5. The method for forming a semiconductor structure according to claim 4, wherein: The floating gate has a floating gate protrusion protruding from the control gate sidewall exposed by the first opening, the ion doping region is located in the floating gate protrusion, and the surface of the floating gate protrusion exposes the ion doping region.

6. The method for forming a semiconductor structure according to claim 4, wherein: The doping ions of the ion-doped region include nitrogen ions.

7. The method for forming a semiconductor structure according to claim 4, wherein: The process of performing ion doping treatment on the floating gate material layer includes an ion implantation process, a microwave plasma treatment process or an annealing process.

8. The method for forming a semiconductor structure according to claim 7, wherein: The parameters of the ion implantation process include: the energy of ion implantation is 0-50 keV; the ion implantation dose is 1E12 ions / cm 2 ~1E16 ions / cm 2 .

9. The method for forming a semiconductor structure according to claim 7, wherein: The gas used in the annealing process includes nitrogen monoxide or nitrogen dioxide.

10. The method for forming a semiconductor structure according to claim 4, wherein: There is a floating gate dielectric layer between the floating gate material layer and the substrate; the control gate sidewall and the control gate dielectric layer sidewall surface also have a sidewall structure; the sidewall structure is formed after forming the control gate dielectric layer and the control gate, and the sidewall structure is formed before etching the floating gate material layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The sidewall structure includes a first sidewall and a second sidewall. The first sidewall is located on the sidewalls on both sides of the control gate and the sidewall surfaces on both sides of the control gate dielectric layer. The second sidewall is located on the first sidewall surface of the control gate sidewall and the control gate dielectric layer sidewall surface exposed by the first opening.

12. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the sidewall structure, the ion-doped region and the floating gate comprises: forming a sidewall structure on the sidewall of the control gate and the sidewall surface of the control gate dielectric layer; using the sidewall structure as a mask, etching the floating gate material layer until the surface of the floating gate dielectric layer is exposed, thereby forming a floating gate and an ion-doped region in the floating gate, wherein the floating gate has a floating gate protrusion that protrudes from the control gate sidewall exposed by the first opening.

13. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the initial storage gate structure includes: forming a control gate dielectric material layer and a control gate material layer on the floating gate material layer; forming a mask layer on the control gate material layer, wherein the mask layer exposes a portion of the control gate material layer surface on the storage area; using the mask layer as a mask, etching the control gate material layer and the control gate dielectric material layer until the surface of the floating gate material layer is exposed to form a control gate and a control gate dielectric layer.

14. The method for forming a semiconductor structure according to claim 4, wherein: After forming the floating gate and the ion doping region, a gate oxide layer is formed on the surface of the logic region.

15. The method for forming a semiconductor structure according to claim 4, wherein: Also includes: After forming the tunnel dielectric layer, an erase gate is formed in the first opening.

16. The method for forming a semiconductor structure according to claim 4, wherein: Also includes: A gate is formed on the gate oxide layer.

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