Memory structure and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a memory structure and a manufacturing method thereof. The method comprises the following steps: providing a semiconductor substrate, forming a memory area stack structure on the semiconductor substrate, and forming a spacing area between two adjacent memory area stack structures; manufacturing a gate spacing insulating layer covering the sidewall of the memory area stack structure and a select gate oxide layer covering the semiconductor substrate; manufacturing a select gate polysilicon on the select gate oxide layer, the select gate polysilicon being located on one side of the memory area stack structure far from the spacing area; depositing a first interlayer dielectric layer, the memory area stack structure and the select gate polysilicon being located in the first interlayer dielectric layer; etching and removing a control gate polysilicon in the memory area stack structure to form a containing cavity; filling the containing cavity with metal to form a metal gate; and depositing a second interlayer dielectric layer, the second interlayer dielectric layer covering the metal gate and the first interlayer dielectric layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a memory structure and a manufacturing method thereof. BACKGROUND

[0002] SONOS is the English acronym of Silicon-Oxide-Nitride-Oxide-Silicon, and is a non-volatile memory closely related to flash memory. The difference between SONOS and mainstream flash memory is that it uses silicon nitride instead of polysilicon as the storage material. One branch of SONOS is SHINOS (Silicon-High Dielectric-Nitride-Oxide-Silicon). SONOS allows lower programming voltage and higher programming-erase cycle times than polysilicon flash memory, and is a relatively active development and research hotspot.

[0003] The SONOS storage unit in the related art includes a control gate (CG) and a select gate (SG), wherein the control gate is used for storing information, and the select gate is used as a switch tube.

[0004] With the continuous reduction of chip area, the active area and the control gate of the SONOS storage unit are also continuously reduced in size to improve product competitiveness. However, the reduction of the control gate width will cause the threshold voltage window to drop, and the product reliability cannot be guaranteed. SUMMARY

[0005] The present application provides a memory structure and a manufacturing method thereof, which can solve the problem that the reduction of the control gate width in the related art will cause the threshold voltage window to drop.

[0006] In order to solve the technical problems in the background art, the first aspect of the present application provides a manufacturing method of a memory structure, the manufacturing method of the memory structure comprising the following steps:

[0007] providing a semiconductor substrate, a storage area stack structure is formed on the semiconductor substrate, and a spacing area is formed between two adjacent storage area stack structures;

[0008] making a gate separation layer covering the sidewall of the storage area stack structure and a select gate oxide layer covering the semiconductor substrate;

[0009] forming a select gate polysilicon on the select gate oxide layer, the select gate polysilicon being located on one side of the storage area stack structure away from the spacing area;

[0010] depositing a first interlayer dielectric layer, the storage area stack structure and the select gate polysilicon being located in the first interlayer dielectric layer;

[0011] etching to remove the control gate polysilicon in the storage area stack structure to form a cavity;

[0012] filling the cavity with metal to form a metal gate;

[0013] depositing a second interlayer dielectric layer covering the metal gate and the first interlayer dielectric layer.

[0014] Optionally, the step of providing a semiconductor substrate and forming a storage area stack structure on the semiconductor substrate comprises:

[0015] providing a semiconductor substrate;

[0016] removing a pad oxide layer on the upper surface of the semiconductor substrate;

[0017] sequentially depositing an ONO layer, a control gate polysilicon layer and a control gate mask layer on the upper surface of the semiconductor substrate;

[0018] defining a storage area photoetching pattern on the control gate mask layer;

[0019] etching the ONO layer, the control gate polysilicon layer and the control gate mask layer based on the storage area photoetching pattern to form a storage area stack structure, and forming a spacing area between two adjacent storage area stack structures.

[0020] Optionally, the step of forming a gate spacer layer covering the sidewall of the storage area stack structure and a select gate oxide layer covering the semiconductor substrate comprises:

[0021] sequentially depositing an isolation oxide layer and an isolation nitride layer on the semiconductor substrate according to the topography of the semiconductor substrate with the storage area stack structure;

[0022] dry etching the isolation nitride layer with the isolation oxide layer as an etching stop layer, and the remaining isolation nitride layer covering the sidewall of the storage area stack structure;

[0023] removing the exposed isolation oxide layer by a wet process;

[0024] depositing a select gate oxide layer covering the exposed upper surface of the semiconductor substrate and the side surface of the isolation nitride layer.

[0025] Optionally, the step of forming a select gate polysilicon on the select gate oxide layer, the select gate polysilicon being located on one side of the storage area stack structure away from the spacing area comprises:

[0026] depositing a select gate polysilicon on the select gate oxide layer, the select gate polysilicon wrapping the storage area stack structure;

[0027] A select gate mask layer is deposited on the select gate polysilicon;

[0028] The select gate polysilicon with the select gate mask layer is subjected to a first self-aligned dry etching process to remove the select gate mask layer longitudinally and thin the select gate polysilicon so that the remaining select gate polysilicon is flush with the memory region stack structure in the longitudinal direction.

[0029] The remaining select gate mask layer covering the side of the select gate polysilicon is removed by wet etching.

[0030] A second self-aligned dry etching process is performed on the remaining select gate polysilicon to thin the select gate polysilicon in the vertical direction, so that the height of the remaining select gate polysilicon in the vertical direction is lower than that of the memory region stack structure.

[0031] Remove the select gate polysilicon located at the interval region, and the remaining select gate polysilicon is located at the sidewall of the memory stack structure away from the interval region.

[0032] Optionally, after the step of forming a select gate polysilicon on the select gate oxide layer, wherein the select gate polysilicon is located on the side of the memory region stack structure away from the spacer region is completed, before the step of depositing a first interlayer dielectric layer, wherein the memory region stack structure and the select gate polysilicon are located in the first interlayer dielectric layer, the following steps are further performed:

[0033] Sidewalls are formed on the exposed sidewalls of the storage area stack structure and on the exposed sidewalls of the select gate polysilicon.

[0034] A metal silicide barrier layer is formed on the upper surface of the selected gate polysilicon and on the exposed upper surface of the semiconductor substrate;

[0035] Blanket deposition of platinum-nickel alloy layers.

[0036] Optionally, the step of depositing to form a first interlayer dielectric layer, wherein the memory region stack structure and the select gate polysilicon are located in the first interlayer dielectric layer, includes:

[0037] A first interlayer dielectric layer is deposited on the nickel-platinum alloy layer, and the memory region stack structure and the select gate polysilicon are located in the first interlayer dielectric layer;

[0038] The upper surface of the first interlayer dielectric layer is planarized through a chemical mechanical polishing process until the upper surface of the storage area stack structure is exposed.

[0039] To solve the technical problems in the background art, the second aspect of the present application provides a memory structure manufactured by the manufacturing method of the memory structure of the first aspect of the present application.

[0040] The technical solution of the present application has at least the following advantages: the manufacturing method of the memory structure and the memory structure manufactured by the method can eliminate the control gate polysilicon loss effect, increase the electric field strength during voltage operation and the control gate polysilicon threshold voltage window, and improve the reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0042] Figure 1 A flow chart of the manufacturing method of the memory structure provided by an embodiment of the present application is shown;

[0043] Figure 2 A schematic diagram of a semiconductor substrate structure with a memory area stack structure is shown;

[0044] Figure 3 A schematic diagram of the cross-sectional structure of the device after step S21 is shown;

[0045] Figure 4 A schematic diagram of the cross-sectional structure of the device after step S22 is shown;

[0046] Figure 5 A schematic diagram of the cross-sectional structure of the device after step S24 is shown;

[0047] Figure 6 A schematic diagram of the cross-sectional structure of the device after step S32 is shown;

[0048] Figure 7 A schematic diagram of the cross-sectional structure of the device after step S33 is shown;

[0049] Figure 8 A schematic diagram of the cross-sectional structure of the device after step S35 is shown;

[0050] Figure 9 A schematic diagram of the cross-sectional structure of the device after step S36 is shown;

[0051] Figure 10 A schematic diagram of the cross-sectional structure of the device after step S4 is shown;

[0052] Figure 11 A schematic diagram of the cross-sectional structure of the device after step S5 is shown;

[0053] Figure 12 A schematic diagram of the cross-sectional structure of the device after step S6 is shown;

[0054] Figure 13 A schematic diagram of the cross-sectional structure of the device after step S7 is shown. Detailed Implementation

[0055] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0056] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0057] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0058] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0059] Figure 1 A flowchart illustrating a method for manufacturing a memory structure according to an embodiment of this application is shown.

[0060] from Figure 1 As can be seen from this, the manufacturing process of this memory structure includes the following steps:

[0061] Step S1: providing a semiconductor substrate on which a memory region stack structure is formed, and a spacing region is formed between two adjacent memory region stack structures.

[0062] Referring to Figure 2 which shows a schematic diagram of a semiconductor substrate structure with memory region stack structures. As can be seen from Figure 2 , the semiconductor substrate 100 has memory region stack structures CG formed thereon with spacing regions formed between two adjacent memory region stack structures CG.

[0063] Exemplarily, step S1 can be implemented according to the following steps S11 to S15.

[0064] Step S11: providing a semiconductor substrate.

[0065] The semiconductor substrate includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer below a thin semiconductor layer that is the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically includes a crystalline semiconductor material silicon, but can also include one or more other semiconductor materials such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or combinations thereof. The semiconductor material can be doped or undoped. Other substrates that can be used include multilayer substrates, graded substrates, or hybrid orientation substrates.

[0066] Step S12: removing a pad oxide layer on the upper surface of the semiconductor substrate.

[0067] The semiconductor substrate provided generally has a pad oxide layer formed thereon, and the pad oxide layer needs to be removed before the memory region stack structure CG is made on the semiconductor substrate. Exemplarily, the pad oxide layer can be removed by a wet process.

[0068] Step S13: sequentially depositing an ONO layer, a control gate polysilicon layer and a control gate mask layer on the upper surface of the semiconductor substrate.

[0069] The ONO layer includes a bottom oxide layer, a nitride layer and an upper oxide layer sequentially covering the semiconductor substrate from bottom to top, and the control gate mask layer can be PESiN. The thickness of the control gate mask layer is 400A.

[0070] Step S14: defining a memory region photoetching pattern on the control gate mask layer.

[0071] Step S15: etching the ONO layer, control gate polysilicon layer and control gate mask layer based on the storage area lithography pattern, forming storage area stack structure, and forming interval area between two adjacent storage area stack structures.

[0072] After step S15 is completed, a device structure as shown in the figure is formed. Figure 2

[0073] Step S2: fabricating gate isolation layer covering the sidewall of the storage area stack structure and selection gate oxide layer covering the semiconductor substrate.

[0074] The gate isolation layer covering the sidewall of the storage area stack structure is an oxide layer-nitride layer-oxide layer structure.

[0075] This step S2 can be implemented according to the following steps S21 to S24:

[0076] Step S21: sequentially depositing isolation oxide layer and isolation nitride layer on the semiconductor substrate according to the topography of the semiconductor substrate with the storage area stack structure.

[0077] Referring to Figure 3 , a cross-sectional structure diagram of the device after step S21 is completed is shown. As can be seen from Figure 3 , the isolation oxide layer 210 and the isolation nitride layer 220 are formed according to the topography of the semiconductor substrate 100 with the storage area stack structure CG, and cover the semiconductor substrate 100. That is, the isolation oxide layer 210 is located below the isolation nitride layer 220, and covers the exposed upper surface of the semiconductor substrate 100, and covers the side surface and the upper surface of the storage area stack structure CG. The isolation oxide layer 210 covering the exposed upper surface of the semiconductor substrate 100 covers the interval area between two adjacent storage area stack structures CG.

[0078] Step S22: dry etching the isolation nitride layer with the isolation oxide layer as the etching stop layer, and the remaining isolation nitride layer covers the sidewall of the storage area stack structure.

[0079] Referring to Figure 4 , a cross-sectional structure diagram of the device after step S22 is completed is shown. As can be seen from Figure 4 , due to the anisotropy of dry etching, the etching rate of the front surface of the isolation nitride layer 220 is greater than that of the side surface of the isolation nitride layer 220, so that after dry etching is completed, the isolation nitride layer 220 covering the exposed upper surface of the semiconductor substrate 100 and the upper surface of the storage area stack structure CG is etched and removed, and the isolation nitride layer 220 covering the side surface of the storage area stack structure CG is retained. ​

[0080] Step S23: removing the exposed isolation oxide layer by a wet process.

[0081] When the wet process is performed, the isolation nitride layer 220 covering the side surface of the memory stack structure CG is retained. The retained isolation nitride layer 220 protects the underlying isolation oxide layer 210, so that the wet process removes the isolation oxide layer 210 covering the exposed upper surface of the semiconductor substrate 100 and the upper surface of the memory stack structure CG. The remaining isolation oxide layer 210 and the isolation nitride layer 220 cover the side surface of the memory stack structure CG.

[0082] Step S24: depositing a select gate oxide layer covering the exposed upper surface of the semiconductor substrate and the side surface of the isolation nitride layer.

[0083] Exemplarily, the select gate oxide layer can be deposited by an ISSG process.

[0084] Referring to Figure 5 which shows a schematic diagram of the cross-sectional structure of the device after step S24 is completed. It can be seen from Figure 5 that the side surface of the memory stack structure CG is covered by the isolation oxide layer 210, the isolation nitride layer 220 and the select gate oxide layer 230 in sequence, and the exposed upper surface of the semiconductor substrate 100 is covered by the select gate oxide layer 230.

[0085] Step S3: depositing a select gate polysilicon on the select gate oxide layer, the select gate polysilicon being located on one side of the memory stack structure away from the spacing region.

[0086] Exemplarily, the step S3 can be implemented according to the following steps S31 to S36:

[0087] Step S31: depositing a select gate polysilicon on the select gate oxide layer, the select gate polysilicon wrapping the memory stack structure.

[0088] Step S32: depositing a select gate mask layer on the select gate polysilicon.

[0089] Referring to Figure 6 which shows a schematic diagram of the cross-sectional structure of the device after step S32 is completed. It can be seen from Figure 6 that the select gate polysilicon 310 deposited in step S32 covers and wraps the memory stack structure CG, i.e. the select gate polysilicon 310 fills the spacing region formed between two adjacent memory stack structures CG, and the select gate mask layer 320 covers the select gate polysilicon 310.

[0090] Step S33: performing first self-aligned dry etching on the select gate polysilicon with the select gate mask layer, removing the select gate mask layer and thinning the select gate polysilicon in the longitudinal direction, so that the remaining select gate polysilicon is flush with the storage region stack structure in the longitudinal direction.

[0091] Referring to Figure 7 , which shows a cross-sectional structure diagram of the device after step S33 is completed. As can be seen from Figure 7 , the anisotropy of dry etching is used, that is, the etching rate on the front surface is greater than that on the side surface. By first self-aligned dry etching, the select gate mask layer 320 is removed in the longitudinal direction and the select gate polysilicon 310 is thinned, so that the select gate polysilicon 310 covering the storage region stack structure CG is flush with the storage region stack structure CG, and the select gate polysilicon 310 covering the surface of the exposed semiconductor substrate 100 is thinned. The remaining select gate mask layer 320 covers the select gate polysilicon 310 on the side of the storage region stack structure CG.

[0092] Step S34: removing the remaining select gate mask layer covering the side of the select gate polysilicon by wet etching.

[0093] Exemplarily, the select gate mask layer covering the side of the select gate polysilicon can be removed by phosphoric acid etching.

[0094] Step S35: performing second self-aligned dry etching on the remaining select gate polysilicon, thinning the select gate polysilicon in the longitudinal direction, so that the remaining select gate polysilicon is lower than the storage region stack structure in the longitudinal direction.

[0095] Due to the etching blocking effect of the control gate mask layer at the top end of the storage region stack structure CG on the second self-aligned dry etching, the second self-aligned dry etching continues to thin the select gate polysilicon in the longitudinal direction, so that the remaining select gate polysilicon is lower than the storage region stack structure in the longitudinal direction.

[0096] Referring to Figure 8 , which shows a cross-sectional structure diagram of the device after step S35 is completed. As can be seen from Figure 8 , after the second self-aligned dry etching is completed, the select gate polysilicon 310 in the interval between the two adjacent storage region stack structures CG and the select gate polysilicon 310 on one side of the storage region stack structure CG away from the interval remain, and the remaining select gate polysilicon 310 is lower than the height of the storage region stack structure CG.

[0097] Step S36: removing the select gate polysilicon at the interval position, and the remaining select gate polysilicon is located at the sidewall position of the storage region stack structure away from the interval.

[0098] Exemplarily, the selected gate polysilicon located at the position of the interval region can be removed by a lithography etching process.

[0099] Referring to Figure 9 which shows a schematic diagram of the cross-sectional structure of the device after step S36 is completed, from Figure 9 it can be seen that the selected gate polysilicon 310 remaining after step S36 is completed is located at the position of the sidewall of the storage region stack structure CG away from the interval region.

[0100] Step S4: a first interlayer dielectric layer is deposited, and the storage region stack structure and the selected gate polysilicon are located in the first interlayer dielectric layer.

[0101] Exemplarily, the first interlayer dielectric layer can be deposited first, which wraps the storage region stack structure and the selected gate polysilicon, and then the upper surface of the first interlayer dielectric layer is planarized to expose the upper surface of the storage region stack structure by a chemical mechanical polishing process.

[0102] Referring to Figure 10 which shows a schematic diagram of the cross-sectional structure of the device after step S4 is completed. From Figure 10 it can be seen that the first interlayer dielectric layer 410 wraps the storage region stack structure CG and the selected gate polysilicon 310, and the upper surface of the storage region stack structure CG is exposed from the first interlayer dielectric layer 410.

[0103] Optionally, after step S3 is completed, the following steps S41 to S43 can be further performed before step S4 is performed.

[0104] Step S41: a sidewall is formed on the exposed sidewall of the storage region stack structure and the exposed sidewall of the selected gate polysilicon.

[0105] Exemplarily, the sidewall can be formed by a deposition and etching process, which covers the exposed sidewall of the storage region stack structure and the exposed sidewall of the selected gate polysilicon. The material of the sidewall can be silicon nitride.

[0106] Step S42: a metal silicide barrier layer is formed on the upper surface of the selected gate polysilicon and the exposed upper surface of the semiconductor substrate.

[0107] Step S43: a platinum-nickel alloy layer is deposited by blanket deposition.

[0108] Exemplarily, the platinum-nickel alloy layer covers the exposed surface of the selected gate polysilicon, the exposed surface of the storage region stack structure, and the exposed surface of the semiconductor substrate.

[0109] Step S5: the control gate polysilicon in the storage region stack structure is etched to form a receiving cavity.

[0110] Exemplarily, the control gate polysilicon in the storage region stack structure can be etched and removed to form a receiving cavity.

[0111] Referring to Figure 11 , a cross-sectional structure diagram of the device after step S5 is shown. As can be seen from Figure 11 , after the control gate polysilicon is removed, a receiving cavity 510 is formed at the original position of the control gate polysilicon.

[0112] Step S6: filling metal into the receiving cavity to form a metal gate.

[0113] Exemplarily, in the process of making the metal gate, metal can be deposited, which fills the receiving cavity, and then the upper surface of the metal gate is planarized by a chemical mechanical polishing process.

[0114] Referring to Figure 12 , a cross-sectional structure diagram of the device after step S6 is shown. As can be seen from Figure 12 , the receiving cavity 510 is filled with a metal gate 520.

[0115] Step S7: depositing a second interlayer dielectric layer, which covers the metal gate and the first interlayer dielectric layer.

[0116] Referring to Figure 13 , a cross-sectional structure diagram of the device after step S7 is shown. As can be seen from Figure 13 , the second interlayer dielectric layer 420 covers the metal gate 520 and the first interlayer dielectric layer 410.

[0117] In subsequent processes, a contact hole structure can be made.

[0118] The application also provides a memory structure, which is made by the method for manufacturing a memory structure. Figure 1 as shown.

[0119] The method for manufacturing a memory structure and the memory structure manufactured thereby provided by the application can eliminate the control gate polysilicon loss effect, increase the electric field strength during voltage operation and the control gate polysilicon threshold voltage window, and improve the reliability of the device.

[0120] Obviously, the above embodiments are only examples for clear illustration, and are not intended to limit the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be exhausted, and the obvious changes or variations derived therefrom are still within the protection scope of the application.

Claims

1. A method of fabricating a memory structure, comprising: The manufacturing method of the memory structure comprises the following steps: providing a semiconductor substrate, a memory zone stack structure is formed on the semiconductor substrate, and a spacing zone is formed between two adjacent memory zone stack structures; forming a gate isolation layer covering the sidewall of the memory zone stack structure and a select gate oxide layer covering the semiconductor substrate; forming a select gate polysilicon on the select gate oxide layer, the select gate polysilicon is located on the side of the memory zone stack structure away from the spacing zone; the method comprises the following steps: depositing a select gate polysilicon on the select gate oxide layer, the select gate polysilicon wraps the memory zone stack structure; depositing a select gate mask layer on the select gate polysilicon; performing a first self-aligned dry etching on the select gate polysilicon with the select gate mask layer, longitudinally removing the select gate mask layer and thinning the select gate polysilicon, so that the remaining select gate polysilicon is flush with the memory zone stack structure in the longitudinal direction; removing the remaining select gate mask layer covering the side of the select gate polysilicon by wet etching; performing a second self-aligned dry etching on the remaining select gate polysilicon, longitudinally thinning the select gate polysilicon, so that the height of the remaining select gate polysilicon in the longitudinal direction is lower than that of the memory zone stack structure; removing the select gate polysilicon located at the position of the spacing zone, and the remaining select gate polysilicon is located at the sidewall position of the memory zone stack structure away from the spacing zone; depositing a first interlayer dielectric layer, the memory zone stack structure and the select gate polysilicon are located in the first interlayer dielectric layer; etching to remove the control gate polysilicon in the memory zone stack structure to form a containing cavity; filling the containing cavity with metal to form a metal gate; depositing a second interlayer dielectric layer, the second interlayer dielectric layer covers the metal gate and the first interlayer dielectric layer.

2. The method of manufacturing a memory structure of claim 1, wherein, The step of providing a semiconductor substrate and forming a memory zone stack structure on the semiconductor substrate comprises: providing a semiconductor substrate; removing a pad oxide layer on the upper surface of the semiconductor substrate; sequentially depositing an ONO layer, a control gate polysilicon layer and a control gate mask layer on the upper surface of the semiconductor substrate; defining a memory zone lithography pattern on the control gate mask layer; etching the ONO layer, the control gate polysilicon layer and the control gate mask layer based on the memory zone lithography pattern to form a memory zone stack structure, and a spacing zone is formed between two adjacent memory zone stack structures.

3. The method of manufacturing a memory structure of claim 1, wherein, The step of forming a gate isolation layer covering the sidewall of the memory zone stack structure and a select gate oxide layer covering the semiconductor substrate comprises: in accordance with the topography of the semiconductor substrate with the memory zone stack structure, sequentially depositing an isolation oxide layer and an isolation nitride layer on the semiconductor substrate; using the isolation oxide layer as an etching stop layer, performing dry etching on the isolation nitride layer, and the remaining isolation nitride layer covers the sidewall of the memory zone stack structure; removing the exposed isolation oxide layer by a wet process; depositing a select gate oxide layer, the select gate oxide layer covers the exposed upper surface of the semiconductor substrate and the side of the isolation nitride layer.

4. The method of manufacturing a memory structure of claim 1, wherein, After the step of fabricating a select gate polysilicon on the select gate oxide, the select gate polysilicon being on a side of the memory stack structure away from the spacer, the step of depositing a first interlayer dielectric layer, the memory stack structure and the select gate polysilicon being in the first interlayer dielectric layer, is preceded by the following steps: Fabricating a sidewall on the exposed sidewall of the memory stack structure and on the exposed sidewall of the select gate polysilicon; Fabricating a metal silicide barrier on the top surface of the select gate polysilicon and on the exposed top surface of the semiconductor substrate; Depositing a platinum nickel alloy layer.

5. The method of manufacturing a memory structure of claim 4, wherein, The step of depositing a first interlayer dielectric layer, the memory stack structure and the select gate polysilicon being in the first interlayer dielectric layer, comprises: Depositing a first interlayer dielectric layer on the platinum nickel alloy layer, the memory stack structure and the select gate polysilicon being in the first interlayer dielectric layer; Planarizing the top surface of the first interlayer dielectric layer to expose the top surface of the memory stack structure by a chemical mechanical polishing process.

6. A memory structure, comprising: The memory structure is manufactured by the method of manufacturing a memory structure according to any one of claims 1 to 5.

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