High modulus carbon doped silicon oxide films for mold stack scaling solutions in advanced memory applications

Abstract

Provided herein is a reduced temperature plasma enhanced chemical vapor deposition process for manufacturing a high modulus oxide thin film on a substrate. The substrate temperature used to deposit the oxide thin film is less than about 700 DEG C.

Description

Incorporated by Reference

[0001] The PCT application form is filed concurrently with this specification as a part of this application. Each application identified in the concurrently filed PCT application form to which this application claims the benefit or priority is incorporated herein by reference in its entirety and for all purposes. Background Art

[0002] The evolution of chip design requires continuous improvement in circuit speed and reliability. This leads to the densification of multiple devices into higher packaging density to achieve faster transistor speed. However, shrinking the size of the device is not always preferred. Increasing the density to the subatomic level will cause resistance-capacitance (RC) delays, thereby reducing transistor performance. One solution is to use low-k intermetallic dielectric films to replace conventional silicon oxide films.

[0003] A material that may be considered suitable for this task is a carbon-doped silicon dioxide film. Using this material to distinguish metal lines can produce devices with reduced propagation delay, crosstalk noise and power consumption. However, replacing the silicon dioxide film may have an adverse effect on other integrated modules. A long-standing problem is the etching of carbon-doped silicon dioxide films. The etching profile may be biased because the film releases excessive carbon byproducts. In addition, the excess carbon derived from the film may interfere with the etching and stop etching before reaching the desired depth, thereby increasing the possibility of incomplete etching. The carbon content may also cause excessive micro-loading (etching rate difference between isolated trenches and dense trenches) that is difficult to adjust. For these reasons, unless it is to reduce the dielectric constant of the film, a high carbon content in the film is generally not ideal. Therefore, it would be advantageous to accurately control the carbon content in the carbon-doped silicon dioxide film, especially for 3D NAND technology that stacks memory cells vertically in multiple layers.

[0004] The background description provided here is for the purpose of generally presenting the background of the present disclosure. The work of the currently designated inventors within the scope described in this background section and aspects of the specification that were not determined to be prior art at the time of filing the application are neither explicitly nor implicitly admitted to be prior art against the present disclosure. Summary of the invention

[0005] Provided herein are methods and apparatus for processing semiconductor substrates and semiconductor devices. Various methods and apparatus are described that relate to thin films produced by reduced temperature plasma enhanced chemical vapor deposition that facilitates large area gap fill applications, such as the formation of advanced 3D NAND devices. These films have improved mechanical properties without sacrificing electrical properties or other properties that facilitate ease of integration.

[0006] Thus, in a first aspect, the present invention comprises a method for plasma enhanced chemical vapor deposition of a thin film. In some embodiments, the method comprises providing a substrate in a deposition chamber at a substrate temperature of less than about 700° C.; generating a plasma of at least one process gas, the at least one process gas comprising at least one reactant; contacting the substrate with the plasma in the deposition chamber; and depositing the thin film on the substrate, the thin film having a Young's modulus of at least 70 GPa.

[0007] In some embodiments, the reactant is a silicon-containing gas source, an aluminum-containing gas source, or a boron-containing gas source.

[0008] In some embodiments, the film is silicon monoxide, silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, borocarbide, or boronitride.

[0009] In some embodiments, the thin film is a doped thin film.

[0010] In some embodiments, the doped film is silicon oxide doped with carbon, nitrogen, boron, phosphorus, or a combination thereof.

[0011] In some embodiments, the doped film has a Young's modulus of at least 90 GPa.

[0012] In some embodiments, the doped film is a borocarbide doped with silicon, nitrogen, germanium, magnesium, nickel, or a combination thereof.

[0013] In some embodiments, the doped thin film is a boronitride doped with bismuth, zinc, copper, or a combination thereof.

[0014] In some embodiments, the doped film is silicon nitride doped with aluminum, phosphorus, carbon, oxygen, or a combination thereof.

[0015] In some embodiments, the thin film is aluminum oxide doped with erbium, titanium, chromium, or a combination thereof.

[0016] In some embodiments, the plasma is generated in situ or remotely.

[0017] In some embodiments, the film has a thickness of less than 300 angstroms.

[0018] In some embodiments, the film has a dielectric constant of about 4 to about 4.5.

[0019] In a second aspect, the present invention comprises a method for plasma enhanced chemical vapor deposition of a carbon-doped silicon oxide film on a substrate. In some embodiments, the method comprises providing the substrate in a deposition chamber at a substrate temperature of less than about 700° C.; generating a plasma of a process gas and a carbon-containing gas source, the process gas comprising a silicon-containing gas source and a carrier gas; contacting the substrate with the plasma in the deposition chamber; and depositing a thin film of carbon-doped silicon dioxide on the substrate, the film having a Young's modulus of at least 70 GPa.

[0020] In some embodiments, the silicon-containing gas source is a gas of a compound having the following chemical formula: SiH n R 1 4-n (I), SiH n (OR 2 ) 4-n (II), O(Si(R 3 3))2(III) or a combination thereof, wherein R 1 , R 2 and R 3 Each is independently optionally substituted aliphatic, optionally substituted alkyl, optionally substituted heteroalkyl, optionally substituted aryl, optionally substituted heteroaryl, optionally substituted cycloalkyl or optionally substituted heterocycloalkyl, and n is an integer from 0 to 4.

[0021] In some embodiments, the silicon-containing gas source is a gas such as silane, tetramethylsilane, tetramethoxysilane, tetraethoxysilane, hexamethyldisilazane, hexamethyldisiloxane, and combinations thereof.

[0022] In some embodiments, the silicon-containing gas source includes tetramethylsilane and silane.

[0023] In some embodiments, the carbon-containing gas source is a gas such as carbon dioxide, carbon monoxide, methane, ethane, and combinations thereof.

[0024] In some embodiments, the carbon-containing gas source also includes a carrier gas such as argon, helium, hydrogen, nitrous oxide, nitrogen, or combinations thereof.

[0025] In some embodiments, the carbon-doped silicon oxide film has a modulus of at least 90 GPa.

[0026] In some embodiments, the carbon-doped silicon oxide film has a carbon content of less than about 5 atomic %.

[0027] In some embodiments, the pressure in the deposition chamber is maintained between about 1 Torr and about 8 Torr.

[0028] In some embodiments, the substrate temperature is greater than about 400°C and less than about 650°C.

[0029] In some embodiments, the ratio of the carbon-containing source gas to the silicon-containing source gas is between about 150:1 and about 10:1.

[0030] In some embodiments, the plasma is generated in situ or remotely.

[0031] In some embodiments, the film has a thickness of less than 300 angstroms.

[0032] In some embodiments, the film has a dielectric constant of about 4 to about 4.5.

[0033] In a third aspect, the present disclosure includes a composition. In some embodiments, the composition is a carbon-doped silicon oxide film having a thickness of less than 300 angstroms, a Young's modulus of at least 90 GPa, a dielectric constant of about 4 to about 4.5, and a carbon content of less than about 5 atomic percent.

[0034] In a fourth aspect, the present disclosure includes an apparatus for processing a substrate. In some embodiments, the apparatus includes a reaction chamber; a substrate support configured to support the substrate in the reaction chamber; one or more inlets for introducing reactants into the reaction chamber; one or more outlets for removing materials from the reaction chamber; and a controller having at least one processor and a memory, wherein the at least one processor and the memory are communicatively connected to each other, and the memory stores computer executable instructions for controlling the at least one processor to cause: providing the substrate in a deposition chamber at a substrate temperature of less than about 700° C.; generating a plasma of at least one process gas, the at least one process gas including at least one reactant; contacting the substrate with the plasma in the deposition chamber; and depositing the thin film on the substrate, the thin film having a Young's modulus of at least 70 GPa.

[0035] In some embodiments, the film has a thickness of less than 300 angstroms.

[0036] In some embodiments, the film has a dielectric constant of about 4 to about 4.5.

[0037] In a fifth aspect, the present disclosure includes an apparatus for forming a carbon-doped silicon oxide film on a substrate. In some embodiments, the apparatus includes: a reaction chamber; a substrate support configured to support the substrate in the reaction chamber; one or more inlets for introducing reactants into the reaction chamber; one or more outlets for removing materials from the reaction chamber; a plasma generator configured to deliver plasma to the reaction chamber; and a controller having at least one processor and a memory, wherein the at least one processor and the memory are communicatively connected to each other, and the memory stores computer-executable instructions for controlling the at least one processor to cause: (i) receiving the substrate in the reaction chamber, (ii) flowing a process gas into the reaction chamber, the process gas comprising a silicon-containing gas source, and (iii) generating the plasma from the carbon-containing gas source and delivering the plasma to the reaction chamber to form the carbon-doped silicon oxide film on the substrate, wherein the carbon-doped silicon oxide film has: a Young's modulus of about 90 GPa or more, and a dielectric constant of about 4 to about 4.5.

[0038] In some embodiments, the carbon-doped silicon oxide film has a thickness of less than 300 angstroms.

[0039] In some embodiments, the carbon-doped silicon oxide film has a carbon content of less than about 5 atomic %.

[0040] These and other aspects will be further described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a process flow diagram depicting the operations of a method for plasma enhanced chemical vapor deposition of thin films according to certain disclosed embodiments.

[0042] Figure 2 is a process flow diagram depicting operations of a method of thin film deposition followed by optional annealing according to certain disclosed embodiments.

[0043] Figures 3 to 12 is a schematic diagram of depositing and annealing a doped silicon oxide film in the context of 3D NAND manufacturing according to certain disclosed embodiments.

[0044] Figures 13 to 15 is a schematic diagram of an exemplary processing chamber and tools for performing certain disclosed embodiments. DETAILED DESCRIPTION

[0045] In the following description, a number of specific details will be presented to provide a thorough understanding of the embodiments. The disclosed embodiments may be implemented in the absence of some or all of these specific details. In other examples, conventional processing operations are not described in detail to avoid unnecessarily obscuring the disclosed embodiments. Although specific embodiments will be used to illustrate the disclosed embodiments, it should be understood that they are not intended to limit the disclosed embodiments. definition

[0046] As used herein, the term "about" means a difference of + / - 10% from any stated value, unless otherwise specified. As used herein, the term modifies any stated value, numerical range, or endpoint(s) of one or more ranges.

[0047] As used herein, the terms "top", "bottom", "upper", "lower", "above", and "below" are used to provide relative relationships between various structures. The use of these terms does not imply or require that a particular structure must be located at a particular location in a device.

[0048] As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical OR, and should not be construed to mean “at least one of A, at least one B, and at least one C.”

[0049] "Aliphatic" means having from at least one carbon atom to 50 carbon atoms (C 1-50 ) of a hydrocarbon group, for example, 1 to 25 carbon atoms (C 1-25 ), or 1 to 10 carbon atoms (C 1-10 ), and includes alkanes (or alkyls), alkenes (or alkenyls), alkynes (or alkynyls), including cyclic forms thereof, and further includes linear and branched arrangements, as well as all stereo and positional isomers. Aliphatic groups are unsubstituted or substituted with functional groups such as those described herein. For example, aliphatic groups may be substituted with one or more substituent groups such as those described herein for alkyl groups.

[0050] "Aryl" means a group containing at least 5 carbon atoms and up to 15 carbon atoms (C 5-15 ) (e.g., five to ten carbon atoms (C 5-10)) is an aromatic carbocyclic group having a single ring or multiple fused rings, the fused rings of which may or may not be aromatic, provided that the point of attachment to the remainder of the compounds disclosed herein is through an atom of the aromatic carbocyclic group. The aryl group may be substituted with one or more groups other than hydrogen (e.g., aliphatic, heteroaliphatic, aromatic, other functional groups, or any combination thereof). Exemplary aryl groups include, but are not limited to, benzyl, naphthalene, phenyl, biphenyl, phenoxybenzene, and the like. The term aryl also includes heteroaryl, which is defined as a group containing an aromatic group having at least one heteroatom incorporated into the ring of the aromatic group. Examples of heteroatoms include, but are not limited to nitrogen, oxygen, sulfur, and phosphorus. Similarly, the term non-heteroaryl, also included in the term aryl, is defined as a group containing an aromatic group and no heteroatoms. The aryl group may be substituted or unsubstituted. The aryl group may be substituted with one, two, three, four, or five substituents, the substituents being independently selected from the group consisting of: (1) C 1-6 Alkanoyl (e.g. -C(O)-R, where R is C 1-6 Alkyl); (2) C 1-6 Alkyl; (3)C 1-6 Alkoxy (e.g. -OR, where R is C 1-6 Alkyl); (4) C 1-6 Alkoxy-C 1-6 Alkyl (e.g. -LOR, where L and R are each independently C 1-6 Alkyl); (5) C 1-6 Alkylsulfinyl (e.g. -S(O)-R, where R is C 1-6 Alkyl); (6) C 1-6 Alkylsulfinyl-C 1-6 Alkyl (e.g. -LS(O)-R, where L and R are each independently C 1-6 Alkyl); (7) C 1-6 Alkylsulfonyl (such as -SO2-R, where R is C 1-6 Alkyl); (8) C 1-6 Alkylsulfonyl-C 1-6 Alkyl (e.g. -L-SO2-R, where L and R are each independently C 1-6 alkyl); (9) aryl; (10) amino (e.g., -NR 1 R 2 , where R 1 With R 2 are each independently selected from hydrogen, aliphatic, heteroaliphatic, halogenated aliphatic, halogenated heteroaliphatic, aromatic, or any combination thereof as defined herein; or R 1 With R 2 Together with the nitrogen atom to which they are attached, they may form a heterocyclic group as defined herein); (11) C 1-6 Aminoalkyl (e.g., -L1 -NR 1 R 2 or -L 2 -C(NR 1 R 2 )(R 3 )-R 4 , where L 1 C 1-6 Alkyl; L 2 For covalent bonds or C 1-6 Alkyl; R 1 With R 2 are each independently selected from hydrogen, aliphatic, heteroaliphatic, halogenated aliphatic, halogenated heteroaliphatic, aromatic, or any combination thereof as defined herein; or R 1 With R 2 Together with the nitrogen atom to which they are attached, they may form a heterocyclic group as defined herein; R 3 With R 4 Each independently is H or C 1-6 alkyl); (12) heteroaryl; (13) C 4-18 Aryl-C 1-6 Alkyl (e.g., -LR, where L is C 1-6 Alkyl and R is C 4-18 aryl); (14) aroyl (e.g., -C(O)-R, wherein R is an aryl group); (15) azido (e.g., -N3); (16) cyano (e.g., -CN); (17) C 1-6 Azidoalkyl (e.g., -L-N3, where L is C 1-6 alkyl); (18) aldehydes (e.g., -C(O)H); (19) aldehydes-C 1-6 Alkyl (e.g., -LC(O)H, where L is C 1-6 Alkyl); (20)C 3-8 Cycloalkyl; (21)C 3-8 Cycloalkyl-C 1-6 Alkyl (e.g., -LR, where L is C 1-6 Alkyl and R is C 3-8 Cycloalkyl); (22) halogen; (23) C 1-6 Haloalkyl (e.g., -L 1 -X or -L 2 -C(X)(R 1 )-R 2 , where L 1 C 1-6 Alkyl; L 2 For covalent bonds or C 1-6 alkyl; X is fluorine, bromine, chlorine or iodine; and R 1 With R 2 Each independently is H or C1-6 alkyl); (24) heterocyclyl (e.g., as defined herein, such as a 5-, 6-, or 7-membered ring containing one, two, three, or four non-carbon heteroatoms); (25) heterocyclyloxy (e.g., -OR, wherein R is a heterocyclyl as defined herein); (26) heterocyclylacyl (e.g., -C(O)-R, wherein R is a heterocyclyl as defined herein); (27) hydroxyl (-OH); (28) C 1-6 Hydroxyalkyl (e.g., -L 1 -OH or -L 2 -C(OH)(R 1 )-R 2 , where L 1 C 1-6 Alkyl; L 2 is a covalent bond or an alkyl group; and R 1 With R 2 are each independently H or C as defined herein 1-6 Alkyl); (29) Nitro; (30) C 1-6 Nitroalkyl (e.g., -L 1 -NO or -L 2 -C(NO)(R 1 )-R 2 , where L 1 C 1-6 Alkyl; L 2 is a covalent bond or an alkyl group; and R 1 With R 2 are each independently H or C as defined herein 1-6 alkyl); (31) N-protected amino; (32) N-protected amino-C 1-6 Alkyl; (33) Oxo (eg, =O); (34) C 1-6 Thioalkyl (e.g., -SR, where R is C 1-6 (35) thio-C 1-6 Alkoxy-C 1-6 Alkyl (e.g., -LSR, wherein L and R are each independently C 1-6 Alkyl); (36)-(CH2) r CO2R 1 , wherein r is an integer from 0 to 4, and R 1 Selected from the group consisting of: (a) hydrogen, (b) C 1-6 Alkyl, (c)C 4-18 Aryl, and (d) C 4-18 Aryl-C 1-6 Alkyl (e.g., -LR, where L is C 1-6 Alkyl and R is C 4-18 Aryl); (37)-(CH2)r CONR 1 R 2 , wherein r is an integer from 0 to 4, and wherein R 1 With R 2 each independently selected from the group consisting of: (a) hydrogen, (b) C 1-6 Alkyl, (c)C 4-18 Aryl, and (d) C 4-18 Aryl-C 1-6 Alkyl (e.g., -LR, where L is C 1-6 Alkyl and R is C 4-18 Aryl); (38)-(CH2) r S02R 1 , wherein r is an integer from 0 to 4, and wherein R 1 Selected from the group consisting of: (a) C 1-6 Alkyl, (b)C 4-18 Aryl, and (c) C 4-18 Aryl-C 1-6 Alkyl (e.g., -LR, where L is C 1-6 Alkyl and R is C 4-18 Aryl); (39)-(CH2) r SO2NR 1 R 2 , wherein r is an integer from 0 to 4 and wherein R 1 With R 2 each independently selected from the group consisting of: (a) hydrogen, (b) C 1-6 Alkyl, (c)C 4-18 Aryl, and (d) C 4-18 Aryl-C 1-6 Alkyl (e.g., -LR, where L is C 1-6 Alkyl and R is C 4-18 Aryl); (40)-(CH2) r NR 1 R 2 , wherein r is an integer from 0 to 4 and wherein R 1 With R 2 Each independently selected from the group consisting of: (a) hydrogen, (b) an N-protecting group, (c) a C 1-6 Alkyl, (d)C 2-6 Alkenyl, (e)C 2-6 Alkynyl, (f)C 4-18 Aryl, (g)C 4-18 Aryl-C 1-6 Alkyl (e.g., -LR, where L is C 1-6 Alkyl and R is C 4-18 Aryl), (h)C 3-8Cycloalkyl, and (i) C 3-8 Cycloalkyl-C 1-6 Alkyl (e.g., -LR, where L is C 1-6 Alkyl and R is C 3-8 (41) thiol (e.g., -SH); (42) perfluoroalkyl (e.g., -(CF2)nCF3, wherein n is an integer from 0 to 10); (43) perfluoroalkoxy (e.g., -O-(CF2)nCF3, wherein n is an integer from 0 to 10); (44) aryloxy (e.g., -OR, wherein R is aryl); (45) cycloalkyloxy (e.g., -OR, wherein R is cycloalkyl); (46) cycloalkylalkoxy (e.g., -OLR, wherein L is alkyl and R is cycloalkyl); and (47) arylalkoxy (e.g., -OLR, wherein L is alkyl and R is aryl). In certain embodiments, the unsubstituted aryl is C 4-18 , C 4-14 , C 4-12 , C 4-10 , C 6-18 , C 6-14 , C 6-12 , or C 6-10 Aryl.

[0051] "Deposition" or "vapor deposition" refers to the process of forming a layer (e.g., metal) on one or more surfaces of a substrate by a vaporized precursor composition, for example, in the case of depositing a metal layer, the precursor composition comprises one or more metal-containing compounds. The precursor composition is vaporized and directed to and / or contacts one or more surfaces of a substrate (i.e., a semiconductor substrate or a semiconductor component) placed in a deposition chamber. Typically, the substrate is heated. These precursor compositions form a non-volatile, thin and uniform layer on the surface of the substrate. One operation of the method can be a cycle, and the process can be repeated for multiple cycles as needed until the desired layer thickness is obtained.

[0052] "Heteroatom" means an atom other than carbon, such as oxygen, nitrogen, sulfur, silicon, boron, selenium, or phosphorus. In particular disclosed embodiments, heteroatoms do not include halogen atoms, such as when valence restrictions do not permit.

[0053] "Heterocyclyl" means a 5-, 6- or 7-membered ring (unless otherwise specified) containing one, two, three or four non-carbon heteroatoms (e.g., independently selected from nitrogen, oxygen, phosphorus, sulfur or halogen). The 5-membered ring has zero to two double bonds, while the 6-membered and 7-membered rings have zero to three double bonds. The term "heterocyclyl" also includes bicyclic, tricyclic and tetracyclic groups, wherein any of the above heterocyclic rings is bound to one, two or three rings independently selected from the group consisting of an aromatic ring, a cyclohexane ring, a cyclohexene ring, a cyclopentane ring, a cyclopentene ring and another monocyclic heterocycle (e.g., indolyl, quinolyl, isoquinolyl, tetrahydroquinolyl, benzofuranyl, benzothienyl and the like). Heterocycles include thiiranyl, thietanyl, tetrahydrothienyl, thianyl, thiepanyl, aziridinyl, azetidinyl, pyrrolidinyl, piperidinyl, azepanyl, pyrrolyl, pyrrolinyl, pyrazolyl, pyrazolinyl, pyrazolidinyl, imidazolyl, imidazolinyl, imidazolidinyl, pyridyl, homopiperidinyl, pyrazinyl, piperazinyl, perazinyl, pyrimidinyl, pyridazinyl, oxazolyl, oxazolidinyl, oxazolidonyl, isoxazolyl, isoxazolidiniyl, morpholinyl, thiomorpholinyl, thiazolyl, thiazolidinyl, isothiazolyl, isothiazolidinyl, indolyl, quinolinyl, isoquinolinyl, benzimidazolyl, benzothiazolyl, benzoxazolyl, furyl,thienyl, thiazolidinyl, isothiazolyl, isoindazoyl, triazolyl, tetrazolyl, oxadiazolyl, uricyl, thiadiazolyl, pyrimidyl, tetrahydrofuranyl, dihydrofuranyl, dihydrothienyl, dihydroindolyl, tetrahydroquinolyl, tetrahydro isoquinolyl, pyranyl, dihydropyranyl, tetrahydropyranyl, dithiazolyl, dioxanyl, dioxinyl, dithianyl, trithianyl, oxazinyl, thiazinyl, oxothiolanyl, triazinyl, benzofuranyl, benzothienyl, and the like.

[0054] "Heterocyclyloxy" means a heterocyclyl, as defined herein, attached to the parent molecular moiety through an oxygen atom. In some embodiments, heterocyclyloxy is -OR, wherein R is a heterocyclyl, as defined herein.

[0055] "Heterocyclyloyl" means a heterocyclyl, as defined herein, attached to the parent molecular moiety through a carbonyl group. In some embodiments, the heterocyclyl is -C(O)-R, wherein R is a heterocyclyl, as defined herein.

[0056] For the purposes of this disclosure, "metal" as used herein should be understood as a conductor having a maximum resistivity of 500 micro-ohm centimeters, including metals and conductive metal salts, particularly conductive metal nitrides, such as TiN.

[0057] In the present disclosure, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate" and "partially manufactured integrated circuit" can be used interchangeably. It is understood by a person of ordinary skill in the art that the term "partially manufactured integrated circuit" can refer to a silicon wafer during any of many stages of integrated circuit manufacturing. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, 300 mm or 450 mm. The following detailed description assumes that the present disclosure is implemented on any wafer. However, the present disclosure is not limited to this. The workpiece can be of various shapes, sizes and materials. In addition to semiconductor wafers, other workpieces that can utilize the present disclosure include various articles, such as printed circuit boards, etc. The term "semiconductor substrate" or "substrate" used herein refers to a substrate containing semiconductor material in its structure at any stage of semiconductor device manufacturing. It should be understood that the semiconductor material in the semiconductor substrate does not need to be exposed. A semiconductor wafer having multiple layers of other materials (e.g., insulators) covering the semiconductor material is an example of a semiconductor substrate. The following detailed description assumes that the disclosed embodiments are implemented on a semiconductor wafer, such as a 200 mm, 300 mm or 450 mm semiconductor wafer. However, the disclosed embodiments are not limited to this. The workpiece can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the disclosed embodiments include various articles of manufacture, such as printed circuit boards, and the like.

[0058] The term "silicon oxide" as used herein refers to a compound containing silicon and oxygen atoms, including all Si x O y The stoichiometric possibilities include integer values ​​of x and y and non-integer values ​​of x and y. For example, "silicon oxide" includes silicon oxides having the formula SiO n Where 1≤n≤2, where n can be an integer or non-integer value. "Silicon oxide" may include substoichiometric compounds such as SiO 1.8 "Silicon oxide" also includes silicon dioxide (SiO2) and silicon monoxide (SiO). "Silicon oxide" also includes natural and synthetic variations and any and all crystalline and molecular structures including tetrahedral coordination of oxygen atoms around a central silicon atom. "Silicon oxide" also includes amorphous silicon oxides and silicates.

[0059] "Silyl" means -SiR 1 R 2 R 3 Or-SiR 1 R 2 - group. In some embodiments, R 1 , R 2 and R 3Each is independently H, optionally substituted aliphatic, optionally substituted heteroaliphatic, optionally substituted aromatic, optionally substituted heteroaromatic, or optionally substituted amino. In certain embodiments, R 1 , R 2 and R 3 Each is independently H, optionally substituted alkyl, optionally substituted alkoxy, optionally substituted aryl, optionally substituted aryloxy, optionally substituted alkyl-aryl, optionally substituted aryl-alkyl, or optionally substituted amino. In other embodiments, silicon is -Si(R) a (OR) b (NR2) c , wherein each R is independently H, optionally substituted aliphatic, optionally substituted heteroaliphatic, optionally substituted aromatic, or optionally substituted heteroaromatic; a, b, and c are each ≥ 0; a+b+c = 3. In specific embodiments, each R is independently H, optionally substituted alkyl, optionally substituted aryl, optionally substituted alkyl-aryl, or optionally substituted aryl-alkyl.

[0060] "Silyloxy" means -OR, wherein R is an optionally substituted silicon group, as described herein. In some embodiments, the silyloxy group is -O-SiR 1 R 2 R 3 , where R 1 , R 2 and R 3 Each is independently H, optionally substituted aliphatic, optionally substituted heteroaliphatic, optionally substituted aromatic, optionally substituted heteroaromatic, or optionally substituted amino. In certain embodiments, R 1 , R 2 and R 3 Each is independently H, optionally substituted alkyl, optionally substituted alkoxy, optionally substituted aryl, optionally substituted aryloxy, optionally substituted alkyl-aryl, optionally substituted aryl-alkyl, or optionally substituted amino. In other embodiments, the siloxy group is -O-Si(R) a (OR) b (NR2) c, wherein each R is independently H, optionally substituted aliphatic, optionally substituted heteroaliphatic, optionally substituted aromatic, or optionally substituted heteroaromatic; a, b, and c are each ≥ 0; a+b+c = 3. In specific embodiments, each R is independently H, optionally substituted alkyl, optionally substituted aryl, optionally substituted alkyl-aryl, or optionally substituted aryl-alkyl.

[0061] "Substituted" means having one or more substituents whose presence does not interfere with the desired function or reactivity. Examples of substituents include alkyl, alkenyl, alkynyl, cycloalkyl (non-aromatic ring), Si(alkyl), Si(alkoxy), alkoxy, amino, alkylamino, alkenylamino, amide, amidine, guanidine, hydroxy, thioether, alkylcarbonyl, alkylcarbonyloxy, alkoxycarbonyloxy, carbonate, alkoxycarbonyl, aminocarbonyl, alkylthiocarbonyl, phosphate, phosphate ester, phosphonate, cyano, halogen, acylamino, imino, sulfhydryl, alkylthio, thiocarboxylate, dithiocarboxylate, sulfate, sulfato, sulfonate, sulfonamide, sulfonamide, nitro, nitrile, azido, heterocyclic, ether, ester, silicon-containing, thioester, or a combination thereof. These substituents themselves may also be substituted. For example, the amino substituent may itself be substituted singly or independently with other substituents as defined above, such as alkyl, alkenyl, alkynyl, and cycloalkyl (non-aromatic ring).

[0062] "Unsubstituted" means that any open valences of the atom are occupied by hydrogen. Additionally, if the occupant of an open valence position on an atom is not specified, it is hydrogen.

[0063] Those skilled in the art will appreciate that the definitions provided above are not intended to encompass impermissible substitution patterns (e.g., a methyl group substituted with five different groups and the like). Those skilled in the art readily appreciate such impermissible substitution patterns. Any functional group disclosed herein and / or defined above may be substituted or unsubstituted, unless otherwise indicated therein.

[0064] Recent advances in semiconductor manufacturing technology have allowed for increased density of components (e.g., memory cells in memory devices) on a substrate. For example, in 3D NAND technology, tall structures are designed to improve device density scaling. New challenges arise from the increased size of these structures. As described herein, novel materials and processing techniques have been developed to address these challenges, including large area gap fill.

[0065] In the 3D NAND manufacturing integration process, alternating oxide and nitride or polysilicon layers are deposited in a stair-like pattern. After the steps are formed, they are filled with an oxide layer, which is then annealed, polished, and etched to form the contact pattern. Traditional oxide films shrink after the thermal annealing step, causing displacement, deformation, and tilting of adjacent features and patterned vias, leading to device failure. Poor thermal stability can also cause cracking of films and structures at different locations of the device. Thermal stability becomes more challenging for more advanced nodes because the aspect ratio and volume of oxide materials are significantly higher.

[0066] In typical current 3D NAND manufacturing, a "mold stack" containing 24 to 64 pairs of oxide and nitride layers (e.g., silicon oxide (SiO2) layers / silicon nitride (Si3N4) layers) is typically deposited in a plasma enhanced chemical vapor deposition (PECVD) dielectric deposition tool. The SiO2 layers and Si3N4 layers are deposited sequentially on each station (also called a pedestal) without moving the wafer until the entire stack or a large portion of the stack has been deposited. Next, vertical channels are etched down through the oxide and nitride layers in the mold stack by etching with a high aspect ratio, and these vertical channels are filled with metal to form contacts. Next, a thick photoresist layer is applied and patterned, the grouped oxide / nitride pairs are etched, the photoresist pattern is then shrunk, and the next pair of oxide / nitride layers is etched. This sequence is repeated to produce a stepped structure at the edge of the array. After a thick oxide layer is deposited and planarized, a wordline trench mask is applied and the trenches are etched down through all the oxide / nitride layers. The nitride layer is then etched away through the wordline trenches. Next, a gate stack of silicon dioxide, silicon nitride, aluminum oxide, tungsten, and tantalum nitride is deposited and etched, and finally the trenches are filled with oxide and tungsten.

[0067] In the manufacture of higher structures involving thicker high-quality film deposition, large area gap filling challenges are faced. For example, in 3D NAND, thick silicon oxide films are used for isolation purposes. Conventional oxide films are subject to high stress, which causes wafer bending and pattern distortion when these films are made thicker, and in turn causes wafer handling problems and integration problems (such as excessive lithography overlap and poor focus). For traditional silicon oxide films, reducing film stress causes high moisture absorption, which can cause oxidation and high resistance values ​​in metal contacts. In addition, these films have high stress offset and film shrinkage when thermally treated, which exacerbates the pattern distortion problem. In addition, the need for further thicker films leads to further increase in chemical mechanical polishing (CMP) time to flatten the device. Therefore, it is necessary to increase the CMP rate to reduce the overall processing cost of the device.

[0068] Sufficiently thick low stress films with high thermal stability, low moisture absorption, and good dielectric properties (e.g., low dielectric constant and high breakdown voltage) are needed for large area gap fill and other applications in current and developing semiconductor processing technologies. For large area gap fill and other applications, such films allow low cost processing and avoid the problems associated with deposition to cumulative thicknesses exceeding 5 micrometers (μm), such as up to 10 μm or up to 20 μm, or thicker. Thick films can be deposited with thicknesses of up to 20 μm or more in a single deposition.

[0069] A viable candidate with suitable physical properties is a doped oxide film. However, the common industrial method for depositing such films is chemical vapor deposition (SACVD) below atmospheric pressure. Although SACVD can form films with high CMP rates and low stress after annealing, the deposition rate is very low, which increases costs. In addition, when deposited to a thickness of many microns, these films absorb moisture, shrink unacceptably and tend to crack.

[0070] Conventional oxide films have a nominal modulus in the range of 75 GPa, which is suitable for high aspect ratio memory OPOP (oxide / polysilicon) and ONON (oxide / nitride) applications. But when thinner layers are applied, they are prone to line bending and collapse. However, high modulus films deposited according to certain embodiments disclosed herein allow the oxide layer to be thinned for the highest stacked integration layer. These films can have one or more of the following characteristics: appropriate dielectric constant, high density, matching or exceeding wet etch rates, and retention of high electrical properties. Any of these characteristics will contribute to the successful integration of future storage technology nodes, and will also be practical when increasing the number of ONON pairs of mold stacks as required by advanced technology nodes.

[0071] Figure 1A non-limiting process for thin film deposition is schematically shown. Process 10 illustrates a plasma enhanced chemical vapor deposition method for thin films. In operation 20, a substrate is provided in a deposition chamber, and the substrate temperature is less than about 700° C., such as less than 650° C. The embodiments disclosed below describe the deposition of materials on substrates such as wafers, substrates or other workpieces. The workpiece can be of various shapes, sizes and materials. In this application, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate" and "partially manufactured integrated circuit" can be used interchangeably. It is understood by a person of ordinary skill in the art to which the present invention belongs that the term "partially manufactured integrated circuit" can refer to a silicon wafer during any of the many stages of integrated circuit manufacturing performed on it. Wafers or substrates used in the semiconductor equipment industry typically have a diameter of 200 mm, 300 mm or 450 mm. Unless otherwise specified, the process details described herein (e.g., flow rates, power levels, etc.) are related to processing a substrate with a diameter of 300 mm, or for processing a chamber, wherein the chamber is configured to process a substrate with a diameter of 300 mm, and can be appropriately scaled according to substrates or chambers of other sizes. In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various articles of manufacture, such as printed circuit boards, etc. The processes and apparatus may be used in the manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, etc.

[0072] In various embodiments, the substrate is a semiconductor substrate. The substrate can be a silicon wafer, such as a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, including a wafer with one or more layers of material (e.g., a dielectric material, a conductive material, or a semiconductor material) deposited thereon. In certain embodiments, the substrate temperature is from about 400°C to less than about 650°C. In certain embodiments, the substrate temperature is from about 350°C to about 500°C. In certain embodiments, the substrate temperature is from about 525°C to about 575°C.

[0073] In certain embodiments, the pressure in the deposition chamber is maintained at about 1 Torr to about 20 Torr, such as about 1 Torr to about 8 Torr. In certain embodiments, the pressure in the deposition chamber is maintained at about 2 Torr to about 5 Torr. In certain embodiments, the plasma power is 150 watts / station to 800 watts / station. In certain embodiments, the plasma power is 200 watts / station to 500 watts / station.

[0074] In some embodiments, plasma is generated in operation 30. Plasma can be generated in situ (inside the deposition chamber; also referred to as direct plasma) or remotely (in a separate device outside the deposition chamber). In some embodiments, a plasma of reactive species is formed. Plasma species may include electrons, positive ions, neutral species, free radicals, and other plasma species. In some embodiments, plasma is formed from at least one processing gas including at least one reactant. In addition to the reactants, the processing gas may also include a carrier gas. In some embodiments, the carrier gas is a passive gas, such as argon, neon, krypton, xenon, or helium. In some cases, the plasma may include other species, such as nitrogen atoms, nitrogen radicals, nitrogen plasma, or a combination thereof.

[0075] The reactant used as the process gas is selected based on the desired film. In certain embodiments, when the film is silicon oxide, silicon dioxide, silicon nitride, or silicon oxynitride, the reactant is a silicon-containing gas source.

[0076] Silicon-containing precursors suitable for use in accordance with the disclosed embodiments include polysilane (H3Si-(SiH2) n -SiH3, wherein n≥0). Examples of silanes are monosilane (SiH4), disilane (Si2H6), and organosilanes such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di-tert-butylsilane, allylsilane, sec-butylsilane, tert-hexylsilane (thexylsilane), isopentylsilane, tert-butyldisilane, di-tert-butyldisilane, and the like.

[0077] Halosilanes include at least one halogen group and may or may not include hydrogen and / or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes and fluorosilanes. Although halosilanes (especially fluorosilanes) may form reactive halide species that can etch silicon materials when plasma is ignited, in some embodiments, halosilanes may not be introduced into the chamber when plasma is ignited, so the formation of reactive halide species from halosilanes may be reduced. Specific chlorosilanes are tetrachlorosilane, trichlorosilane, dichlorosilane, monochlorosilane, chloroallyl silane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di-tert-butylchlorosilane, chloroisopropylsilane, chlorosec-butylsilane, tert-butyldimethylchlorosilane, tert-hexyldimethylchlorosilane, etc.

[0078] Aminosilanes contain at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes are monoaminosilane (H3Si(NH2)4), diaminosilane (H2Si(NH2)2), triaminosilane (HSi(NH2)3) and tetraaminosilane (Si(NH2)4), as well as substituted monoaminosilanes, diaminosilanes, triaminosilanes and tetraaminosilanes, such as tert-butylaminosilane, methylaminosilane, di(isopropylamino)silane (DIPAS), di(sec-butylamino)silane, tert-butylsilanamine, bis(tert-butylamino)silane (SiH2(NHC(CH3)3)2, BTBAS), tert-butylsilylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3, etc. A further example of an aminosilane is trisilylamine (N(SiH3)3).

[0079] The silicon-containing gas source may be a gas having the chemical formula SiH n R 1 4-n (I), SiH n (OR 2 ) 4-n (II), O(Si(R 3 3)) a gas of a compound of 2(III) or a combination thereof, wherein R 1 , R 2 and R 3 Each is independently optionally substituted aliphatic, optionally substituted alkyl, optionally substituted heteroalkyl, optionally substituted aryl, optionally substituted heteroaryl, optionally substituted cycloalkyl or optionally substituted heterocycloalkyl, and n is an integer from 0 to 4.

[0080] Suitable silicon-containing reactants include dimethylaminotrimethylsilane, diethylaminotrimethylsilane, diisopropylaminotrimethylsilane, piperidinyltrimethylsilane, 2,6-dimethylpiperidinyltrimethylsilane, di(sec-butyl)aminotrimethylsilane, isopropyl-sec-butylaminotrimethylsilane, tert-butylaminotrimethylsilane, isopropylaminotrimethylsilane, tert-amylaminotrimethylsilane, diethylaminodimethylsilane, dimethylaminodimethylsilane, diisopropylaminodimethylsilane, piperidinyltrimethylsilane, 2,6-dimethylpiperidinyltrimethylsilane, di(sec-butyl)aminodimethylsilane, isopropyl-sec-butylaminodimethylsilane, tert-butylaminodimethylsilane, isopropylaminodimethylsilane, tert-amylaminodimethylsilane, dimethylaminomethylsilane, diethylaminodimethylsilane, diisopropylaminodimethylsilane, isopropyl-sec-butylaminodimethylsilane, tert-butylaminodimethylsilane, Sec-butylaminomethylsilane, 2,6-dimethylpiperidinylmethylsilane, di(sec-butyl)aminomethylsilane, bis(dimethylamino)methylsilane, bis(diethylamino)methylsilane, bis(diisopropylamino)methylsilane, bis(isopropyl-sec-butylamino)methylsilane, bis(2,6-dimethylpiperidinyl)methylsilane, bis(piperidinyl)methylsilane, bis(isopropylamino)methylsilane, bis(tert-butylamino) Methylsilane, bis(sec-butylamino)methylsilane, bis(tert-amylamino)methylsilane, bis(isobutylamino)methylsilane, bis(cyclohexylamino)methylsilane, bis(isopropylamino)dimethylsilane, bis(isobutylamino)dimethylsilane, bis(sec-butylamino)dimethylsilane, bis(tert-butylamino)dimethylsilane, bis(tert-amylamino)dimethylsilane, bis(cyclohexylamino)dimethylsilane, and combinations thereof.

[0081] In certain embodiments, the silicon-containing gas source can be a gas such as silane, tetramethylsilane, tetramethoxysilane, tetraethoxysilane, hexamethyldisilazane, hexamethyldisiloxane, and combinations thereof.

[0082] In certain embodiments, the silicon-containing gas source includes tetramethylsilane and silane.

[0083] In certain embodiments, the film is aluminum oxide; and the reactant is an aluminum-containing gas source. In certain embodiments, the reactant is trimethylaluminum, triisopropoxyaluminum, aluminum trichloride, or aluminum acetylacetonate.

[0084] In certain embodiments, the film is a borocarbide or a boronitride; the reactant is a boron-containing gas source. In certain embodiments, the reactant is trimethylboron, boron trichloride, or triethylboron.

[0085] In certain embodiments, the film formed by the plasma enhanced chemical vapor deposition method of the present disclosure is a doped film. In certain embodiments, the film is silicon dioxide doped with carbon, nitrogen, boron, phosphorus or a combination thereof. In certain embodiments, the source of the boron dopant is triethyl borate (TEB). In certain embodiments, the source of the phosphorus dopant is triethyl phosphate (TEPO). In certain embodiments, the carbon dopant is carbon dioxide, carbon monoxide, methane, ethane or a combination thereof. In certain embodiments, the carbon-containing gas source (dopant) may also include a carrier gas such as argon, helium, hydrogen, nitrous oxide, nitrogen and a combination thereof. In certain embodiments, the flow ratio of the carrier gas to the carbon-containing gas source is as high as 3: 1.

[0086] In certain embodiments, the film is a borocarbide doped with silicon, nitrogen, germanium, magnesium, nickel, or a combination thereof. In certain embodiments, the film is a boronitride doped with bismuth, zinc, copper, or a combination thereof. In certain embodiments, the film is a silicon nitride doped with aluminum, phosphorus, carbon, oxygen, or a combination thereof. In certain embodiments, the film is an aluminum oxide doped with erbium, titanium, chromium, or a combination thereof. In certain embodiments, the film is a carbon material doped with silicon. In certain embodiments, the film is a silicon carbide doped with oxygen, nitrogen, or a combination thereof.

[0087] In certain embodiments, the film formed by the plasma enhanced chemical vapor deposition method of the present disclosure is a carbon-doped silicon oxide film. The carbon-containing gas source dopant can be a gas such as carbon dioxide, carbon monoxide, methane, ethane, or a combination thereof. The ratio of the carbon-containing gas source (dopant) to the silicon-containing gas source (reactant) is between about 150:1 and about 10:1.

[0088] Back to Figure 1 In operation 40, the substrate is exposed to a plasma of the process gas; the process gas comprises at least one reactant. In certain embodiments, the process gas further comprises a carrier gas. In certain embodiments, the process optionally comprises one or more dopants.

[0089] In operation 50, a thin film is deposited on a substrate. The deposited thin film may have a thickness of less than 300 angstroms, a Young's modulus of at least 70 GPa, and a dielectric constant of about 4 to 4.5. In some embodiments, the thin film is a carbon-doped silicon dioxide film having a Young's modulus of at least 90 GPa, a thickness of less than 300 angstroms, a carbon content of about 5% (atomic) or less, and a dielectric constant of about 4 to 4.5. In some embodiments, the carbon-doped film may have an undetectable carbon content. In some embodiments, the film not only has a high Young's modulus (e.g., at least 70 GPa, such as 90 GPa or more), and thus has greater mechanical strength, but also retains the electrical properties and dielectric constant of conventional silicon oxides with lower Young's modulus (e.g., less than 70 GPa). In some embodiments, the Young's modulus of the film is greater than 100. In some embodiments, the film matches or exceeds the wet etching rate and / or density of conventional silicon oxides. Conventional oxide films formed by plasma enhanced chemical vapor deposition of tetraethylorthosilicate (TEOS) or undoped silicate glass (USG) as a silicon-containing gas source have Young's modulus values ​​in the range of 70 GPa to 80 GPa. For such conventional oxide films, undesirable line bending and line collapse can be predicted at pitch lengths of 40 nm or less (when thinner oxide layers are used).

[0090] In certain embodiments, according to Figure 1 The process shown, plasma enhanced chemical vapor deposition of carbon-doped silicon oxide thin film includes a substrate temperature of about 400° C. to about 600° C.; a deposition chamber pressure of about 1 Torr to about 7 Torr; a ratio of CO2 to silicon-containing compound of about 40:1; and a plasma power of about 250 W / station to 750 W / station. In certain embodiments, the flow rate of the silicon-containing gas source can be about 50 sccm / station to 100 sccm / station, and the flow rate of CO2 can be about 1000 sccm / station to 5000 sccm / station.

[0091] Figure 2 A non-limiting process of plasma enhanced chemical vapor deposition of thin films is schematically shown. Process 60 illustrates a method for depositing a doped silicon oxide film and selectively annealing it, wherein the doped silicon oxide film is configured to expand after annealing. In some embodiments, the annealing can be performed in the presence of nitrogen at a temperature of about 500° C. to about 1000° C. for about 10 minutes to about 60 minutes. At 70, a patterned semiconductor substrate is provided, for example, to a processing chamber of a chemical deposition tool. In some embodiments, the pattern is a staircase pattern of alternating oxide layers and nitride layers formed on the substrate. Figure 3 In FIG. 1 , an exemplary substrate 100 is provided in schematic diagram.

[0092] The method involves depositing a thin film (e.g., a doped silicon oxide film) on a patterned semiconductor substrate at 80. The thin film can have a thickness of, for example, at least 5 μm, for example up to 10 μm, or even up to 20 μm or more. The thin film can be deposited at a high rate of at least 1 μm / minute, for example about 1.25 μm / minute or more. In some embodiments, the deposition of the thin film can be performed before depositing an undoped silicon oxide liner (e.g., having a thickness of about to thickness) and then proceed.

[0093] At 90, the doped silicon oxide film is then optionally annealed to a temperature above the film glass transition temperature. At the glass transition temperature, the film begins to expand and relax, and the film stress is reduced. In some embodiments, annealing of the doped silicon oxide film causes the film to reflow.

[0094] The post-deposition anneal may be performed on the substrate in the same process chamber or in a different process chamber. In some embodiments, the post-anneal may be performed in the process chamber at a temperature in the range of 500° C. to 950° C. for a period in the range of 20 to 60 minutes. In some instances, the anneal may be performed in nitrogen (N2) or another inert gas. In some instances, the anneal is performed in N2 at 750° C. for up to 30 minutes.

[0095] In various embodiments, the deposited oxide layer is a silicon oxide layer. In various embodiments, the deposited nitride layer is a silicon nitride layer. Each oxide and nitride layer is deposited to approximately the same thickness, such as between about 10 nm and about 100 nm, or about 10 nm in some embodiments. The oxide layer may be deposited at a deposition temperature, for example, between about room temperature and about 600°C.

[0096] The oxide and nitride layers used to form the alternating oxide and nitride film stack may be deposited using any suitable technique, such as atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or sputtering. In various embodiments, the oxide and nitride layers are deposited by PECVD.

[0097] The film stack may include between 48 and 512 layers of alternating oxide and nitride layers, wherein each oxide or nitride layer constitutes one layer. A film stack including alternating oxide and nitride layers may be referred to as an ONON stack.

[0098] Figure 4An exemplary schematic diagram of a substrate 100 having alternating oxide (101) and nitride (102) films deposited on the substrate 100 is shown. Note that although Figure 4 The structure depicted shows oxide deposited first followed by nitride, oxide, nitride, etc., but nitride may be deposited first and followed by oxide, nitride, oxide, etc.

[0099] After deposition of the ONON stack, channels can be etched in the substrate ( Figure 4 ). Subsequently, a staircase pattern is formed on the substrate. The "staircase pattern" referred to herein includes two or more steps, each step including an oxide and a nitride layer. It should be understood that the top layer of each group of oxide and nitride layers can be an oxide or nitride used to form the steps in the staircase. In various embodiments, the staircase pattern includes, for example, between 24 and 256 steps. A variety of patterning techniques can be used to form the staircase pattern. For example, one technique may include depositing a sacrificial layer above the substrate, and masking an area of ​​the substrate to etch each group of oxide and nitride layers to form the staircase.

[0100] Figure 5 An example of a substrate 100 is provided, wherein the substrate comprises a stair-step pattern of oxide (111) and nitride (112) layers, with a hard mask 110 located above the topmost nitride layer. Figure 5 A staircase pattern with four steps is shown, but it should be understood that the staircase pattern will typically have more steps, for example between 24 and 256 steps. Each step includes nitride and oxide layers, and as shown in FIG. Figure 5 They are shown spaced "d" from each other, for example, between about 150 nm and about 1000 nm, such as about 500 nm. This region of each step extending outwardly from the edge of the step above it may be referred to as a "pad."

[0101] For discussion purposes, the following discussion of the substrate and subsequent schematic diagrams will include a half view 199, such as Figure 6 shown.

[0102] The oxide film is deposited over the stepped pattern on the substrate. In the context of 3D NAND, the deposited doped film can be tuned to expand in response to annealing and exhibit essentially zero stress just after deposition and a stress shift after annealing. Figure 7 An exemplary substrate 100 is shown including an ONON step, a hard mask 110 , and a doped oxide film 122 configured to be deposited over the step and expanded after annealing 122 .

[0103] Return to Figure 2The doped silicon oxide film is then annealed at a temperature above the film glass transition temperature, as described above, in operation 90. In some embodiments, reflow of the film may occur.

[0104] Reference Figure 8 In some embodiments, vertical slits 130 may be etched in the substrate after the doped oxide film is deposited and annealed. Figure 8 A side view of the substrate 100 is shown after etching the vertical slits 130 .

[0105] In some embodiments, the nitride layer in the ONON stack is etched relative to the oxide on the substrate. Etching can be performed using a selective etching process, wherein the nitride layer is etched at a faster rate than the etching rate of the oxide. Appropriate selective etching processes can be dry or wet. For example, appropriate dry selective nitride layer etching can be performed by exposing the substrate to any one or more of the following gases: chlorine (Cl2), oxygen (O2), nitrous oxide (N2O), tetrafluoromethane (CF4), sulfur tetrafluoride (SF4), carbon dioxide (CO2), fluoromethane (CH3F), nitrogen trifluoride (NF3), nitrogen (N2), hydrogen (H2), ammonia (NH3), methane (CH4), sulfur hexafluoride (SF6), argon (Ar), carbonyl sulfide (COS), carbon disulfide (CS2), hydrogen sulfide (H2S), and nitric oxide (NO). In this operation, the etching material can flow into the vertical slit 130 and selectively etch the nitride laterally, thereby removing these nitride layers from the ONON stack. Alternatively, a wet etching process may be used to etch the nitride layer in the ONON stack, for example by exposing the substrate to phosphoric acid (H3PO4) and / or dilute hydrofluoric acid (DHF) or a mixture of these solutions. Fig. 9 An exemplary schematic diagram of a substrate 100 having a horizontal gap 132 formed by etching nitride is shown.

[0106] In some embodiments, a conductor (typically tungsten) is deposited into the gap of the substrate to form the word line. The tungsten can be deposited by any suitable technique, such as ALD, CVD, PEALD, and / or PECVD. In some embodiments, a barrier layer and / or a tungsten nucleation layer is deposited prior to depositing the bulk tungsten. Fig.10 An example of a substrate 100 including a deposited tungsten wordline 140 is shown, wherein the nitride 112 has been previously etched.

[0107] It should also be understood that in other embodiments, an alternative to the ONON stack may be a stack of deposited alternating dielectric and conductor layers. An example of this is a stack consisting of alternating oxide polysilicon layers, sometimes referred to as an OPOP stack. Such an OPOP stack can be etched according to known techniques to form a staircase pattern, avoiding the need to replace nitride with tungsten in the ONON stack as described above.

[0108] Reference Fig.11 In some embodiments, the doped oxide film 122 is vertically etched to form the via 137. The doped oxide film 122 can be etched by dry etching with exposure to one or more of the following gases: O2, Ar, C4F6, C4F8, SF6, CHF3, and CF4. Fig.11 An exemplary substrate 100 including an oxide / conductor stack in a stair-like pattern is shown, with vias 137 thereby etched in the doped oxide 122 .

[0109] Reference Fig.12 In some embodiments, a conductor (eg, tungsten) may be deposited in the vias 137 to form interconnects 142 to the word lines, completing the 3D NAND structure.

[0110] Thus, another aspect relates to a method for performing large area gap filling in the manufacture of a 3D NAND structure. The method involves: providing a patterned semiconductor substrate containing a 3D NAND structure having alternating oxide and nitride or polysilicon layers in a stair-like pattern; depositing a doped silicon oxide film on the patterned semiconductor substrate and above the stair-like pattern, the doped silicon oxide film being configured to expand when annealed at a temperature above the film glass transition temperature; and annealing the doped silicon oxide film to a temperature above the film glass transition temperature. In some embodiments, reflow of the film may occur. The doped silicon oxide film is deposited by a chemical vapor deposition (CVD) process using precursors for silicon oxide, B dopants, and optionally P dopants. The silicon oxide precursor may be tetraethyl orthosilicate (TEOS), and suitable dopant precursors are triethyl borate (TEB) and triethyl phosphate (TEPO) for B and P dopants, respectively, but others may be used. Other potential features including material composition, size, and properties are described herein above.

[0111] And therefore, another aspect relates to a semiconductor device including a 3D NAND structure having alternating oxide and nitride or polysilicon layers in a stair-like pattern, and a doped silicon oxide film disposed on the stair-like pattern and annealed. The doped silicon oxide film disposed on the stair-like pattern and annealed expands upon annealing and exhibits substantially zero as-deposited stress, and substantially zero post-annealing stress excursion. Other potential features of such a device, including material composition, dimensions, and properties, are described herein above in terms of fabrication methods. Device

[0112] Another aspect relates to an apparatus for processing a semiconductor substrate by depositing a doped silicon oxide film onto a patterned semiconductor substrate, the apparatus comprising: a reaction chamber including a substrate; a plasma source coupled to the reaction chamber and configured to generate a plasma outside the reaction chamber; one or more first gas inlets coupled to the reaction chamber; a second gas inlet coupled to the reaction chamber; and a controller comprising instructions for performing the following operations: depositing a doped silicon oxide film on a patterned semiconductor substrate disposed in the chamber, the doped silicon oxide film being configured to expand when annealed at a temperature above the film glass transition temperature; and annealing the doped silicon oxide film to a temperature above the film glass transition temperature. The instructions may also include depositing the doped silicon oxide film using a chemical vapor deposition (CVD)-based process of reactants of silicon oxide and a carbon dopant. The CVD process may be a plasma enhanced CVD (PECVD) process. The composition and processing conditions of the doped silicon oxide film may be tailored so that the film exhibits substantially zero stress as deposited and substantially zero stress excursion after annealing. The following description provides some details of an apparatus (semiconductor chamber and tool) suitable for implementing the methods described herein and for fabricating the apparatus.

[0113] Fig.13 A schematic diagram of an embodiment of a deposition process chamber 1300 is depicted, which can be suitable for depositing and processing films as described herein. The chamber can be operated as a chemical vapor deposition (CVD) chamber, particularly a plasma enhanced CVD (PECVD) chamber. The process chamber 1300 has a process chamber body 1302 for maintaining a low pressure environment. Multiple process stations 1300 can be included as process stations in a shared low pressure process tool environment. For example, Fig.14 An embodiment of a multi-station processing tool 1400 is depicted.

[0114] See also Fig.13, the processing station 1300 is in fluid communication with a reactant delivery system 1301 to deliver process gases to a distribution showerhead 1306. The reactant delivery system 1301 includes a mixing vessel 1304 for mixing and / or conditioning process gases such as silicon oxide precursor gases (e.g., TEOS) or second reactant gases (e.g., dopant reactants) for delivery to the showerhead 1306. One or more mixing vessel inlet valves 1320 can control the introduction of process gases to the mixing vessel 1304. Plasma can also be delivered to the showerhead 1306, or can be generated in the processing chamber 1300. The reactant delivery system 1301 can be configured to deliver process gases to deposit a doped oxide film over a substrate disposed in the processing chamber 1300.

[0115] As an example, Fig.13 Embodiments include a vaporization point 1303 for vaporizing liquid reactants to be supplied to a mixing container 1304. In some embodiments, the vaporization point 1303 may be a heated vaporizer. The saturated reactant vapor produced by such a vaporizer may condense in a downstream delivery pipeline. Incompatible gases exposed to condensed reactants may produce small particles. These small particles may clog pipelines, hinder valve operation, contaminate substrates, etc. Some methods to solve these problems involve cleaning and / or emptying the delivery pipeline to remove residual reactants. However, cleaning the delivery pipeline may increase the processing station cycle time and reduce the throughput of the processing station. Therefore, in some embodiments, the delivery pipeline downstream of the vaporization point 1303 can be heated and tracked. In some examples, the mixing container 1304 can also be heated and tracked. In a non-limiting example, the pipeline downstream of the vaporization point 1303 has an increased temperature distribution extending from about 100°C to about 150°C at the mixing container 1304.

[0116] In some embodiments, liquid precursors or liquid reactants can be vaporized at the liquid injector. For example, the liquid injector can inject a pulse of liquid reactants into the carrier gas flow upstream of the mixing container. In one embodiment, the liquid injector can vaporize the reactant by flashing the liquid from a higher pressure to a lower pressure. In another example, the liquid injector can atomize the liquid into dispersed droplets, which are then vaporized in a heated delivery pipe. Smaller droplets may vaporize faster than larger droplets, thereby reducing the delay between liquid injection and complete vaporization. Faster vaporization can reduce the length of the pipeline downstream of the vaporization point 1303. In one case, the liquid injector can be directly mounted to the mixing container 1304. In another case, the liquid injector can be directly mounted to the spray head 1306.

[0117] In some embodiments, a liquid flow controller (LFC) upstream of the vaporization point 1303 may be provided to control the mass flow of the liquid to vaporize and be delivered to the processing station 1300. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC may then be adjusted in response to a feedback control signal provided by a proportional-integral-differential (PID) controller in electrical communication with the MFM. However, it may take one second or longer to stabilize the liquid flow using feedback control. This may extend the dosing time of the liquid reactant. Therefore, in some embodiments, the LFC can be dynamically switched between a feedback control mode and a direct control mode. In some embodiments, this can be performed by disabling the sensing tubes of the LFC and PID controller.

[0118] The showerhead 1306 distributes the process gas toward the substrate 1312. Fig.13 In the illustrated embodiment, substrate 1312 is positioned below showerhead 1306 and is shown resting on pedestal 1308. Showerhead 1306 can have any suitable shape and can have any suitable number and arrangement of ports for distributing process gases to substrate 1312.

[0119] In some embodiments, the pedestal 1308 may be raised or lowered to expose the substrate 1312 to the volume between the substrate 1312 and the showerhead 1306. It will be appreciated that in some embodiments, the pedestal height may be programmatically adjusted by a suitable computer controller 1350.

[0120] In another case, in an embodiment where a plasma is ignited, adjusting the height of the pedestal 1308 can enable changing the plasma density during a plasma activation cycle in a process. At the end of a process phase, the pedestal 1308 can be lowered in another substrate transfer phase to enable removal of the substrate 1312 from the pedestal 1308.

[0121] In some embodiments, the temperature of the susceptor 1308 can be controlled via the heater 1310. In some embodiments, the susceptor 1308 can be heated to a temperature of at least about 400° C., or in some embodiments, less than about 300° C., such as about 250° C., during deposition of silicon nitride films as described in the disclosed embodiments. In some embodiments, the susceptor is set to a temperature between about 400° C. and about 600° C. for doped oxide film deposition. In some embodiments, the susceptor is set to a temperature between about 500° C. and about 950° C. for annealing of doped oxide films as described herein.

[0122] Additionally, in some embodiments, pressure control of the processing station 1300 may be provided by a butterfly valve 1318. Fig.13In the embodiment shown in FIG. 1 , butterfly valve 1318 regulates the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, the pressure control of process station 1300 can also be adjusted by varying the flow rate of one or more gases introduced into process station 1300.

[0123] In some embodiments, the position of the showerhead 1306 can be adjusted relative to the pedestal 1308 to change the volume between the substrate 1312 and the showerhead 1306. In addition, it should be understood that the vertical position of the pedestal 1308 and / or the showerhead 1306 can be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 1308 can include a rotation axis for rotating the orientation of the substrate 1312. It should be understood that in some embodiments, one or more of these example adjustments can be performed programmatically by one or more suitable computer controllers 1350.

[0124] In some embodiments where plasma can be used as described above, the showerhead 1306 and the base 1308 are electrically connected to a radio frequency (RF) power supply 1313 and a matching network 1316 for powering the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the processing station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power supply 1314 and the matching network 1316 can be operated at any suitable power to form a plasma of free radical species with a desired composition. Examples of suitable power are included above. Similarly, the RF power supply 1314 can provide RF power of any suitable frequency. In some embodiments, the RF power supply 1314 can be configured to control high-frequency and low-frequency RF power sources independently of each other. Exemplary low-frequency RF frequencies can include, but are not limited to, frequencies between 0kHz and 500kHz. Exemplary high-frequency RF frequencies can include, but are not limited to, frequencies between 1.8MHz and 2.45GHz, or frequencies greater than about 13.56MHz, or frequencies greater than 27MHz, or frequencies greater than 180MHz, or frequencies greater than 60MHz. It will be appreciated that any suitable parameter may be modulated discretely or continuously to provide plasma energy for surface reactions.

[0125] In some embodiments, plasma can be monitored in situ by one or more plasma monitors. In one case, plasma power can be monitored by one or more voltage, current sensors (e.g., VI probes). In another case, plasma density and / or process gas concentration can be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters can be programmed to adjust based on the measurement results from such in-situ plasma monitors. For example, an OES sensor can be used in a feedback loop to provide programmed control of plasma power. It should be understood that in some embodiments, other monitors can be used to monitor plasma and other processing characteristics. Such monitors can include but are not limited to infrared (IR) monitors, sound monitors, and pressure sensors.

[0126] In some embodiments, one or more hardware parameters of the processing station 1300, including the hardware parameters described in detail below, can be programmatically adjusted by one or more computer controllers 1350.

[0127] In some embodiments, instructions for controller 1350 may be provided via input / output control (IOC) sequencing instructions. In one example, instructions for setting the conditions of a treatment phase may be included in a corresponding recipe phase of a treatment recipe. In some cases, the treatment recipe phases may be arranged in sequence so that all instructions for a treatment phase are executed simultaneously with the treatment phase. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe phase. It should be understood that within the scope of the embodiments of the present disclosure, these recipe phases may be further subdivided and / or repeated in any suitable manner.

[0128] As described above, one or more processing chambers may be included as stations in a multi-station processing tool. Fig.14 A schematic diagram of one embodiment of a multi-station processing tool 1400 is shown that includes a processing chamber 1414 having multiple processing stations in a low pressure environment. The processing chamber 1414 can be configured to maintain a low pressure environment so that substrates can be transferred between processing stations without experiencing a vacuum break and / or air exposure.

[0129] The tool 1400 also includes an inbound load lock 1402 and an outbound load lock 1404, either or both of which may include a remote plasma source. A robot 1406 at atmospheric pressure is configured to move a wafer from a box loaded by a wafer boat 1408 into the inbound load lock 1402 via an atmospheric port 1410. The wafer is placed on a pedestal 1412 in the inbound load lock 1402 by the robot 1406, the atmospheric port 1410 is closed, and the load lock 1402 is evacuated. In the case where the inbound load lock 1402 includes a remote plasma source, the wafer can be exposed to a remote plasma treatment in the inbound load lock 1402 before being introduced into the processing chamber 1414. In addition, the wafer can also be heated in the inbound load lock 1402, for example, to remove moisture and adsorbed gases. Next, the chamber transfer port 1416 to the process chamber 1414 is opened and another robot (not shown) places the wafer into the reactor on a susceptor at the first station shown in the reactor for processing. Fig.14 The embodiment depicted in FIG. 1 includes a load lock, but it should be understood that in some embodiments, the wafer may be allowed to enter the processing station directly.

[0130] The depicted processing chamber 1414 includes four processing stations, Fig.14 In the embodiment shown, the processing stations are numbered 1 to 4. Each processing station can be configured to deposit TEOS-based disiloxane and silane-based silicon nitride. Each processing station is composed of a shared mixing vessel (1404, such as in Fig.14 The process gas is supplied by a process station to mix and / or condition the process gas before delivery to the various process stations. Fig.14 Each process station shown includes a process station substrate holder (shown as 1418 for station 1) and a process gas delivery line inlet. In some embodiments, one or more of the process station substrate holders 1418 may be heated.

[0131] In some embodiments, each processing station may have different or multiple purposes. For example, a processing station may switch between an ultra-smooth PECVD processing mode and a conventional PECVD or CVD mode. Additionally or alternatively, in some embodiments, the processing chamber 1414 may include one or more matched pairs of ultra-smooth PECVD and conventional PECVD stations (e.g., a pair including an ultra-smooth PECVD SiO2 station and a conventional PECVD SiN station). In another embodiment, the processing station may switch between two or more film types so that stacks of different film types can be deposited in the same processing chamber. Although the processing chamber 1414 shown includes four stations, it should be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations.

[0132] Fig.14 Also depicted is an embodiment of a substrate handling system 1490 for transferring substrates within the processing chamber 1414. In some embodiments, the substrate handling system 1490 can be configured to transfer substrates between various processing stations and / or between a processing station and a load lock. It should be understood that any suitable substrate handling system can be utilized. Non-limiting examples include substrate conveyors and substrate handling robots.

[0133] The multi-station processing tool 1400 also includes an embodiment of a system controller 1450 for controlling processing conditions and hardware states of the processing tool 1400. For example, in some embodiments, the system controller 1450 can control one or more processing parameters during a PECVD film deposition phase to control characteristics of the deposited film, including, among other things, the composition and thickness of the deposited film.

[0134] The system controller 1450 may include one or more memory devices 1456, one or more mass storage devices 1454, and one or more processors 1452. The processor 1452 may include a CPU or computer, analog and / or digital input / output connections, a stepper motor controller board, and the like.

[0135] In some embodiments, the system controller 1450 controls all actions of the process tool 1400. The system controller 1450 executes machine-readable system control software 1458 stored in the mass storage device 1454, loaded into the memory device 4256, and executed on the processor 1452. The system control software 1458 may include instructions for controlling the timing, gas mixtures, chamber and / or station pressures, chamber and / or station temperatures, substrate temperatures, target power levels, RF power levels, substrate pedestals, chuck and / or carrier positions, and other parameters of a particular process performed by the process tool 1400. The system control software 1458 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of process tool components that perform various process tool processes. The system control software 1458 may be encoded in any suitable computer-readable programming language.

[0136] In some embodiments, the system control software 1458 may include input / output control (IOC) sequencing instructions for controlling various parameters as described above. For example, each stage of a PECVD process may include one or more instructions executed by the system controller 1450. Instructions for setting process conditions for a PECVD process stage may be included in a corresponding PECVD recipe stage, such as the thick doped silicon oxide film deposition described herein. In some embodiments, the PECVD recipe stages may be arranged in sequence so that all instructions for a PECVD process stage are executed simultaneously with the process stage.

[0137] In some embodiments, other computer software and / or programs stored on the mass storage device 1454 and / or the memory device 1456 associated with the system controller 1450 may be employed. Examples of programs or program segments used for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

[0138] The substrate positioning program may include program code for the processing tool components to load a substrate onto the processing station substrate holder 1418 and control the spacing between the substrate and other parts of the processing tool 1400.

[0139] The process gas control program may include code for controlling gas composition and flow rate, and optionally for flowing gas into one or more process stations to stabilize the pressure of the process station prior to deposition. The pressure control program may include code for controlling the pressure in the process station by adjusting, for example, a throttle valve in the exhaust system of the process station, gas flow into the process station, etc.

[0140] The heater control program may include code for controlling the flow of current to a heating unit for heating the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (eg, helium) to the substrate.

[0141] The plasma control program may include code for setting the RF power level applied to the process electrodes in one or more process stations.

[0142] In some embodiments, there may be a user interface associated with the system controller 1450. The user interface may include a display screen, a graphical software display of apparatus and / or processing conditions, and a user input device such as a pointing device, a keyboard, a touch screen, a microphone, etc.

[0143] In some embodiments, the parameters adjusted by the system controller 1450 may relate to process conditions. Non-limiting examples include process gas composition and flow, temperature, pressure, plasma conditions (such as RF bias power level), pressure, temperature, etc. These parameters may be provided to the user in the form of a recipe that may be entered using a user interface.

[0144] Signals for monitoring the process may be provided through analog and / or digital input connections from various process tool sensors of the system controller 1450. Signals for controlling the process may be output on analog and digital output connections of the process tool 1400. Non-limiting examples of process tool sensors that may be monitored include: mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with the data from these sensors to maintain process conditions.

[0145] System controller 1450 may provide program instructions for implementing the above-described deposition process. The program instructions may control various process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. In accordance with various embodiments described herein, the instructions may control the parameters to operate the in-situ deposition of the film stack.

[0146] In some implementations, the system controller 1450 is part of a system, which can be part of the above examples. Such a system can include a semiconductor processing device, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems can be integrated with electronic devices for controlling their operation before, during, and after the processing of semiconductor wafers or substrates. The electronic device can be referred to as a "controller" that can control various components or subcomponents of one or more systems. Depending on the processing requirements and / or the type of system, the system controller 1450 can be programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer delivery in and out of tools and other delivery tools and / or load locks connected to or interfaced with a specific system.

[0147] Broadly speaking, the system controller 1450 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits can include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions delivered to the system controller 1450 or system in the form of various separate settings (or program files) that define operating parameters for performing specific processes on or for semiconductor wafers. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the manufacture of one or more (kinds of) layers, materials, metals, oxides, silicon, silicon oxides, surfaces, circuits, and / or dies of a wafer.

[0148] In some embodiments, the system controller 1450 can be a part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the system controller 1450 can be in the "cloud" or in all or part of a wafer factory (fab) host system, which can allow remote access to wafer processing. The computer can implement remote access to the system to monitor the current progress of manufacturing operations, check the history of past manufacturing operations, study trends or performance metrics from multiple manufacturing operations, change the parameters of the current processing, set the processing steps to follow the current processing, or start a new processing. In some examples, a remote computer (such as a server) can provide a processing recipe to the system through a network (which can include a local network or the Internet). The remote computer can include a user interface that enables input or programming of parameters and / or settings, and then the parameters and / or settings are delivered to the system from the remote computer. In some examples, the system controller 1450 receives instructions in the form of data that specify the parameters of each processing step to be performed during one or more operations. It should be understood that the parameters can be specific to the type of processing to be performed and the type of tool, and the system controller 1450 is configured to interface with the tool or control the tool. Thus, as described above, the system controller 1450 may be distributed, for example, by including one or more discrete system controllers 1450 networked together and working toward a common purpose, such as the processing and control described herein. An example of a distributed controller for such a purpose would be one or more integrated circuits on the chamber communicating with one or more integrated circuits located remotely (e.g., at a platform level or as part of a remote computer), which combine to control the processing on the chamber.

[0149] Exemplary systems may include, but are not limited to, chemical vapor deposition (CVD / PECVD) chambers or modules, plasma etch chambers or modules, track chambers or modules, and any other semiconductor processing systems that may be associated with or used in the manufacture and / or production of semiconductor wafers. Etching operations described herein, such as for etching nitrides or oxides, may be performed in any suitable processing chamber. In some embodiments, a substrate may be etched in a capacitively coupled confined RF plasma reactor with an adjustable gap, which may be used to perform the etching operations described herein.

[0150] As described above, depending on one or more processing steps to be performed by the tool, the system controller 1450 can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in the transport of materials for transporting wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing facility.

[0151] It should be understood that in some embodiments, a low pressure transfer chamber may be included in a multi-station processing tool to facilitate transfer between multiple processing chambers. Fig.15 Another embodiment of a multi-station processing tool 1500 is schematically shown. Fig.15 In the illustrated embodiment, the multi-station processing tool 1500 includes a plurality of processing chambers 1514, and the processing chamber 1515 includes a plurality of processing stations (numbered 1 to 4). The processing chamber 1514 interfaces with a low-pressure transfer chamber 1504, which includes a robot 1506 configured to transfer substrates between the processing chamber 1515 and a load lock 1519. An atmospheric pressure substrate transfer module 1510 including an atmospheric pressure robot 1512 is configured to facilitate the transfer of substrates between the load lock 1519 and the wafer boat 1508. Although Fig.15 Not shown, but it should be understood that embodiments of the multi-station processing tool 1500 may include an appropriate system controller, such as shown in FIG. Fig.14 In and reference Fig.14 An implementation of a system controller 1450 is described. in conclusion

[0152] Although the foregoing embodiments have been described in considerable detail for the purpose of clarity of understanding, it will be apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems and devices of the present embodiments. Therefore, the present embodiments are to be considered illustrative rather than restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. A method for plasma enhanced chemical vapor deposition of a carbon-doped silicon oxide film on a substrate, comprising: providing the substrate in a deposition chamber at a substrate temperature of less than about 700° C.; generating a plasma of a process gas and a carbon-containing gas source, the process gas comprising a silicon-containing gas source and a carrier gas; exposing the substrate to the plasma in the deposition chamber; and depositing a thin film of carbon-doped silicon dioxide on the substrate, The film has a Young's modulus of at least 70 GPa.

2. The method according to claim 1, wherein: The silicon-containing gas source is a gas of a compound having the following chemical formula: SiH n R 1 4-n (I), SiH n (OR 2 ) 4-n (II) O(Si(R 3 3))2(III) or a combination thereof, Where R 1 , R 2 and R 3 each is independently optionally substituted aliphatic, optionally substituted alkyl, optionally substituted heteroalkyl, optionally substituted aryl, optionally substituted heteroaryl, optionally substituted cycloalkyl or optionally substituted heterocycloalkyl, and n is an integer from 0 to 4.

3. The method according to claim 1, wherein: The silicon-containing gas source includes silane, tetramethylsilane, tetramethoxysilane, tetraethoxysilane, hexamethyldisilazane, hexamethyldisiloxane or a combination thereof.

4. The method according to claim 3, wherein: The silicon-containing gas source includes tetramethylsilane and silane.

5. The method according to claim 1, wherein: The carbon-containing gas source includes carbon dioxide, carbon monoxide, methane, ethane or a combination thereof.

6. The method according to claim 5, wherein: The carbon-containing gas source further includes a carrier gas of argon, helium, hydrogen, nitrous oxide, nitrogen, or a combination thereof.

7. The method according to claim 1, wherein: The carbon-doped silicon oxide film has a modulus of at least 90 GPa.

8. The method according to claim 1, wherein: The carbon-doped silicon oxide film has a carbon content of about 5 atomic % or less.

9. The method according to claim 1, wherein: The pressure in the deposition chamber is maintained between about 1 Torr and about 8 Torr.

10. The method according to claim 1, wherein: The substrate temperature is greater than about 400°C and less than about 650°C.

11. The method according to claim 1, wherein: The ratio of the carbon-containing source gas to the silicon-containing source gas is between about 150:1 and about 10:

1.

12. The method according to claim 1, wherein: The plasma is generated in situ or remotely.

13. The method according to claim 12, wherein: The film has a thickness of less than 300 angstroms.

14. The method according to claim 12, wherein: The film has a dielectric constant of about 4 to about 4.

5.

15. An apparatus for forming a carbon-doped silicon oxide film on a substrate, the apparatus comprising: Reaction chamber; a substrate support configured to support the substrate in the reaction chamber; one or more inlets for introducing reactants into the reaction chamber; one or more outlets for removing material from the reaction chamber; a plasma generator configured to deliver plasma to the reaction chamber; as well as A controller having a memory and at least one processor, wherein the at least one processor and the memory are communicatively connected to each other, and the memory stores computer executable instructions for controlling the at least one processor to cause: (i) receiving the substrate in the reaction chamber, (ii) flowing a process gas into the reaction chamber, the process gas comprising a silicon-containing source, and (iii) generating the plasma from a carbon-containing gas source and delivering the plasma to the reaction chamber to form the carbon-doped silicon oxide film on the substrate, wherein the carbon-doped silicon oxide film comprises: (1) a Young's modulus of about 90 GPa or more, and (2) A dielectric constant of about 4 to about 4.

5.

16. The device according to claim 15, wherein: The carbon-doped silicon oxide film has a thickness of less than 300 angstroms.

17. The device according to claim 15, wherein: The carbon-doped silicon oxide film has a carbon content of about 5 atomic % or less.

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