Laminated structure and thin film transistor

Abstract

A laminated structure (10) is provided with a crystalline oxide semiconductor film (11) having I n as the main component, and an insulating film (12) laminated in contact with the crystalline oxide semiconductor film (11). The crystalline oxide semiconductor film (11) has one or more regions in which a rare gas concentration is in the range of 0.5 at% or more and less than 5 at% and which are continuous at 3 nm or more in the film thickness direction.

Description

Technical Field

[0001] The invention relates to a stacked structure and a thin film transistor. Background Art

[0002] Thin film transistors (TFTs) using an amorphous oxide semiconductor for a channel layer are widely known (see Patent Document 1). However, since the mobility of such TFTs is relatively low, improvement is required.

[0003] As a TFT that can obtain higher mobility characteristics than a TFT that uses an amorphous oxide semiconductor for a channel layer, a TFT that uses a crystalline oxide thin film for a channel layer is known (for example, refer to Patent Document 2).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent No. 5118810

[0007] Patent Document 2: International Publication No. 2013 / 035335 Summary of the invention

[0008] However, in the technology of Patent Document 2, although the mobility is improved, there is a tendency for the S value to become too small, and it is difficult to achieve an appropriate S value capable of showing excellent grayscale performance.

[0009] An object of the present invention is to provide a stacked structure that exhibits excellent grayscale performance when applied to a TFT, and also to provide a thin film transistor having the stacked structure.

[0010] According to the present invention, the following stacked structure and the like are provided.

[0011] 1. A stacked structure comprising a crystalline oxide semiconductor film with In as a main component and an insulating film stacked in contact with the crystalline oxide semiconductor film, wherein the crystalline oxide semiconductor film has one or more of the following regions: a region in which a rare gas concentration is in a range of 0.5 at % or more and less than 5 at % and is continuous for more than 3 nm in a film thickness direction.

[0012] 2. In the stacked structure according to 1, the region is continuous by 5 nm or more in a film thickness direction of the crystalline oxide semiconductor film.

[0013] 3. In the layered structure according to 1 or 2, the rare gas atoms are argon.

[0014] 4. In the multilayer structure according to any one of 1 to 3, the insulating film is any one of an oxide film mainly composed of silicon (Si), a nitride film mainly composed of silicon (Si), or an oxynitride film mainly composed of silicon (Si).

[0015] 5. In the multilayer structure according to any one of 1 to 4, the insulating film is an oxide film mainly composed of silicon (Si).

[0016] 6. In the stacked structure according to any one of 1 to 5, the crystalline oxide semiconductor film further contains Ga.

[0017] 7. In the stacked structure according to any one of 1 to 6, the crystalline oxide semiconductor film further contains one or more additional elements selected from B, Al, Si, Sc, Zn, Ge, Y, Zr, Sn, Sm and Yb.

[0018] 8. In the stacked structure according to any one of 1 to 7, an atomic ratio of In to all metal elements contained in the crystalline oxide semiconductor film ([In] / ([In]+[all metal elements other than In])×100) is 62 at % or more.

[0019] 9. In the stacked structure according to any one of 6 to 8, the atomic ratio of Ga to all metal elements contained in the crystalline oxide semiconductor film ([Ga] / ([Ga]+[all metal elements other than Ga])×100) is 30 at % or less.

[0020] 10. In the stacked structure described in any one of items 7 to 9, the total amount of the additive elements relative to the atomic ratio of all metal elements contained in the crystalline oxide semiconductor film ([total amount of additive elements] / ([total amount of additive elements]+[all metal elements other than additive elements])×100) is less than 10 at %.

[0021] 11. The stacked structure according to any one of 1 to 10, wherein the carrier concentration of the crystalline oxide semiconductor film at room temperature is 1×10 18 cm -3 the following.

[0022] 12. The stacked structure according to any one of 1 to 11, wherein the crystalline oxide semiconductor film includes crystal grains of a bixbyite structure.

[0023] 13. A thin film transistor, which is a thin film transistor with a stacked structure as described in any one of items 1 to 12, comprising: a channel layer, a source electrode and a drain electrode respectively connected to the channel layer, and a gate electrode stacked on the channel layer via a gate insulating film, wherein the channel layer is a crystalline oxide semiconductor film in the stacked structure, and the gate insulating film is an insulating film in the stacked structure.

[0024] 14. The thin film transistor according to 13, which is a top-gate transistor.

[0025] 15. A semiconductor device using the stacked structure according to any one of 1 to 12.

[0026] 16. A diode, a thin film transistor, a MOSFET or a MESFET using the semiconductor element described in 15.

[0027] 17. An electronic circuit comprising the diode, thin film transistor, MOSFET or MESFET according to 16.

[0028] 18. An electrical device, electronic device, vehicle or power machine, comprising the electronic circuit according to 17.

[0029] According to the present invention, a stacked structure showing excellent grayscale performance when applied to a TFT can be provided. In addition, a thin film transistor having the stacked structure can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic cross-sectional view of a stacked structure according to an example of the present embodiment.

[0031] Figure 2 This is a schematic cross-sectional view of an example of a TFT according to this embodiment.

[0032] Figure 3 This is a schematic cross-sectional view of another example of the TFT of this embodiment.

[0033] Figure 4 This is a schematic cross-sectional view of another example of the TFT of this embodiment.

[0034] Figure 5 This is a schematic cross-sectional view of a TFT fabricated in the example.

[0035] Figure 6 Schematic diagram showing an example of the existence of a rare gas region in a crystalline oxide semiconductor film in an arbitrary cross section of the stacked structure of the present embodiment.

[0036] Figure 7 FIG. 1 is a schematic diagram showing another example of the existence of the rare gas region in the crystalline oxide semiconductor film in any cross section of the stacked structure of the present embodiment. DETAILED DESCRIPTION

[0037] Ordinal numbers such as "1st", "2nd" and "3rd" used in this specification are added to avoid confusion among components, and components for which no fixed order is described are not limited to the order of the numbers in the ordinal numbers.

[0038] In this specification and the like, the term "film" or "thin film" and the term "layer" can be used interchangeably as appropriate.

[0039] In the sintered body and the oxide thin film in this specification and the like, the term "compound" and the term "crystalline phase" can be used interchangeably as appropriate.

[0040] In this specification, the "oxide sintered body" may be simply referred to as a "sintered body".

[0041] In this specification, a "sputtering target" may be simply referred to as a "target".

[0042] In this specification, etc., "electrical connection" includes connection via "a substance having a certain electrical function". Here, "a substance having a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. For example, "a substance having a certain electrical function" includes electrodes, wiring, switching elements (transistors, etc.), resistors, inductors, capacitors, and elements having various other functions.

[0043] In this specification, the functions of the source and drain of a transistor may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification, the terms source and drain may be used interchangeably.

[0044] In the present specification, "x to y" represents a numerical range of "x or more and y or less." The upper limit value and the lower limit value described in the numerical range can be arbitrarily combined.

[0045] Furthermore, combinations of two or more of the aspects of the present invention described below also belong to aspects of the present invention.

[0046] 1.Layered structure

[0047] The stacked structure of this embodiment includes a crystalline oxide semiconductor film containing In as a main component and an insulating film (hereinafter simply referred to as an insulating film) stacked in contact with the crystalline oxide semiconductor film.

[0048] Figure 1 This is a schematic cross-sectional view of a stacked structure according to an example of the present embodiment.

[0049] The stacked structure 10 includes a crystalline oxide semiconductor film 11 and an insulating film 12 stacked in contact with the crystalline oxide semiconductor film 11 .

[0050] (Crystalline Oxide Semiconductor Film)

[0051] The crystalline oxide semiconductor film 11 in this embodiment (hereinafter simply referred to as a crystalline oxide semiconductor film) contains In element as a main component.

[0052] The main component is the In element, which means that the atomic ratio of In relative to all metal elements of the crystalline oxide semiconductor film ([In] / ([In]+[all metal elements other than In])×100) (atomic %: at%) is 50 at% or more. The atomic ratio of In is preferably 62 at% or more, preferably 70 at% or more, more preferably 80 at% or more, more preferably 84 at% or more, and further preferably 85 at% or more. If 50 at% or more of the total number of atoms of the metal elements constituting the crystalline oxide semiconductor film is the In element, when the stacked structure of this embodiment is used for a TFT, a sufficiently high mobility can be achieved.

[0053] The crystalline oxide semiconductor film may be composed of a single crystal oxide semiconductor or a polycrystalline oxide semiconductor. However, since it is difficult to form a uniform single crystal on a large-area substrate in many cases, it is preferably composed of a polycrystalline oxide semiconductor.

[0054] The crystalline oxide semiconductor film has one or more regions having a rare gas concentration in the range of 0.5 at % to less than 5 at % and continuous for 3 nm or more in the film thickness direction (in the following description, this region may be referred to as a “rare gas region”).

[0055] The rare gas concentration of the crystalline oxide semiconductor film is the rare gas concentration contained in an arbitrary measurement region relative to all detectable atoms contained in the region.

[0056] The measurement method and calculation method of the rare gas concentration are described in detail in the examples.

[0057] A rare gas (gas) is sealed in the crystalline oxide semiconductor film of the stacked structure constituting the present embodiment. The distribution of the rare gas in the polycrystalline oxide semiconductor film may not necessarily be uniform. Even in the case where the distribution of the rare gas is uneven, it is sufficient as long as there is one or more regions where the rare gas concentration is within the range of 0.5 at% and less than 5 at% and is continuous for more than 3 nm in the film thickness direction (vertical direction), that is, a region that is integrated.

[0058] For example, an arbitrary cross section of the stacked structure 10 of the present embodiment including the crystalline oxide semiconductor film 11 and the insulating film 12 is shown in FIG. Figure 6 In this cross section, two rare gas regions 13 (13a and 13b) having a predetermined rare gas concentration and continuous with a thickness of 3 nm or more in the film thickness direction can be confirmed. The rare gas region 13 may be formed in the crystalline oxide semiconductor film 11 from the interface with the insulating film 12, such as the rare gas region 13a, or may be formed in the crystalline oxide semiconductor film 11 separated from the interface, such as the rare gas region 13b.

[0059] Here, in observing Figure 6 In any other cross section of the stacked structure 10 indicated by AA in FIG. 1 , the rare gas region may not be confirmed. As long as the rare gas region is confirmed in any cross section, the crystalline oxide semiconductor film 11 may not be continuous in the plane direction of the crystalline oxide semiconductor film 11 .

[0060] In one embodiment, if Figure 7 As shown, the rare gas region 13 has a shape of a layer continuous in the plane direction (lateral direction) of the crystalline oxide semiconductor film 11. In this case, the rare gas region is confirmed in any cross section AA of the stacked structure 10. Here, there may be a plurality of rare gas regions 13 continuous in the plane direction.

[0061] The rare gas region is present in the film thickness direction of the crystalline oxide semiconductor film with a film thickness of preferably more than 3 nm, more preferably not less than 5 nm, and further preferably not less than 10 nm and not more than 50 nm.

[0062] By providing a crystalline oxide semiconductor film with a rare gas region, when a stacked structure including the crystalline oxide semiconductor film is applied to a TFT, an appropriate S value (eg, approximately 0.8 V / dec.) can be obtained, and excellent grayscale performance can be obtained.

[0063] The rare gas concentration in the rare gas region of the crystalline oxide semiconductor film can be greater than 0.5at%, greater than 0.51at%, greater than 0.53at% or greater than 0.54at%, and can be less than 5.0at%, less than 3.0at%, less than 2.0at%, less than 1.5at%, or less than 1.0at%.

[0064] The rare gas concentration in the rare gas region of the crystalline oxide semiconductor film may be 0.5 to 5 at %, 0.5 to 2 at %, or 0.5 to 1 at %.

[0065] In one embodiment, the rare gas region is continuous over the entire film thickness of the crystalline oxide semiconductor film. The rare gas region is more preferably continuous over a thickness of about half the entire film thickness of the crystalline oxide semiconductor film. The rare gas region is further preferably continuous over a thickness of about one third of the entire film thickness of the crystalline oxide semiconductor film.

[0066] Further, the rare gas region preferably extends to occupy 5 nm or more in the film thickness direction of the crystalline oxide semiconductor film.

[0067] Therefore, when a stacked structure including the crystalline oxide semiconductor film is applied to a TFT, an appropriate S value (eg, approximately 0.8 V / dec.) can be obtained more stably, and excellent grayscale performance can be obtained.

[0068] In order to form the above-mentioned rare gas region in the crystalline oxide semiconductor film, it is possible to dope the rare gas element by supplying rare gas atoms to the crystalline oxide semiconductor film from the insulating film side of the stacked structure of the crystalline oxide semiconductor film and the insulating film. The specific supply method of supplying the rare gas element to the crystalline oxide semiconductor film is described in detail in the manufacturing method of the stacked structure.

[0069] The type of the rare gas atom is not particularly limited, and examples thereof include Ar, He, Ne, and Kr. From the viewpoint of stability in the crystalline oxide semiconductor film, Ar and He are preferred, and Ar is more preferred.

[0070] In one embodiment, the crystalline oxide semiconductor film may contain Ga in addition to In.

[0071] In the case where the crystalline oxide semiconductor film contains Ga, the atomic ratio of Ga to all metal elements in the crystalline oxide semiconductor film ([Ga] / ([Ga]+[all metal elements other than Ga])×100) (atomic %: at %) is preferably 30 at % or less, more preferably 20 at % or less, more preferably 16 at % or less, and further preferably 15 at % or less.

[0072] When the Ga element accounts for 30 at % or less of the total atomic number of metal elements constituting the crystalline oxide semiconductor film, when the multilayer structure of this embodiment is used for a TFT, sufficiently high mobility can be exhibited.

[0073] In addition to In, the crystalline oxide semiconductor film may also contain one or more elements selected from the group consisting of H, B, C, N, O, F, Mg, Al, Si, O, S, Cl, Ar, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Sn, Sb, Cs, Ba, Ln, Hf, Ta, W, Re, Os, Ir, Pt, Au, Pb and Bi.

[0074] In one embodiment, the crystalline oxide semiconductor film may contain, in addition to In, one or more additional elements Z selected from B, Al, Si, Sc, Zn, Ge, Y, Zr, Sn, Sm, and Yb.

[0075] In the case where the crystalline oxide semiconductor film contains an additive element Z, the atomic ratio of the total amount of the additive element Z to all metal elements in the crystalline oxide semiconductor film ([total amount of the additive element Z] / ([total amount of the additive element Z]+[all metal elements other than the additive element Z])×100) (atomic %: at%) is preferably 10 at% or less, more preferably 7.5 at% or less, and further preferably 5 at% or less.

[0076] When the multilayer structure of this embodiment is used for a TFT, if the total amount of the additional element Z in the total atomic number of metal elements constituting the crystalline oxide semiconductor film is 10 at % or less, sufficiently high mobility can be exhibited.

[0077] In this embodiment, the crystalline oxide semiconductor film may be substantially composed of only elements selected from In, Mg, Al, Si, Zn, Ga, Mo, Sn, Ln elements (lanthanide elements), and O. Here, “substantially” means that the crystalline oxide semiconductor film having the stacked structure of this embodiment may contain other components within the range where the effect of the present invention brought about by the combination of In, Mg, Al, Si, Zn, Ga, Mo, Sn, Ln, and O described above is produced.

[0078] In this embodiment, a more preferred first aspect of the crystalline oxide semiconductor film is that the metal element is composed of In and Ga, and the atomic ratio satisfies the following formula (11).

[0079] [Ga] / ([In]+[Ga])]<22at% (11)

[0080] In addition, as a metal element, F or H may be contained in addition to inevitable impurities and O. By setting the composition range as above, the In ratio becomes large, and even at a low temperature of annealing such as 300°C, Ga can be substituted to the In site and crystallized into a bixbyite structure. Furthermore, by adding Ga having a strong bonding force with oxygen, oxygen vacancies after annealing can be suppressed, and a stable film can be formed as a semiconductor.

[0081] In this embodiment, a more preferred second scheme of the crystalline oxide semiconductor film is composed of In as a metal element and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In is set to X, the atomic ratio satisfies the following formula (12).

[0082] [X] / ([In]+[X])]<15at% (12)

[0083] In addition, as a metal element, F or H may be contained in addition to inevitable impurities and O. By setting the composition range as described above, the In ratio becomes large, and even with low temperature annealing such as 300° C., it is possible to crystallize into a bixbyite structure in which X substitutes for the In site. Furthermore, by adding an element X having a strong bonding force with oxygen, oxygen vacancies after annealing can be suppressed, and a stable film can be formed as a semiconductor.

[0084] In this embodiment, a more preferred third scheme of the crystalline oxide semiconductor film is composed of In and Ga as metal elements and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal elements other than In and Ga are set as the added element X, the atomic ratio satisfies the following formulas (13) and (14).

[0085] [Ga] / ([In]+[Ga]+[X])]<22.5at% (13)

[0086] [X] / ([In]+[Ga]+[X])]<8.0at% (14)

[0087] Furthermore, as a metal element, in addition to inevitable impurities and O, F or H may be contained.

[0088] By setting the composition range as described above, the In ratio becomes larger, and even with low temperature annealing at 300° C., it is possible to crystallize into a bixbyite structure in which Ga replaces the In site. In addition, by adding an additional element X having a strong bonding force with oxygen, oxygen vacancies after annealing can be further suppressed, and a stable film can be formed as a semiconductor.

[0089] In this embodiment, a more preferred fourth scheme of the crystalline oxide semiconductor film is composed of In and Sn as metal elements and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In and Sn is set as the element X, the atomic ratio satisfies the following formulas (15) and (16).

[0090] [Sn] / ([In]+[Sn]+[X])]<20at% (15)

[0091] [X] / ([In]+[Sn]+[X])]<8.0at% (16)

[0092] Furthermore, as a metal element, in addition to inevitable impurities and O, F or H may be contained.

[0093] By setting the composition range to this, the In ratio becomes larger, and even with low-temperature annealing at 300°C, it is possible to crystallize into a bixbyite structure in which Sn replaces the In site. Sn has a large ion radius and a large overlap with the In orbital, so it is possible to maintain a high mobility. And by adding an additional element X with a strong bonding force with oxygen, oxygen vacancies after annealing can be further suppressed, forming a stable film as a semiconductor.

[0094] In this embodiment, a more preferred fifth embodiment of the crystalline oxide semiconductor film is composed of In and Zn as metal elements and one or more elements X selected from B, Al, Sc, Mg, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In and Zn is set as the element X, the atomic ratio satisfies the following formulas (17) and (18).

[0095] [Zn] / ([In]+[Zn]+[X])]<12at% (17)

[0096] [X] / ([In]+[Zn]+[X])]<8.0at% (18)

[0097] Furthermore, as a metal element, in addition to inevitable impurities and O, F or H may be contained.

[0098] By setting the composition range as described above, the In ratio becomes larger, and even with low-temperature annealing at 300°C, it is possible to crystallize into a bixbyite structure in which Zn replaces the In site. By adding Zn, the film immediately after film formation can be made amorphous, and when semiconductor patterning is performed using acid during TFT production, processing can be performed without residue. Furthermore, by adding an additional element X that has a strong bonding force with oxygen, oxygen vacancies after annealing can be suppressed, and a stable film can be formed as a semiconductor.

[0099] The content (atomic ratio) of each metal element in the crystalline oxide semiconductor film can be determined by measuring the amount of each element by ICP (Inductive Coupled Plasma) measurement or XRF (X-ray Fluorescence) measurement. In ICP measurement, an inductively coupled plasma optical emission spectrometer (ICP-OES, manufactured by Agilent) can be used. In XRF measurement, a thin film fluorescence X-ray spectrometer (AZX400, manufactured by Rigaku Corporation) can be used.

[0100] In addition, the content (atomic ratio) of each metal element in the crystalline oxide semiconductor film can be analyzed with an error accuracy within 2 at % by TEM-EDS measurement using an electron microscope, ICP measurement using an inductively coupled plasma emission spectrometer, and SIMS analysis using a sector dynamic secondary ion mass spectrometer.

[0101] In one embodiment, the carrier concentration of the crystalline oxide semiconductor film is 1×10 18 cm -3 Below, preferably 1×10 17 cm -3 Below, more preferably 1×10 16 cm -3 As a result, in the Id-Vg curve when the TFT is driven by applying Vd=0.1V, Vth is close to 0V, indicating good performance of the normally-off characteristic.

[0102] The carrier concentration was measured by the following method.

[0103] The crystalline oxide semiconductor film was cut into 1 cm squares, and electrodes were added at the four corners using In solder to make a Hall effect measurement element, and the carrier concentration was measured by performing AC Hall effect measurement at room temperature using ResiTest 8400 (manufactured by Toyo Technica Corporation).

[0104] The measurement conditions are as follows: As the measurement accuracy, the value of the electron carrier concentration when the F value is 0.9 or more and the absolute value of the Hall voltage phase is 170° to 180° is adopted.

[0105] Current value: 1×10 -12 ~1×10 -3 A

[0106] Magnetic field strength: 0.36T

[0107] The film thickness of the crystalline oxide semiconductor film is preferably 1000 nm or less, more preferably 100 nm or less, further preferably 50 nm or less, further preferably 35 nm or less, and particularly preferably 30 nm or less. By making the film thickness of the crystalline oxide semiconductor film 1000 nm or less, a stable element shape can be obtained when the stacked structure of this embodiment is applied to a TFT.

[0108] In one embodiment, the thickness of the crystalline oxide semiconductor film is preferably 100 nm or less, more preferably 52 nm or less, further preferably 50 nm or less, and particularly preferably 35 nm or less.

[0109] By setting the thickness of the crystalline oxide semiconductor film to 100 nm or less, rare gas atoms supplied from the insulating film in a manufacturing step of a stacked structure described later are appropriately diffused in the crystalline oxide semiconductor film, and a rare gas region can be stably formed in the crystalline oxide semiconductor film.

[0110] In one embodiment, the film thickness of the crystalline oxide semiconductor film is preferably 70 nm or less, more preferably 60 nm or less, further preferably 45 nm or less, and further preferably 35 nm or less.

[0111] By making the film thickness of the crystalline oxide semiconductor film less than 70 nm, in the manufacturing process of the stacked structure described later, the rare gas ions injected into the crystalline oxide semiconductor film by ion implantation or plasma treatment are moderately dispersed in the crystalline oxide semiconductor film, so that a rare gas region can be stably formed in the crystalline oxide semiconductor film.

[0112] On the other hand, the film thickness of the crystalline oxide semiconductor film is, for example, greater than 3 nm, greater than 5 nm, or greater than 8 nm. By making the film thickness of the crystalline oxide semiconductor film greater than 3 nm, high-quality crystals can be grown without being affected by the substrate during annealing crystallization (when forming the crystalline oxide semiconductor film).

[0113] In this specification, the film thickness is measured based on a cross-sectional TEM observation image (sometimes referred to as a “cross-sectional TEM image”).

[0114] In one embodiment, electron beam diffraction of the crystalline oxide semiconductor film includes crystal grains of a bixbyite structure. Since the crystal grains of the bixbyite structure are cubic crystals with good symmetry, the decrease in TFT characteristics (mobility) can be suppressed even across the grain boundary.

[0115] Whether or not the crystal grains in the crystalline oxide semiconductor film have a bixbyite structure is evaluated by observing an electron beam diffraction pattern of a sample obtained by observing a cross-sectional TEM image.

[0116] Specifically, an electron microscope (JEOL "JEM-2800") was used to measure the diffraction pattern of the oxide thin film area observed in the cross-sectional TEM image. The electron beam was irradiated with an irradiation area of ​​about 100 nmφ and an acceleration voltage of 200 kV by limiting the field aperture, and the camera length was set to 2 m.

[0117] Furthermore, in order to identify the crystal structure, the electron beam diffraction pattern of the pyroxene structure of In2O3 was simulated using the electron beam diffraction simulation software ReciPro (free software ver4.641 (2019 / 03 / 04)). In the simulation, the crystal structure data of the pyroxene structure used ICSD (Inorganic Crystal Structure Database: Chemical Information Association) 14388, and the space group: Ia-3, lattice constant: Atomic coordinates In site (0.250, 0.250, 0.250), In site (0.466, 0.000, 0.250), O site (0.391, 0.156, 0.380).

[0118] Furthermore, the camera length was set to 2 m, and the simulation was carried out using 11 reciprocal lattice vectors (100), (111), (110), (211), (311), (221), (331), (210), (310), (321), and (230) as the directions of the incident electron beam.

[0119] The electron beam diffraction pattern of the oxide thin film was compared with the diffraction spot results of the obtained simulation patterns. When the pattern matched any of the 11 simulation patterns, it was determined that the oxide thin film contained crystal grains of a bixbyite structure.

[0120] The crystalline oxide semiconductor film preferably has crystal grains of a bixbyite structure, but as described above, when an electron beam diffraction pattern is confirmed in an oxide thin film region observed with an electron microscope, the oxide thin film can be regarded as a crystalline oxide semiconductor film.

[0121] (Insulating film)

[0122] The material forming the insulating film is not particularly limited, and any commonly used material can be selected, and a laminated film can be used. For example, SiO2, SiNx, silicon oxynitride, Al2O3, Ta2O5, TiO2, MgO, ZrO2, Ga2O3, GeO2, Nd2O3, La2O3, CeO2, K2O, Li2O, Na2O, Rb2O, Sc2O3, Y2O3, HfO2, CaHfO3, PbTiO3, BaTa2O6, SrTiO3, Sm2O3, and AlN can be used. In addition, the oxidation number of each material can also be changed.

[0123] In one embodiment, the insulating film is any one of an oxide film mainly composed of silicon (Si), a nitride film mainly composed of silicon (Si), or an oxynitride film mainly composed of silicon (Si).

[0124] Therefore, in the manufacturing process of the stacked structure described later, when rare gas diffusion occurs from the insulating film, it is easier to obtain a state in which rare gas atoms are appropriately diffused in the crystalline oxide semiconductor film, and a crystalline oxide semiconductor film having the above-mentioned rare gas region can be stably obtained.

[0125] From the viewpoint of easy availability and stability of the insulating film, the insulating film is more preferably an oxide film containing silicon (Si) as a main component.

[0126] An oxide film with silicon (Si) as the main component means that the atomic ratio of silicon (Si) to all cationic atoms contained in the oxide film is greater than 90at%. A nitride film with silicon (Si) as the main component means that the atomic ratio of silicon (Si) to all cationic atoms contained in the nitride film is greater than 90at%. An oxynitride film with silicon (Si) as the main component means that the atomic ratio of silicon (Si) to all cationic atoms contained in the oxynitride film is greater than 90at%.

[0127] The thickness of the insulating film may be, for example, not less than 40 nm, or not less than 50 nm, or not less than 60 nm.

[0128] By making the thickness of the insulating film 40 nm or more, a rare gas region can be stably formed in the crystalline oxide semiconductor film. For example, in the manufacturing process of the stacked structure described later, in the crystalline oxide semiconductor film obtained by the rare gas diffusion from the insulating film, the rare gas atoms diffused into the crystalline oxide semiconductor film are difficult to diffuse out of the crystalline oxide semiconductor film, and the rare gas region can be stably formed in the crystalline oxide semiconductor film.

[0129] The upper limit of the film thickness of the insulating film is not particularly limited, and may be, for example, 300 nm or less, 200 nm or less, or 150 nm or less.

[0130] By setting the film thickness of the insulating film to be 300 nm or less, when the multilayer structure of this embodiment is applied to a TFT, a stable element shape can be obtained.

[0131] The insulating film 12 may be a single-layer film or a laminated film. In the case of a laminated film, the appropriate film thickness described for the insulating film 12 is the film thickness of the laminated film as a whole. In addition, in the case of obtaining a film in the rare gas supply step in the method for manufacturing a laminated structure described later, the film and the layer formed thereon become one and function as a laminated film, that is, the insulating film 12, and as a gate insulating film 24 of the TFT.

[0132] 2. Method for manufacturing laminated structure

[0133] The stacked structure of this embodiment can be manufactured, for example, by forming an oxide thin film with In oxide as the main component on the substrate, buffer layer, insulating layer, etc. constituting the lower layer of the TFT and performing a crystallization process to form a crystalline oxide semiconductor film (crystalline oxide semiconductor film formation process), and then forming an insulating film (insulating film film formation process) in contact with the crystalline oxide semiconductor film. In order to form a rare gas region in the crystalline oxide semiconductor film, a rare gas supply process is performed, for example, between the formation of the crystalline oxide semiconductor film and the formation of the insulating film, or during the formation of the insulating film. The rare gas supply process will be described later.

[0134] The method for forming an oxide thin film mainly composed of In oxide is not particularly limited, and examples thereof include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, ion plating, ALD, PLD, MO-CVD, ICP-CVD, sol-gel method, coating method, and atomized CVD.

[0135] When the film is formed by sputtering, the film may be formed by a device using a planar sputtering cathode or a device using a rotary sputtering cathode.

[0136] As an example of a method for forming an oxide thin film, the oxide thin film can be produced by forming a film by DC sputtering using a sputtering target including an oxide sintered body containing In oxide as a main component.

[0137] The atomic composition ratio of the oxide thin film obtained by sputtering reflects the atomic composition ratio of the oxide sintered body in the sputtering target. Therefore, it is preferable to form a film using a sputtering target including an oxide sintered body having the same atomic composition ratio as the desired oxide thin film.

[0138] In addition, after the oxide thin film is formed, heat treatment may be performed. The heat treatment process is not particularly limited, and a hot air furnace, an IR furnace, a lamp annealing device, a laser annealing device, a thermal plasma device, etc. may be used.

[0139] After annealing, plasma oxidation treatment using N2O or plasma oxidation treatment using O2 may be performed. The apparatus for plasma oxidation treatment is not particularly limited, and PE-CVD and the like may be mentioned.

[0140] The impurity metal of the target used in the sputtering method is preferably 500 ppm or less, more preferably 100 ppm or less. The content of the impurity metal in the target can be measured by ICP or SIMS, as with the crystalline oxide semiconductor film. The "impurities" contained in the target refer to elements that are mixed in the raw materials or manufacturing processes and are not intentionally added, and are trace elements that do not substantially affect the performance of the target and the semiconductor. "Impurity metals" refer to metal elements among the elements that are "impurities".

[0141] In the present embodiment, the sputtering target may be substantially composed of only In and an element selected from Mg, Al, Si, Zn, Ga, Mo, Sn, Ln elements (lanthanide elements), and O. Here, "substantially" means that in addition to the above-mentioned In, the sputtering target may also contain other components within the range that the effect of the present invention brought about by the combination of Mg, Al, Si, Zn, Ga, Mo, Sn, Ln and O is produced.

[0142] Similar to the crystalline oxide semiconductor film having the stacked structure of the present invention described above, in the present embodiment, a more preferred first aspect of the sputtering target is an oxide in which the metal elements are In and Ga, and the atomic ratio satisfies the following formula (11).

[0143] [Ga] / ([In]+[Ga])]<22at% (11)

[0144] A more preferred second embodiment of the sputtering target is an oxide composed of In as a metal element and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In is set to X, the atomic ratio satisfies the following formula (12).

[0145] [X] / ([In]+[X])]<15at% (12)

[0146] A more preferred third embodiment of the sputtering target is an oxide composed of In and Ga as metal elements and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Sn, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In and Ga is set as the added element X, the atomic ratio satisfies the following formulas (13) and (14).

[0147] [Ga] / ([In]+[Ga]+[X])]<22.5at% (13)

[0148] [X] / ([In]+[Ga]+[X])]<8.0at% (14)

[0149] A more preferred fourth embodiment of the sputtering target is an oxide composed of In and Sn as metal elements and one or more elements X selected from B, Al, Sc, Mg, Zn, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In and Sn is set as element X, the atomic ratio satisfies the following formulas (15) and (16).

[0150] [Sn] / ([In]+[Sn]+[X])]<20at% (15)

[0151] [X] / ([In]+[Sn]+[X])]<8.0at% (16)

[0152] A more preferred fifth embodiment of the sputtering target is an oxide composed of In and Zn as metal elements and one or more elements X selected from B, Al, Sc, Mg, Ti, Y, Zr, Mo, Hf, W, Nb, Ta, Ge, Si, La, Ce, Pr, Nd, Sm, Dy, Ho, Er, Tm, Yb and Lu, and when the metal element other than In and Zn is set as element X, the atomic ratio satisfies the following formulas (17) and (18).

[0153] [Zn] / ([In]+[Zn]+[X])]<12at% (17)

[0154] [X] / ([In]+[Zn]+[X])]<8.0at% (18)

[0155] As a preferred embodiment of the sputtering target, the atomic ratio of In to all metal elements contained in the sputtering target ([In] / ([In]+[all metal elements other than In])×100) is 62 at % or more.

[0156] As a preferred embodiment of the sputtering target, the atomic ratio of Ga to all metal elements contained in the sputtering target ([Ga] / ([Ga]+[all metal elements other than Ga])×100) (atomic %: at %) is 30 at % or less.

[0157] As a preferred embodiment of the sputtering target, the total amount of the added element Z (one or more selected from B, Al, Si, Sc, Zn, Ge, Y, Zr, Sn, Sm and Yb) is less than 10 at% relative to the total metal elements contained in the sputtering target ([total amount of added element Z] / ([total amount of added element Z]+[total metal elements other than added element Z])×100) (atomic %: at%).

[0158] The oxide thin film obtained by sputtering film formation using a sputtering target with indium oxide as the main component can be an amorphous oxide thin film. The amorphous oxide thin film is patterned into an island shape by photolithography, and heated to crystallize it before forming a protective film, thereby obtaining a crystalline oxide semiconductor film with a single crystal orientation on the surface crystal.

[0159] Below, with Figure 1 Each step will be described by taking the method for manufacturing the stacked structure shown as an example.

[0160] The stacked structure of the present embodiment can be manufactured, for example, by forming an oxide thin film mainly composed of In oxide on a substrate, a buffer layer, an insulating layer, etc. constituting the lower layer of the TFT, and then performing a crystallization treatment to form a crystalline oxide semiconductor film (a process of forming a crystalline oxide semiconductor film); and forming an insulating film in contact with the crystalline oxide semiconductor film and performing a heat treatment to form an insulating film (a process of forming an insulating film).

[0161] [Step of Forming Crystalline Oxide Semiconductor Film]

[0162] (Film formation of oxide thin films)

[0163] In the film forming process of the oxide thin film, the above-mentioned sputtering target is used, for example, one or more gases selected from the group consisting of argon and oxygen that are substantially free of impurity gases are used as sputtering gas to form an oxide thin film by sputtering. In this process, it is preferred that the sputtering target is mounted on an RF magnetron sputtering device or a DC magnetron sputtering device for sputtering.

[0164] The sputtering gas "does not substantially contain impurity gases" means that, except for the introduction of adsorbed water accompanying the charging of the gas, and gases that cannot be removed (inevitable impurity gases) such as leakage or adsorbed gases in the chamber, no impurity gases other than the sputtering gas are actively introduced. If possible, it is preferred to exclude impurities from the gas (sputtering gas) introduced during sputtering film formation.

[0165] The proportion of the impurity gas in the sputtering gas is preferably 0.1 volume % or less, and more preferably 0.05 volume % or less. As long as the proportion of the impurity gas is 0.1 volume % or less, crystallization of the oxide thin film will proceed without any problem.

[0166] The purity of high-purity argon and high-purity oxygen, which are examples of sputtering gas, is preferably 99% by volume or more, more preferably 99.9% by volume or more, and even more preferably 99.99% by volume or more.

[0167] The gas introduced during sputtering film formation (sputtering gas) is not particularly limited, and examples thereof include argon, nitrogen, oxygen, water, hydrogen, or a mixed gas containing two or more of these gases.

[0168] As an example, the oxygen partial pressure in the mixed gas when using argon and oxygen is preferably greater than 0 volume % and less than 50 volume %, and more preferably greater than 0 volume % and less than 20 volume %. If the oxygen partial pressure exceeds 0 volume % and is less than 50 volume %, it is easy to crystallize and semiconductor when heated. By changing the oxygen partial pressure, the degree of oxidation of the oxide film, that is, the degree of crystallization, can be adjusted. The oxygen partial pressure can be appropriately selected as needed.

[0169] As an example, the water partial pressure in the mixed gas when using argon and water is preferably more than 0.03 volume % and less than 10 volume %, more preferably more than 0.03 volume % and less than 5 volume %. If the water partial pressure exceeds 0.03 volume % and is less than 5 volume %, it is easy to crystallize and semiconductorize when heated. In addition, a mixed gas of hydrogen and oxygen can also be used instead of water.

[0170] By heating the oxide thin film obtained by sputtering in a heat treatment process described later, crystals can be grown (for example, columnar crystals relative to the lower layer). By applying the crystalline oxide semiconductor film formed as described above to a small TFT, the electron carrier injection property is excellent during driving, and the result shows high mobility.

[0171] The film thickness of the oxide thin film (crystalline oxide semiconductor film) is preferably 1000 nm or less, more preferably 100 nm or less, further preferably 50 nm or less, further preferably 35 nm or less, and particularly preferably 30 nm or less. By making the film thickness of the crystalline oxide semiconductor film 1000 nm or less, a stable element shape can be obtained when the stacked structure of this embodiment is applied to a TFT.

[0172] In the insulating film formation process described later, when rare gas atoms are diffused from the insulating film into the oxide semiconductor film, the film thickness of the oxide thin film (crystalline oxide semiconductor film) is preferably less than 100 nm, more preferably less than 52 nm, further preferably less than 50 nm, and particularly preferably less than 35 nm.

[0173] By making the film thickness of the oxide thin film (crystalline oxide semiconductor film) less than 100 nm, in the insulating film formation process described later, when rare gas diffusion occurs from the insulating film, it is easy to obtain a state in which the rare gas atoms are moderately diffused in the crystalline oxide semiconductor film, and a crystalline oxide semiconductor film having a region with the above-mentioned rare gas concentration can be stably obtained.

[0174] In one embodiment, the thickness of the crystalline oxide semiconductor film is preferably 70 nm or less, more preferably 60 nm or less, further preferably 45 nm or less, and particularly preferably 35 nm or less.

[0175] By making the film thickness of the crystalline oxide semiconductor film less than 70 nm, in the manufacturing process of the stacked structure described later, the rare gas ions injected into the crystalline oxide semiconductor film by ion implantation or plasma treatment are moderately dispersed in the crystalline oxide semiconductor film, and the above-mentioned rare gas concentration area can be stably formed in the crystalline oxide semiconductor film.

[0176] On the other hand, the film thickness of the oxide thin film (crystalline oxide semiconductor film) is, for example, 3 nm or more, 5 nm or more, or 8 nm or more. By making the film thickness of the oxide thin film (crystalline oxide semiconductor film) 3 nm or more, high-quality crystals can be grown without being affected by the substrate during annealing and crystallization (when forming a crystalline oxide semiconductor film).

[0177] (Heat Treatment of Oxide Thin Films)

[0178] After the oxide thin film is formed, a heat treatment is performed. This heat treatment is sometimes called annealing. The annealing of the oxide thin film can be performed before or after the formation of the insulating film described later, but is preferably performed before the formation.

[0179] By performing annealing before forming the insulating film, oxygen and hydrogen diffuse during annealing to obtain columnar and high-quality crystals, and after forming the insulating film, a small TFT with a small interface electron trap level and high mobility can be obtained.

[0180] The temperature of the heat treatment of the oxide thin film is preferably 250°C to 500°C, more preferably 280°C to 470°C, and further preferably 300°C to 450°C.

[0181] If the heat treatment temperature after the oxide thin film is formed is 250°C or higher, the oxide thin film is easily crystallized. If the heat treatment temperature after the oxide thin film is formed is 500°C or lower, abnormal crystal growth and enlargement of crystal grains can be prevented, and the crystal grain size can be controlled to be small.

[0182] The heating time in the heat treatment step of the oxide thin film is preferably 0.1 hour to 5 hours, more preferably 0.3 hour to 3 hours, and even more preferably 0.5 hour to 2 hours.

[0183] Even if the heating time in the heat treatment process is less than 0.1 hours, the crystallization of the oxide film proceeds to a certain extent. However, if it is more than 0.1 hours, atomic diffusion in the oxide film proceeds easily and it is easy to stabilize after crystallization, so a stable crystalline oxide semiconductor film can be easily obtained.

[0184] When the heating time in the heat treatment step is 5 hours or less, excellent economic efficiency is achieved.

[0185] The "heating time" refers to the time (holding time) during which a predetermined maximum temperature is maintained during heat treatment.

[0186] The temperature increase rate in the heat treatment step of the oxide thin film is preferably 2° C. / minute to 40° C. / minute, more preferably 3° C. / minute to 20° C. / minute.

[0187] When the temperature increase rate in the heat treatment step of the oxide thin film is 2° C. / minute or more, the production efficiency of the oxide thin film is improved compared to a case where the temperature increase rate is less than 1° C. / minute.

[0188] When the temperature increase rate in the heat treatment step of the oxide thin film is 40° C. / min or less, the metal element diffuses uniformly during crystallization, and crystals in which the metal is not segregated at the grain boundaries can be formed.

[0189] In addition, the temperature rise rate in the heat treatment process is different from the value calculated based on the set temperature and set time of the furnace, and is the value obtained by dividing the actual temperature of the oxide film by the time. The actual temperature of the oxide film can be obtained by measuring the area within 1 cm of the oxide film in the furnace with a thermocouple, for example.

[0190] The heat treatment step of the oxide thin film is preferably performed in an atmosphere with a humidity of 10% or more at 25° C. By performing the heat treatment step in an atmosphere with a humidity of 10% or more, hydrogen and oxygen diffuse in the film during annealing, thereby promoting crystallization.

[0191] The heat treatment process of the oxide thin film is preferably performed after the patterning of the oxide thin film. By performing the heat treatment process after the patterning, the excess oxygen present in the film during film formation and the organic matter attached during patterning can be removed while promoting crystallization. As a result, a film with no organic matter, excess oxygen and fewer crystal defects in the crystal grains can be formed, and an oxide thin film with fewer electron traps and good conductive properties can be formed.

[0192] The crystal defects of the film after the heat treatment process of the oxide thin film can be evaluated by defect analysis such as cathode luminescence (CL). When there are many defects originating from oxygen, the luminescence of 680nm light is strongly detected. In order to obtain an oxide thin film with few electron traps and good conductive properties, it is necessary to adjust the film formation method and annealing conditions to obtain a film quality in which CL luminescence is as undetectable as possible.

[0193] In addition, the heat treatment process of the oxide thin film can also be performed multiple times. For example, the above-mentioned heat treatment process (first heat treatment process) can be performed after the patterning of the oxide thin film, and then after the TFT element is manufactured, a heat treatment process (second heat treatment process) is performed as the final process. The second heat treatment process is preferably performed at an annealing temperature higher than that of the first heat treatment process.

[0194] [Rare gas supply process]

[0195] Examples of a method for forming a rare gas region in a crystalline oxide semiconductor film include a method of performing a rare gas supply treatment on the crystalline oxide semiconductor film, a method of performing a surface treatment (sometimes referred to as a channel layer pretreatment) on the crystalline oxide semiconductor film and then performing a rare gas supply treatment, and the like.

[0196] (Channel layer pre-treatment)

[0197] As the channel layer pretreatment, there can be mentioned a method of forming a film on the crystalline oxide semiconductor film by sputtering and annealing the obtained film.

[0198] As a sputtering target for sputtering film formation used for channel layer pretreatment, a sputtering target for forming an insulating film can be mentioned, among which SiO2 is preferred.

[0199] The sputtering temperature during the channel layer pretreatment is not particularly limited, and the temperature during the formation of the insulating film can be used.

[0200] The sputtering atmosphere is not particularly limited, and may or may not contain a rare gas element, or may be air.

[0201] The film thickness of the film formed by the channel layer pretreatment may be 1 to 20 nm, or 3 to 15 nm.

[0202] By making the film thickness of the pretreatment layer 1 nm or more, it is possible to suppress excessive diffusion of rare gas atoms from the film that serves as a rare gas supply source into the crystalline oxide semiconductor film. In addition, by making the film thickness of the film formed by the channel layer pretreatment 15 nm or less, the diffusion of rare gas atoms from the film that serves as a rare gas supply source into the crystalline oxide semiconductor film proceeds smoothly.

[0203] The temperature during annealing is not particularly limited, and is, for example, in the range of 250 to 500°C, preferably 350 to 450°C, and more preferably about 400°C.

[0204] By performing the channel layer pretreatment, diffusion of rare gas atoms from the film serving as a rare gas supply source into the crystalline oxide semiconductor film proceeds smoothly.

[0205] Alternatively, an insulating film formed by CVD instead of sputtering may be used as a channel layer pretreatment. When the film is formed at a temperature of 240° C. to 450° C. during CVD, the subsequent heat treatment (annealing) step may be omitted.

[0206] (Rare gas supply process)

[0207] Examples of the rare gas supply process include a method of performing sputtering film formation in an atmosphere containing a rare gas element, plasma treatment in a rare gas atmosphere, and ion implantation using rare gas ions.

[0208] When utilizing sputtering in an atmosphere containing a rare gas element, the sputtering target used is not particularly limited, and a sputtering target generally used for forming an insulating film can be used, and among these, SiO 2 is preferred.

[0209] The type of the rare gas used as the film formation atmosphere gas is not particularly limited, and examples thereof include Ar, He, Ne, Kr, etc. From the viewpoint of stability in the crystalline oxide semiconductor film, Ar and He are preferred, and Ar is more preferred.

[0210] The atmosphere containing the rare gas element may contain only the rare gas element, or may contain a gas such as O 2 in addition to the rare gas element.

[0211] As an example, when argon and oxygen are used as the film-forming atmosphere gas, the argon partial pressure in the mixed gas is preferably 50 volume % or more, and more preferably 70 volume % or more. If the argon partial pressure is 70 volume % or more and 90 volume % or less, a part of the argon gas is easily mixed into the insulating film during sputtering film formation, and the argon gas is easily diffused toward the crystalline oxide semiconductor film side.

[0212] When argon and oxygen are used, the oxygen partial pressure in the mixed gas is preferably greater than 0% by volume and less than 50% by volume, and more preferably greater than 0% by volume and less than 40% by volume.

[0213] The thickness of the obtained film is not particularly limited, and may be 10 nm or more, 30 nm or more, 40 nm or more, 80 nm or more, or 90 nm or more. Thus, it is easy to mix a sufficient amount of rare gas atoms into the film obtained by sputtering, and it is easy to suppress the rare gas atoms that temporarily diffuse from the film into the crystalline oxide semiconductor film from diffusing outward to the outside of the crystalline oxide semiconductor film.

[0214] The upper limit of the film thickness of the obtained film is not particularly limited, and may be, for example, 300 nm or less, 200 nm or less, or 150 nm or less.

[0215] By setting the film thickness of the obtained film to be 300 nm or less, when the stacked structure obtained in this embodiment is applied to a TFT, a stable element shape can be obtained.

[0216] When the film is formed by sputtering, it is preferable not to perform heat treatment (annealing) after the film formation.

[0217] When heat treatment (annealing) is performed, the rare gas (for example, argon) component diffused into the oxide semiconductor film may diffuse from the oxide semiconductor film to the insulating film side and further diffuse outward from the insulating film surface.

[0218] After film formation in the rare gas supply process, another film (for example, a film for a gate electrode) is formed over the film without performing heat treatment (annealing), whereby a rare gas region can be stably formed in the crystalline oxide semiconductor film.

[0219] However, annealing can be performed as long as the temperature is such that the rare gas does not diffuse outward from the crystalline oxide semiconductor film even after sputtering, specifically, lower than 400° C., preferably lower than 300° C., and more preferably lower than 250° C.

[0220] In the case of plasma treatment in a rare gas atmosphere, the type of rare gas element in the atmosphere is not particularly limited, and may be one or two or more rare gas elements. Among them, Ar is preferred.

[0221] Specifically, Ar plasma treatment is performed on the surface of the crystalline oxide semiconductor film directly or through other layers, and Ar in the plasma treatment atmosphere is reduced. + Ions (a rare gas supply source) are taken into the film of the crystalline oxide semiconductor film.

[0222] The apparatus for the Ar plasma treatment is not particularly limited, and for example, a dry etching apparatus or the like can be used.

[0223] Ar plasma treatment is not particularly limited as long as it is performed in an argon atmosphere. For example, when plasma treatment is performed at a power of 10 to 500 W, preferably 30 to 300 W, the plasma treatment is preferably performed for 30 to 200 seconds, more preferably 50 to 150 seconds.

[0224] A film is not formed during the plasma treatment, but an insulating film is formed after the plasma treatment.

[0225] When ion implantation using rare gas ions is used, the type of rare gas ions used is not particularly limited, but Ar + ion.

[0226] The dose of rare gas ions implanted can be 1×10 15 ions / cm 2 ~15×10 15 ions / cm 2 , or 0.2×10 15 ions / cm 2 ~12×10 15 ions / cm 2 , or 0.3×10 16 ions / cm 2 ~10×10 15 ions / cm 2 .

[0227] When a rare gas region is formed in the crystalline oxide semiconductor film by ion implantation, the implantation energy may be 0.1 keV to 1000 keV, or 1 keV to 100 keV, or 5 keV to 50 keV.

[0228] In the case of ion implantation, no film is formed, and an insulating film is formed after ion implantation in the crystalline oxide semiconductor film. In addition, regarding ion implantation, a rare gas supply process can also be performed on the crystalline oxide semiconductor film after the insulating film is formed.

[0229] By performing the rare gas supply process, the rare gas diffuses into the crystalline oxide semiconductor film, thereby forming a rare gas region in the crystalline oxide semiconductor film.

[0230] In addition, the film formed in the channel layer pre-process, the film formed in the rare gas supply process, and the film formed in the insulating film forming step are integrated in the TFT and function as a gate insulating film.

[0231] [Insulating film forming step]

[0232] The insulating film in the stacked structure of the present invention may be a film formed in the rare gas supplying step, or may be a film formed separately on the crystalline oxide semiconductor film after the rare gas supplying step, or may be a film formed in the rare gas supplying step and a film formed separately thereon. The film formed in the rare gas supplying step and the film formed separately thereon are integrated to function as the gate insulating film 24 in the TFT.

[0233] Alternatively, the film formed in the rare gas supplying step and a film formed separately thereon may be integrated to function as a layer other than the gate insulating film, for example, a protective film or a buffer layer.

[0234] (Film formation of insulating film)

[0235] The insulating film forming method is not particularly limited. Examples of the production method include PE-CVD, ALD, PLD, MO-CVD, RF sputtering, ICP sputtering, reactive sputtering, ICP-CVD, ion plating, sol-gel method, coating method, atomized CVD, etc. In addition, as a gas type for PE-CVD, tetraethoxysilane (TEOS) can be used in addition to silane (SiH4).

[0236] When the insulating film is formed by sputtering, the film is formed using a sputtering target including an oxide sintered body having the same atomic composition ratio as that of a desired insulating film.

[0237] As the sputtering target, for example, a target containing a silicon (Si)-containing compound (for example, SiO 2 , SiN x , silicon oxynitride, etc.) as a main component can be used.

[0238] As the sputtering gas, similarly to the above-mentioned film formation of the oxide thin film, it is preferable to use one or more gases selected from the group consisting of argon and oxygen which do not substantially contain an impurity gas.

[0239] The appropriate ranges of the ratio of the impurity gas in the sputtering gas and the purity of the high-purity argon and high-purity oxygen in the sputtering gas are the same as those in the above-mentioned film formation of the oxide thin film.

[0240] When the crystalline oxide semiconductor film is subjected to ion implantation or Ar plasma treatment as the rare gas supply treatment, the film formation atmosphere gas introduced when the insulating film is formed may not necessarily contain a rare gas (eg, argon), but preferably contains a rare gas.

[0241] The sputtering film formation atmosphere gas is not particularly limited, and examples thereof include argon, nitrogen, oxygen, water, hydrogen, or a mixed gas containing two or more of these gases.

[0242] The preferred range of oxygen partial pressure in the mixed gas when using argon and oxygen is the same as the description of the gas introduced during sputtering film formation described in the above-mentioned rare gas supply process. By changing the oxygen partial pressure, the atomic ratio of silicon (Si) contained in the insulating film relative to all atoms can be adjusted. The oxygen partial pressure can be appropriately selected as needed.

[0243] When the insulating film is formed by chemical vapor deposition (CVD), the temperature during the CVD treatment is preferably 240° C. to 500° C., more preferably 280° C. to 470° C., and even more preferably 300° C. to 450° C. When the temperature during the CVD treatment is within the above range, an insulating film can be stably obtained.

[0244] In addition, the temperature during CVD processing refers to the temperature of the substrate in the CVD apparatus.

[0245] (Heat treatment of insulating film)

[0246] In the rare gas supplying step, when the film formed by sputtering is an insulating film, it is preferable not to perform heat treatment on the insulating film. By not performing heat treatment, it is possible to prevent the rare gas from diffusing outward from the crystalline oxide semiconductor film.

[0247] When plasma treatment is used in the rare gas supplying step, heat treatment of the insulating film formed separately may or may not be performed, but is preferably not performed. By not performing heat treatment, it is possible to prevent the rare gas from diffusing outward from the crystalline oxide semiconductor film.

[0248] When ion implantation is used in the rare gas supplying step, heat treatment of an insulating film formed separately may be performed.

[0249] When the insulating film is formed by chemical vapor deposition (CVD), the obtained insulating film may or may not be subjected to heat treatment.

[0250] When heat treatment is performed on the insulating film, the temperature of the heat treatment after the insulating film is formed is preferably 250° C. to 500° C., more preferably 280° C. to 470° C., and further preferably 300° C. to 450° C.

[0251] From the viewpoint of suppressing outdiffusion of a rare gas from the crystalline oxide semiconductor film, the temperature is preferably 400° C. or lower, and more preferably 350° C. or lower.

[0252] The heating time in the heat treatment step after the insulating film is formed is preferably 0.1 hour to 5 hours, more preferably 0.3 hour to 3 hours, and even more preferably 0.5 hour to 2 hours.

[0253] The temperature increase rate in the heat treatment step after the insulating film is formed is preferably 2° C. / minute to 40° C. / minute, more preferably 3° C. / minute to 20° C. / minute.

[0254] The heat treatment step after forming the insulating film is preferably performed in an air atmosphere at 25° C. and a humidity of 10% or more.

[0255] By performing heat treatment (annealing treatment) after the formation of the insulating film, hydrogen contained in the insulating film diffuses into the crystalline oxide semiconductor film, and crystal defects existing on the surface of the crystalline oxide semiconductor film are terminated with hydroxyl groups, resulting in a crystalline oxide semiconductor film with few electron traps and good conductive properties.

[0256] 3. Thin Film Transistor (TFT)

[0257] The TFT of this embodiment includes the above-mentioned stacked structure of the present invention.

[0258] In one embodiment, the TFT has a buffer layer, a channel layer stacked on the buffer layer, a source electrode and a drain electrode respectively connected to the channel layer, and a gate electrode stacked on the channel layer via a gate insulating film, the channel layer is a crystalline oxide semiconductor film included in the stacked structure of the present invention, and the gate insulating film is an insulating film included in the stacked structure of the present invention.

[0259] In the following Figure 2 and Figure 3 , the following configuration is shown: the two end sides of the channel layer, that is, the vicinity of the region connected to the source electrode and the drain electrode, are the low resistance region A of the crystalline oxide semiconductor film, and the region in contact with the lower surface of the gate insulating film is the high resistance region B. That is, the configuration in which the gate insulating film is formed in the high resistance region B, and the source electrode and the drain electrode are formed in the low resistance region A is shown.

[0260] As the structure of the TFT of this embodiment, for example, a conventionally known structure can be adopted.

[0261] The TFT of this embodiment can be manufactured by adopting the manufacturing method of the stacked structure described above. That is, a manufacturing method has a crystalline oxide semiconductor film forming step and an insulating film forming step, the crystalline oxide semiconductor film forming step includes: using a sputtering target, using one or more gases selected from the group consisting of argon, nitrogen, hydrogen, water and oxygen that are substantially free of impurity gases as a sputtering gas, and forming an oxide thin film by sputtering (sometimes referred to as an oxide thin film forming step); and a step of heat treating the oxide thin film (sometimes referred to as an oxide thin film heat treatment step), the insulating film forming step includes: for example, using a sputtering target mainly composed of silicon dioxide to form an insulating film by sputtering on a crystalline oxide semiconductor film (sometimes referred to as an insulating film forming step); and a step of heat treating the insulating film (sometimes referred to as an insulating film heat treatment step). The conditions of each film forming step and heat treatment step are as described above. The source electrode, drain electrode, gate electrode and gate insulating film can be formed by known materials and formation methods.

[0262] In the stacked structure of one embodiment, the crystalline oxide semiconductor film has high mobility.

[0263] By using this stacked structure for the channel layer of a TFT, high mobility and an appropriate S value (eg, approximately 0.8 V / dec.) can be stably obtained, and when used as a drive transistor for supplying current to an OLED, for example, excellent grayscale performance can be obtained.

[0264] In this specification, the mobility when Vd=20V is applied is defined as the saturation mobility. Specifically, the calculation can be performed by generating a transfer characteristic Id-Vg graph when Vd=20V is applied, calculating the transconductance (Gm) at each Vg, and finding the mobility using the equation in the saturation region.

[0265] In the following description, current Id is the current between the source electrode and the drain electrode, voltage Vd is the voltage applied between the source electrode and the drain electrode (drain voltage), and voltage Vg is the voltage applied between the source electrode and the gate electrode (gate voltage).

[0266] The shape of the thin film transistor of this embodiment is not particularly limited, and is preferably a top-gate transistor, a back-channel etched transistor, an etch-stop transistor, etc. In addition, these transistors may be self-aligned.

[0267] In one embodiment, a top-gate transistor is preferred.

[0268] Hereinafter, the embodiments will be described with reference to the accompanying drawings, etc. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and various changes can be made to the plans and details without departing from the gist and scope thereof. Therefore, the present invention is not limited to the following descriptions of the embodiments and is not interpreted.

[0269] In the drawings, the size, thickness of the layer, and the region are sometimes exaggerated for clarity. Therefore, the present invention is not limited to the size, thickness of the layer, and the region shown in the drawings. In addition, the drawings are diagrams schematically showing ideal examples, and the present invention is not limited to the shapes and values ​​shown in the drawings.

[0270] Figure 2 This is a schematic cross-sectional view of an example of a TFT according to this embodiment.

[0271] TFT50 is a top-gate TFT having a substrate 21 , a buffer layer 22 , a channel layer (crystalline oxide semiconductor film) 11 , an ITO layer 23 , a gate insulating film (insulating film) 24 , a gate electrode 25 , an interlayer insulating film 26 , a source electrode 27 , a drain electrode 28 and a protective film 29 .

[0272] The TFT 50 has a structure in which a substrate 21, a buffer layer 22, and a channel layer (crystalline oxide semiconductor film) 11 are stacked in this order. The channel layer 11 has a high resistance region 11B in the central portion, and a gate insulating film 24 (insulating film) and a gate electrode 25 are stacked in this order on the high resistance region 11B. The gate insulating film 24 is an insulating film that blocks conduction between the gate electrode 25 and the crystalline oxide semiconductor film 11.

[0273] On both sides of the high resistance region 11B are the low resistance regions 11A-1 and 11A-2 of the channel layer 11. The low resistance regions 11A-1, 11A-2 and the gate electrode 25 are covered with an ITO layer 23 and an interlayer insulating film 26. The ITO layer 23 is used to form the low resistance region of the channel layer 11.

[0274] Specifically, the low resistance regions 11A-1 and 11A-2 are formed by reducing the resistance of the target portion of the channel layer 11 by heat treatment (annealing) in the presence of the ITO layer 23. The region without the ITO layer 23 becomes the high resistance region B.

[0275] The source electrode 27 and the drain electrode 28 are connected to the low resistance regions 11A-1 and 11A-2 respectively through contact holes provided in the ITO layer 23 and the interlayer insulating film 26. The source electrode 27 and the drain electrode 28 are conductive terminals for allowing source current and drain current to flow through the channel layer 11.

[0276] A protective film 29 is provided so as to cover the interlayer insulating film 26 , the source electrode 27 , the drain electrode 28 and other TFT constituent layers.

[0277] The TFT of this embodiment can be improved by a known structure.

[0278] For example, although in Figure 2 Although not shown in the figure, in TFT50, a layer may be provided between substrate 21 and buffer layer 22 as shown in FIG. Figure 3 The light shielding layer 31 may be formed as shown, or may be formed as an intermediate layer of the buffer layer 22 in which a plurality of layers are stacked.

[0279] Figure 3 This is a schematic cross-sectional view of another example of the TFT of this embodiment.

[0280] TFT51 has the same structure as TFT50 except that a light shielding layer 31 is provided between substrate 21 and buffer layer 22. Light shielding layer 31 is formed to suppress malfunction of TFT caused by light. Light shielding layer may be connected to source electrode 27 or gate electrode 25.

[0281] In addition, Figure 2 In the embodiment, the two end sides of the channel layer 11, that is, the areas near the areas connected to the source electrode 27 and the drain electrode 28, are set as the low resistance areas 11A of the crystalline oxide semiconductor film, and the areas in contact with the lower surface of the gate insulating film 24 are set as the high resistance areas 11B. Such a configuration example is shown as an example of the TFT of the present invention, but the TFT of the present invention is not limited to this configuration. That is, the TFT of the present invention can also use a crystalline oxide semiconductor film with a uniform resistance value in the surface direction as the channel layer 11. In this case, it can be as follows Figure 4 As shown, the ITO layer 23 is not formed.

[0282] Figure 4 This is a schematic cross-sectional view of another example of the TFT of this embodiment.

[0283] TFT52 has the same structure as TFT50 except that the channel layer (crystalline oxide semiconductor film) 11 is a layer without a resistance boundary (the channel layer (crystalline oxide semiconductor film) 11 is not divided into a low resistance region 11A and a high resistance region 11B) and the ITO layer 23 is not provided.

[0284] In this embodiment, when the TFT is a small TFT, the crystalline oxide semiconductor film as a channel layer for the source electrode and the drain electrode has, for example, a channel length (L length; in Figure 2 In the contact region between the channel layer 11 and the gate insulating layer 24, the length in the direction of the source electrode 27-drain electrode 28) is 1 μm or more and 50 μm or less, and the channel width (W length; in Figure 2In the embodiment, the length of the channel layer 11 in the contact region with the gate insulating layer 24 in the direction perpendicular to the source electrode 27 - drain electrode 28 direction) is greater than or equal to 1 μm and less than or equal to 80 μm.

[0285] The TFT of this embodiment can be improved by a known structure.

[0286] The material forming the substrate is not particularly limited, and any commonly used material can be selected. For example, a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate can be used. In addition, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SIO (Silicon In Insulator) substrates can also be used, and substrates obtained by providing semiconductor elements on these substrates can also be used as substrates.

[0287] In addition, a flexible substrate can be used as a substrate. In addition, as a method of providing a TFT on a flexible substrate, in addition to a method of directly manufacturing the TFT on the flexible substrate, there is also a method of manufacturing the TFT on a non-flexible substrate, peeling off the TFT, and providing it on the flexible substrate. In this case, a peeling layer can be provided between the non-flexible substrate and the TFT.

[0288] The buffer layer 22 may be composed of a single layer or may have a stacked structure of two or more layers. In addition, a metal layer may be provided between the buffer layer 22 and the substrate 21 .

[0289] Among them, it is preferred that the channel layer 11 and the buffer layer 22 are as follows Figure 2 Directly connected as shown.

[0290] The material forming the buffer layer is not particularly limited, and any commonly used material can be selected, and a laminated film can be used as the buffer layer. For example, SiO2, SiN x , silicon oxynitride, Al2O3, Ta2O5, TiO2, MgO, ZrO2, Ga2O3, GeO2, Nd2O3, La2O3, CeO2, K2O, Li2O, Na2O, Rb2O, Sc2O3, Y2O3, HfO2, CaHfO3, PbTiO3, BaTa2O6, SrTiO3, Sm2O3, AlN. In addition, the oxidation number of each material may also be changed.

[0291] The light shielding layer 31 may be connected to the source electrode 27 and may also be connected to the gate electrode 25 .

[0292] The material forming the light shielding layer is not particularly limited, and any commonly used material can be selected. Specifically, metal electrodes such as Al, Ag, Cu, Cr, Ni, Co, Mo, Au, Ti, Zr, Ru, Y, Nb, Ta, and W, and metal electrodes composed of alloys containing two or more of these metals can be cited. In addition, stacked electrodes of two or more layers can also be used.

[0293] exist Figure 3 In the embodiment of the present invention, a second buffer layer may be provided between the light shielding layer 31 and the substrate 21. There is no particular limitation on the material forming the second buffer layer, and any commonly used material may be selected arbitrarily, and a laminated film may be used as the second buffer layer. As the material of the second buffer layer, for example, SiO2, SiNx, silicon oxynitride, Al2O3, Ta2O5, TiO2, MgO, ZrO2, Ga2O3, GeO2, Nd2O3, La2O3, CeO2, K2O, Li2O, Na2O, Rb2O, Sc2O3, Y2O3, HfO2, CaHfO3, PbTiO3, BaTa2O6, SrTiO3, Sm2O3, and AlN may be used. In addition, the oxidation number of each material may also be changed.

[0294] As a material for forming the gate insulating film, the materials described as the material of the insulating film can be used.

[0295] The materials forming the drain electrode, the source electrode and the gate electrode are not particularly limited, and any commonly used materials can be selected. Specifically, transparent electrodes such as ITO, IZO, ZnO, SnO2, metal electrodes such as Al, Ag, Cu, Cr, Ni, Co, Mo, Au, Ti, Zr, Ru, Y, Nb, Ta, W, or metal electrodes composed of alloys containing two or more of these metals can be cited. In addition, stacked electrodes of more than two layers can also be used.

[0296] The material forming each interlayer insulating film is not particularly limited, and any commonly used material can be selected, and a stacked film can be used as the interlayer insulating film.

[0297] For example, SiO2, SiN x , silicon oxynitride, Al2O3, Ta2O5, TiO2, MgO, ZrO2, Ga2O3, GeO2, Nd2O3, La2O3, CeO2, K2O, Li2O, Na2O, Rb2O, Sc2O3, Y2O3, HfO2, CaHfO3, PbTiO3, BaTa2O6, SrTiO3, Sm2O3, AlN. In addition, the oxidation number of each material may also be changed.

[0298] Regardless of the structure of the TFT, it is preferred to provide a protective film on the drain electrode, the source electrode, and the conductive region. By providing the protective film, it is easy to improve the durability even when the TFT is driven for a long time.

[0299] The method for producing the insulating film of the buffer layer, gate insulating film, interlayer insulating film, and protective film is not particularly limited. Examples of the production method include PE-CVD, ALD, PLD, MO-CVD, RF sputtering, ICP sputtering, reactive sputtering, ICP-CVD, ion plating, sol-gel method, coating method, atomized CVD, etc. In addition, as a gas type for PE-CVD, tetraethoxysilane (TEOS) can be used in addition to silane (SiH4).

[0300] For example, when formed by PE-CVD, it sometimes becomes a process based on high temperature. In addition, the protective film or insulating film often contains impurity gas just after film formation, and it is preferably subjected to heat treatment (annealing treatment). By removing the impurity gas by heat treatment, a stable protective film or insulating film is formed, and a TFT with high durability is easily formed.

[0301] (Characteristics of Thin Film Transistors)

[0302] The saturation mobility of the TFT is preferably 10.0 cm 2 / V·s or more, more preferably 20.0cm 2 / V·s or above.

[0303] By setting the saturation mobility of the TFT to 10.0 cm 2 / V·s or above, it is possible to achieve high-definition, high-frame-rate, and large-area displays.

[0304] The saturation mobility of the TFT is obtained from the transfer characteristics when a drain voltage of 20 V is applied. The method for measuring the saturation mobility of the TFT is described in detail in the examples.

[0305] The threshold voltage (Vth) is preferably -3.0V to 3.0V, more preferably -2.0V to 2.0V, and even more preferably -1.0V to 1.0V. If the threshold voltage (Vth) is -3.0V to 3.0V, a Vth correction circuit can be installed in the TFT to correct Vth = 0V. When the TFT obtained in this way is installed in a panel, the display can be driven without causing uneven brightness and screen burn-in.

[0306] The threshold voltage (Vth) can be calculated from the transfer characteristic graph with Id=10 -9 A is defined by Vg.

[0307] The on-off ratio is preferably 106 More than 10 7 More than 10 8 If the on-off ratio is 10 6 If the on-off ratio is 10 8 If the on-off ratio can be 10 10 Above and make the shutdown current 10 -12 A or less, a display element having excellent low power consumption and capable of being driven at a low frequency of about 1 Hz can be provided.

[0308] The on-off ratio was obtained by determining the ratio [on-current value / off-current value] by setting the value of Id when Vd=10V and Vg=-10V as the off-current value and the value of Id when Vd=10V and Vg=20V as the on-current value.

[0309] The shutdown current value is preferably 10 -10 A or less, more preferably 10 -11 A or less, more preferably 10 -12 A or less. If the cut-off current value is 10 -10 A or less, it is possible to drive an organic EL with a large contrast. In addition, when used for a transfer transistor or a reset transistor of a CMOS image sensor, it is possible to extend the image retention time or improve the sensitivity.

[0310] A transistor with a low S value has excellent low power consumption, and thus a transistor with a low S value generally tends to be good.

[0311] On the other hand, when used as a driving transistor for an OLED or the like that operates as a display element driven by current, for example, the S value is preferably a value of about 0.8 V / dec. When used as a driving transistor for an OLED, if the S value is 0.3 V / dec. or less, it means that the current value changes by more than one digit when the Vg value changes by 0.3 V, so sometimes the current value is controlled by a small voltage change, and grayscale control of the OLED becomes difficult.

[0312] For example, when used as a driving transistor of a current-driven display element such as an OLED, the S value is preferably 0.8±0.5V / dec, more preferably 0.8±0.3V / dec, and further preferably 0.8±0.1V / dec. By making the S value within the above range, the phenomenon that the Vg applied voltage becomes higher during grayscale control, which is a problem that requires improvement more than power consumption, can be suppressed.

[0313] The S value (Swing Factor) is a value indicating how steeply the drain current rises from the off state to the on state when the gate voltage is increased from the off state. As defined by the following formula, the increase in gate voltage when the drain current rises by 1 bit (10 times) is set to the S value.

[0314] S value = dVg / dlog(Ids)

[0315] The smaller the S value, the steeper the rise. If the S value is large, the gate voltage required to switch from on to off becomes higher. The method for measuring the S value of a TFT is described in detail in the examples.

[0316] The TFT of this embodiment can be suitably used in electronic devices such as solar cells, liquid crystal elements, display elements such as organic electroluminescent elements and inorganic electroluminescent elements, power semiconductor elements, and touch panels.

[0317] The thin film transistor of this embodiment can also be applied to various integrated circuits such as field effect transistors (MOSFET, MESFET), logic circuits, storage circuits, and differential amplifier circuits, and can be applied to electronic equipment, electrical equipment, vehicles, or power machines, etc. Furthermore, in addition to field effect transistors, the thin film transistor involved in this embodiment can also be applied to static induction transistors and Schottky barrier transistors.

[0318] The thin film transistor according to this embodiment can be suitably used in display devices such as portable or vehicle-mounted display devices, solid-state imaging devices, etc. Furthermore, the thin film transistor according to this embodiment can also be suitably used as a transistor for a flat panel detector for an X-ray image sensor for medical use.

[0319] Furthermore, the crystalline oxide semiconductor film according to this embodiment can also be applied to a Schottky diode, a resistance variable memory, and a resistor element.

[0320] Example

[0321] Hereinafter, the present invention will be specifically described based on Examples. However, the present invention is not limited to the Examples.

[0322] [Fabrication of small TFTs with self-aligned top-gate structure]

[0323] Example 1

[0324] Produced through the following processes Figure 5 The thin film transistor (TFT) 53 shown in FIG. 5 is provided with the same Figure 2 The TFT 50 shown has the same structure.

[0325] (1) Formation of buffer layer 22

[0326] Using a SiO2 sputtering target, a SiO2 layer with a thickness of 300 nm was formed on a 4-inch diameter alkali-free glass substrate 21 (EAGLE XG manufactured by Corning Incorporated) by sputtering. x The sputtering conditions are as follows.

[0327] Substrate temperature: 25°C

[0328] Ultimate pressure: 8.5×10 -5 Pa

[0329] Atmosphere gas: Ar

[0330] Sputtering pressure (total pressure): 0.4Pa

[0331] Input voltage: RF300W

[0332] Distance between S (substrate) and T (target): 70 mm

[0333] (2) Formation of oxide film

[0334] Next, a channel layer was formed by sputtering using an oxide sputtering target obtained from a raw material mixture having a charge composition ratio shown in Table 1-1. The metal composition ratio (unit: at %) in the oxide sputtering target is shown in Table 1-1.

[0335] The film formation conditions during sputtering and the thickness of the channel layer are shown in Table 1-1. The sputtering conditions other than those described in Table 1-1 are as follows.

[0336] Substrate temperature: 25°C

[0337] Ultimate pressure: 1.0×10 -4 Pa

[0338] Atmosphere gas: a mixture of Ar and H2O

[0339] Sputtering pressure (total pressure): 0.5Pa

[0340] Input voltage: DC300W

[0341] Distance between S (substrate) and T (target): 70 mm

[0342] (3) Formation of channel layer 11

[0343] Next, the oxide film is patterned into an island shape by photolithography to form a channel layer 11. First, a film of photoresist is formed on the oxide film. As a photoresist, AZ1500 (manufactured by Anzhi Electronic Materials Co., Ltd.) is used. Exposure is performed through a photomask having a pattern. After exposure, development is performed with tetramethylammonium hydroxide (TMAH). After development, the oxide film is etched using oxalic acid (ITO-06N manufactured by Kanto Chemical). After etching, the photoresist is peeled off to obtain a substrate 21 with a patterned oxide film (channel layer 11).

[0344] (4) Annealing

[0345] Next, the substrate with the channel layer 11 formed thereon was placed in a furnace, heated to 350°C at 10°C / min in the atmosphere, and then maintained for 1 hour. After the interior of the furnace was maintained at 350°C for 1 hour, it was naturally cooled, and the substrate was taken out of the furnace after the interior temperature of the furnace returned to room temperature.

[0346] (5) Channel layer pre-treatment

[0347] Next, pretreatment of the channel layer 11 is performed by the following method.

[0348] First, a SiO2 sputtering target was used to sputter to form a 10 nm thick SiO x Layer (pre-processing layer).

[0349] SiO x The SiO layer (pretreatment layer) with a thickness of 100 nm formed in the "(7) rare gas supply process" described later. x The layers are integrated to form a gate insulating film 24 .

[0350] The sputtering conditions were as follows.

[0351] Substrate temperature: 25°C

[0352] Ultimate pressure: 8.5×10 -5 Pa

[0353] Atmosphere gas: Ar+O2 mixed gas (O2 flow rate 30%)

[0354] Sputtering pressure (total pressure): 0.4Pa

[0355] Input voltage: RF300W

[0356] Distance between S (substrate) and T (target): 70 mm

[0357] The SiO formed by sputtering x The thickness of the layer (pretreatment layer) is shown in the "Pretreatment method" column of Table 1-1.

[0358] (6) Annealing after pretreatment

[0359] Next, SiO x The substrate of the layer was placed in a furnace, heated to 400°C at 10°C / min in the atmosphere, and then kept for 1 hour. The interior of the furnace was kept at 400°C for 1 hour, and then naturally cooled. After the temperature in the furnace returned to room temperature, the substrate was taken out of the furnace.

[0360] (7) Rare gas supply processing

[0361] Next, a SiO2 sputtering target was used to form a 100 nm thick SiO x Layer (rare gas supply source). The sputtering conditions are as follows.

[0362] Substrate temperature: 25°C

[0363] Ultimate pressure: 8.5×10 -5 Pa

[0364] Atmosphere gas: Ar+O2 mixed gas (O2 flow rate 30%)

[0365] Sputtering pressure (total pressure): 0.4Pa

[0366] Input voltage: RF300W

[0367] Distance between S (substrate) and T (target): 70 mm

[0368] In addition, in the table, the column “SiO2, Ar + " means that the SiO2 layer formed by sputtering film formation takes in a part of the Ar gas present as the film formation atmosphere gas of sputtering as Ar + Ions included.

[0369] Thus, the SiO film formed in this step is formed. x The SiO layer (thickness 100 nm) formed in the above-mentioned "(5) Channel layer pretreatment" x The layers (thickness 10 nm) are integrated to form the gate insulating film 24. Thus, the total thickness of the gate insulating film 24 becomes 110 nm.

[0370] The SiO formed by sputtering x The thickness of the layer is shown in the "Rare gas supply amount" column of Table 1-1.

[0371] (8) Formation of Gate Electrode 25

[0372] Next, a Mo film with a thickness of 150 nm was formed using a sputtering target of Mo. The sputtering conditions were as follows.

[0373] Substrate temperature: 25°C

[0374] Ultimate pressure: 8.5×10 -5 Pa

[0375] Atmosphere gas: Ar

[0376] Sputtering pressure (total pressure): 0.4Pa

[0377] Input voltage: DC100W

[0378] Distance between S (substrate) and T (target): 70 mm

[0379] (9) Patterning of the Gate Electrode 25 and the Gate Insulation Film 24

[0380] Next, the Mo film and the gate insulating film 24 are patterned into an island shape by photolithography. First, a film of photoresist is formed on the channel layer. As a photoresist, AZ1500 (manufactured by Anzhi Electronic Materials Co., Ltd.) is used. Exposure is performed through a photomask having a pattern formed with a horizontal size of 10 μm. After exposure, development is performed with tetramethylammonium hydroxide (TMAH). After development, the Mo film is etched using PAN (a mixed acid of phosphoric acid, nitric acid and acetic acid) to form a gate electrode 25.

[0381] Next, the gate insulating film 24 is etched using buffered hydrofluoric acid (BHF) and patterned into an island shape.

[0382] Next, after the photoresist was peeled off, the region where the channel layer 11 was exposed was etched to a thickness of 10 nm using oxalic acid (ITO-06N manufactured by Kanto Chemical), and then cleaned.

[0383] The size of the portion of the obtained gate electrode layer 25 and gate insulating film 24 overlapping with the channel layer 11 was 10 μm in width×20 μm in height.

[0384] (10) Low resistance treatment

[0385] The low resistance region A (11A-1, 11A-2) is formed in the channel layer 11 by self-alignment using the gate electrode 25. Using an ITO sputtering target, a 2 nm thick ITO layer 23 is formed. The sputtering conditions are as follows.

[0386] Substrate temperature: 25°C

[0387] Ultimate pressure: 8.5×10 -5 Pa

[0388] Atmosphere gas: Ar+O2 mixed gas (O2 flow rate 2%)

[0389] Sputtering pressure (total pressure): 0.4Pa

[0390] Input voltage: DC50W

[0391] Distance between S (substrate) and T (target): 70 mm

[0392] Next, the substrate after the low resistance treatment was placed in a furnace, heated to 350°C at 10°C / min in the atmosphere, and then kept at that temperature for 1 hour for annealing. The interior of the furnace was kept at 350°C for 1 hour, and then cooled naturally. After the temperature in the furnace returned to room temperature, the substrate was taken out of the furnace.

[0393] (11) Formation of Interlayer Insulation Film 26

[0394] Next, a SiO2 sputtering target was used to sputter to form a 150 nm thick SiO x The sputtering conditions are as follows.

[0395] Substrate temperature: 25°C

[0396] Ultimate pressure: 8.5×10 -5 Pa

[0397] Atmosphere gas: Ar+O2 mixed gas (O2 flow rate 30%)

[0398] Sputtering pressure (total pressure): 0.4Pa

[0399] Input voltage: RF300W

[0400] Distance between S (substrate) and T (target): 70 mm

[0401] (12) Formation of Contact Holes in Interlayer Insulation Film 26

[0402] The substrate with the interlayer insulating film 26 formed thereon was exposed to light through a photomask using photoresist AZ1500 (manufactured by AZ Electronic Materials Co., Ltd.) and then developed using tetramethylammonium hydroxide (TMAH). After development, a contact hole of 12 μm in width and 18 μm in length was formed using buffered hydrofluoric acid (BHF).

[0403] (13) Formation of Source Electrode 27 and Drain Electrode 28

[0404] The source electrode 27 and the drain electrode 28 were patterned by a lift-off process using the image reversal resist AZ5214 and a photomask. The image reversal resist AZ5214 was exposed through a photomask, and the entire surface was exposed after a reverse baking process, and developed with TMAH. For the substrate with the patterned resist, a Mo layer with a thickness of 150 nm was formed under the following sputtering conditions.

[0405] Substrate temperature: 25°C

[0406] Ultimate pressure: 8.5×10 -5 Pa

[0407] Atmosphere gas: Ar

[0408] Sputtering pressure (total pressure): 0.4Pa

[0409] Input voltage: DC100W

[0410] Distance between S (substrate) and T (target): 70 mm

[0411] Then, the substrate on which the Mo layer was formed was peeled off in acetone, thereby patterning the source electrode 27 and the drain electrode 28 .

[0412] (14) Final annealing

[0413] Finally, annealing was performed at 300°C for 1 hour in a N2 atmosphere, thereby obtaining a self-aligned top-gate structured small TFT.

[0414] Tables 1-1 to 1-3 and 2 show the outline of the TFT production conditions.

[0415] Example 2

[0416] A TFT was produced in the same manner as in Example 1, except that the thickness of the channel layer formed in "(2) Formation of an oxide thin film" was changed as shown in Table 1-1.

[0417] Example 3

[0418] After the "(7) rare gas supply process" is performed and before the "(8) formation of the gate electrode 25" is performed, the SiO x A TFT was produced in the same manner as in Example 1 except for annealing the substrate of the layer (rare gas supply source).

[0419] The SiO x Annealing treatment of the substrate with a layer (rare gas supply source).

[0420] First, a SiO film is formed on it. x The substrate with the layer (rare gas supply source) is placed in a furnace, heated to 200°C at 10°C / min in the atmosphere, and then maintained for 1 hour. The interior of the furnace is maintained at 200°C for 1 hour, and then cooled naturally. After the temperature in the furnace returns to room temperature, the substrate 21 is taken out of the furnace.

[0421] Example 4

[0422] A TFT was produced in the same manner as in Example 1 except that "(5) channel layer pretreatment" was not performed.

[0423] In Example 4, a SiO film with a thickness of 100 nm was formed by the "(7) rare gas supply process". x The layer alone constitutes the gate insulating film 24 .

[0424] Example 5

[0425] In addition to the SiO film formed in the "(7) rare gas supply process" x The SiO layer (rare gas supply source) was formed in the same manner as in Example 1 except that the thickness of the layer (rare gas supply source) was changed as shown in Table 1-1. x Layer (rare gas supply source).

[0426] The above SiO x The channel layer (rare gas supply source) is connected to the 10 nm thick SiO2 film formed by "(5) Channel layer pretreatment" x The SiO layer (pretreatment layer) and the SiO layer with a thickness of 50 nm formed by the "(7') Formation of the gate insulating film 24" described later. x The layers are integrated and function as a gate insulating film 24 of the TFT.

[0427] Next, after “(7) rare gas supply process” and before “(8) formation of gate electrode 25”, “(7′) formation of gate insulating film 24” is performed by the following method (chemical vapor deposition (CVD) method).

[0428] First, the substrate after the "(7) rare gas supply process" was placed in a plasma CVD device, the substrate was maintained at 350°C, and SiH4, N2O, and N2 were introduced at a pressure of 110 Pa in a ratio of 2 sccm of SiH4, 100 sccm of N2O, and 120 sccm of N2 to form a SiO2 layer with a thickness of 50 nm. x layer.

[0429] Thus, the SiO film formed in this step is formed. x The SiO layer (thickness 50 nm) is formed in the above-mentioned "(5) Channel layer pretreatment" with a thickness of 10 nm. x layer (pretreatment layer), and a 50 nm thick SiO film formed in "(7) rare gas supply process" x The layers (Si supply sources) are integrated to form a gate insulating film 24. The total thickness of the gate insulating film 24 is 110 nm.

[0430] Embodiment 6-7

[0431] A TFT was produced in the same manner as in Example 1, except that in "(7) Rare gas supply process", the film formation atmosphere gas was changed to an atmosphere gas shown in the "Film formation atmosphere gas or injection gas" column of Table 1-1.

[0432] In Examples 6 and 7, the O 2 flow rate of each film-forming atmosphere gas was set to 30%.

[0433] Example 8

[0434] In "(7) rare gas supply process", Ar plasma processing using a dry etching device was performed instead of film formation by sputtering. The plasma processing was performed under the conditions of a power of 100 W and a processing time of 100 seconds in an Ar gas atmosphere.

[0435] The processing time of the Ar plasma treatment is shown in the column of “Rare Gas Supply Amount” in Table 1-2.

[0436] In the table, the "Ar + " indicates that Ar is supplied to the channel layer as a rare gas supply source by Ar plasma treatment. + ion.

[0437] Next, after “(7) rare gas supply process” and before “(8) formation of gate electrode 25 ”, “(7′) formation of gate insulating film 24 ” is performed by the following method (sputtering).

[0438] First, a SiO2 sputtering target was used to form a 100 nm thick SiO x The sputtering conditions are as follows.

[0439] Substrate temperature: 25°C

[0440] Ultimate pressure: 8.5×10 -5 Pa

[0441] Atmosphere gas: Ar+O2 mixed gas (O2 flow rate 30%)

[0442] Sputtering pressure (total pressure): 0.4Pa

[0443] Input voltage: RF300W

[0444] Distance between S (substrate) and T (target): 70 mm

[0445] In Example 8, the SiO2 film having a thickness of 100 nm formed by “(7′) Formation of the gate insulating film 24” after “(7) Rare gas supply process” was x The layer constitutes the gate insulating film 24 .

[0446] The other steps were carried out in the same manner as in Example 4 to produce a TFT.

[0447] Embodiments 9-10

[0448] In the "(7) rare gas supply process" of Example 1, Ar is injected into the channel layer 11. + Ion implantation: Ion implantation was performed using an ion implantation device at 50 keV.

[0449] Ar based on ion implantation + The ion dose is shown in the "Rare gas supply amount" column of Table 1-2.

[0450] Next, after performing "(7) rare gas supply process" and before performing "(8) formation of gate electrode 25", similarly to Example 8, "(7') formation of gate insulating film 24" was performed to form a 100 nm thick SiO2 film by sputtering. x layer.

[0451] Thus, the SiO film formed in this step is formed. x The SiO layer (thickness 100 nm) formed in the "(5) Channel layer pretreatment" x The layers (thickness 10 nm) are integrated to form a gate insulating film 24. The total thickness of the gate insulating film 24 is 110 nm.

[0452] Next, before “(8) Formation of gate electrode 25 ”, the substrate on which the gate insulating film 24 was formed was annealed under the conditions shown in Table 1-2.

[0453] In the annealing of the substrate with the gate insulating film 24 formed thereon, the same method as in Example 3 was used for the substrate with the SiO2 film formed thereon except that the maximum temperature was changed to the temperature shown in Table 1-2. x Annealing of the substrate of the layer (rare gas supply source) is performed in the same manner.

[0454] The other steps were carried out in the same manner as in Example 1 to produce a TFT.

[0455] Embodiment 11

[0456] A TFT was produced in the same manner as in Example 10, except that the thickness of the channel layer formed in "(2) Formation of an oxide thin film" was changed as shown in Table 1-2.

[0457] Examples 12 to 18

[0458] TFT is manufactured in the same manner as in Example 1, except that in "(2) Formation of oxide thin film", the composition ratio of the sputtering target used for forming the channel layer, the oxygen partial pressure and the water partial pressure of the film-forming atmosphere gas during the formation of the channel layer are changed as shown in Tables 1-2 to 1-3.

[0459] Reference Example 1

[0460] TFTs were fabricated in the same manner as in Example 1, except that in "(7) Rare gas supply process", the film forming atmosphere gas was changed to He and O 2 shown in the "Film forming atmosphere gas or injection gas" column of Table 1-3.

[0461] Comparative Example 1

[0462] In addition to forming SiO x A TFT was produced in the same manner as in Example 3 except that the maximum temperature of annealing of the substrate of the layer (Si supply source) was changed as shown in Table 1-3.

[0463] The TFTs obtained in the examples, reference examples, and comparative examples were evaluated as follows. The results are shown in Tables 1-1 to 1-3. In the tables, “E+XX” means “×10 XX ”.

[0464] (A) Evaluation of the stacked structure of TFT

[0465] (1) Average concentration of rare gas in the channel layer (crystalline oxide semiconductor film)

[0466] The noble gas concentration was measured using transmission electron microscopy-energy dispersive X-ray spectroscopy (TEM-EDX).

[0467] The measurement of the rare gas concentration in the channel layer (crystalline oxide semiconductor film) by TEM-EDX is performed as follows.

[0468] First, the TFTs obtained in each embodiment and comparative example were processed by focused ion beam: FIB (Focused Ion Beam) at an acceleration voltage of 20 to 30 kV using a composite beam processing and observation device (manufactured by JEOL Ltd., “JIB-4700F”). Then, a focused ion beam processing and observation device (FIB) (manufactured by Hitachi High-Technologies Corporation, “FB-2100”) was used at an acceleration voltage of 40 kV to obtain thin film samples for cross-sectional TEM observation by a microsampling method.

[0469] The thin film sample for cross-sectional TEM observation was prepared as a thin film covering the entire region in the thickness direction of the channel layer (the stacking direction of the TFT) and was prepared to have the same film thickness (film thickness: 60 to 80 nm) in all examples and comparative examples.

[0470] The “average rare gas concentration in the crystalline oxide semiconductor film” in Tables 1-1 to 1-3 is a value calculated by taking the arithmetic average of the respective rare gas concentrations acquired at the respective measurement locations over the entire film thickness in the above-mentioned EDX line analysis.

[0471] (2) Film Thickness of the Rare Gas Region in the Crystalline Oxide Semiconductor Film

[0472] A cross-sectional TEM observation is performed on the thin film sample for cross-sectional TEM observation, and EDX line analysis is performed along the film thickness direction from the buffer layer side 22 to the gate insulating film 24 side for the field of view area of ​​the central part of the channel layer (crystalline oxide semiconductor film) in the field of view including the channel layer (crystalline oxide semiconductor film).

[0473] EDX analysis was performed using an energy dispersive X-ray analyzer (manufactured by JEOL Ltd., “JED-2300T”) under the following conditions.

[0474] Accelerating voltage: 200 kV

[0475] Measurement mode: STEM mode

[0476] Spot diameter: 0.16nm

[0477] Measuring interval: 1nm

[0478] As the elements to be detected (detectable elements), all elements detectable by the device are selected, the sum of all selected elements is used as the denominator, the sum of rare gas elements (Ne, Ar, Kr, Xe, Rn) is used as the numerator, and line analysis is performed in the film thickness direction of the channel layer (crystalline oxide semiconductor film) to perform EDX analysis.

[0479] The EDX spectrum intensity obtained by EDX line analysis was automatically calculated using the initial setting value by the dedicated software of the energy dispersive X-ray analyzer (manufactured by JEOL Ltd., “JED-2300T”), thereby calculating the rare gas concentration.

[0480] The calculation of the rare gas concentration is performed at each measurement point in the measurement field of view, and the film thickness of the region in the crystalline oxide semiconductor film where the rare gas concentration is within the range of greater than 0.5 at % and less than 5 at % and is continuous in the film thickness direction is shown in the "Film thickness of the rare gas region in the crystalline oxide semiconductor film" column of Tables 1-1 to 1-3.

[0481] In addition, the above-mentioned concentration analysis based on EDX line analysis is performed with the sum of all selected elements as the denominator and the various cationic elements contained in the channel layer (crystalline oxide semiconductor film) as the numerator, and the channel layer (crystalline oxide semiconductor film) region in the TFT is set as the region where the In concentration shows the maximum value among the various cation concentrations.

[0482] In addition, He contained in the channel layer cannot be detected by TEM-EDX. Therefore, for Reference Example 1, the analysis of the crystalline oxide semiconductor film was performed using a sector dynamic secondary ion mass spectrometer SIMS (IMS 7f-Auto, manufactured by AMETEK) instead of the measurement based on TEM-EDX, and He was identified based on the mass spectrum of each element. Thus, it was confirmed that He was contained in the thin film sample collected from the TFT of Reference Example 1.

[0483] (B) Evaluation of TFT characteristics

[0484] The obtained TFT was measured at room temperature in a light-shielded environment (in a shielded box) using a semiconductor parameter analyzer ("B1500" manufactured by Agilent Technologies). In addition, a drain voltage (Vd) was applied at 20 V. For Vd application, the gate voltage (Vg) was varied from -5 V to 20 V in 0.1 V steps to measure the current value Id, thereby obtaining Id-Vg characteristics.

[0485] Various parameters calculated from the Id-Vg characteristics are shown in Tables 1-1 to 1-3. The calculation method of each parameter is as follows.

[0486] (a) S value

[0487] The S value and the threshold voltage (Vth) were evaluated from the graphs of the Id-Vg characteristics. -11 ~10 -10 In the region [A], the value obtained by the following formula (d) is calculated as the S value.

[0488] [Number 1]

[0489]

[0490] (b) Initial characteristics

[0491] In the measurement of the initial characteristics, a drain voltage (Vd) of 20 V was applied. For Vd application, the gate voltage (Vg) was varied from -5 V to 20 V in 0.1 V steps to measure the current value Id, thereby obtaining the Id-Vg characteristics. -9 The Vg voltage value of A is defined as the on-state voltage V on , V onThe initial characteristics at 0±0.5V are set to "0".

[0492] [Table 1-1]

[0493]

[0494] [Table 1-2]

[0495]

[0496] [Table 1-3]

[0497]

[0498] [Table 2]

[0499]

[0500] As shown in Tables 1-1 to 1-3, after a film is formed on the surface of the crystalline oxide semiconductor film by channel layer pretreatment, a film serving as a rare gas supply source is sputtered to form a rare gas region in the crystalline oxide semiconductor film. The average concentration of the rare gas in the crystalline oxide semiconductor film of the TFTs of Examples 1 to 3, 5, 7, 12 to 18 is greater than 0.5 at % and less than 5 at %, and an appropriate value of 0.8±0.5 V / dec is obtained as the S value, showing excellent grayscale performance and excellent initial characteristics.

[0501] In the TFT of Example 4, in which a film serving as a rare gas supply source (a film functioning as a gate insulating film) is sputtered without performing annealing without performing channel layer pretreatment, the average concentration of the rare gas in the crystalline oxide semiconductor film is 2.5 at %, and an appropriate value of 0.8±0.5 V / dec is obtained as the S value, which also shows excellent grayscale performance and excellent initial characteristics.

[0502] In Example 8, in which a gate insulating film is formed by performing rare gas supply treatment through plasma treatment without performing channel layer pre-treatment and no annealing of the gate insulating film is performed, the average concentration of the rare gas in the crystalline oxide semiconductor film is 3.20 at %, and an appropriate value of 0.8±0.5 V / dec is obtained as the S value, which also shows excellent grayscale performance and excellent initial characteristics.

[0503] In addition, in Examples 9 to 11, in which channel layer pretreatment and rare gas supply treatment were performed by ion implantation, a gate insulating film was sputtered and annealed, the average concentration of the rare gas in the crystalline oxide semiconductor film was greater than 0.5 at % and less than 5 at %, and an appropriate value of 0.8±0.5 V / dec was obtained as the S value, which also showed excellent grayscale performance and excellent initial characteristics.

[0504] It is found that in Comparative Example 1, in which the film obtained (film to be the gate insulating film) was annealed after the channel layer pre-treatment and the rare gas supply treatment were performed by sputtering film formation, the average concentration of the rare gas in the crystalline oxide semiconductor film was low, being less than 0.3 at %, and the S value was also low, being 0.28. This is considered to be because the rare gas diffused outward from the crystalline oxide semiconductor film by annealing the film to be the rare gas supply source.

[0505] In Reference Example 1, in which a film as a rare gas supply source is formed by sputtering using He as an atmosphere gas after forming a film on the surface of the crystalline oxide semiconductor film by channel layer pretreatment, as described above, He cannot be detected by EDX analysis, and therefore the He concentration in the crystalline oxide semiconductor film cannot be measured, but SIMS analysis can confirm that the crystalline oxide semiconductor film contains He. In the evaluation of TFT characteristics, the S value is 0.90 and the initial characteristics are also good, so it is inferred that there is a high possibility that there is a region in which the He concentration in the crystalline oxide semiconductor film is within the range of 0.5 at% or more and less than 5 at% and is continuous in the film thickness direction.

[0506] Industrial Applicability

[0507] The laminated structure of the present invention can be suitably used as a component of a thin film transistor, such as a channel layer and a gate insulating film. In addition, the thin film transistor of the present invention including the laminated structure of the present invention can be used in electronic circuits used in electrical equipment, electronic equipment, vehicles, and power machines.

[0508] The above embodiments and / or examples of the present invention have been described in some detail, but those skilled in the art can easily make many changes to these illustrative embodiments and / or examples without departing from the new teachings and effects of the present invention. Therefore, these many changes are included in the scope of the present invention.

[0509] The contents of all the documents described in this specification and the applications serving as the basis for the priority claim based on the Paris Convention of the present application are hereby cited.

Claims

1. A stacked structure, characterized in that: have: A crystalline oxide semiconductor film containing In as a main component; an insulating film stacked in contact with the crystalline oxide semiconductor film, The crystalline oxide semiconductor film has one or more regions in which the rare gas concentration is within a range of 0.5 at % to less than 5 at % and which are continuous for 3 nm or more in the film thickness direction.

2. The stacked structure according to claim 1, characterized in that The region is continuous by 5 nm or more in the film thickness direction of the crystalline oxide semiconductor film.

3. The laminate structure according to claim 1 or 2, characterized in that: The noble gas atoms are argon.

4. The laminate structure according to any one of claims 1 to 3, characterized in that: The insulating film is any one of an oxide film mainly composed of silicon (Si), a nitride film mainly composed of silicon (Si), or an oxynitride film mainly composed of silicon (Si).

5. The laminate structure according to any one of claims 1 to 4, characterized in that: The insulating film is an oxide film containing silicon (Si) as a main component.

6. The laminate structure according to any one of claims 1 to 5, characterized in that: The crystalline oxide semiconductor film further contains Ga.

7. The laminate structure according to any one of claims 1 to 6, wherein: The crystalline oxide semiconductor film further contains one or more additional elements selected from B, Al, Si, Sc, Zn, Ge, Y, Zr, Sn, Sm, and Yb.

8. The laminate structure according to any one of claims 1 to 7, wherein: The atomic ratio of In to all metal elements contained in the crystalline oxide semiconductor film ([In] / ([In]+[all metal elements other than In])×100) is 62 at % or more.

9. The laminate structure according to any one of claims 6 to 8, characterized in that: The atomic ratio of Ga to all metal elements contained in the crystalline oxide semiconductor film ([Ga] / ([Ga]+[all metal elements other than Ga])×100) is 30 at % or less.

10. The laminate structure according to any one of claims 7 to 9, characterized in that: The atomic ratio of the total amount of the additive elements to all metal elements contained in the crystalline oxide semiconductor film ([total amount of additive elements] / ([total amount of additive elements]+[all metal elements other than additive elements])×100) is 10 at % or less.

11. The laminate structure according to any one of claims 1 to 10, characterized in that: The carrier concentration of the crystalline oxide semiconductor film at room temperature is 1×10 18 cm -3 the following.

12. The laminate structure according to any one of claims 1 to 11, wherein: The crystalline oxide semiconductor film includes crystal grains of a bixbyite structure.

13. A thin film transistor comprising the stacked structure according to any one of claims 1 to 12, characterized in that: have: Channel layer; a source electrode and a drain electrode respectively connected to the channel layer; a gate electrode stacked on the channel layer via a gate insulating film, The channel layer is a crystalline oxide semiconductor film in the stacked structure, The gate insulating film is an insulating film in the stacked structure.

14. The thin film transistor according to claim 13, wherein: It is a top-gate transistor.

15. A semiconductor device, characterized in that: The laminate structure according to any one of claims 1 to 12 is used.

16. A diode, a thin film transistor, a MOSFET or a MESFET, characterized in that: The semiconductor element according to claim 15 is used.

17. An electronic circuit, characterized in that: A diode, a thin film transistor, a MOSFET or a MESFET comprising the diode, the thin film transistor, the MOSFET or the MESFET as claimed in claim 16.

18. An electrical device, electronic device, vehicle or power machine, characterized in that: An electronic circuit comprising the electronic circuit of claim 17.

Images