Self-aligned backside contact with increased contact area

Abstract

The first source-drain region is adjacent to the first transistor, the second source-drain region is adjacent to the second transistor, the upper source-drain contact is arranged above the first source-drain region, the bottom source-drain contact is arranged below the second source-drain region, and the bottom source-drain contact and the upper source-drain contact are arranged on two opposite sides. A horizontal surface of the bottom source drain contact is adjacent to a horizontal surface of the dielectric side spacer surrounding the second source drain region. In an embodiment, a bottom source-drain contact surrounds a vertical side of a source-drain region. A method includes forming first and second nanosheet stacks, forming a top source-drain contact of a first source-drain region adjacent to the first nanosheet stack, and forming a bottom source-drain contact of a lower horizontal surface of a second source-drain region adjacent to the second nanosheet stack.

Description

Background Art

[0001] The present invention relates generally to the field of semiconductor manufacturing and more particularly to backside contacts.

[0002] Complementary metal oxide semiconductor (CMOS) technology is commonly used for field effect transistors (hereinafter referred to as "FETs") as part of advanced integrated circuits (hereinafter referred to as "ICs"), such as central processing units (hereinafter referred to as "CPUs"), memories, storage devices, etc. As the demand for reducing the size of transistor devices continues, nanosheet FETs help to achieve a smaller FET device footprint while maintaining the performance of FET devices. Nanosheet devices include one or more layers of semiconductor channel material portions having a vertical thickness that is substantially less than its width. Nanosheet FETs include multiple stacked nanosheets extending between a pair of source / drain epitaxial regions. The device can be a full-surround gate device or transistor, in which the gate surrounds a portion of the nanosheet channel. Summary of the invention

[0003] According to an embodiment, a semiconductor device is provided. The semiconductor device includes: a first source-drain region adjacent to a first transistor on a substrate; a second source-drain region adjacent to a second transistor on the substrate; an upper source-drain contact vertically aligned above the first source-drain region and electrically connected to the first source-drain region; and a bottom source-drain contact vertically aligned below the second source-drain region and electrically connected to the second source-drain region, wherein the bottom source-drain contact and the upper source-drain contact are located on opposite sides of the semiconductor device, wherein a horizontal surface of the bottom source-drain contact is adjacent to a horizontal surface of a dielectric side spacer surrounding the second source-drain region, and wherein a width of the bottom source-drain contact is wider than a width of the second source-drain.

[0004] According to an embodiment, a semiconductor device is provided, comprising a first source and drain region and a bottom source and drain contact vertically aligned below the first source and drain region and electrically connected to the first source and drain region, wherein the bottom source and drain contact surrounds a vertical side of a second source and drain region.

[0005] According to an embodiment, a method is provided. The method includes forming a first nanosheet stack and a second nanosheet stack on a substrate, forming a top source-drain contact to an upper horizontal surface of a first source-drain region adjacent to the first nanosheet stack, bonding a carrier wafer to an upper surface of the substrate above the first nanosheet stack and the second nanosheet stack, and forming a bottom source-drain contact to a lower horizontal surface of a second source-drain region adjacent to the second nanosheet stack, the bottom source-drain contact and the second source-drain region being vertically aligned, wherein the bottom source-drain contact surrounds a vertical side of the second source-drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which will be read in conjunction with the accompanying drawings. The various features of the drawings are not to scale, as the illustrations are for clarity to assist those skilled in the art in understanding the present invention in conjunction with the specific embodiments. In the drawings:

[0007] Figure 1 shows a top view of a semiconductor structure at an intermediate stage of fabrication according to an exemplary embodiment;

[0008] 2 and 3 respectively show a cross-sectional view of a Figure 1 A cross-sectional view of a semiconductor structure;

[0009] 4 and 5 illustrate cross-sectional views of a semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment, and illustrate the formation of a stacked sacrificial layer;

[0010] 6 and 7 illustrate cross-sectional views of a semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment, and illustrate the formation of a sacrificial layer and a semiconductor layer;

[0011] Figure 8 A top view of a semiconductor structure according to an exemplary embodiment is shown, and the formation of a sacrificial layer gate and a gate cap is shown;

[0012] 9 and 10 respectively show a cross-sectional view of a Figure 8 A cross-sectional view of a semiconductor structure;

[0013] 11 and 12 illustrate cross-sectional views of a semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment, and illustrate the formation of source / drain trenches;

[0014] 13 and 14 illustrate cross-sectional views of a semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment and illustrate selective removal of layers;

[0015] Fig.15 shows a top view of a semiconductor structure according to an exemplary embodiment and illustrates the formation of an organic patterned layer;

[0016] 16 and 17 respectively illustrate a cross-sectional view of a Fig.15 A cross-sectional view of a semiconductor structure;

[0017] 18 and 19 illustrate cross-sectional views of a semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment and illustrate the formation of a sacrificial backside contact placeholder;

[0018] 20 and 21 are cross-sectional views of the semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment, and illustrate the formation of an inner spacer and a source drain;

[0019] 22 and 23 illustrate cross-sectional views of a semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment, and illustrate the formation of an interlayer dielectric;

[0020] 24 and 25 illustrate cross-sectional views of the semiconductor structure along section lines XX and YY, respectively, according to exemplary embodiments, and illustrate the removal of the sacrificial gate and sacrificial layer and the formation of a replacement high-K metal gate;

[0021] 26 and 27 illustrate cross-sectional views of a semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment and illustrate the formation of interlayer dielectrics and contacts;

[0022] 28 and 29 illustrate cross-sectional views of a semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment, and illustrate the formation of back-end layers and the bonding of a carrier wafer to the semiconductor structure;

[0023] 30 and 31 illustrate cross-sectional views of a semiconductor structure along section lines XX and YY, respectively, according to exemplary embodiments, and illustrate flipping of the semiconductor structure and removal of a portion of a substrate of the semiconductor structure;

[0024] 32 and 33 illustrate cross-sectional views of the semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment and illustrate the removal of the sacrificial back contact placeholder and the formation of the bottom contact opening;

[0025] 34 and 35 illustrate cross-sectional views of a semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment and illustrate pre-epitaxial cleaning;

[0026] 36 and 37 illustrate cross-sectional views of the semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment and illustrate the formation of a bottom contact;

[0027] 38 and 39 illustrate cross-sectional views of a semiconductor structure along section lines XX and YY, respectively, according to an exemplary embodiment and illustrate the formation of an interlayer dielectric, backside power rails, and backside power delivery network;

[0028] 40 and 41 illustrate cross-sectional views of alternative semiconductor structures along section lines XX and YY, respectively, and illustrate the formation of a bottom contact according to an exemplary embodiment; and

[0029] 42 and 43 illustrate cross-sectional views of alternative semiconductor structures along section lines XX and YY, respectively, according to example embodiments and illustrate the formation of an interlayer dielectric, backside power rails, and backside power delivery network.

[0030] It should be understood that for simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale. For example, for clarity, the size of some elements may be exaggerated relative to other elements. In addition, where deemed appropriate, reference numerals may be repeated in the drawings to indicate corresponding or similar features. DETAILED DESCRIPTION

[0031] Specific embodiments of the claimed structures and methods are disclosed herein; however, it is understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be implemented in various forms. However, the present invention may be implemented in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0032] With reference to the specification, "an embodiment", "an example embodiment", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. In addition, these phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not it is clearly described, it is considered to be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments.

[0033] It should be understood that when an element as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0034] In order not to obscure the presentation of embodiments of the present invention, in the following specific embodiments, some processing steps or operations well known in the art may be combined together for presentation and for illustration purposes, and may not be described in detail in some instances. In other cases, some processing steps or operations well known in the art may not be described at all. It should be understood that the following description is more focused on the distinguishing features or elements of various embodiments of the present invention.

[0035] Nanosheet field effect transistors (hereinafter referred to as "FETs") can be formed from alternating layers of silicon and silicon germanium, which are then formed into stacked nanosheets. A full surround gate structure can be formed on all vertical sides and on the horizontal upper surface of a portion of a nanosheet. A source-drain structure can be formed at opposite ends of the stacked nanosheet structure.

[0036] The formation of a nanosheet FET may have the following steps. A stacked nanosheet layer is formed on a substrate, trenches are formed in the stacked nanosheet layer parallel to each other to form a fin, and then a sacrificial gate is formed perpendicular to the trench. An additional trench perpendicular to the original trench is formed between the sacrificial gates. In an embodiment of the present invention, the trench may extend into the substrate, and into a sacrificial layer formed in a portion of the trench in the substrate. The trench may be formed at a back contact where a source and drain are subsequently formed. An outer portion of the sacrificial layer of the stacked nanosheets may be removed, and an inner spacer may be formed at the removal of the outer portion of the sacrificial layer of the stacked nanosheets. A source and drain region extending from the exposed channel layer of the nanosheet stack is formed. The source and drain region may be formed above the trench. The sacrificial gate is removed, and the remaining portion of the sacrificial layer is removed. A metal gate surrounding the channel layer may be formed at the removal of the sacrificial gate and the remaining portion of the sacrificial layer. Contacts to the metal gate and the source and drain may be formed, particularly contacts to the source and drain regions without the sacrificial layer below the source and drain. Back-end of line (BEOL) layers of wiring and vias may be further formed.

[0037] Embodiments of forming a back contact may include bonding a carrier substrate to the upper surface of the formed nanosheet FET with BEOL layers, inverting the structure above the BEOL layers, and then forming a back opening above the sacrificial layer and removing the sacrificial layer. Self-aligned sacrificial back contacts to the source and drain may be formed in the back opening. Additional line layers and via layers may be formed above the back contact and may be connected to the back contact.

[0038] Embodiments of forming a backside contact may include using a different material than the material of the bottom dielectric isolation below the nanosheet stack for the dielectric spacer vertically surrounding the source and drain. When forming the backside opening, portions of the dielectric spacer may be selectively removed, and a self-aligned sacrificial backside contact may be formed that surrounds a portion of the vertical side surfaces of the source and drain and covers the bottom surface of the source and drain.

[0039] There are several advantages to forming self-aligned sacrificial back contacts, including the flexibility of forming source and drain contacts from above or below the structure, and forming contacts with greater spacing since fewer contacts overall may be required above the nanosheet device. Having self-aligned contacts is an additional advantage due to the relative alignment accuracy of backside lithography compared to frontside lithography, which is due to wafer deformation or thickness non-uniformity. Self-aligned contacts are formed by forming sacrificial backside contact placeholders below the source and drain epitaxy so that the location of the backside contacts is predefined and the formation is no longer dependent on the coverage performance of the backside lithography process.

[0040] The present invention relates generally to the field of semiconductor manufacturing and more particularly to backside contacts.

[0041] According to an illustrative embodiment, the following Figure 1 The embodiments of the present invention described in detail in the drawings in -43 disclose structures and methods for forming FET nanosheets with self-aligned back contacts.

[0042] Reference now Figure 1 , 2 and 3 illustrate a semiconductor structure 100 (hereinafter referred to as a “structure”) at an intermediate stage of fabrication according to an exemplary embodiment. Figure 1 is a top view of structure 100 .

[0043] FIG. 2 is a cross-sectional view of the structure 100 along section line XX; FIG. 3 is a cross-sectional view of the structure 100 along section line YY and perpendicular to section line XX. Figure 1 The structure 100 may include a substrate and a silicon germanium layer 106 .

[0044] The substrate may be a silicon-on-insulator (hereinafter referred to as "SOI") substrate, which includes a silicon substrate 102, a buried oxide layer 104 (hereinafter referred to as "BOX SiO2") on the silicon substrate 102, and a thin silicon layer 105 on the BOX SiO2 104. In other embodiments, the substrate may be, for example, a bulk substrate, which may be made of any of several well-known semiconductor materials, such as silicon, germanium, silicon-germanium alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide and indium phosphide, or indium gallium arsenide. Typically, the substrate may be about, but not limited to, several hundred microns thick.

[0045] Referring now to Figures 4 and 5, a structure 100 according to an exemplary embodiment is shown. Figures 4 and 5 are cross-sectional views of the structure 100 along section lines XX and YY, respectively. Figures 4 and 5 are perpendicular to each other. A stacked sacrificial layer 108 and a silicon oxide layer 107 are formed by a silicon germanium layer 106 and a thin silicon layer 105.

[0046] Silicon germanium layer 106 may be epitaxially grown and conformally cover the upper surface of thin silicon layer 105 on structure 100. Silicon germanium layer 106 may be, for example, silicon germanium having a germanium concentration of approximately 35 atomic % to 85 atomic %, although percentages greater than 85% and less than 35% may be used.

[0047] The terms "epitaxial growth and / or deposition" and "epitaxially grown and / or deposited" refer to the growth of semiconductor material on a deposition surface of the semiconductor material, wherein the grown semiconductor material has the same crystal properties as the semiconductor material of the deposition surface. In epitaxial deposition techniques, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and adapt themselves to the crystal arrangement of the atoms of the deposition surface. Thus, the epitaxial semiconductor material has the same crystal properties as the deposition surface on which the epitaxial semiconductor material is formed.

[0048] Examples of various epitaxial growth techniques include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature of epitaxial deposition is generally in the range of about 550° C. to about 900° C. Although higher temperatures generally result in faster deposition, faster deposition can result in crystal defects and film cracking.

[0049] The structure 100 may undergo a thermal oxidation process, which causes germanium to diffuse from the silicon germanium layer 106 into the thin silicon layer 105 to form a stacked sacrificial layer 108 and a silicon oxide layer 107 .

[0050] For example, the stacked sacrificial layer 108 can be silicon germanium with a germanium concentration of about 55 atomic percent, although percentages greater than 55% and less than 55% can be used. The stacked sacrificial layer 108 is then selectively removed from the remaining alternating layers as described below. The thin silicon layer 105 of the substrate can be converted to the stacked sacrificial layer 108 by growing a silicon germanium layer 106 followed by a silicon germanium condensation process.

[0051] Referring now to FIGS. 6 and 7 , a structure 100 is shown according to an exemplary embodiment. FIGS. 6 and 7 are cross-sectional views of the structure 100 along section lines XX and YY, respectively. FIGS. 6 and 7 are perpendicular to each other. The silicon oxide layer 107 may be removed. Stacked nanosheets may be formed on the structure 100.

[0052] The silicon oxide layer 107 may be removed by methods known in the art, thereby exposing the upper surface of the stacked sacrificial layer 108 .

[0053] The alternating layers of sacrificial semiconductor material and semiconductor channel material can be collectively referred to as stacked nanosheets.

[0054] The alternating layers of sacrificial semiconductor material and semiconductor channel material may include a sacrificial semiconductor material layer 110 (hereinafter referred to as "sacrificial layer"), which is covered by a semiconductor channel material layer 112 (hereinafter referred to as "channel layer"), covered by the sacrificial layer 110, covered by the channel layer 112, covered by the sacrificial layer 110, and covered by the channel layer 112.

[0055] The alternating layers of sacrificial layer 110 and channel layer 112 can be formed by sequential epitaxial growth of alternating layers of a first semiconductor material and a second semiconductor material on a substrate, wherein the alternating layers of the first semiconductor material and the second semiconductor material are stacked one on top of the other. It should be noted that although a limited number of alternating layers are described, any number of alternating layers can be formed. The epitaxial growth of the first and second semiconductor materials that provide the sacrificial semiconductor material layer and the semiconductor channel material layer, respectively, can be performed using any known precursor gas or gas mixture. Carrier gases such as hydrogen, nitrogen, helium and argon can be used.

[0056] Each sacrificial layer 110 is composed of a first semiconductor material that is different in composition from at least the upper portion of BOXSiO2 104, the channel layer 112, and the stacked sacrificial layer 108. In an embodiment, each sacrificial layer 110 may be a silicon-germanium semiconductor alloy and have a germanium concentration of less than 50% atomic percent. In another example, each sacrificial layer 110 may have a germanium concentration ranging from about 20% atomic percent to about 40% atomic percent. Each sacrificial layer 110 may be formed using known deposition techniques or epitaxial growth techniques as described above.

[0057] Each channel layer 112 is composed of a second semiconductor material that is different in composition from at least the upper portion of BOXSiO2 104, the sacrificial layer 110, and the stacked sacrificial layer 108. Each channel layer 112 has an etch rate different from the first semiconductor material of the sacrificial layer 110, and has an etch rate different from the stacked sacrificial layer 108. The second semiconductor material can be, for example, silicon. The second semiconductor material for each channel layer 112 can be formed using a known deposition technique or an epitaxial growth technique as described above.

[0058] The sacrificial layer 110 may have a thickness ranging from about 5 nm to about 15 nm, and the channel layer 112 may have a thickness ranging from about 4 nm to about 12 nm. Each sacrificial layer 110 may have a thickness that is the same as or different from the thickness of each channel layer 112. In an embodiment, each sacrificial layer 110 has the same thickness. In an embodiment, each channel layer 112 has the same thickness. The stacked sacrificial layers 108 may each have a thickness ranging from about 5 nm to about 12 nm.

[0059] Reference now Figure 8 , 9 and 10 , illustrate a structure 100 according to an exemplary embodiment. Figure 8 is a top view of the structure 100. Figures 9 and 10 are cross-sectional views of the structure 100 along section lines XX and YY, respectively. Figures 9 and 10 are perpendicular to each other.

[0060] The active device area is defined by removing unwanted portions of the nanosheet to form trenches 114. A sacrificial gate 116 and a gate cap 118 may be formed. Section XX is along the fins of the nanosheet stack, parallel to adjacent trenches 114 and perpendicular to the sacrificial gates 116. Section YY is between adjacent sacrificial gates 116, parallel to the sacrificial gates 116 and perpendicular to the fins of the nanosheet stack.

[0061] The stacked sacrificial layer 108 and the alternating layers of the sacrificial layer 110 and the channel layer 112 can be formed into a fin. The fin can have a length perpendicular to the section line YY and parallel to the section line XX. The fin can be formed by methods known in the art and include steps such as forming a hard mask on the alternating layers, patterning the hard mask, and then forming one or more grooves 114 by removing portions of each layer of the stacked nanosheets. The grooves 114 can be formed into fins by anisotropic etching techniques (e.g., reactive ion etching (RIE)) and stopping when etching a portion of the BOX SiO2 104 between each nanosheet stack. The BOX SiO2 104 can provide physical isolation and electrical isolation between adjacent nanosheet stacks.

[0062] Each fin of the nanosheet stack may include a stacked sacrificial layer 108, covered by a sacrificial layer 110, covered by a channel layer 112, covered by a sacrificial layer 110, covered by a channel layer 112, covered by a sacrificial layer 110, covered by a channel layer 112. As an illustration, three fins are depicted in the drawings of the present application, but any number of fins may be formed.

[0063] The material stacks that can be used in embodiments of the present invention are not limited to Figure 8 , 9 and 10. Figure 8, 9 and 10, and by way of example only, the nanosheet stack includes three layers of sacrificial layers 110 alternating with three channel layers 112. The nanosheet stack may include any number of sacrificial layers 110 and channel layers 112. The nanosheet stack is used to fabricate a gate-all-around device including vertically stacked nanosheets of semiconductor channel material for a p-FET or n-FET.

[0064] The sacrificial gate 116 and the gate cap 118 are formed orthogonally (perpendicularly) to the fin. As an illustration, three sacrificial gates 116 are depicted in the drawings of the present application, although any number of sacrificial gates 116 may be formed. The sacrificial gate 116 may include a single sacrificial material or a stack of two or more sacrificial materials. At least one sacrificial material may be formed by forming a capping layer (or multiple layers) of a material (or various materials) and then patterning the material (or various materials) by photolithography and etching. The sacrificial gate 116 may include any material, including, for example, polycrystalline silicon, amorphous silicon, or a multilayer combination thereof. In an embodiment using amorphous silicon as the material of the sacrificial gate 116, a thin layer of SiO2 is first deposited to separate the nanosheet stack from the amorphous silicon. The sacrificial gate 116 may be formed using any deposition technique, including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin coating techniques. Optionally, according to known techniques, the gate cap 118 may be formed as part of the sacrificial gate 116.

[0065] In an embodiment, the deposition thickness of the sacrificial gate 116 is sufficient to fill or substantially fill the space between adjacent nanosheet structures and cover the horizontal upper surface of the uppermost channel layer 112 of the nanosheet stack. The sacrificial gate 116 may be adjacent to the vertical side surface of the nanosheet stack or fin. The sacrificial gate 116 may cover the upper horizontal surface of the BOXSiO2 104 between adjacent nanosheet stacks. The height of the sacrificial gate 116 may be much thicker than the underlying structure and may have a height between 100nm and 150nm around the nanosheet stack. The gate cap 118 may cover the upper horizontal surface of the sacrificial gate 116. The gate patterning may be performed by conventional photolithography and etching processes so that portions of the gate cap 118 and portions of the sacrificial gate 116 are removed from subsequently formed source and drain regions.

[0066] Referring now to FIGS. 11 and 12 , a structure 100 according to an exemplary embodiment is shown. FIGS. 11 and 12 are cross-sectional views of the structure 100 along section lines XX and YY, respectively. FIGS. 11 and 12 are perpendicular to each other. The stacked sacrificial layer 108 may be removed. A bottom dielectric isolation 122 (hereinafter referred to as “BDI”) and a dielectric spacer 124 may be formed.

[0067] The stacked sacrificial layer 108 may be selectively removed by methods known in the art. For example, a dry etching technique may be used to selectively remove the stacked sacrificial layer 108, such as dry etching using gaseous HCl. The stacked sacrificial layer 108 may be selectively removed from the silicon substrate 102, BOXSiO2 104, the channel layer 112, the sacrificial layer 110, the sacrificial gate 116, and the gate cap 118.

[0068] BDI 122 may be formed where the stack sacrificial layer 108 is removed. BDI 122 may be formed below the lowermost sacrificial layer 110 and above BOX SiO2 104 of the nanosheet stack.

[0069] Dielectric spacers 124 may be formed on vertical side surfaces of the nanosheet stack, including vertical side surfaces of the channel layer 112 and vertical side surfaces of the sacrificial layer 112. Dielectric spacers 124 may be formed on vertical side surfaces of the sacrificial gate 116 and the gate cap 118.

[0070] The BDI 122 and the dielectric spacer 124 may be formed by conformally depositing a dielectric material followed by isotropic etching. The spacer 124 may be formed by conformal dielectric material deposition and an anisotropic RIE process. The BDI 122 and the dielectric spacer 124 may be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin coating techniques, followed by an anisotropic vertical etching process such as reactive ion etching (RIE) or any suitable etching process. In an embodiment, the BDI 122 and the dielectric spacer 124 may each include one or more layers. The BDI 122 and the dielectric spacer 124 may each include any dielectric material, such as silicon nitride (SiN), silicon boron carbon nitride (SiBCN), silicon oxycarbonitride (SiOCN), aluminum oxide (AlOx), SiC, and may include a single layer or may include multiple layers of dielectric material. The BDI 122 and the dielectric spacer 124 may each include the same material or different materials.

[0071] Referring now to Figures 13 and 14, a structure 100 is shown according to an exemplary embodiment. Figures 13 and 14 are cross-sectional views of the structure 100 along section lines XX and YY, respectively. Figures 13 and 14 are perpendicular to each other. Source / drain trenches 120 may be formed.

[0072] The alternating layers of sacrificial layer 110, channel layer 112, and BDI 122 can be formed into a nanosheet stack by methods known in the art. The source / drain trench 120 can have a length perpendicular to the section line XX, parallel to the section line YY, and perpendicular to the fin. The source / drain trench 120 can be formed between each sacrificial gate 116 with a surrounding dielectric spacer 124 by an anisotropic etching technique, such as reactive ion etching (RIE), and stopped when etching a portion of the BOX SiO2 104 between each nanosheet stack. The BOX SiO2 104 can provide physical isolation and electrical isolation between adjacent nanosheet stacks.

[0073] Each nanosheet stack may include a BDI 122 covered by a sacrificial layer 110, covered by a channel layer 112, covered by a sacrificial layer 110, covered by a channel layer 112, covered by a sacrificial layer 110, covered by a channel layer 112. Above the nanosheet stack is a sacrificial gate 116 and a gate cap 118 with dielectric spacers 124 on opposite vertical sides. The nanosheet stack may be vertically aligned with the dielectric spacers 124 surrounding the sacrificial gate and gate cap 118.

[0074] 14, portions of the nanosheet stack may be removed between adjacent sacrificial gates 116, gate caps 118, and dielectric spacers 124. The dielectric spacers 124 may remain vertically where the nanosheet stack is removed along section line XX.

[0075] Reference now Fig.15 , 16 and 17 , illustrate a structure 100 according to an exemplary embodiment. Fig.15 16 and 17 are cross-sectional views of the structure 100 along section lines XX and YY, respectively. FIGS. 16 and 17 are perpendicular to each other. Conventional photolithography and etching processes may be used to pattern back contact trenches 134 in BOX SiO2 104. A photolithography soft mask such as an organic planarization layer 130 (hereinafter referred to as "OPL") may be used for the patterning process.

[0076] OPL 130 may be formed by blanket deposition using typical deposition techniques such as spin coating. OPL 130 may be a self-planarizing organic material including carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon. OPL 130 may be a standard C x H yPolymer. Non-limiting examples of the material include, but are not limited to, CHM701B commercially available from Cheil Chemical Co., Ltd., HM8006 and HM8014 commercially available from JSR Corporation, and ODL-102 or ODL-401 commercially available from ShinEtsu Chemical., Co., Ltd.

[0077] A dry etching technique may be used to selectively remove a portion of the OPL 130 that is subsequently used to form the back contact trench 134 .

[0078] A back contact trench 134 may be formed between an adjacent pair of sacrificial gates 116, a gate cap 118, and a dielectric spacer 124 surrounding each sacrificial gate 116, above an adjacent nanosheet stack, as shown by section line XX of FIG. 12, and a back contact trench 134 may be formed between a pair of dielectric spacers 124, wherein a portion of the nanosheet stack is removed between adjacent sacrificial gates 116, as shown by section line YY of FIG. 13.

[0079] The back contact trench 134 may be formed by an anisotropic etching technique, such as reactive ion etching (RIE), removing aligned portions of the OPL 130 and the BOX SiO 2 104 and stopping when etching a portion of the silicon substrate 102 .

[0080] The back contact trench 134 can facilitate the formation of a self-aligned back contact. The back contact trench 134 can be formed in a selected area of ​​the structure 100 where a future bottom contact to a subsequently formed source or drain can be formed. There can be one or more back contact trenches 134 on the structure 100.

[0081] Referring now to Figures 18 and 19, a structure 100 is shown in accordance with an exemplary embodiment. Figures 18 and 19 are cross-sectional views of the structure 100 along section lines XX and YY, respectively. Figures 18 and 19 are perpendicular to each other. A sacrificial backside contact placeholder 136 may be formed.

[0082] A sacrificial back contact placeholder 136 may be formed in the back contact trench 134, filling a portion of the back contact trench 134. A lower surface of the sacrificial back contact placeholder 136 may be adjacent to an upper surface of the silicon substrate 102. A vertical side surface of the sacrificial back contact placeholder 136 may be adjacent to a vertical side surface of the BOX SiO2 104. A portion of the vertical side surface of the sacrificial back contact placeholder 136 may be adjacent to a portion of a vertical side surface of the dielectric spacer 124 surrounding the back contact trench 134. A portion of the vertical side surface of the sacrificial back contact placeholder 136 may be adjacent to a portion of a vertical side surface of the BDI 122.

[0083] The sacrificial back contact placeholder 136 may be formed by conformally depositing or growing a sacrificial material followed by a combination of dry and wet anisotropic etching and recessing steps. The sacrificial back contact placeholder 136 may be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin coating techniques, followed by an anisotropic vertical etching process, such as reactive ion etching (RIE) or any suitable etching process. The sacrificial placeholder material, such as a semiconductor material, may also be selectively grown from the substrate 102 by epitaxy. In an embodiment, the sacrificial back contact placeholder 136 may include one or more layers. In an embodiment, the sacrificial back contact placeholder 136 may include any material that can selectively remove a layer relative to the BOX SiO2 104, such as SiGe, Ge, III-V semiconductors, silicon oxynitride, silicon nitride, SiBCN, SiOC, SiC, AlOx, TiOx, or any combination of these materials.

[0084] Referring now to FIGS. 20 and 21 , structure 100 according to an exemplary embodiment is shown. FIGS. 20 and 21 are cross-sectional views of structure 100 along section lines XX and YY, respectively. FIGS. 20 and 21 are perpendicular to each other. OPL 130 may be removed. Outer portions of sacrificial layer 110 may be removed. Inner spacers 140 may be formed. Source drains 144 may be formed.

[0085] The OPL 130 may be removed selectively to the silicon substrate 102 , the BOX SiO 2 104 , the sacrificial layer 110 , the channel layer 112 , the sacrificial gate 116 , the gate cap 118 , the BDI 122 , the dielectric spacers 124 , and the sacrificial back contact placeholder 136 using wet etching or dry ashing techniques.

[0086] The outer portions of the sacrificial layer 110 may be selectively removed using known techniques. For example, a wet or dry etching process may be used to remove portions of each sacrificial layer 110 using appropriate chemistries. The materials used for the etching process may be selective so that the channel layer 112, sacrificial back contact placeholder 136, dielectric spacer 124, BDI 122, gate cap 118, sacrificial gate 116, channel layer 112, BOX SiO2 104, and silicon substrate 102 remain without being etched. After etching, the portions of the sacrificial layer 110 covered by the sacrificial gate 116 on the opposite side may remain as part of the nanosheet stack.

[0087] The inner spacer 140 may be formed by conformally depositing or growing a dielectric material, followed by a combination of dry and wet isotropic etching and recessing steps. The inner spacer 140 may be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition, and spin coating techniques, followed by an isotropic etching process, such as a wet etching process, or any suitable etching process. In an embodiment, the inner spacer 140 may include one or more layers. In an embodiment, the inner spacer 140 may include any dielectric material, such as silicon oxynitride, silicon nitride, SiBCN, SiOC, or any combination of these materials.

[0088] The inner spacers 140 may completely fill the spaces between the channel layers 112 where portions of the sacrificial layers 110 have been previously removed.

[0089] Vertical side surfaces of the inner spacer 140 may be aligned with vertical side surfaces of the channel layer 112 and vertical side surfaces of the dielectric spacer 124 surrounding the sacrificial gate 116 and the gate cap 118 .

[0090] The source and drain 144 may be epitaxially grown around the vertical portion of the nanosheet stack on the opposite side of the sacrificial gate 116. The lower surface of the source and drain 144 may be adjacent to the upper surface of the sacrificial back contact placeholder 136. In those areas where there is no sacrificial back contact placeholder 136, the lower surface of the source and drain 144 may be adjacent to the upper surface of the BOX SiO2 104. The vertical side surfaces of the source and drain 144 may be adjacent to the vertical side surfaces of the inner spacer 140, the vertical side surfaces of the BDI 122, and the vertical side surfaces of the channel layer 112. The upper surface of the source and drain 144 may be farther from the BOX SiO2 104 than the upper surface of the uppermost channel layer 112.

[0091] Referring now to Figures 22 and 23, structure 100 is shown according to an exemplary embodiment. Figures 22 and 23 are cross-sectional views of structure 100 along section lines XX and YY, respectively. Figures 22 and 23 are perpendicular to each other. An interlayer dielectric (hereinafter "ILD") 148 may be formed.

[0092] ILD 148 can be formed by conformally depositing or growing dielectric materials, followed by CMP or etching steps. ILD 148 can be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), chemical vapor deposition (CVD), physical vapor deposition (PVD), high density plasma (HDP) deposition and spin coating techniques, followed by a planarization process such as CMP, or any suitable etching process. In an embodiment, ILD 148 may include one or more layers. In an embodiment, ILD 148 may include any dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, SiBCN, SiOC, low-k dielectrics, or any combination of these materials. The lower surface of ILD 148 may be adjacent to the upper surface of source drain 144. The additional lower surface of ILD 148 may be adjacent to the upper surface of BOX 104. The vertical side surface of ILD 148 may be adjacent to the vertical side surface of dielectric spacer 124.

[0093] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of structure 100, removing gate cap 118 and exposing the upper horizontal surface of sacrificial gate 116. The upper surface of structure 100 may also include the upper horizontal surface of ILD 148 and the upper horizontal surface of dielectric spacer 124.

[0094] Referring now to FIGS. 24 and 25 , structure 100 is shown according to an exemplary embodiment. FIGS. 24 and 25 are cross-sectional views of structure 100 along section lines XX and YY, respectively. FIGS. 24 and 25 are perpendicular to each other. Sacrificial gate 116 may be removed. Sacrificial layer 110 may be removed. High-k metal gate 152 may be formed.

[0095] The sacrificial gate 116 may be removed by methods known in the art. The sacrificial layer 110 is selectively removed relative to the channel layer 112, the inner spacer 140, the ILD 148, the dielectric spacer 124, the BDI 122, the sacrificial back contact placeholder 136, the BOX SiO2 104, and the silicon substrate 102. For example, a dry etching process may be used to selectively remove the sacrificial layer 110, such as dry etching using gaseous HCl. The upper and lower surfaces of the channel layer 112 may be exposed. The upper surface of the BDI 122 may be exposed.

[0096] According to an exemplary embodiment, a high-k metal gate 152 may be conformally formed on the structure 100. The high-k metal gate 152 is formed in each cavity of the nanosheet stack and surrounds the suspended portion of the channel layer 112. The high-k metal gate 152 forms a layer around the exposed portion of the nanosheet stack. The high-k metal gate 152 may cover the exposed upper horizontal surface of the BDI 122, the exposed vertical side surface of one side of the side spacer 140, the exposed vertical surface of one side of the dielectric spacer 124, and the exposed upper horizontal surface of the BDI 122. The high-k metal gate 152 may cover the vertical side surface, the upper horizontal surface, and the lower horizontal surface of the channel layer 110. The high-k metal gate 152 may fill the space between the dielectric spacers 124 above the nanosheet stack, where the sacrificial gate 116 is removed.

[0097] The high-k metal gate 152 may be deposited using typical deposition techniques, such as atomic layer deposition (ALD), molecular layer deposition (MLD), and chemical vapor deposition (CVD). In an embodiment, the high-k metal gate 152 may include more than one layer, for example, a conformal layer of a high-k dielectric material such as HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfO x N y 、ZrO x N y 、La2O x N y 、Al2O x N y 、TiO x N y 、SrTiO x N y 、LaAlO x N y 、Y2O x N y 、SiON、SiN x , silicates thereof, and alloys thereof. In an embodiment, the work function metal of a p-FET device may include a metal nitride, such as titanium nitride or tantalum nitride, titanium carbide, titanium aluminum carbide, or other suitable materials known in the art. In an embodiment, the work function metal of an n-FET device may include, for example, titanium aluminum carbide or other suitable materials known in the art. In an embodiment, the work function metal may include one or more layers to achieve desired device characteristics.

[0098] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of structure 100. The upper surface of structure 100 may include an upper horizontal surface of ILD 148, an upper horizontal surface of dielectric spacers 124, and an upper horizontal surface of high-k metal gate 152.

[0099] Referring now to FIGS. 26 and 27 , structure 100 according to an exemplary embodiment is shown. FIGS. 26 and 27 are cross-sectional views of structure 100 along section lines XX and YY, respectively. FIGS. 26 and 27 are perpendicular to each other. Interlayer dielectric (hereinafter “ILD”) 154 may be formed. Upper contact 156 may be formed.

[0100] ILD 154 may be conformally formed as described for ILD 148 . A lower horizontal surface of ILD 154 may be adjacent to an upper horizontal surface of high-k metal gate 152 , an upper horizontal surface of dielectric spacer 124 , and an upper horizontal surface of ILD 148 .

[0101] Openings (not shown) may be made in structure 100 through ILD 154 and ILD 148 to expose the upper horizontal surface of source drain 144. Upper contacts 156 may be formed in the openings (not shown) to form contacts to source drain 144. As shown in FIG. 23 , there are two upper contacts 156. There may be any number of upper contacts 156 on structure 100.

[0102] An upper contact 156 may be made to a source drain 144 that does not have a sacrificial back contact placeholder 136 below the source drain 144. A source drain 144 with a sacrificial back contact placeholder 136 may have a bottom contact formed in a subsequent processing step. Each source drain 144 may have an upper contact 156 or a bottom contact.

[0103] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of structure 100 , exposing the upper horizontal surface of ILD 154 and the upper horizontal surface of upper contact 156 .

[0104] Referring now to FIGS. 28 and 29 , structure 100 is shown according to an exemplary embodiment. FIGS. 28 and 29 are cross-sectional views of structure 100 along section lines XX and YY, respectively. FIGS. 28 and 29 are perpendicular to each other. Back end of line (BEOL) layers 160 (BEOL) may be formed. Carrier wafer 162 may be bonded to structure 100.

[0105] BEOL layers 160 may include wiring layers and via layers formed over existing structures, contacts 145, and ILD 154. In an embodiment, BEOL layers 160 may include 12 or more metal line layers and via layers. BEOL layers 160 may be formed using known techniques.

[0106] A carrier wafer 162 may be attached to the upper surface of structure 100, mounted on the upper surface of BEOL layer 160. The carrier wafer may be attached using conventional wafer bonding processes, such as dielectric-to-dielectric bonding or copper-to-copper bonding processes.

[0107] Referring now to Figures 30 and 31, structure 100 is shown according to an exemplary embodiment. Figures 30 and 31 are cross-sectional views of structure 100 along section lines XX and YY, respectively. Figures 30 and 31 are perpendicular to each other. Structure 100 can be flipped over and silicon substrate 102 can be removed.

[0108] The structure 100 can be turned so that the carrier wafer 162 is now shown at the bottom of Figures 30 and 31, at the lowest point of the structure, and the lower surface of the silicon substrate 102 is now shown at the upper level of the structure for further processing.

[0109] The silicon substrate 102 may be selectively removed using a combination of process steps such as wafer grinding, CMP, RIE, and wet etching processes. The final stage of the process may include selectively etching any remaining silicon of the silicon substrate 102 to expose the surface of the BOX SiO2 104 and expose the sacrificial back contact placeholder 136.

[0110] The silicon substrate 102 may be removed, and the upper horizontal surface of the structure 100 includes the upper horizontal surface of the sacrificial back contact placeholder 136 and the upper horizontal surface of the BOX SiO2 104. There may be more than one sacrificial back contact placeholder 136. Each sacrificial back contact placeholder 136 may be adjacent to a source drain 144 that does not have an upper contact 156.

[0111] Referring now to Figures 32 and 33, structure 100 is shown according to an exemplary embodiment. Figures 32 and 33 are cross-sectional views of structure 100 along section lines XX and YY, respectively. Figures 32 and 33 are perpendicular to each other. Sacrificial back contact placeholder 136 may be removed and bottom contact opening 166 may be formed.

[0112] The sacrificial back contact placeholder 136 may be selectively removed using known techniques to form the bottom contact opening 166. For example, a wet or dry etching process may be used with appropriate chemistry to remove the sacrificial back contact placeholder 136. The material used for the etching process may be selective so that the BDI 122 and BOX SiO2 104 remain and are not etched.

[0113] Referring now to Figures 34 and 35, structure 100 is shown according to an exemplary embodiment. Figures 34 and 35 are cross-sectional views of structure 100 along section lines XX and YY, respectively. Figures 34 and 35 are perpendicular to each other. Contact opening enlargement cleaning may be performed.

[0114] A contact opening enlargement clean may be performed, which may enlarge the size of the bottom contact opening 166 and remove any native oxide above the source drain 144, and during this process, horizontal portions of the BOX SiO2 104 and vertical portions of the BOX SiO2 104 may be etched, thereby increasing the size of the bottom contact opening 166. Examples of contact opening enlargement cleans may include a DHF wet clean or a SiCoNi dry clean process. Siconi is a trademark of Applied Materials, Inc.

[0115] The contact opening enlargement cleaning may expose a portion of the upper surface of the BDI 122. The contact opening enlargement cleaning may expose a portion of the upper surface and a portion of the vertical surface of a pair of dielectric spacers 124 surrounding the bottom contact opening 166. When the bottom contact opening 166 is enlarged, the high-k metal gate 152 is isolated from the bottom contact opening 166 by the BDI 122. The enlarged bottom contact opening 166 facilitates the formation of a larger silicide and metal plug volume, thereby helping to reduce the contact resistance of the contact subsequently formed in the bottom contact opening 166.

[0116] Referring now to Figures 36 and 37, structure 100 is shown in accordance with an exemplary embodiment. Figures 36 and 37 are cross-sectional views of structure 100 along section lines XX and YY, respectively. Figures 36 and 37 are perpendicular to each other. Bottom contacts 172 may be formed.

[0117] A bottom contact 172 may be formed in the bottom contact opening 166 to form a contact to the source and drain 144. As shown in Figures 36 and 37, there is one bottom contact 172. There may be any number of bottom contacts 172 on the structure 100.

[0118] Forming the bottom contact 172 includes filling the bottom contact opening 166 with a highly conductive metal material. For clarity, the individual metal materials within the bottom contact 172 are not shown. Although the body of the bottom contact 172 includes a base metal such as Co, Ru or Mo to reduce its body resistivity, a metal compound directly adjacent to the semiconductor of the source drain 144 is selected to reduce the contact resistance between the bottom contact 172 and the semiconductor of the source drain 144. In one embodiment, the metal compound adjacent to the semiconductor of the source drain 144 is a metal silicide or germanium silicide. The compound can be produced by reacting a base metal (e.g., titanium) with the semiconductor of the source drain 144. Although the metal silicide / germanium silicide is made thin, typically less than 3nm, it sets the Schottky barrier of the semiconductor-metal interface and ultimately sets the contact resistivity of the interface. The metal silicide / germanium silicide can be separated from the base metal filling of the bottom contact 172 by a thin conductive metal liner (such as a titanium nitride liner). The high concentration of free carriers in the semiconductor of the source and drain 144 and the low Schottky barrier between the metal silicide / germanium silicide and the semiconductor of the source and drain 144 allow for a back contact structure of about 10% for both n-type and p-type semiconductors. - 9 W cm 2 The presence of multiple metal compounds in the bottom contact 172 does not affect its series resistance much because the additional interface compounds and liner are made thinner than the basic metal filler, and the individual metal-metal interface resistances are at least an order of magnitude lower than the semiconductor-metal interface resistance.

[0119] The contact resistivity of the adjacent metal compound from the source / drain 144 to the bottom contact 172 may be equal to or less than 1e-9 Ohmcm 2 The volume concentration of free electric carriers (electrons or holes) of the source and drain 144 may be equal to or greater than 7e20 cm -3 .

[0120] In contrast, the contact resistance between the source / drain 144 and the contact 156 may be greater than or equal to 2e-9 Ohm cm 2 The volume concentration of free electric carriers (electrons or holes) of the source and drain 144 may be less than or equal to 5e20 cm -3 .

[0121] Bottom contact 172 can be made to source drain 144 without upper contact 156. Source drain 144 can have upper contact 156 or bottom contact 172. This provides more options for source drain contacts. In an example, source drain 144 of an n-FET nanosheet stack can each have an upper contact 156, and source drain 144 of a p-FET nanosheet stack can each have a bottom contact 172. The alternative is also an embodiment.

[0122] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of structure 100. The upper surface of structure 100 may include an upper horizontal surface of BOX SiO2 104 and an upper horizontal surface of bottom contact 172.

[0123] Referring now to FIGS. 38 and 39 , structure 100 is shown in accordance with an exemplary embodiment. FIGS. 38 and 39 are cross-sectional views of structure 100 along section lines XX and YY, respectively. FIGS. 38 and 39 are perpendicular to each other. An interlayer dielectric (hereinafter referred to as “ILD”) 176 may be formed. A backside power rail (hereinafter referred to as “BPR”) 178 and a backside power supply network (hereinafter referred to as “BSPDN”) 180 may be formed.

[0124] ILD 176 may be formed by conformally depositing or growing a dielectric material, as described for ILD 148 . A lower surface of ILD 148 may be adjacent to an upper horizontal surface of BOX SiO 2 104 and an upper horizontal surface of bottom contact 172 .

[0125] BPR 178 can be formed in an opening (not shown) in ILD 176 using known techniques. In an embodiment, BPR 178 can be parallel to section line XX and perpendicular to section line YY. The lower horizontal surface of BPR 178 can be adjacent to the upper horizontal surface of bottom contact 172. As shown in FIG. 39 , there are three BPRs 178, however, any number of BPRs 178 can be present in structure 100.

[0126] BSPDN 180 may be formed on ILD 176 and BPR 178. BSPDN 180 may include additional wiring layers and via layers formed on top of existing structures, on ILD 176, and on BPR 178. In an embodiment, BSPDN 180 may include 3 or more wiring layers and via layers. BSPDN 180 may be formed using known techniques.

[0127] The resulting structure 100 includes a FET nanosheet with a self-aligned back contact, bottom contact 172, which provides a contact with an enlarged size without shorting to the high-k metal gate 152, providing an additional option for forming a bottom contact 172 to the FET nanosheet on the back side of the structure.

[0128] Referring now to FIGS. 40 and 41 , structure 101 is shown in accordance with an exemplary embodiment. FIGS. 40 and 41 are cross-sectional views of structure 101 along section lines XX and YY, respectively. FIGS. 40 and 41 are perpendicular to each other. Structure 101 is an alternative embodiment of structure 100. Structure 101 may be formed as described for structure 100 and is an alternative embodiment depicting processing steps subsequent to the steps shown in FIGS. 34 and 35 , and all parts having similar names may be referred to as above. Figure 1 To form as described in 39.

[0129] 34 and 35, the opening 166 can be enlarged by selectively removing the portion of the dielectric spacer 124 surrounding the source and drain 144 of the opening 166. In the embodiment, the dielectric spacer 124 is a different material from the BDI 122 and can be selectively etched. In the embodiment, the dielectric spacer 124 can include SiN, SiBCN or SiOCN, and the BDI can include SiC.

[0130] Bottom contact 173 may be formed in opening 166 , which now has an increased volume. Bottom contact 173 may surround portions of side surfaces of source drain 144 .

[0131] A bottom contact 173 may be formed in the bottom contact opening 166 to form a contact to the source drain 144. As shown in Figures 40 and 41, there is one bottom contact 173. There may be any number of bottom contacts 173 on the structure 101.

[0132] Bottom contact 173 can be made to source drain 144 without upper contact 156. Source drain 144 can have upper contact 156 or bottom contact 173. This provides more options for source drain contacts. In an example, source drain 144 of an n-FET nanosheet stack can each have an upper contact 156, and source drain 144 of a p-FET nanosheet stack can each have a bottom contact 173. The alternative is also an embodiment.

[0133] Chemical mechanical polishing (CMP) techniques may be used to remove excess material and polish the upper surface of structure 101. The upper surface of structure 101 may include an upper horizontal surface of BOX SiO2 104 and an upper horizontal surface of bottom contact 173.

[0134] Referring now to FIGS. 42 and 43, structure 101 is shown in accordance with an exemplary embodiment. FIGS. 42 and 43 are cross-sectional views of structure 101 along section lines XX and YY, respectively. FIGS. 42 and 43 are perpendicular to each other. An interlayer dielectric (hereinafter referred to as "ILD") 176 may be formed. A backside power rail (hereinafter referred to as "BPR") 178 and a backside power supply network (hereinafter referred to as "BSPDN") 180 may be formed.

[0135] ILD 176 may be formed by conformally depositing or growing a dielectric material, as described for ILD 148 . A lower surface of ILD 148 may be adjacent to an upper horizontal surface of BOX SiO 2 104 and an upper horizontal surface of bottom contact 173 .

[0136] BPR 178 can be formed in an opening (not shown) in ILD 176 using known techniques. In an embodiment, BPR 178 can be parallel to section line XX and perpendicular to section line YY. The lower horizontal surface of BPR 178 can be adjacent to the upper horizontal surface of bottom contact 173. As shown in FIG. 43 , there are three BPRs 178, however, any number of BPRs 178 can be present in structure 100.

[0137] BSPDN 180 may be formed on ILD 176 and BPR 178. BSPDN 180 may include additional wiring layers and via layers formed on top of existing structures, on ILD 176, and on BPR 178. In an embodiment, BSPDN 180 may include 3 or more wiring layers and via layers. BSPDN 180 may be formed using known techniques.

[0138] The resulting structure 101 includes a FET nanosheet with a self-aligned backside contact, contact 173, providing a contact with an enlarged size compared to contact 172 of FIG. 100. Contact 172 is formed by extending into an area where portions of dielectric spacers 124 surrounding source drain 144 are removed to form a wraparound contact around source drain 144 that does not have a short circuit to high-k metal gate 15. This provides an additional option for forming a contact to the FET nanosheet on the backside of the structure.

[0139] An advantage of structure 101 over structure 100 is that bottom contact 173 has a larger surface area in contact with source drain 144 in structure 101 than bottom contact 172 in structure 100. This has the advantage of reducing contact resistance for a given contact resistivity of the materials used.

[0140] The description of various embodiments of the present invention has been given for the purpose of illustration, but is not intended to be exhaustive or to limit the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0141] In a preferred embodiment of the present invention described herein, there is provided a semiconductor device comprising: a first source-drain region; a bottom source-drain contact, the bottom source-drain contact being vertically aligned below the first source-drain region and electrically connected to the first source-drain region, wherein the bottom source-drain contact surrounds a vertical side of the second source-drain region. The bottom source-drain contact may include a vertical side surface adjacent to a vertical side surface of a bottom dielectric isolation region below a second nanosheet stack. The bottom source-drain contact may include a horizontal surface adjacent to a horizontal surface of a pad surrounding the first source-drain region. The device may also include: a back power rail below the bottom source-drain contact, connected to the bottom source-drain contact. The device may also include: a back power supply network below the buried power rail.

Claims

1. A semiconductor device, comprising: a first source and drain region adjacent to a first transistor on the substrate; a second source and drain region adjacent to a second transistor on the substrate; an upper source-drain contact vertically aligned above the first source-drain region and electrically connected to the first source-drain region; as well as a bottom source-drain contact vertically aligned below the second source-drain region and electrically connected to the second source-drain region, wherein the bottom source-drain contact and the upper source-drain contact are located on opposite sides of the semiconductor device, wherein a horizontal surface of the bottom source-drain contact is adjacent to a horizontal surface of a dielectric side spacer surrounding the second source-drain region, The width of the bottom source drain contact is wider than the width of the second source drain.

2. The semiconductor device according to claim 1, wherein The bottom source-drain contact includes a vertical side surface adjacent to a vertical side surface of a bottom dielectric isolation region below the second transistor.

3. The semiconductor device according to claim 1, wherein The bottom source-drain contact includes a portion of a horizontal upper surface adjacent to a portion of a horizontal lower surface of a bottom isolation region between the substrate and the second transistor.

4. The semiconductor device according to claim 1, further comprising: A back side power rail is below the bottom source drain contact and connected to the bottom source drain contact.

5. The semiconductor device according to claim 5, further comprising: Backside delivery network beneath the buried power rail.

6. A method comprising: forming a first nanosheet stack and a second nanosheet stack on a substrate; forming a top source-drain contact to an upper horizontal surface of a first source-drain region adjacent to the first nanosheet stack; bonding a carrier wafer to an upper surface of the substrate above the first nanosheet stack and the second nanosheet stack; as well as forming a bottom source-drain contact to a lower horizontal surface of a second source-drain region adjacent to the second nanosheet stack, the bottom source-drain contact being vertically aligned with the second source-drain region, wherein The bottom source-drain contact surrounds vertical sides of the second source-drain region.

7. The method according to claim 6, wherein The bottom source-drain contact includes a vertical side surface adjacent to a vertical side surface of a bottom dielectric isolation region below the second nanosheet stack.

8. The method according to claim 7, wherein The bottom source drain contact includes a vertical side surface adjacent to a vertical side surface of a liner of the second source drain, wherein the liner of the second source drain is between the second source drain and a work function metal of a gate of the second nanosheet stack.

9. The method according to claim 6, further comprising: An epitaxial region is between the bottom source-drain contact and the second source-drain region.

10. The method according to claim 9, wherein A lower horizontal surface of the epitaxial region is below a lower horizontal surface of a bottom dielectric isolation region below the second nanosheet stack.

11. The method according to claim 6, further comprising: a buried power rail above the bottom source-drain contact and connected to the bottom source-drain contact; as well as A backside power delivery network is above the buried power rail.

12. The method according to claim 6, further comprising: A bottom dielectric isolation region is below the first nanosheet stack and below the second nanosheet stack.

13. The method according to claim 6, wherein The first nanosheet stack comprises alternating layers of work function metal and semiconductor channel material, the alternating layers being vertically aligned and stacked one on top of another; and The second nanosheet stack includes alternating layers of a work function metal and the semiconductor channel material, the alternating layers being vertically aligned and stacked one on top of another, vertically aligned and stacked one on top of another.

14. The method according to claim 6, further comprising: An undoped silicon buffer epitaxial region is between the bottom source and drain contacts and the first source and drain regions.

15. The method according to claim 6, further comprising: Vertical spacers are on opposite sides of the first source and drain regions.

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