Three-dimensional memory devices with lateral block isolation structures and methods of forming same

Abstract

A three-dimensional memory device includes an alternating stack of insulating strips and electrically conductive strips, a backside trench between adjacent pairs of the alternating stack, a memory opening extending vertically through the alternating stack, and a memory opening fill structure within the memory opening. In some embodiments, dielectric etch stop structures may be located within or outside the backside trenches such that each of the dielectric etch stop structures includes a respective pair of dielectric sidewalls located within a pair of longitudinal sidewalls of a respective of the backside trenches. In some other embodiments, a dielectric isolation structure may laterally contact each of the insulating strips within the alternating stack. Lateral insulating contact via structures may be provided to provide electrical contact with respective ones of the conductive strips.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 386,815 filed on December 9, 2022 and U.S. Provisional Patent Application No. 63 / 386,824 filed on December 9, 2022, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and in particular to a three-dimensional memory device including an inter-block word line lateral isolation structure for a step-free layer contact via structure and a method for forming the same. Background Art

[0004] A three-dimensional memory device including three-dimensional vertical NAND strings with one bit per cell is disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to one aspect of the present disclosure, a three-dimensional memory device is provided, the three-dimensional memory device comprising: an alternating stack of insulating layers and composite layers, the insulating layers and composite layers alternating in a vertical direction, wherein each of the composite layers comprises a combination of a dielectric connection plate and a plurality of conductive strips, the dielectric connection plate and the plurality of conductive strips extending laterally in a first horizontal direction, being laterally spaced apart in a second horizontal direction by backside grooves extending laterally in the first horizontal direction, and having respective sidewalls adjacent to respective sidewall surface segments of the dielectric connection plate, wherein end portions of the backside grooves are laterally bounded by the dielectric connection plates of the composite layers; an array of memory openings extending vertically through the alternating stack; a memory opening filling structure, the memory opening filling structure being located in the memory opening, wherein each memory opening in the memory opening filling structure The port-fill structure includes a vertical semiconductor channel and a corresponding vertical memory element stack located at the level of the conductive strip; a backside trench filling structure, which is located in the backside trench and extends vertically from at least a first horizontal plane including the bottommost surface of the alternating stack and extends at least to a second horizontal plane including the topmost surface of the alternating stack; and a dielectric etch stop structure, which is located inside or outside a corresponding one of the backside trenches, wherein each of the dielectric etch stop structures includes a corresponding pair of dielectric sidewalls located within a pair of longitudinal sidewalls of the corresponding one of the backside trenches, wherein the dielectric sidewalls of the dielectric etch stop structure extend laterally along the first horizontal direction and extend vertically from at least the first horizontal plane and extend at least to the second horizontal plane.

[0006] According to another aspect of the present disclosure, a method includes: forming a vertical alternating sequence of insulating layers and sacrificial material layers above a substrate, wherein the sacrificial material layers include dielectric materials; forming backside trenches extending laterally through the vertical alternating sequence along a first horizontal direction, wherein the backside trenches are laterally spaced apart along a second horizontal direction, and stripe portions of the vertical alternating sequence between adjacent pairs of the backside trenches are interconnected to each other by connecting portions of the vertical alternating sequence, the connecting portions being connected to each of the stripe portions of the vertical alternating sequence; and forming at least one dielectric etch stop structure before or after forming the backside trenches, such that the at least one dielectric etch stop structure extends from at least the vertical alternating sequence including the backside trenches. A first horizontal plane of the bottommost surface of the column extends vertically and extends at least to a second horizontal plane including the topmost surface of the vertical alternating sequence, and the at least one dielectric etch stop structure includes a pair of dielectric sidewalls located within a corresponding one of the backside trenches; a backside groove is formed by performing an isotropic etching process, which selectively removes a portion of the sacrificial material layer proximate the backside groove with respect to the material of the insulating layer and the dielectric etch stop structure, wherein the remaining portion of the sacrificial material layer after the isotropic etching process includes a dielectric connecting plate contacting each dielectric etch stop structure in the dielectric etch stop structure; and a conductive strip is formed in the backside groove.

[0007] According to yet another aspect of the present disclosure, a three-dimensional memory device is provided, the three-dimensional memory device comprising: an alternating stack of insulating strips and conductive strips, the insulating strips and the conductive strips alternating in a vertical direction, wherein each of the alternating stacks extends laterally in a first horizontal direction, and the alternating stacks are laterally spaced apart from each other by backside trenches in a second horizontal direction; a memory opening array, the memory opening array extending vertically through the alternating stacks; a memory opening filling structure, the memory opening filling structure being located in the memory opening, wherein each of the memory opening filling structures comprises a backside trench located in the conductive strips; a vertical semiconductor channel at the level of the strips and a corresponding vertical memory element stack; a vertical alternating sequence of insulating plates and dielectric material plates, the vertical alternating sequence being laterally spaced from the alternating stack along the first horizontal direction, wherein each of the insulating plates is located at the same level as, has the same thickness as, and has the same material composition as, a corresponding subset of the insulating strips within the alternating stack; and a dielectric isolation structure, the dielectric isolation structure laterally contacting each of the insulating strips within the alternating stack and each insulating plate and each dielectric material plate within the vertical alternating sequence, and extending laterally along the second horizontal direction.

[0008] According to yet another aspect of the present disclosure, a method includes: forming a vertical alternating sequence of an insulating layer and a sacrificial material layer above a substrate, wherein the sacrificial material layer comprises a dielectric material; forming backside trenches and isolation trenches through the vertical alternating sequence, wherein the backside trenches extend laterally along the first horizontal direction and are laterally spaced apart along the second horizontal direction, and the isolation trenches extend laterally along the second horizontal direction and are laterally spaced apart from the backside trenches along the first horizontal direction; forming an isolation cavity by laterally extending the isolation trenches, wherein an alternating stack of insulating strips and sacrificial material strips is formed, wherein the insulating strips are portions of the insulating layer located between corresponding adjacent pairs of the backside trenches, wherein the sacrificial material strips are discrete remaining portions of the sacrificial material layer, and wherein each of the sacrificial material strips is laterally spaced apart from all other sacrificial material strips located at the same vertical level by a combination of the backside trenches and the isolation cavity; forming a dielectric isolation structure in the isolation cavity; and replacing the sacrificial material strips with conductive strips to form alternating stacks of corresponding subsets of the insulating strips and corresponding subsets of the conductive strips. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a vertical cross-sectional view of the first exemplary structure after forming alternating stacks of insulating layers and sacrificial material layers, a memory opening, and a support opening according to the first embodiment of the present disclosure.

[0010] Figure 1B yes Figure 1A A top view of the first exemplary structure of FIG. The vertical plane AA' is Figure 1A Vertical section plane.

[0011] Figure 2A is a vertical cross-sectional view of the first exemplary structure after forming a sacrificial memory opening filling structure and a sacrificial support opening filling structure according to the first embodiment of the present disclosure.

[0012] Figure 2B yes Figure 2A A top view of the first exemplary structure of FIG. The vertical plane AA' is Figure 2A Vertical section plane.

[0013] Figure 3 is a vertical cross-sectional view of the first exemplary structure after removal of a sacrificial support opening-filling structure according to the first embodiment of the present disclosure.

[0014] Figure 4 is a vertical cross-sectional view of a first exemplary structure after forming a supporting column structure according to the first embodiment of the present disclosure.

[0015] Figure 5is a vertical cross-sectional view of the first exemplary structure after removal of a sacrificial support opening-filling structure according to the first embodiment of the present disclosure.

[0016] 6A to 6H is a vertical cross-sectional view of a memory opening during formation of a memory opening filling structure.

[0017] Fig. 7A is a vertical cross-sectional view of the first exemplary structure after forming a memory opening filling structure according to the first embodiment of the present disclosure.

[0018] Figure 7B yes Fig. 7A A top view of the first exemplary structure of FIG. The vertical plane AA' is Fig. 7A Vertical section plane.

[0019] Figure 7C is a vertical cross-sectional view of the first exemplary structure after forming a contact via cavity according to the first embodiment of the present disclosure.

[0020] Fig.7D is a vertical cross-sectional view of a first exemplary structure after forming a tubular insulating spacer according to the first embodiment of the present disclosure.

[0021] Fig. 7E is a vertical cross-sectional view of the first exemplary structure after forming a sacrificial via structure according to the first embodiment of the present disclosure.

[0022] Fig. 8A is a vertical cross-sectional view of the first exemplary structure after forming backside trenches according to the first embodiment of the present disclosure.

[0023] Figure 8B yes Fig. 8A A top view of the first exemplary structure of FIG. The hinged vertical plane A-A' is Fig. 8A A plane of a vertical section.

[0024] Figure 8C is along Figure 8B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0025] Fig.8D is along Figure 8B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0026] Fig. 8E is along Figure 8B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane EE'.

[0027] Fig. 9Ais a vertical cross-sectional view of the first exemplary structure after forming a conformal etch mask material layer according to the first embodiment of the present disclosure.

[0028] Fig. 9B yes Fig. 9A A top view of the first exemplary structure of FIG. The hinged vertical plane A-A' is Fig. 9A A plane of a vertical section.

[0029] Fig. 9C is along Fig. 9B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0030] Fig.9D is along Fig. 9B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0031] Fig.9E is along Fig. 9B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane EE'.

[0032] Fig. 10A is a vertical cross-sectional view of the first exemplary structure after patterning a conformal etch mask material layer according to the first embodiment of the present disclosure.

[0033] Fig. 10B yes Fig. 10A A top view of the first exemplary structure of FIG. The hinged vertical plane A-A' is Fig. 10A A plane of a vertical section.

[0034] Fig. 10C is along Fig. 10B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0035] Fig. 10D is along Fig. 10B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0036] Fig.10E is along Fig. 10B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane EE'.

[0037] Fig.11A is a vertical cross-sectional view of the first exemplary structure after forming a backside groove according to the first embodiment of the present disclosure.

[0038] Fig. 11B yes Fig.11A A top view of the first exemplary structure of FIG. The hinged vertical plane A-A' is Fig.11A A plane of a vertical section.

[0039] Fig. 11C is along Fig. 11B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0040] Fig.11D is along Fig. 11B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0041] Fig.11E is along Fig. 11B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane EE'.

[0042] Fig. 12A is a vertical cross-sectional view of a first exemplary structure after forming a conductive layer according to the first embodiment of the present disclosure.

[0043] Fig. 12B yes Fig. 12A A top view of the first exemplary structure of FIG. The hinged vertical plane A-A' is Fig. 12A A plane of a vertical section.

[0044] Fig. 12C is along Fig. 12B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0045] Fig.12D is along Fig. 12B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0046] Fig.12E is along Fig. 12B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane EE'.

[0047] Fig.12F is along Fig. 12A A horizontal cross-sectional view of the first exemplary structure taken along a horizontal plane FF'.

[0048] Fig.13A is a vertical cross-sectional view of the first exemplary structure after forming a backside trench fill structure according to the first embodiment of the present disclosure.

[0049] Fig. 13B yes Fig.13A A top view of the first exemplary structure of FIG. The hinged vertical plane A-A' is Fig.13A A plane of a vertical section.

[0050] Fig. 13C is along Fig. 13B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0051] Fig.13D is along Fig. 13B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0052] Fig.13E is along Fig. 13B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane EE'.

[0053] FIG. 14A to FIG. 14C are sequential vertical cross-sectional views of a contact region during a process of replacing a layer contact assembly with a layer contact assembly according to a first embodiment of the present disclosure.

[0054] Fig.15A is a vertical cross-sectional view of the first exemplary structure after forming a drain contact via structure according to the first embodiment of the present disclosure.

[0055] Fig. 15B yes Fig.15A A top view of a first exemplary structure.

[0056] Fig.16 is a vertical cross-sectional view of the first exemplary structure after forming an upper dielectric material layer and an upper metal interconnect structure according to the first embodiment of the present disclosure.

[0057] Fig.17 is a vertical cross-sectional view of the first exemplary structure after removal of the carrier substrate according to the first embodiment of the present disclosure.

[0058] Fig.18 is a vertical cross-sectional view of the first exemplary structure after forming a lower metal interconnection structure according to the first embodiment of the present disclosure.

[0059] Fig.19 is a vertical cross-sectional view of an alternative configuration of a first exemplary structure in which a substrate may be retained according to the first embodiment of the present disclosure.

[0060] Fig. 20 is a vertical cross-sectional view of a logic die according to a first embodiment of the present disclosure.

[0061] Fig.21 is a vertical cross-sectional view of a first exemplary structure after attaching a logic die to a memory die according to the first embodiment of the present disclosure.

[0062] Fig. 22 is a vertical cross-sectional view of an alternative configuration of the first exemplary structure after forming a conformal etch mask material layer according to the first embodiment of the present disclosure.

[0063] Fig.23Ais a vertical cross-sectional view of an alternative configuration of the first exemplary structure after forming a sacrificial backside trench fill structure according to the first embodiment of the present disclosure.

[0064] Fig. 23B yes Fig.23A A top view of the first exemplary structure of FIG. The hinged vertical plane A-A' is Fig.23A A plane of a vertical section.

[0065] Fig.23C is along Fig. 23B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0066] Fig.23D is along Fig. 23B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0067] Fig.23E is along Fig. 23B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane EE'.

[0068] Fig.24A is a vertical cross-sectional view of an alternative configuration of the first exemplary structure after removing an unmasked portion of the sacrificial backside trench fill structure according to the first embodiment of the present disclosure.

[0069] Fig. 24B yes Fig.24A A top view of the first exemplary structure of FIG. The hinged vertical plane A-A' is Fig.24A A plane of a vertical section.

[0070] Fig.24C is along Fig. 24B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0071] Fig.24D is along Fig. 24B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0072] Fig.24E is along Fig. 24B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane EE'.

[0073] Fig.25A is a vertical cross-sectional view of an alternative configuration of the first exemplary structure after patterning a conformal etch mask material layer according to the first embodiment of the present disclosure.

[0074] Fig.25B yes Fig.25A A top view of the first exemplary structure of FIG. The hinged vertical plane A-A' is Fig.25AA plane of a vertical section.

[0075] Fig.25C is along Fig.25B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0076] Fig.25D is along Fig.25B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0077] Fig.25E is along Fig.25B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane EE'.

[0078] Fig.26A is a vertical cross-sectional view of an alternative configuration of the first exemplary structure after removing the remaining portion of the sacrificial backside trench fill structure according to the first embodiment of the present disclosure.

[0079] Fig.26B yes Fig.26A A top view of the first exemplary structure of FIG. The hinged vertical plane A-A' is Fig.26A A plane of a vertical section.

[0080] Fig.26C is along Fig.26B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0081] Fig.26D is along Fig.26B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0082] Fig.26E is along Fig.26B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane EE'.

[0083] Fig.27A is a vertical cross-sectional view of a second exemplary structure after forming an array of dielectric spacer pillars according to the second embodiment of the present disclosure.

[0084] Fig.27B yes Fig.27A A top view of the second exemplary structure of FIG. The hinged vertical plane A-A' is Fig.27A A plane of a vertical section.

[0085] Fig.27C is along Fig.27B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0086] Fig.27D is along Fig.27BA vertical cross-sectional view of the second exemplary structure taken along a vertical plane DD'.

[0087] Fig.27E is along Fig.27B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane EE'.

[0088] Fig.28A is a vertical cross-sectional view of a second exemplary structure after a contact via structure in a forming process according to a second embodiment of the present disclosure.

[0089] Fig.28B yes Fig.28A A top view of the second exemplary structure of FIG. The hinged vertical plane A-A' is Fig.28A A plane of a vertical section.

[0090] Fig.29 is a vertical cross-sectional view of a second exemplary structure after forming a contact-level dielectric layer according to the second embodiment of the present disclosure.

[0091] Fig. 30A is a vertical cross-sectional view of a second exemplary structure after forming backside trenches according to the second embodiment of the present disclosure.

[0092] Fig. 30B yes Fig. 30A A top view of the second exemplary structure of FIG. The hinged vertical plane A-A' is Fig. 30A A plane of a vertical section.

[0093] Fig. 30C is along Fig. 30B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0094] Fig.30D is along Fig. 30B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane DD'.

[0095] Fig.30E is along Fig. 30B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane EE'.

[0096] Fig.31A is a vertical cross-sectional view of a second exemplary structure after forming a backside groove according to the second embodiment of the present disclosure.

[0097] Fig.31B yes Fig.31A A top view of the second exemplary structure of FIG. The hinged vertical plane A-A' is Fig.31A A plane of a vertical section.

[0098] Fig.31Cis along Fig.31B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0099] Fig.31D is along Fig.31B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane DD'.

[0100] Fig.31E is along Fig.31B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane EE'.

[0101] Fig.32A is a vertical cross-sectional view of a second exemplary structure after forming a conductive layer according to the second embodiment of the present disclosure.

[0102] Fig.32B yes Fig.32A A top view of the second exemplary structure of FIG. The hinged vertical plane A-A' is Fig.32A A plane of a vertical section.

[0103] Fig.32C is along Fig.32B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0104] Fig.32D is along Fig.32B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane DD'.

[0105] Fig.32E is along Fig.32B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane EE'.

[0106] Fig.32F is along Fig.32A A horizontal cross-sectional view of the second exemplary structure taken along a horizontal plane FF'.

[0107] Fig.33A is a vertical cross-sectional view of a second exemplary structure after forming a backside trench fill structure according to the second embodiment of the present disclosure.

[0108] Fig.33B yes Fig.33A A top view of the second exemplary structure of FIG. The hinged vertical plane A-A' is Fig.33A A plane of a vertical section.

[0109] Fig.33C is along Fig.33B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0110] Fig.33D is along Fig.33B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane DD'.

[0111] Fig.33E is along Fig.33B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane EE'.

[0112] Fig.33F is along Fig.33A A horizontal cross-sectional view of the second exemplary structure taken along a horizontal plane FF'.

[0113] Fig.34 is a vertical cross-sectional view of a second exemplary structure after forming a drain contact via structure, an upper metal interconnect structure, and a memory side pad and bonding with a logic die according to the second embodiment of the present disclosure.

[0114] Fig.35A is a vertical cross-sectional view of an alternative configuration of the second exemplary structure after forming backside trenches according to the second embodiment of the present disclosure.

[0115] Fig.35B yes Fig.35A A top view of the second exemplary structure of FIG. The hinged vertical plane A-A' is Fig.35A A plane of a vertical section.

[0116] Fig.35C is along Fig.35B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0117] Fig.35D is along Fig.35B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane DD'.

[0118] Fig.35E is along Fig.35B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane EE'.

[0119] Fig.36A is a vertical cross-sectional view of an alternative configuration of the second exemplary structure after forming a backside trench fill structure according to the second embodiment of the present disclosure.

[0120] Fig.36B yes Fig.36A A top view of the second exemplary structure of FIG. The hinged vertical plane A-A' is Fig.36A A plane of a vertical section.

[0121] Fig.36C is along Fig.36B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0122] Fig.36D is along Fig.36B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane DD'.

[0123] Fig.36E is along Fig.36B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane EE'.

[0124] Fig.36F is along Fig.36A A horizontal cross-sectional view of the second exemplary structure taken along a horizontal plane FF'.

[0125] Fig.37A is a vertical cross-sectional view of an alternative configuration of the second exemplary structure after forming a drain contact via structure, an upper metal interconnect structure, and a memory-side pad and bonding with a logic die according to the second embodiment of the present disclosure.

[0126] Fig.37B is a vertical sectional view of an additional alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure.

[0127] Fig.38A is a vertical cross-sectional view of a third exemplary structure after forming a memory opening filling structure and a support pillar structure according to the third embodiment of the present disclosure.

[0128] Fig.38B is along Fig.38A Horizontal cross-section of a second exemplary structure along horizontal plane HP2.

[0129] Fig.39A is a vertical cross-sectional view of a third exemplary structure after forming backside trenches according to a third embodiment of the present disclosure.

[0130] Fig.39B yes Fig.39A A top view of the third exemplary structure of FIG. The hinged vertical plane A-A' is Fig.39A A plane of a vertical section.

[0131] Fig.40A is a vertical cross-sectional view of the third exemplary structure after forming a sacrificial backside trench fill structure according to the third embodiment of the present disclosure.

[0132] Fig.40B yes Fig.40A A top view of the third exemplary structure of FIG. The hinged vertical plane A-A' is Fig.40A A plane of a vertical section.

[0133] Fig.41Ais a vertical cross-sectional view of a third exemplary structure after forming a fin-shaped trench according to a third embodiment of the present disclosure.

[0134] Fig.41B yes Fig.41A A top view of the third exemplary structure of FIG. The hinged vertical plane A-A' is Fig.41A A plane of a vertical section.

[0135] Fig.42A is a vertical cross-sectional view of a third exemplary structure after forming a fin-shaped dielectric isolation structure according to the third embodiment of the present disclosure.

[0136] Fig.42B yes Fig.42A A top view of the third exemplary structure of FIG. The hinged vertical plane A-A' is Fig.42A A plane of a vertical section.

[0137] Fig.43A is a vertical cross-sectional view of the third exemplary structure after removal of the sacrificial backside trench fill structure according to the third embodiment of the present disclosure.

[0138] Fig.43B yes Fig.43A A top view of the third exemplary structure of FIG. The hinged vertical plane A-A' is Fig.43A A plane of a vertical section.

[0139] Fig.44A is a vertical cross-sectional view of a third exemplary structure after forming a backside groove according to a third embodiment of the present disclosure.

[0140] Fig.44B yes Fig.44A A top view of the third exemplary structure of FIG. The hinged vertical plane A-A' is Fig.44A A plane of a vertical section.

[0141] Fig.45A is a vertical cross-sectional view of a third exemplary structure after forming a conductive layer and a backside trench fill structure according to a third embodiment of the present disclosure.

[0142] Fig.45B yes Fig.45A A top view of the third exemplary structure of FIG. The hinged vertical plane A-A' is Fig.45A A plane of a vertical section.

[0143] Fig.45C It is along Fig.45A A horizontal cross-sectional view of the third exemplary structure taken along a horizontal plane CC'.

[0144] Fig.46Ais a vertical cross-sectional view of a third exemplary structure after forming a drain contact via structure according to the third embodiment of the present disclosure.

[0145] Fig.46B yes Fig.46A A top view of a third exemplary structure of FIG.

[0146] Fig.47 is a vertical cross-sectional view of a third exemplary structure after attaching a logic die to a memory die according to the third embodiment of the present disclosure.

[0147] Fig.48A is a vertical cross-sectional view of the fourth exemplary structure after forming a patterned photoresist layer and removing an unmasked sacrificial backside trench fill structure according to the fourth embodiment of the present disclosure.

[0148] Fig.48B yes Fig.48A A top view of a fourth exemplary structure of FIG. The hinged vertical plane A-A' is Fig.48A A plane of a vertical section.

[0149] Fig.49A is a vertical cross-sectional view of a fourth exemplary structure after forming isolation trenches according to the fourth embodiment of the present disclosure.

[0150] Fig.49B yes Fig.49A A top view of a fourth exemplary structure of FIG. The hinged vertical plane A-A' is Fig.49A A plane of a vertical section.

[0151] Fig.50A is a vertical cross-sectional view of a fourth exemplary structure after forming a dielectric isolation structure according to a fourth embodiment of the present disclosure.

[0152] Fig.50B yes Fig.50A A top view of a fourth exemplary structure of FIG. The hinged vertical plane A-A' is Fig.50A A plane of a vertical section.

[0153] Fig.51A is a vertical cross-sectional view of the fourth exemplary structure after removal of the sacrificial backside trench fill structure according to the fourth embodiment of the present disclosure.

[0154] Fig.51B yes Fig.51A A top view of a fourth exemplary structure of FIG. The hinged vertical plane A-A' is Fig.51A A plane of a vertical section.

[0155] Fig.52Ais a vertical cross-sectional view of a fourth exemplary structure after forming a conductive layer and a backside trench fill structure according to a fourth embodiment of the present disclosure.

[0156] Fig.52B yes Fig.52A A top view of a fourth exemplary structure of FIG. The hinged vertical plane A-A' is Fig.52A A plane of a vertical section.

[0157] Fig.52C is along Fig.52A A horizontal cross-sectional view of the fourth exemplary structure taken along a horizontal plane CC'.

[0158] Fig.53A is a vertical cross-sectional view of a fourth exemplary structure after forming a drain contact via structure according to the fourth embodiment of the present disclosure.

[0159] Fig.53B yes Fig.53A A top view of a fourth exemplary structure of FIG.

[0160] Fig.54 is a vertical cross-sectional view of a fourth exemplary structure after attaching a logic die to a memory die according to a fourth embodiment of the present disclosure. DETAILED DESCRIPTION

[0161] As described above, embodiments of the present disclosure relate to a three-dimensional memory device including an inter-block word line lateral isolation structure for a step-less contact via structure and a method of forming the same, and various aspects thereof are now described in detail.

[0162] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of an element is shown, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first," "second," and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0163] The same reference numerals represent the same element or similar element. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other, the two elements are "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or a "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0164] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a first continuous structure. For example, a layer may be located between the top and bottom surfaces of a first continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the first continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0165] As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from the vertical direction at an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or a substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0166] As used herein, a "memory level" or "memory array level" refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the array of memory elements and a second horizontal plane including the bottommost surface of the array of memory elements. As used herein, a "through-stack" element refers to an element that extends vertically through a memory level.

[0167] As used herein, "semiconductor material" refers to a semiconductor material having a-5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m, and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0×10 7 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / m. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material (i.e., providing a conductivity greater than 1.0×10 5 S / m) of a semiconductor material. A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 7 S / m in the range of 1000 Å / s. A semiconductor material having an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with a conductivity in the range of 1000 Å / s. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0168] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded through, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Generally speaking, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some restrictions. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. Pages are also the smallest units that can be selected for read operations.

[0169] refer to Figure 1A and Figure 1B , according to the first exemplary structure of the first embodiment of the present disclosure, includes a substrate 8. The substrate 8 may be a carrier substrate that is subsequently removed. The substrate 8 may include a semiconductor material (e.g., a silicon wafer), an insulating material, a conductive material, or a combination thereof. The substrate 8 includes a material that can provide structural support for a material portion that is subsequently formed thereon. The substrate 8 includes a substrate material layer 9 at least at its upper portion. In one embodiment, the substrate material layer 9 may be a semiconductor material layer, such as a doped well in a silicon layer or a silicon wafer. In another embodiment, the substrate material layer 9 may be an insulating layer, such as silicon oxide. Optionally, the lower metal interconnect structure 480 may be located below the insulating substrate material layer 9 or may be embedded in the insulating substrate material layer 9.

[0170] The first exemplary structure includes a memory array region 100 where a three-dimensional memory array is subsequently formed, a contact region 200 where a layer contact via structure is subsequently formed, and a connection region 400 where a connection via structure is subsequently formed.

[0171] An alternating stack of insulating layers 32 and sacrificial material layers 42 may be formed over substrate 8. The alternating stack of insulating layers 32 and sacrificial material layers 42 is a vertical alternating sequence of insulating layers 32 and sacrificial material layers 42 that alternate in a vertical direction. Each insulating layer 32 may include an insulating material, and each sacrificial material layer 42 may include a sacrificial material. As used herein, "sacrificial material" refers to a material that is removed during a subsequent processing step.

[0172] As used herein, the alternating stacking of the first element and the second element refers to a structure in which an instance of the first element and an instance of the second element are alternating. Each instance of the first element that is not an end element of the alternating plurality of elements adjoins two instances of the second element on both sides, and each instance of the second element that is not an end element of the alternating plurality of elements adjoins two instances of the first element on both ends. The first element may have the same thickness therebetween, or may have different thicknesses. The second element may have the same thickness therebetween, or may have different thicknesses. The alternating plurality of first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, an instance of the first element and an instance of the second element may form a unit that is periodically repeated within the alternating plurality of elements.

[0173] Insulating materials that can be used for insulating layer 32 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials, which are generally referred to as high dielectric constant (high-k) dielectric oxides. In one embodiment, the first material of insulating layer 32 may be silicon oxide.

[0174] The sacrificial material of sacrificial material layer 42 includes a material that is selectively removable with respect to the material of insulating layer 32. As used herein, removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0175] The sacrificial material layer 42 may include a dielectric material, a semiconductor material, or a conductive material. The material of the sacrificial material layer 42 may then be replaced with a conductive electrode that may be used, for example, as a control gate electrode of a vertical NAND device. In one embodiment, the sacrificial material layer 42 may be a material layer including silicon nitride.

[0176] In one embodiment, the insulating layer 32 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The insulating layer 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the sacrificial material layer 42 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0177] The thickness of the insulating layer 32 and the sacrificial material layer 42 may be in the range of 20 nm to 50 nm, but lesser and greater thicknesses may be used for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of the insulating layer 32 and sacrificial material layer 42 pair may be in the range of 2 to 1,024, typically 8 to 256, but greater numbers of repetitions may also be used. In one embodiment, each sacrificial material layer 42 in the vertical alternating sequence (32, 42) may have a uniform thickness that is substantially constant within each respective sacrificial material layer 42. The bottommost layer in the insulating layer 32 is referred to herein as the bottommost insulating layer 32B. The topmost layer in the insulating layer 32 is referred to herein as the topmost insulating layer 32T.

[0178] A photoresist material stack (not shown) including at least a photoresist layer may be formed over the topmost insulating layer 32T and may be photolithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region 100 and a second set of openings formed over the contact region 200 and the connection region 400. The pattern in the photoresist material stack may be transferred through the alternating stack (32, 42) by at least one anisotropic etching using the patterned photoresist material stack as an etching mask. Portions of the alternating stack (32, 42) below the openings in the patterned photoresist material stack are etched to form memory openings 49 and support openings 19. As used herein, "memory opening" refers to a structure in which a memory element such as a memory stack structure is subsequently formed therein. As used herein, "support opening" refers to a structure in which a support structure (such as a support column structure) that mechanically supports other elements is subsequently formed. Memory opening 49 is formed in the memory array region 100. Support opening 19 is formed in the contact region 200 and in the connection region 400.

[0179] The chemistry of the anisotropic etching process used to etch through the material of the alternating stack (32, 42) can be alternating to optimize the etching of the first material and the second material in the alternating stack (32, 42). The anisotropic etching can be, for example, a series of reactive ion etchings. The sidewalls of the storage opening 49 and the support opening 19 can be substantially vertical, or can be tapered. The patterned photolithographic material stack can then be removed, for example, by ashing.

[0180] The memory openings 49 and the support openings 19 may extend from the top surface of the alternating stack (32, 42) to at least a horizontal plane including the topmost surface of the substrate material layer 9. In one embodiment, after the top surface of the substrate material layer 9 is physically exposed at the bottom of each memory opening 49 and each support opening 19, overetching of the substrate material layer 9 may be optionally performed. Overetching may be performed before or after removing the photolithographic material stack. In other words, the recessed surface of the substrate material layer 9 may be vertically offset from the non-recessed top surface of the substrate material layer 9 by a recessed depth. The recessed depth may be in the range of, for example, 1 nm to 50 nm, but smaller and larger recessed depths may also be used. Overetching is optional and may be omitted. If overetching is not performed, the bottom surfaces of the memory openings 49 and the support openings 19 may be coplanar with the topmost surface of the substrate material layer 9.

[0181] Each of the memory opening 49 and the support opening 19 may include a sidewall (or multiple sidewalls) extending substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings 49 may be formed in the memory array region 100. A two-dimensional array of support openings 19 may be formed in the contact region 200 and the connection region 400.

[0182] refer to Figure 2A and Figure 2B , sacrificial fill material can be deposited in the memory opening 49 and the support opening 19. The sacrificial fill material can be any material that can be selectively removed from the materials of the insulating layer 32, the sacrificial material layer 42, and the substrate material layer 9. For example, the sacrificial fill material may include a carbon-based material (such as amorphous carbon or diamond-like carbon), a semiconductor material (such as a silicon-germanium alloy, polycrystalline silicon, or amorphous silicon), or a dielectric material (such as borosilicate glass or organic silicate glass). Optionally, a thin etch stop liner (not shown) may be used to facilitate subsequent selective removal of the sacrificial fill material. Excess portions of the sacrificial fill material may be removed from above a horizontal plane including the top surface of the topmost insulating layer 32T. Each remaining portion of the sacrificial fill material filling the memory opening 49 constitutes a sacrificial memory opening filling structure 47. Each remaining portion of the sacrificial fill material filling the support opening 19 constitutes a sacrificial support opening filling structure 17.

[0183] refer to Figure 3, a photoresist layer (not shown) may be applied over the exemplary structure and may be photolithographically patterned to cover the memory array region 100 without covering the contact region 200 and the connection region 400. The sacrificial support opening filling structure 17 may be removed by removing the sacrificial filling material in the area not covered by the photoresist layer. For example, the sacrificial filling material may be removed by ashing or by performing an etching process such as a wet etching process. A cavity is formed in the support opening 19. The photoresist layer may be removed, for example, by ashing.

[0184] refer to Figure 4 , a dielectric fill material such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass may be deposited in the support opening 19 using a conformal deposition process such as a chemical vapor deposition process. For example, the portion of the dielectric fill material covering the topmost insulating layer 32T may be removed by chemical mechanical polishing or by an etch-back process such as a wet etch process using dilute hydrofluoric acid. The remaining portion of the dielectric fill material filling the support opening 19 includes a support post structure 20, which is a dielectric post structure that provides structural support to the exemplary structure during a subsequent processing step of removing the sacrificial material layer 42.

[0185] refer to Figure 5 , the sacrificial filling material of the sacrificial memory opening filling structure 47 can be removed selectively to the materials of the insulating layer 32, the sacrificial material layer 42, the semiconductor material layer 10, and the support pillar structure 20. The sacrificial memory opening filling structure 47 can be removed by ashing or by performing an etching process such as a wet etching process. A cavity is formed in the volume from which the sacrificial memory opening filling structure 47 is removed.

[0186] 6A to 6H is a vertical cross-sectional view of a memory opening during formation of a memory opening filling structure 58. The same structural changes occur simultaneously in each of the other memory openings 49,

[0187] refer to Fig. 6A , showing Figure 5 Memory opening 49 in an exemplary device structure of FIG. Memory opening 49 extends through the topmost insulating layer 32 (32T), the alternating stack (32, 42), and optionally extends into the upper portion of substrate material layer 9. The bottom surface of each memory opening may be recessed to a depth in the range of 0 nm to 30 nm relative to the top surface of substrate material layer 9, but a greater recess depth may also be employed. Optionally, sacrificial material layer 42 may be partially recessed laterally to form a lateral groove (not shown), for example, by isotropic etching.

[0188] refer to Figure 6B, an optional pedestal channel portion (e.g., epitaxial pedestal) 11 may be formed, for example, by selective epitaxy, at the bottom portion of each memory opening 49 and each support opening 19. Each pedestal channel portion 11 includes a single crystalline semiconductor material (e.g., single crystalline silicon) epitaxially aligned with the single crystalline substrate material layer 9. In one embodiment, the pedestal channel portion 11 may be doped with an electrical dopant of the same conductivity type as the substrate material layer 9. In one embodiment, the top surface of each pedestal channel portion 11 may be formed above a horizontal plane including the top surface of at least one bottommost sacrificial material layer 42. In this case, at least one source select gate electrode may be subsequently formed by replacing each sacrificial material layer 42 located below the horizontal plane including the top surface of the pedestal channel portion 11 with a corresponding conductive material layer. The pedestal channel portion 11 may be a portion of a transistor channel extending between a source region that will be subsequently formed in or above the substrate material layer 9 and a drain region that will be subsequently formed in an upper portion of the memory opening 49. A memory cavity 49' exists in an unfilled portion of the memory opening 49 above the pedestal channel portion 11. In one embodiment, the pedestal channel portion 11 may comprise single crystal silicon. In one embodiment, the pedestal channel portion 11 may have a doping of a first conductivity type that is the same conductivity type as the substrate material layer 9 that the pedestal channel portion contacts.

[0189] refer to Figure 6C A stack of layers including an optional blocking dielectric layer 52 , a memory material layer 54 , a dielectric material liner 56 , and an optional sacrificial capping material layer 601 may be sequentially deposited in the memory opening 49 by respective conformal deposition processes.

[0190] The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is essentially composed of a dielectric metal oxide. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. In one embodiment, the blocking dielectric layer 52 may include multiple dielectric metal oxide layers having different material compositions. Alternatively or in addition, the blocking dielectric layer 52 may include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may include silicon oxide. The thickness of the blocking dielectric layer 52 may be in the range of 3nm to 20nm, but smaller and larger thicknesses may also be used. Alternatively, the blocking dielectric layer 52 may be omitted, and a backside blocking dielectric layer may be formed after a backside groove is formed on the surface of the memory film to be formed subsequently.

[0191] Subsequently, a memory material layer 54 may be formed. In general, the memory material layer 54 may include any memory material that can store data bits. The data bits may be stored in the form of charge trapped therein, in the form of a resistive state of the material, due to a change in the phase, resistivity, or ferroelectric properties of the material. In one embodiment, the memory material layer 54 may include a charge storage layer. In one embodiment, the memory material layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the memory material layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer 42 within a lateral groove. In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 may have vertically coincident sidewalls, and the memory material layer 54 may be formed as a single continuous layer.

[0192] In another embodiment, the sacrificial material layer 42 may be laterally recessed relative to the sidewalls of the insulating layer 32, and a combination of a deposition process and anisotropic etching process may be employed to form the memory material layer 54 into a plurality of vertically spaced memory material portions. Although the memory material layer 54 is shown as a single continuous layer, embodiments in which the memory material layer 54 is replaced by a plurality of vertically spaced discrete memory material portions (which may be charge trapping material portions or electrically isolated conductive material portions) are expressly contemplated herein. The memory material layer 54 may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the memory material layer 54 may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be employed.

[0193] The dielectric material liner 56 includes a dielectric material. In one embodiment, the dielectric material liner 56 may include a tunneling dielectric layer through which charge tunneling may be performed under suitable electrical bias conditions. Charge tunneling may be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be used. Alternatively, different types of dielectric material layers may be used as the dielectric material liner 56.

[0194] The optional sacrificial covering material layer 601 includes a sacrificial material that can be subsequently selectively removed for the material of the dielectric material liner 56. In one embodiment, the sacrificial covering material layer 601 may include a semiconductor material such as amorphous silicon, or may include a carbon-based material such as amorphous carbon or diamond-like carbon (DLC). The sacrificial covering material layer 601 may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the sacrificial covering material layer 601 may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be used. The memory cavity 49' is formed in the space of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 601).

[0195] refer to Fig.6D, at least one anisotropic etching process is used to anisotropically etch the optional sacrificial covering material layer 601, the dielectric material liner 56, the memory material layer 54 and the blocking dielectric layer 52 covering the topmost insulating layer 32 (32T) in sequence. The portions of the sacrificial covering material layer 601, the dielectric material liner 56, the memory material layer 54 and the blocking dielectric layer 52 located above the top surface of the topmost insulating layer 32 (32T) can be removed by at least one anisotropic etching process. In addition, the horizontal portions of the sacrificial covering material layer 601, the dielectric material liner 56, the memory material layer 54 and the blocking dielectric layer 52 at the bottom of each memory cavity 49' can be removed to form an opening in the remaining portion thereof. Each of the sacrificial covering material layer 601, the dielectric material liner 56, the memory material layer 54 and the blocking dielectric layer 52 can be etched by a corresponding anisotropic etching process using a corresponding etching chemistry, which can be the same or different for the various material layers.

[0196] Each remaining portion of the sacrificial capping material layer 601 may have a tubular configuration. The memory material layer 54 may include a charge trapping material, a floating gate material, a ferroelectric material, a resistive memory material that can provide at least two different levels of resistivity (such as a phase change material), or any other memory material that can store information by changing state. In one embodiment, each memory material layer 54 may include a vertical stack of charge storage regions that store charge when programmed. In one embodiment, the memory material layer 54 may be a memory material layer in which each portion adjacent to the sacrificial material layer 42 constitutes a charge storage region.

[0197] The surface of the base channel portion 11 (or the surface of the substrate material layer 9 in the case where the base channel portion 11 is not adopted) can be physically exposed below the opening through the sacrificial cover material layer 601, the dielectric material liner 56, the memory material layer 54 and the blocking dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49' can be vertically recessed, so that the recessed semiconductor surface below the memory cavity 49' is vertically offset from the topmost surface of the base channel portion 11 (or the substrate material layer 9 in the case where the base channel portion 11 is not adopted) by a recessed distance. The dielectric material liner 56 is located above the memory material layer 54. A set of blocking dielectric layers 52, memory material layers 54 and dielectric material liner 56 in the memory opening 49 constitutes a memory film 50, which includes a plurality of charge storage regions (including a portion of the memory material layer 54), and the plurality of charge storage regions are insulated from surrounding materials by the blocking dielectric layer 52 and the dielectric material liner 56. In one embodiment, the sacrificial capping material layer 601, the dielectric material liner 56, the memory material layer 54, and the blocking dielectric layer 52 may have vertically coincident sidewalls. Optionally, the sacrificial capping material layer 601 may be subsequently removed selectively to the material of the dielectric material liner 56. If the sacrificial capping material layer 601 comprises amorphous silicon, a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH) may be performed to remove the sacrificial capping material layer 601.

[0198] refer to Fig. 6E , the semiconductor channel layer 60L can be deposited directly on the semiconductor surface of the base channel portion 11 or on the substrate material layer 9 (if the base channel portion 11 is omitted), and directly on the dielectric material liner 56 (or on the silicon sacrificial cap material layer 601, if it still exists). The semiconductor channel layer 60L includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0199] In one embodiment, the semiconductor channel layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel layer 60L may have a first conductivity type of doping, which is the same as the conductivity type of the substrate material layer 9 and the base channel portion 11. The semiconductor channel layer 60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer 60L can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The semiconductor channel layer 60L can partially fill the memory cavity 49' in each memory opening, or can completely fill the cavity in each memory opening.

[0200] refer to Fig. 6F In the case where the memory cavity 49' in each memory opening is not completely filled with the semiconductor channel layer 60L, a dielectric core layer 62L can be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' within each memory opening. The dielectric core layer 62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer 62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD) or by a self-planarization deposition process such as spin coating.

[0201] refer to Figure 6G , horizontal portions of dielectric core layer 62L may be removed, for example, by a recess etching process, so that each remaining portion of dielectric core layer 62L is located within a corresponding memory opening 49 and has a corresponding top surface below a horizontal plane including a top surface of topmost insulating layer 32 (32T). Each remaining portion of dielectric core layer 62L constitutes dielectric core 62.

[0202] refer to Figure 6H , a doped semiconductor material having a doping of the second conductivity type may be deposited in each recessed region above the dielectric core 62. The deposited semiconductor material may have a doping of the second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material may be between 5.0×10 18 / cm 3 Up to 2.0×10 21 / cm 3 The doped semiconductor material may be, for example, doped polysilicon.

[0203] Excess portions of the deposited semiconductor material of the horizontal portion of the doped semiconductor channel layer 60L having the second conductivity type can be removed from above the horizontal plane including the top surface of the topmost insulating layer 32 (32T) (e.g., by chemical mechanical planarization (CMP) or a recess etching process). Each remaining portion of the doped semiconductor material having the second conductivity type constitutes a drain region 63. Each remaining portion of the doped semiconductor channel layer 60L having the first conductivity type constitutes a vertical semiconductor channel 60. The vertical semiconductor channel 60 is formed directly on the dielectric material liner 56.

[0204] Each adjacent group of the blocking dielectric layer 52, the memory material layer 54, and the dielectric material liner 56 together constitutes a memory film 50 that can store charge or polarization for a macroscopic retention time. As used herein, the macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and a backside blocking dielectric layer may be subsequently formed after forming the backside grooves.

[0205] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a semiconductor channel, a dielectric material liner, a plurality of memory elements embodied as part of a memory material layer 54, and an optional blocking dielectric layer 52. The entire set of material portions filling the memory opening 49 is referred to herein as a memory opening filling structure 58. The entire set of material portions filling the support opening 19 constitutes a support pillar structure.

[0206] Generally, a memory opening filling structure 58 may be formed within each memory opening 49. The memory opening filling structure 58 includes an optional blocking dielectric layer 52, a memory material layer 54, an optional dielectric material liner 56, and a vertical semiconductor channel 60. The dielectric material liner 56 may laterally surround the vertical semiconductor channel 60. The memory material layer 54 may laterally surround the dielectric material liner 56.

[0207] In the case where blocking dielectric layer 52 is present in each memory opening filling structure 58, blocking dielectric layer 52 may be formed on the sidewalls of memory opening 49, and a vertical stack of memory elements (which may include portions of memory material layer 54) may be formed on blocking dielectric layer 52. In one embodiment, the vertical stack of memory elements includes portions of the charge storage layer (including memory material layer 54) at the level of sacrificial material layer 42.

[0208] refer to Fig. 7A and Figure 7B , shows an exemplary structure after forming a memory opening filling structure 58 and a support pillar structure 20 in the memory opening 49 and the support opening 19, respectively. Figure 5 An instance of memory opening fill structure 58 is formed within each memory opening 49 of the structure. Figure 5 An instance of a support pillar structure 20 is formed within each support opening 19 of the structure. Alternatively, alternative memory stack structures including different layer stacks or structures for the memory film 50 and / or for the vertical semiconductor channel 60 may actually be used.

[0209] refer to Figure 7C, contact via cavities 89 having different depths may be formed in the contact region 200. Each of the contact via cavities 89 extends vertically through a respective subset of the layers within the alternating stack (32, 42) and has a respective bottom surface that includes a segment of a respective sacrificial material layer 42. Generally speaking, the support post structures 20 positioned within the region of the contact via cavities 89 may be recessed side by side during the formation of the contact via cavities 89. In one embodiment, a major portion of each support post structure 20 positioned within the region of the contact via cavities 89 has a recessed surface that is coplanar or substantially coplanar with a physically exposed segment of the sacrificial material layer 42 that is located below the respective contact via cavity 89.

[0210] In one embodiment, each sacrificial material layer 42 that is subsequently replaced with a word line level conductive layer (i.e., word line) can be physically exposed to at least one contact via cavity 89. In other words, the contact via cavities 89 can be formed such that each of the sacrificial material layers 42 that are subsequently replaced with a corresponding word line level conductive layer is physically exposed to a set of at least one contact via cavity 89 within the contact region. In one embodiment, one or more topmost sacrificial material layers 42 are subsequently replaced with a drain select level conductive layer (i.e., drain select gate electrode), and each of the sacrificial material layers 42 except the topmost sacrificial material layer 42 can include a corresponding surface segment that is physically exposed below the corresponding contact via cavity in the contact via cavity 89. The contact via cavity can also be formed to the level of the source select gate electrode located below the word line level.

[0211] In general, any suitable method may be used to form the contact via cavity 89. For illustrative purposes, one embodiment method of forming the contact via cavity 89 is described below.

[0212] In one embodiment, a sacrificial etch mask layer (not shown) may be formed above the alternating stack (32, 42). The sacrificial etch mask layer may include any etch mask material that can withstand the ashing process for subsequently removing the patterned photoresist material layer. For example, the sacrificial etch mask layer may include a dielectric metal oxide material, a metallic material, or a carbon-based material. A high-fidelity photoresist material such as a deep ultraviolet (DUV) photoresist material may be applied above the sacrificial etch mask layer and may be patterned to form an opening that defines the area of ​​all contact via cavities 89 to be subsequently formed. An anisotropic etching process may be performed to form an opening through the sacrificial etch mask layer. An array of openings is formed through the sacrificial etch mask layer. The high-fidelity photoresist material may then be removed.

[0213] A combination of a series of barrier-level photoresist materials, such as mid-ultraviolet (MUV) photoresist materials, and a series of anisotropic etching processes can then be used to sequentially cover corresponding subsets of the openings in the sacrificial etching mask layer, and extend the pattern of the openings in the sacrificial etching mask layer through the stack of corresponding numbers of insulating layers 32 and sacrificial material layers 42. For example, about half of all openings through the sacrificial etching mask layer can be covered by a first barrier-level photoresist layer, and one insulating layer 32 and one sacrificial material layer 42 can be etched by performing an anisotropic etching process under the openings through the unmasked portions of the sacrificial material layer. Any unmasked portions of the support post structure 20 can be etched together by selecting the etching chemistry of the various etching steps of the anisotropic etching process so that the overall etching rate of the material of the support post structure 20 matches the overall etching rate of the combination of the insulating layer 32 and the sacrificial material layer 42. The first barrier-level photoresist layer can then be removed. About half of all openings through the sacrificial etching mask layer can be covered by a second barrier-level photoresist layer. Approximately half of the unmasked openings are in the openings previously covered by the first barrier level photoresist layer, and the remaining unmasked openings are in the openings previously masked by the first barrier level photoresist layer. Two pairs of insulating layers 32 and sacrificial material layers 42 (i.e., two insulating layers 32 and two sacrificial material layers 42) can be etched by performing an anisotropic etching process beneath the openings through the unmasked portions of the sacrificial material layers. Any unmasked portions of the support column structure 20 can be co-etched by selecting the etching chemistries of the various etching steps of the anisotropic etching process so that the overall etching rate of the material of the support column structure 20 matches the overall etching rate of the combination of the insulating layer 32 and the sacrificial material layer 42. The second barrier level photoresist layer can then be removed. The above scheme can be repeated until the Nth barrier level photoresist layer, and etching 2 is performed. (N-1) Nth anisotropic etching process for insulating layer 32 and sacrificial material layer 42. For example, a terminal anisotropic etching process may be performed in the absence of any barrier-level photoresist layer to etch through corresponding groups of unmasked portions of the two insulating layers 32 and sacrificial material layer 42 that are located below any openings through the sacrificial etch mask layer.

[0214] With 2 N Contact via cavities 89 of different depths may be formed in the contact region 200. In an illustrative example, if N is 8, the total number of sacrificial material layers 42 may be 2. 8+M, which corresponds to 256 word line level sacrificial material layers and M source and drain select level sacrificial material layers. Although the present disclosure is described for the case where M is 2, embodiments in which M can be an integer greater than 2 are expressly contemplated herein. The sacrificial etch mask layer can then be removed, for example, by ashing or by performing an etching process that selectively removes the material of the sacrificial etch mask layer with respect to the material of the alternating stack (32, 42).

[0215] refer to Fig.7D , the insulating material layer can be conformally deposited over the physically exposed surface of the contact via cavity 89 and over the alternating stack (32, 42). The insulating material layer includes an insulating material, such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass. The thickness of the insulating material layer can be in the range of 10nm to 100nm, but smaller and larger thicknesses can also be used. In one embodiment, an anisotropic etching process (i.e., a sidewall spacer etching process) can be performed to remove the horizontal extension of the insulating material layer at the bottom of each contact via cavity 89 and over the alternating stack (32, 42). Each remaining portion of the insulating material layer includes an insulating spacer having a tubular configuration and is referred to herein as a tubular insulating spacer 84. A void 89' exists within each unfilled volume of the contact via cavity 89. Alternatively, an anisotropic etching process can be performed at a later step after removing the sacrificial fill material from the void 89' and replacing the sacrificial material layer 42 with a conductive layer.

[0216] refer to Fig. 7E , a sacrificial fill material can be deposited in the void 89' within the contact via cavity 89. The sacrificial fill material includes a material that can be selectively removed subsequently with respect to the material of the tubular insulating spacer 84, the insulating layer 32, and the support column structure 20. For example, the sacrificial fill material may include a carbon-based material (such as amorphous carbon or diamond-like carbon), a semiconductor material (such as amorphous silicon, polycrystalline silicon, or a silicon-germanium alloy), or a dielectric material (such as borosilicate glass or organic silicate glass). Excess portions of the sacrificial fill material can be removed from above a horizontal plane including the top surface of the alternating stack using a planarization process. The planarization process may include a recessed etching process or a chemical mechanical polishing process. Each remaining portion of the sacrificial fill material constitutes a sacrificial via structure 85.

[0217] Each successive combination of tubular insulating spacers 84 and sacrificial via structures 85 is referred to herein as a mid-process layer contact component 26. The mid-process layer contact component 26 is formed in the contact region 200 through a corresponding subset of the layers within the alternating stack (32, 42) and directly on the top surface of a corresponding sacrificial material layer in the sacrificial material layers 42 within the alternating stack (32, 42). Each of the mid-process layer contact components 26 includes a corresponding tubular insulating spacer 84 and a corresponding sacrificial via structure 85.

[0218] Generally speaking, the memory stack structure 55 is located within the memory array region 100, and the process layer contact component 26 is located in the contact region 200 that is laterally offset from the memory array region 100. In one embodiment, the contact region 200 may not contain any memory stack structure 55. Instead, the support column structure 20 including the dielectric material and / or substantially consisting of the dielectric material may be located within the contact region 200. The support column structure 20 may contact the substrate 8 including the substrate material layer 9, and may extend through at least the bottommost insulating layer 32B within the alternating stack (32, 42). In one embodiment, a subset of the support column structures 20 may have a topmost recessed surface that contacts the bottom surface of the corresponding process layer contact component in the process layer contact component 26. In subsequent figures, the support column structure 20 is omitted for clarity.

[0219] Still refer to Fig. 7E The contact level dielectric layer 80 may be formed over the alternating stack (32, 42) and the process layer contact component 26 by conformal or non-conformal deposition of dielectric material. The contact level dielectric layer 80 includes a dielectric material such as undoped silicate glass or doped silicate glass. The thickness of the contact level dielectric layer 80 may be in the range of 50 nm to 600 nm, such as 100 nm to 300 nm, but lesser and greater thicknesses may also be used.

[0220] refer to FIG. 8A to FIG. 8E , a photoresist layer (not shown) may be applied over the contact level dielectric layer 80 and photolithographically patterned to form elongated openings in the regions between the clusters of memory opening fill structures 58. The pattern in the photoresist layer may be transferred through the contact level dielectric layer 80 and the alternating stack (32, 42) using anisotropic etching to form backside trenches 79. The backside trenches 79 extend vertically from the top surface of the contact level dielectric layer 80 to the top surface of the substrate 8. The backside trenches 79 extend laterally along a first horizontal direction hd1 between adjacent arrays of memory opening fill structures 58 and between adjacent arrays of in-process layer contact components 26. In one embodiment, the backside trenches 79 may extend laterally through the memory array region 100 and the contact region 200.

[0221] In one embodiment, the backside trenches 79 may extend laterally along a first horizontal direction (e.g., a word line direction) hd1, and may be laterally spaced apart from each other along a second horizontal direction (e.g., a bit line direction) hd2 perpendicular to the first horizontal direction hd1. The memory opening filling structures 58 may be arranged in rows extending along the first horizontal direction hd1. Multiple rows of memory opening filling structures 58 may be located between each adjacent pair of backside trenches 79 in a corresponding memory block. Thus, the backside trenches separate adjacent memory blocks along the bit line direction hd2. The photoresist layer may be removed, for example, by ashing.

[0222] Generally, backside trenches 79 extending laterally along a first horizontal direction hd1 may be formed through a vertical alternating sequence of insulating layers 32 and sacrificial material layers 42. Backside trenches 79 are laterally spaced apart along a second horizontal direction hd2. Figure 8B As shown, the strip portions SP of the vertical alternating sequence located between adjacent pairs of backside trenches 79 can be interconnected with each other in the connection area 400 through the connection portions CP of the vertical alternating sequence, which are connected to each strip portion of the vertical alternating sequence of strip portions SP. Therefore, adjacent memory blocks separated along the bit line direction hd2 are still connected to each other through the connection portions CP located in the connection area 400.

[0223] refer to 9A to 9E , a dielectric material different from the material of the sacrificial material layer 42 can be conformally deposited in the peripheral portion of the backside trench 79 and deposited above the contact level dielectric layer 80 to form a conformal dielectric material layer, which is then used as an etching mask structure. The conformal dielectric material layer is referred to as a conformal etching mask material layer 81L herein. The conformal etching mask material layer 81L includes a dielectric material, such as silicon oxide, and can have a thickness in the range of 5nm to 100nm (such as 10nm to 50nm), but smaller and larger thicknesses can also be used. The conformal etching mask material layer 81L can be formed by a conformal deposition process such as a chemical vapor deposition process. The conformal etching mask material layer 81L can cover all surfaces of the backside trench 79.

[0224] refer to FIG. 10A to FIG. 10E, a photoresist layer 77 may be applied on the conformal etch mask material layer 81L and may be photolithographically patterned to cover end portions of the backside trenches 79 in the connection portion CP extending into the connection region 400 without covering a major portion of each of the backside trenches 79 in the contact region 200 and the memory array region 100. In one embodiment, the patterned photoresist layer 77 may cover an area of ​​the connection region 400 and an area of ​​a peripheral portion of the contact region 200 proximate to the connection region 400 without covering an area of ​​the memory array region 100 and without covering an area of ​​a portion of the contact region 200 that is not proximate to the connection region 400. In one embodiment, the patterned photoresist layer 77 may have a straight edge that extends laterally along the second horizontal direction hd2 and crosses each longitudinal sidewall of the backside trench 79 near a boundary between the contact region 200 and the connection region 400 (e.g., a boundary of the connection portion CP).

[0225] The conformal etch stop material layer 81L may be patterned by etching portions of the conformal etch stop material layer 81L that are not covered by the patterned photoresist layer 77. A wet or dry etching process may be performed to remove portions of the conformal etch stop material layer 81L that are not covered by the patterned photoresist layer 77. The remaining portion of the conformal etch stop material layer 81L that remains in the connection region 400 (e.g., in the connection portion CP) constitutes a dielectric etch stop structure 81. The dielectric etch stop structure 81 covers and contacts an end portion of each longitudinal sidewall of the backside trench 79 and a lateral sidewall of each backside trench in the backside trench 79. Therefore, each backside trench 79 has an end portion in the connection portion CP that is masked by the dielectric etch stop structure 81.

[0226] The dielectric etch stop structure 81 extends vertically from at least a first horizontal plane HP1 including the bottommost surface of the vertical alternating sequence of the insulating layer 32 and the sacrificial material layer 42 and extends at least to a second horizontal plane HP2 including the topmost surface of the vertical alternating sequence (32, 42). The dielectric etch stop structure 81 includes a pair of dielectric sidewalls located within a corresponding one of the backside trenches 79. The dielectric etch stop structure 81 includes a portion located within a corresponding one of the backside trenches 79. A subset of the dielectric sidewalls of the dielectric etch stop structure 81 extends laterally along a first horizontal direction hd1 and extends vertically from at least the first horizontal plane HP1 and extends at least to a second horizontal plane HP2.

[0227] refer to FIG. 11A to FIG. 11E, an etchant that selectively etches the material of the sacrificial material layer 42 relative to the material of the insulating layer 32, the outermost layer of the memory film 50, and the material of the tubular insulating spacer 84 may be introduced into the backside trench 79, for example, using an isotropic etching process. For example, the sacrificial material layer 42 may include silicon nitride, and the materials of the insulating layer 32 and the tubular insulating spacer 84 and the outermost layer of the memory film 50 may include silicon oxide. A backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed.

[0228] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which the etchant is introduced in the vapor phase into the backside trench 79. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process may be a wet etching process in which the first exemplary structure is immersed in a wet etching bath including phosphoric acid, which etches silicon nitride in a manner selective to silicon oxide, silicon, and various other materials used in the art.

[0229] Each of the backside grooves 43 may be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside grooves 43 may be greater than the height of the corresponding backside groove 43. Each of the backside grooves 43 may extend laterally substantially parallel to the top surface of the substrate 8. The backside grooves 43 may be vertically bounded by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each of the backside grooves 43 may have a uniform height throughout.

[0230] A plurality of backside recesses 43 are formed at each level of the sacrificial material layer 42. The plurality of backside recesses 43 are laterally spaced apart from each other by the backside trenches 79. Generally speaking, the length of the laterally extending portion of the dielectric etch stop structure 81 that is located within the backside trenches 79 and that laterally extends along the first horizontal direction hd1 is greater than the etching distance of the isotropic etching process that forms the backside recesses 43. Therefore, each portion of the dielectric etch stop structure 81 that is located within the corresponding backside trench 79 is in laterally contact with the remaining portion of each of the sacrificial material layers 42. Therefore, adjacent pairs of backside recesses 43 that are located at the same vertical level are laterally spaced apart by a combination of the backside trenches 79 and the vertically extending portions of the dielectric etch stop structure 81.

[0231] The unetched remaining portion of the sacrificial material layer 42 may remain in the connection region 400. The remaining portion of the sacrificial material layer 42 includes a dielectric material layer and may be referred to as a dielectric connection plate 42C hereinafter. Each dielectric connection plate 42C may laterally contact each of the vertical extensions of the dielectric etch stop structure 81. The dielectric connection plates 42C and the insulating layer 32 in the connection region electrically isolate adjacent memory blocks from each other.

[0232] Generally, the backside cavity exists within the volume of the backside trench 79 that is not filled with the dielectric etch stop structure 81. The backside recess 43 may be formed by performing an isotropic etching process that removes a portion of the sacrificial material layer 42 proximate to the backside cavity selective to the material of the insulating layer 32 and the dielectric etch stop structure 81. The remaining portion of the sacrificial material layer 42 after the isotropic etching process includes a dielectric connecting plate 42C that contacts the dielectric etch stop structure 81.

[0233] refer to FIG. 12A to FIG. 12F , an optional backside blocking dielectric layer may be optionally deposited in the backside recess 43 and the backside trench 79 and above the contact level dielectric layer 80. If employed, the backside blocking dielectric layer comprises a dielectric metal oxide (such as aluminum oxide), a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element and / or at least one lanthanide element. Alternatively or in addition, the backside blocking dielectric layer may include a silicon oxide layer. The backside blocking dielectric layer may be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The backside blocking dielectric layer is formed on the sidewalls of the backside trench 79 and the tubular insulating spacer 84, the horizontal surface and sidewalls of the insulating layer 32, and the sidewall surface of the memory opening filling structure 58 that are physically exposed to the backside recess 43. A backside cavity exists in the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer.

[0234] The metal barrier strip 46A may be deposited in the backside recess 43, in the peripheral portion of the backside trench 79, and above the contact level dielectric layer 80. The metal barrier strip 46A includes a conductive metal material that can serve as a diffusion barrier layer and / or adhesion promotion layer for a subsequently deposited metal fill material. The metal barrier strip 46A may include a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or may include a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier strip 46A may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier strip 46A may be in the range of 2 nm to 8 nm, such as 3 nm to 6 nm, but smaller and larger thicknesses may also be used. In one embodiment, the metal barrier strip 46A may be substantially composed of a conductive metal nitride such as TiN.

[0235] Metal fill material is deposited in the plurality of backside recesses 43, on the sidewalls of the at least one backside trench 79, and over the top surface of the contact level dielectric layer 80 to form metal fill material strips 46B. The metal fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal fill material strips 46B can be substantially composed of at least one elemental metal. The at least one elemental metal of the metal fill material strips 46B can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal fill material strips 46B can be substantially composed of a single elemental metal. In one embodiment, the metal fill material strips 46B can be deposited using a fluorine-containing precursor gas such as WF6. In one embodiment, the metal fill material strips 46B can be a tungsten layer including residual fluorine atoms as impurities. Metal fill material strip 46B is spaced apart from insulating layer 32 and memory opening fill structure 58 by metal barrier strip 46A, which is a metal barrier strip that blocks fluorine atoms from diffusing therethrough.

[0236] An etch-back process may be performed to remove portions of metal fill material strip 46B and metal barrier strip 46A from inside backside trench 79 and from above contact level dielectric layer 80. The etch-back process may include an isotropic etching process and / or an anisotropic etching process. Each combination of the remaining portion of metal barrier strip 46A and the remaining portion of metal fill material strip 46B remaining in the corresponding backside recess 43 constitutes conductive strip 46. The backside blocking dielectric layer may or may not remain in backside trench 79.

[0237] Each conductive strip 46 includes a portion of a metal barrier strip 46A and a portion of a metal fill material strip 46B located between vertically adjacent pairs of dielectric material layers, such as a pair of insulating layers 32. Each sacrificial material layer 42 may be replaced by a conductive strip 46. In general, alternating stacks (32, 46) of insulating strips 32 and conductive strips 46 may be formed over substrate 8.

[0238] Each adjacent combination of a dielectric connecting plate 42C and a plurality of conductive strips 46 extending laterally along a first horizontal direction hd1 constitutes a composite layer (46, 42C). The plurality of conductive strips 46 are laterally spaced apart along a second horizontal direction hd2 by backside trenches 79 extending laterally along the first horizontal direction hd1. Each of the plurality of conductive strips 46 has a corresponding sidewall adjacent to a corresponding sidewall surface segment of the dielectric connecting plate 42C. The end portions of the backside trenches 79 are laterally bounded by the dielectric connecting plate 42C of the composite layer (46, 42C). Therefore, the conductive strips (e.g., word lines and select gate electrodes) 46 in each memory block are electrically isolated from the conductive strips 46 in the laterally adjacent memory blocks by the corresponding backside trenches 79 and the dielectric connecting plate 42C.

[0239] Alternating stacks (32, 46) of respective portions of the insulating layer 32 and respective subsets of the conductive strips 46 are formed within each memory block between adjacent pairs of the backside trenches 79 when the conductive strips 46 are formed. Each of the conductive strips 46 has a respective lateral extent along the second horizontal direction hd2 that is no greater than the lateral spacing between a pair of closest pairs of the backside trenches 79. In one embodiment, the lateral extent of each of the conductive strips 46 is the same as the lateral spacing between a pair of closest pairs of the backside trenches 79 throughout each of the conductive strips 46.

[0240] Portions of the dielectric etch stop structure 81 may be located within a respective one of the backside trenches 79. Each portion of the dielectric etch stop structure 81 located within a respective backside trench 79 includes a respective pair of dielectric sidewalls located within a pair of longitudinal sidewalls of the respective backside trench 79 (and thus extending laterally along the first horizontal direction hd1). The dielectric sidewalls of these portions of the dielectric etch stop structure 81 may extend vertically from at least the first horizontal plane HP1 and to at least the second horizontal plane HP2.

[0241] Generally, the dielectric etch stop structure 81 can be formed after the backside trenches 79 are formed so that each portion of the dielectric etch stop structure 81 located within a respective backside trench 79 extends from at least a first horizontal plane HP1 including the bottommost surface of the vertical alternating sequence of insulating layer 32 and composite layer (46, 42C) and at least to a second horizontal plane HP2 including the topmost surface of the vertical alternating sequence {32, (46, 42C)}. Each portion of the dielectric etch stop structure 81 located within a respective backside trench 79 includes a respective pair of dielectric sidewalls located within a respective one of the backside trenches 79.

[0242] In one embodiment, each portion of the dielectric etch stop structure 81 located within a respective backside trench 79 includes a respective pair of dielectric sidewalls located within, directly contacting, and overlapping a pair of longitudinal sidewalls of a respective one of the backside trenches 79. Such dielectric sidewalls of the portion of the dielectric etch stop structure 81 located within the respective backside trench 79 extend laterally along a first horizontal direction hd1 and extend vertically from at least a first horizontal plane HP1 and extend at least to a second horizontal plane HP2.

[0243] like Fig.12FAs shown in , each portion of the dielectric etch stop structure 81 located within the corresponding backside trench 79 includes: a corresponding pair of inner longitudinal sidewalls ILS, the corresponding pair of inner longitudinal sidewalls are parallel to the first horizontal direction hd1 and have a first lateral spacing therebetween; a corresponding pair of outer longitudinal sidewalls OLS, the corresponding pair of outer longitudinal sidewalls are parallel to the first horizontal direction hd1 and have a second lateral spacing therebetween, the second lateral spacing being greater than the first lateral spacing; and a corresponding connecting sidewall CS, the corresponding connecting sidewall connecting the corresponding pair of outer longitudinal sidewalls OLS and contacting each of the dielectric connecting plates 42C in the alternating stack (32, 42). In one embodiment, for each portion of the dielectric etch stop structure 81 located within the corresponding backside trench 79, the pair of dielectric sidewalls of the portion of the dielectric etch stop structure 81 include a pair of outer longitudinal sidewalls OLS that coincide with the longitudinal sidewalls of the corresponding backside trench 79.

[0244] refer to FIG. 13A to FIG. 13E , an insulating material layer can be formed in the backside trench 79 and above the contact level dielectric layer 80 by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organic silicate glass, or a combination thereof. In one embodiment, the insulating material layer may include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in the range of 1.5 nm to 60 nm, but smaller and larger thicknesses can also be used.

[0245] An anisotropic etch is performed to remove horizontal portions of the insulating material layer from above the contact level dielectric layer 80 and from the bottom of each backside trench 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A backside cavity exists within the volume surrounded by each insulating spacer 74.

[0246] The back contact via structure 76 can be formed in each back side cavity. Each back side contact via structure 76 can fill the corresponding cavity. Each contact via structure 76 can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the back side cavity) of the back side groove 79. For example, the at least one conductive material may include a conductive pad and a conductive filling material portion. The conductive pad may include a conductive metal pad, such as TiN, TaN, WN, TiC, TaC, WC, their alloys or their stacks. The thickness of the conductive pad may be in the range of 3nm to 30nm, but smaller and larger thicknesses may also be used. The conductive filling material portion may include a metal or a metal alloy. For example, the conductive filling material portion may include W, Cu, Al, Co, Ru, Ni, their alloys or their stacks.

[0247] The contact level dielectric layer 80 may be used as a stop layer to planarize the at least one conductive material. If a chemical mechanical planarization (CMP) process is used, the contact level dielectric layer 80 may be used as a CMP stop layer. Each remaining continuous portion of the at least one conductive material in the backside trench 79 constitutes a backside contact via structure 76. Each continuous combination of the insulating spacer 74 and the backside contact via structure 76 constitutes a backside trench filling structure (74, 76). In general, the backside trench filling structure (74, 76) may extend vertically from at least a first horizontal plane HP1 including the bottommost surface of the alternating stack {32, (46, 42C)} and at least to a second horizontal plane HP2 including the topmost surface of the alternating stack {32, (46, 42C)}.

[0248] In one embodiment, the planarization process can simultaneously remove the horizontally extending portion of the dielectric etch stop structure 81 that covers the horizontal plane including the top surface of the contact-level dielectric layer 80. When the horizontally extending portion of the dielectric etch stop structure 81 is removed from above the horizontal plane including the top surface of the contact-level dielectric layer 80, each remaining portion of the dielectric etch stop structure 81 can be completely located within a corresponding one of the backside trenches 79. Thus, as described in reference FIG. 10A to FIG. 10E The dielectric etch stop structure 81 formed in the described processing steps is divided into a plurality of dielectric etch stop structures 81 located within a corresponding one of the backside trenches 79 .

[0249] exist Fig.13E In one embodiment shown, each of the dielectric etch stop structures 81 includes: a corresponding pair of inner longitudinal sidewalls ILS, the pair of inner longitudinal sidewalls are parallel to the first horizontal direction hd1 and have a first lateral spacing therebetween; a corresponding pair of outer longitudinal sidewalls OLS, the corresponding pair of outer longitudinal sidewalls are parallel to the first horizontal direction hd1 and have a second lateral spacing therebetween, the second lateral spacing being greater than the first lateral spacing; and a corresponding connecting sidewall CS, the corresponding connecting sidewall connecting the corresponding pair of outer longitudinal sidewalls OLS and contacting each of the dielectric connecting plates 42C in the alternating stack {32, (46, 42C)}. In one embodiment, for each of the dielectric etch stop structures 81, the pair of dielectric sidewalls includes a pair of inner longitudinal sidewalls ILS.

[0250] Fig.14A 14D are sequential vertical cross-sectional views of the contact region during the process of replacing the layer contact assembly 26 with the layer contact assembly 28 according to the first embodiment of the present disclosure.

[0251] refer to Fig.14A, a photoresist layer 97 may be applied over the contact level dielectric layer 80 and may be photolithographically patterned to form openings over the process level contact components 26. An anisotropic etching process may be performed to transfer the pattern of openings in the photoresist layer through the contact level dielectric layer 80. An array of openings 27 may be formed through the contact level dielectric layer 80. The top surface of the sacrificial via structure 85 may be physically exposed through the contact level dielectric layer 80 at the bottom of each opening 27.

[0252] refer to Fig. 14B , a selective etching process may be performed to selectively remove the sacrificial via structure 85 for the contact level dielectric layer 80, the insulating layer 32, the annular dielectric spacer 82, and the tubular insulating spacer 84. In an illustrative example, if the sacrificial contact opening filling structure 87 comprises silicon, a wet etching process of hot trimethyl-2-hydroxyethylammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH) may be employed to remove the sacrificial via structure 85. The contact opening 29 may be formed within the volume of the contact via cavity 89.

[0253] refer to Fig. 14C , at least one conductive material may be deposited in the contact opening 29. The at least one conductive material may include a metal barrier material and a metal filling material. The metal barrier material may include a metal nitride material (such as TiN, TaN or WN) and / or a metal carbide material (such as TiC, TaC or WC). The metal filling material may include W, Ti, Ta, Ru, Co, Mo, Cu, etc. The at least one conductive material may be deposited by chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, or a combination thereof. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the contact level dielectric layer 80 by performing a planarization process, which may employ a chemical mechanical polishing (CMP) process or a recess etching process. Each remaining portion of the at least one conductive material filling the corresponding contact opening 29 constitutes a contact via structure 86 that contacts the top surface of the corresponding conductive strip 46. Each contact via structure 86 may be laterally surrounded by a corresponding tubular dielectric spacer 84. Each combination of a contact via structure 86 and a corresponding tubular dielectric spacer 84 comprises a layer contact component 28, (ie, a word line or select gate electrode contact via structure.

[0254] refer to Fig.15A and Fig. 15B, additional conductive via structures (88, 386) may be formed. The additional conductive via structures (88, 386) may include, for example, a drain contact via structure 88 formed directly on the top surface of a corresponding one of the drain regions 63 through the contact level dielectric layer 80, and a connecting via structure 386 formed in the peripheral region through the stack of dielectric material plates 42' (which is the remaining portion of the sacrificial material layer 42) and through each of the insulating layers 32.

[0255] refer to Fig.16 , an upper metal interconnect structure 380 and an upper dielectric material layer 360 may be formed above the contact level dielectric layer 80. The upper metal interconnect structure 380 covers the alternating stack {32, (46, 42C)} and is embedded in the upper dielectric material layer 360. The upper metal interconnect structure 380 includes an upper metal via structure 382 and an upper metal line structure 384. In one embodiment, the upper metal via structure 382 may have a corresponding lateral extent that increases with the vertical distance upward from the topmost surface of the alternating stack {32, (46, 42C)}. The upper metal interconnect structure 380 may include a bit line that is electrically connected to a corresponding subset of the drain region 63 through a corresponding subset of the drain contact via structure 88.

[0256] The memory side pad 388 may be formed within the upper dielectric material layer 360. The memory side pad 388 may be electrically connected to the upper metal interconnection structure 380.

[0257] refer to Fig.17 If the lower metal interconnect structure 480 has not been formed between the substrate 8 and the alternating stack {32, (46, 42C)}, the substrate 8 (which may be a carrier substrate) including the substrate material layer 9 may be removed, for example, by grinding, polishing, anisotropic etching process and / or isotropic etching process. Alternatively, the substrate 8 may be removed by cleaving.

[0258] refer to Fig.18 , a lower metal interconnect structure 480 and a lower dielectric material strip 460 may be formed above the bottommost insulating layer 32B. The lower metal interconnect structure 480 is located below the alternating stack {32, (46, 42C)} (when viewed in an orientation where the upper dielectric material layer 360 covers the alternating stack {32, (46, 42C)}) and is embedded within the lower dielectric material strip 460. The lower metal interconnect structure 480 may include a lower metal via structure 482 and a lower metal line structure 484. In one embodiment, the lower metal via structure 482 may have a corresponding lateral extent that increases with the vertical distance downward from the bottommost surface of the alternating stack {32, (46, 42C)}.

[0259] In one embodiment, the connecting via structure 386 extends vertically through the dielectric connecting plate 42C within the alternating stack {32, (46, 42C)} and provides an electrical connection between a corresponding one of the upper metal interconnect structures 380 and a corresponding one of the lower metal interconnect structures 480.

[0260] refer to Fig.19 In an alternative configuration of the first embodiment, if Figure 1A If the step shown in FIG. 4 has formed a lower metal interconnect structure 480 between the substrate 8 and the alternating stack {32, (46, 42C)}, the substrate 8 may be retained.

[0261] refer to Fig. 20 , a logic die 700 may be provided. The logic die 700 includes a logic side substrate 709 (which may be a semiconductor substrate), a logic side semiconductor device 720 including a peripheral circuit for controlling the operation of a three-dimensional memory device within the memory die 900, a logic side metal interconnect structure 780 embedded in a logic side dielectric material layer 760, and a logic side pad 788 configured to cooperate with the memory die pad 388. The logic side metal interconnect structure 780 may include a logic side metal line 784 and a logic side metal through-hole structure 782. The logic side metal through-hole structure 782 may have a corresponding variable lateral range that increases with a vertical distance from a horizontal plane including an interface between the logic side substrate 709 and the logic side dielectric material layer 760.

[0262] Generally speaking, the logic-side semiconductor device 720 includes a control circuit configured to control the operation of the vertical stack of memory elements (e.g., memory cells) within each memory opening filling structure 58 in the memory die 900. The logic-side semiconductor device 720 may be electrically connected to the logic-side pad 788 through the logic-side metal interconnect structure 780. Therefore, the logic-side pad 788 is electrically connected to the logic-side semiconductor device 720 through the logic-side metal interconnect structure 780.

[0263] refer to Fig.21 , the logic die 700 may be attached to the memory die 900, for example, by bonding the memory side pads 388 to the logic side pads 788. For example, the memory side pads 388 may be bonded to the logic side pads 788 by metal-to-metal bonding (e.g., copper-to-copper bonding). In some embodiments, a hybrid bond may be employed, in which the contact surfaces of the upper dielectric material layer 960 and the logic side dielectric material layer 760 are bonded by dielectric-to-dielectric bonding (such as oxide-to-oxide bonding). The substrate 8 may be omitted or retained in the bonded assembly of the logic die 700 and the memory die 900.

[0264] refer to Fig. 22, shows an alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure after forming a conformal etch mask material layer 81L. The alternative configuration of the first exemplary structure can be 9A to 9E The first exemplary structure shown is the same.

[0265] refer to FIG. 23A to FIG. 23E , a sacrificial fill material may be deposited in the backside trench 79. Excess portions of the sacrificial fill material may be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 80. Each remaining portion of the sacrificial fill material located within a respective backside trench 79 comprises a sacrificial backside trench fill structure 171. Each sacrificial backside trench fill structure 171 is laterally surrounded by a respective vertically extending portion of the conformal etch mask material layer 81L. The sacrificial backside trench fill structure 171 may include a semiconductor material (such as amorphous silicon), a carbon-based material (such as spin-on carbon), an organosilicate glass, a polymer material, or a combination thereof.

[0266] refer to FIG. 24A to FIG. 24E , a photoresist layer 77 may be applied over the conformal etch mask material layer 81L and the sacrificial backside trench filling structures 171, and the photoresist layer may be photolithographically patterned to form an elongated opening that covers a corresponding one of the backside trenches 79 except for an end portion of the backside trench 79 that is close to the connection region 400. Thus, a major portion of each of the sacrificial backside trench filling structures 171 may be exposed within the elongated opening in the photoresist layer 77, while an end portion of the sacrificial backside trench filling structures 171 that is close to the connection region 400 (e.g., located in the connection portion CP) is covered by the patterned photoresist layer 77.

[0267] The unmasked portions of the sacrificial backside trench fill structures 171 may be removed by an anisotropic etching process using the patterned photoresist layer 77 as an etching mask. In one embodiment, the anisotropic etching process may be selective to the material of the conformal etching mask material layer 81L. The remaining portions of the sacrificial backside trench fill structures 171 are located below the patterned photoresist layer 77 within the end portions of the corresponding backside trenches 79. Thus, each remaining portion of the sacrificial backside trench fill structures 171 covers the end segments of a pair of longitudinal sidewalls of the corresponding backside trench 79 and covers the end sidewalls of the corresponding backside trench 79. FIG. 24A to FIG. 24E The patterned photoresist layer 77 may or may not be removed during and / or after the processing steps.

[0268] refer to FIG. 25A to FIG. 25E, the conformal etch stop material layer 81L may be patterned by etching portions of the conformal etch stop material layer 81L that are not covered by the sacrificial backside trench fill structure 171 (or the patterned photoresist layer 77, if present). For example, a selective etching process may be performed to remove portions of the conformal etch stop material layer 81L that are not covered by the sacrificial backside trench fill structure 171 (or the patterned photoresist layer 77, if present).

[0269] In the presence of the patterned photoresist layer 77 during the selective etching process, the remaining portion of the conformal etch stop material layer 81L that remains in the connection area 400 constitutes a dielectric etch stop structure 81, which includes a horizontally extending portion covering the contact level material layer 80 and a plurality of vertically extending portions extending vertically into the end portions of the backside trenches 79. The dielectric etch stop structure 81 covers and contacts the end portion of each longitudinal sidewall of the backside trenches 79 and the lateral sidewalls of each of the backside trenches 79. Thus, each backside trench 79 includes an end portion masked by the dielectric etch stop structure 81. The patterned photoresist layer 77 may then be removed, for example, by ashing.

[0270] Although the drawings illustrate an embodiment in which the photoresist layer 77 is removed after the isotropic etching process, embodiments in which the photoresist layer is removed before the selective etching process is performed are expressly contemplated herein. In this case, a plurality of remaining portions of the conformal etch stop material layer 81L may be formed within the end portions of the backside trenches 79. Each remaining portion of the conformal etch stop material layer 81L may remain in the end portion of a corresponding one of the backside trenches 79 proximate to the connection region 400. Thus, a plurality of dielectric etch stop structures 81 may be formed that are completely located within a corresponding one of the backside trenches 79. The plurality of dielectric etch stop structures 81 may be formed with the backside trenches 79 being disposed adjacent to the connection region 400. FIG. 13A to FIG. 13E The multiple dielectric etch stop structures 81 shown in FIG. 8 are substantially identical.

[0271] refer to FIG. 26A to FIG. 26E The sacrificial backside trench fill structures 171 may be removed selectively to at least one dielectric etch stop structure 81 and the alternating stack (32, 42). If the sacrificial backside trench fill structures 171 comprise carbon materials, they may be removed in a single ashing step along with the patterned photoresist layer 77. If the sacrificial backside trench fill structures 171 comprise non-carbon materials, the sacrificial backside trench fill structures may be removed by etching.

[0272] Then, you can execute the reference FIG. 11A to FIG. 21 The processing steps described provide Fig.21 The first exemplary structure shown in .

[0273] refer to FIG. 27A to FIG. 27E , can be self-contained by forming an array of dielectric isolation pillars 181 through the alternating stacks (32, 42) Fig. 7A The first exemplary structure shown leads to a second exemplary structure according to a second embodiment of the present disclosure. The array of dielectric isolation pillars 181 can be arranged as a one-dimensional periodic array, which is arranged along the second horizontal direction hd2 at the boundary between the contact area 200 and the connection area 400. The array of dielectric isolation pillars 181 can be formed in an area where the end portion of the backside trench will be subsequently formed near the connection area 400. The dielectric isolation pillars 181 are dielectric material portions that are subsequently used as etching stop structures during the formation of the backside grooves, and are therefore referred to herein as dielectric etching stop structures 181.

[0274] The dielectric etch stop structure 181 may be formed, for example, by applying a photoresist layer over the topmost insulating layer 32T; patterning the photoresist layer by photolithography to form an array of discrete openings arranged along the second horizontal direction hd2 close to the boundary between the contact area 200 and the connection area 400; forming discrete column cavities through the alternating stack (32, 42) by adopting an anisotropic etching process; by removing the photoresist layer; and by depositing a dielectric filling material (such as silicon oxide) in the discrete column cavities. Excess portions of the dielectric filling material may be removed from above a horizontal plane including the top surface of the topmost insulating layer 32T by performing a planarization process (such as a chemical mechanical polishing (CMP) process). Each portion of the dielectric filling material that fills the corresponding discrete column cavity constitutes a dielectric etch stop structure 181, which is a dielectric isolation column 181. Each of the dielectric etch stop structures 181 vertically extends from at least a first horizontal plane HP1 including the bottommost surface of the vertical alternating sequence of the insulating layer 32 and the sacrificial material layer 42 and extends to at least a second horizontal plane HP2 including the topmost surface of the vertical alternating sequence (32, 42). In one embodiment, each of the dielectric etch stop structures 181 may have a straight sidewall extending vertically from the first horizontal plane HP1 to the second horizontal plane HP2.

[0275] refer to Fig.28A and Fig.28B , you can execute reference FIG. 7C to FIG. 7E The processing steps are described to form a mid-level contact component 26 in the contact region 200 .

[0276] refer to Fig.29 , you can execute reference Fig. 7E Processing steps are described to form a contact level dielectric layer 80 .

[0277] refer to FIG. 30A to FIG. 30E , you can execute reference FIG. 8A to FIG. 8EThe processing steps described are to form backside trenches 79 through the alternating stack (32, 42). According to one aspect of the present disclosure, each of the backside trenches 79 can cut through the peripheral portion of a corresponding one of the dielectric etch stop structures 181. In a second embodiment, the dielectric etch stop structures 181 can be formed by a vertical alternating sequence of insulating layers 32 and sacrificial material layers 42 before forming the backside trenches 79, and each of the backside trenches 79 can cut into the peripheral portion of a corresponding one of the dielectric etch stop structures 181.

[0278] The strip portions SP (eg, memory blocks) of the vertical alternating sequence (32, 42) may be laterally spaced apart from each other by a combination of backside trenches 79 and at least one dielectric etch stop structure 181, such as Fig. 30B Note that additional contact regions 200 may be provided at opposite sides of the memory array region 100 , and each backside trench 79 may be adjoined by a pair of two dielectric etch stop structures 181 , each located at a distal end of a respective contact region 200 .

[0279] The dielectric etch stop structure 181 may be located outside of a corresponding one of the backside trenches 79 and in contact with an end portion of a corresponding one of the backside trenches 179. Each of the dielectric etch stop structures 181 includes a corresponding pair of dielectric sidewalls located within and coincident with a pair of longitudinal sidewalls of a corresponding one of the backside trenches 79. The dielectric sidewalls of the dielectric etch stop structure 181 extend laterally along a first horizontal direction hd1 and extend vertically from at least a first horizontal plane HP1 and extend at least to a second horizontal plane HP2.

[0280] exist Fig. 30B In one embodiment shown, each of the dielectric etch stop structures 181 includes: a corresponding pair of inner longitudinal sidewalls ILS, the pair of inner longitudinal sidewalls are parallel to the first horizontal direction hd1 and have a first lateral spacing therebetween; a corresponding pair of outer longitudinal sidewalls OLS, the corresponding pair of outer longitudinal sidewalls are parallel to the first horizontal direction hd1 and have a second lateral spacing therebetween, the second lateral spacing being greater than the first lateral spacing; and a corresponding connecting sidewall CS, the corresponding connecting sidewall connecting the corresponding pair of outer longitudinal sidewalls OLS. In one embodiment, for each of the dielectric etch stop structures 181, the pair of dielectric sidewalls includes a pair of inner longitudinal sidewalls ILS. In one embodiment, each of the dielectric etch stop structures 181 is located outside a corresponding one of the backside trenches 79; and each of the backside trenches 79 may always have a uniform width.

[0281] refer to FIG. 31A to FIG. 31E , you can execute reference FIG. 11A to FIG. 11E The processing steps are described to remove the portion of the sacrificial material layer 42 proximate the backside trench 79 and form the backside recess 43. The plurality of backside recesses 43 are laterally spaced apart from each other by the combination of the backside trench 79 and the dielectric etch stop structure 181. Generally speaking, the length of the dielectric etch stop structure 181 along the first horizontal direction hd1 is greater than the etching distance of the isotropic etching process for forming the backside recess 43. Therefore, each portion of the dielectric etch stop structure 181 located on the end portion of the corresponding backside trench 79 is laterally in contact with the remaining portion of each of the sacrificial material layers 42. Therefore, adjacent pairs of backside recesses 43 located at the same vertical level are laterally spaced apart by the combination of the corresponding backside trench 79 and the corresponding dielectric etch stop structure 181.

[0282] The unetched remaining portion of the sacrificial material layer 42 may remain in the connection area 400. The remaining portion of the sacrificial material layer 42 includes a dielectric material layer and may be referred to as a dielectric connection plate 42C hereinafter. Each dielectric connection plate 42C may laterally contact each of the vertically extending portions of the dielectric etch stop structure 181.

[0283] Generally, the backside cavity exists within the volume of the backside trench 79. The backside recess 43 may be formed by performing an isotropic etching process that removes a portion of the sacrificial material layer 42 proximate the backside cavity selective to the material of the insulating layer 32 and the dielectric etch stop structure 181. The remaining portion of the sacrificial material layer 42 after the isotropic etching process includes a dielectric connecting plate 42C that contacts the dielectric etch stop structure 181.

[0284] refer to FIG. 32A to FIG. 32F A backside blocking dielectric layer may optionally be deposited in the backside recess 43 and the backside trench 79 and over the contact level dielectric layer 80, as described above with respect to the first embodiment. FIG. 12A to FIG. 12F A backside cavity exists within the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer. Then, as described above, a conductive strip 46 is formed in the backside cavity.

[0285] The dielectric etch stop structures 181 may be located outside of a corresponding one of the backside trenches 79. Each dielectric etch stop structure 181 includes a corresponding pair of dielectric sidewalls located within a pair of longitudinal sidewalls of the corresponding backside trench 79 (and thus extending laterally along the first horizontal direction hd1). The dielectric sidewalls of these portions of the dielectric etch stop structures 81 may extend vertically from at least the first horizontal plane HP1 and extend to at least the second horizontal plane HP2.

[0286] Generally, the dielectric etch stop structures 181 may be formed before forming the backside trenches 79, and the backside trenches 79 may be formed such that each remaining portion of the dielectric etch stop structures 181 is located outside of the corresponding backside trenches 79. The dielectric etch stop structures 181 extend vertically from at least a first horizontal plane HP1 including the bottommost surface of the vertical alternating sequence of the insulating layer 32 and the composite layer (46, 42C) and extend at least to a second horizontal plane HP2 including the topmost surface of the vertical alternating sequence {32, (46, 42C)}. Each dielectric etch stop structure 181 includes a corresponding pair of dielectric sidewalls located within a corresponding one of the backside trenches 79.

[0287] In one embodiment, each dielectric etch stop structure 181 includes a corresponding pair of dielectric sidewalls that are located within, directly contacting, and overlapping a pair of longitudinal sidewalls of a corresponding one of the backside trenches 79. Such dielectric sidewalls of the dielectric etch stop structure 181 extend laterally along a first horizontal direction hd1 and extend vertically from at least a first horizontal plane HP1 and extend at least to a second horizontal plane HP2.

[0288] Each dielectric etch stop structure 181 located within a corresponding backside trench 79 includes: a corresponding pair of inner longitudinal sidewalls ILS, the corresponding pair of inner longitudinal sidewalls being parallel to a first horizontal direction hd1 and having a first lateral spacing therebetween; a corresponding pair of outer longitudinal sidewalls OLS, the corresponding pair of outer longitudinal sidewalls being parallel to the first horizontal direction hd1 and having a second lateral spacing therebetween, the second lateral spacing being greater than the first lateral spacing; and a corresponding connecting sidewall CS, the corresponding connecting sidewall connecting the corresponding pair of outer longitudinal sidewalls OLS and contacting each of the dielectric connecting plates 42C in the alternating stack (32, 42). In one embodiment, for each dielectric etch stop structure 181 located directly on a corresponding backside trench 79, a pair of dielectric sidewalls of the dielectric etch stop structure 181 includes a pair of inner longitudinal sidewalls ILS that coincide with the longitudinal sidewalls of the corresponding backside trench 79.

[0289] refer to FIG. 33A to FIG. 33F , you can execute reference FIG. 13A to FIG. 13EThe processing steps are described to form backside trench fill structures (74, 76) in the backside trenches 79. Each of the backside trench fill structures (74, 76) may extend vertically from at least a first horizontal plane HP1 including a bottommost surface of the alternating stack {32, (46, 42C)} and at least to a second horizontal plane HP2 including a topmost surface of the alternating stack {32, (46, 42C)}. The dielectric etch stop structure 181 may be located outside a corresponding one of the backside trenches 79. Each of the dielectric etch stop structures 181 includes a corresponding pair of dielectric sidewalls located within a pair of longitudinal sidewalls of a corresponding one of the backside trenches 79.

[0290] refer to Fig.34 , you can execute reference FIG. 14A to FIG. 21 The processing steps are described to provide a second exemplary structure.

[0291] Reference is made to Figures 1 to Fig.34 And according to various embodiments of the present disclosure, there is provided a three-dimensional memory device, the three-dimensional memory device comprising: an alternating stack {32, (46, 42C)} of insulating layers 32 and composite layers (46, 42C), the insulating layers and the composite layers alternating in a vertical direction, wherein each of the composite layers (46, 42C) comprises a combination of a dielectric connecting plate 42C and a plurality of conductive strips 46, the dielectric connecting plate and the plurality of conductive strips extending laterally in a first horizontal direction hd1, being laterally spaced apart in a second horizontal direction hd2 by backside grooves 79 extending laterally in the first horizontal direction hd1, and having respective sidewalls adjacent to respective sidewall surface segments of the dielectric connecting plate 42C, wherein end portions of the backside grooves 79 are laterally bounded by the dielectric connecting plate 42C of the composite layers (46, 42C);

[0292] An array of memory openings 49 extending vertically through the alternating stack; memory opening filling structures 58 located in the memory openings, wherein each of the memory opening filling structures 58 includes a vertical semiconductor channel 60 and a corresponding vertical stack of memory elements (e.g., portions of the memory film 50) located at the level of the conductive strips 46; and backside trench filling structures (74, 76) located in the backside trenches 79 and extending vertically from at least a first horizontal plane HP1 including the bottommost surface of the alternating stack {32, (46, 42C)} and extending at least to a first horizontal plane HP2 including the bottommost surface of the alternating stack {32, (46, 42C)}. a second horizontal plane HP2 of the topmost surface of the stack {32, (46, 42C)}; and a dielectric etch stop structure (81, 181), which is located inside or outside a corresponding one of the back side grooves 79, wherein each of the dielectric etch stop structures (81, 181) includes a corresponding pair of dielectric side walls located within a pair of longitudinal side walls of the corresponding one of the back side grooves 79, wherein the dielectric side walls of the dielectric etch stop structure (81, 181) extend laterally along the first horizontal direction hd1 and extend vertically from at least the first horizontal plane HP1 and extend at least to the second horizontal plane HP2.

[0293] In one embodiment, each of the conductive strips 46 has a respective lateral extent along the second horizontal direction hd2 that is no greater than a lateral spacing between a closest pair of backside trenches 79 .

[0294] In one embodiment, the lateral extent of each of the conductive strips 46 is the same as the lateral spacing between the closest pairs of backside trenches 79 throughout each of the conductive strips 46 (eg, as shown in the first exemplary structure).

[0295] In one embodiment, the lateral extent of each of the conductive strips 46 is the same as the lateral spacing between a pair of closest pairs of back side grooves 79 within a first portion of each of the conductive strips 46, which first portion is away from the dielectric connection plate 42C contacted by the corresponding conductive strip 46; and the lateral extent of each of the conductive strips 46 is less than the lateral spacing between a pair of closest pairs of back side grooves 79 among the back side grooves 79 within a second portion of each of the conductive strips 46, which second portion is close to the dielectric connection plate 42C contacted by the corresponding conductive strip 46 (for example, as shown in the second exemplary structure).

[0296] In one embodiment, each of the dielectric etch stop structures (81, 181) includes: a corresponding pair of inner longitudinal side walls ILS, which are parallel to the first horizontal direction hd1 and have a first lateral spacing therebetween; a corresponding pair of outer longitudinal side walls OLS, which are parallel to the first horizontal direction hd1 and have a second lateral spacing therebetween, and the second lateral spacing is greater than the first lateral spacing; and a corresponding connecting side wall CS, which connects the corresponding pair of outer longitudinal side walls OLS and contacts each dielectric connecting plate in the alternating stack {32, (46, 42C)}.

[0297] In one embodiment, for each of the dielectric etch stop structures 81, the pair of dielectric sidewalls includes a pair of outer longitudinal sidewalls OLS (eg, as shown in the first exemplary structure).

[0298] In one embodiment, for each of dielectric etch stop structures 181, the pair of dielectric sidewalls includes a pair of inner longitudinal sidewalls ILS (eg, as shown in the second exemplary structure).

[0299] In one embodiment, each of the dielectric etch stop structures 81 is located within a corresponding one of the back side trenches 79; and each of the back side trench filling structures (74, 76) has a first portion and a second portion, the first portion having the same width as the corresponding one of the back side trenches 79, and the second portion having a smaller width than the corresponding one of the back side trenches 79.

[0300] In one embodiment, each of the dielectric etch stop structures 181 is located outside a corresponding one of the backside trenches 79 ; and each of the backside trench filling structures ( 74 , 76 ) always has a uniform width that is the same as the width of the corresponding backside trench 79 .

[0301] In one embodiment, the three-dimensional memory device includes: an upper metal interconnect structure 380 covering the alternating stack {32, (46, 42C)} and embedded in the upper dielectric material layer 360; a memory side pad 388 electrically connected to the upper metal interconnect structure 380 and embedded in the upper dielectric material layer 360; and a logic die 700 including a logic side semiconductor device 720 and a logic side pad 788 electrically connected to the logic side semiconductor device 720 through the logic side metal interconnect structure 780, wherein the logic side pad 788 is bonded to the memory side pad 388. In one embodiment, the logic side semiconductor device 720 includes a control circuit configured to control the operation of the vertical stack of memory elements.

[0302] In one embodiment, the three-dimensional memory device further includes a connecting via structure 386 that extends vertically through the dielectric connecting plates 42C within the alternating stack {32, (46, 42C)} and provides electrical connection to the upper metal interconnect structure 380.

[0303] In one embodiment, the three-dimensional memory device further includes a lateral insulated contact via structure (84, 86) extending vertically through a corresponding subset of the alternating stacks located between corresponding adjacent pairs of backside trenches 79 and contacting a corresponding one of the conductive strips 46S. The lateral insulated contact via structure (84, 86) is located in a contact region 200 that has no steps (e.g., vertical step surfaces) in the alternating stacks. In one embodiment, the alternating stacks are located in different memory blocks that are electrically isolated from each other by backside trenches and dielectric etch stop structures.

[0304] refer to FIG. 35A to FIG. 35E , can be obtained by forming additional trenches in addition to the backside trenches 79. FIG. 30A to FIG. 30E The second exemplary structure shown in the figure leads to an alternative configuration of the second exemplary structure. The alternative trench is referred to herein as isolation trench 179. The isolation trench 179 can be formed simultaneously with the formation of the backside trench 79 by modifying the pattern of the opening in the photoresist layer used as an etching mask during the anisotropic etching process used to form the backside trench 79. The isolation trench 179 extends laterally along the second horizontal direction hd2 and cuts through each of the dielectric etch stop structures 181. In one embodiment, in FIG. 27A to FIG. 27EEach of the dielectric etch stop structures 181 formed in the process step of may be divided into two rows of dielectric etch stop structures 181. Each row of dielectric etch stop structures 181 may be arranged along the second horizontal direction hd2, and the two rows of dielectric etch stop structures 181 may be laterally spaced apart from each other along the first horizontal direction hd1 by the isolation trench 179. In one embodiment, the isolation trench 179 may have a pair of straight longitudinal sidewalls extending laterally along the second horizontal direction hd2 and laterally spaced apart from each other along the first horizontal direction hd1.

[0305] The isolation trench 179 does not contact or overlap with the backside trench 79. This reduces or prevents the trench (79, 179) from penetrating into the substrate 8. The lack of perforation reduces or prevents short circuits between the contact via structure 76 to be formed in the trench and the metal interconnect structure 480 located below the alternating stack. In contrast, if the isolation trench 179 does contact or overlap with the backside trench 79, the etching rate at the overlap area (i.e., at the corner where the trenches 79 and 179 meet) is higher than the etching rate in the straight (i.e., non-overlapping) portion of the trench (79, 179). The higher etching rate at the overlap area can result in penetration into the substrate 8, which can result in a short circuit between the contact via structure 76 and the lower metal interconnect structure 480.

[0306] The patterned portions of insulating layer 32 located in connection region 400 are referred to herein as insulating plates 32P. The patterned portions of sacrificial material layer 42 located in connection region 400 are referred to herein as dielectric material plates 42P. A vertical alternating sequence of insulating plates 32P and dielectric material plates 42P may be formed in connection region 400.

[0307] refer to FIG. 36A to FIG. 36F , you can execute reference FIG. 31A to FIG. 31E The processing steps are described to form the backside recess 43 around the backside trench 79 and around the isolation trench 179. All portions of the sacrificial material layer 42 located in the memory array region 100 or in the contact region 200 and closer to the memory array region 100 than the isolation trench 179 may be removed during the isotropic etching process for forming the backside recess 43. In addition, additional backside recesses 43 may be formed after removing portions of the sacrificial material layer 42 located near the isolation trench 179 and in the connection region 400. The sidewalls of the dielectric material plate 42P physically exposed to the isolation trench 179 may be laterally recessed further away from the memory array region 100 along the first horizontal direction hd1 than the sidewalls of the insulating plate 32P physically exposed to the isolation trench 179.

[0308] Subsequently, you can execute the reference FIG. 32A to FIG. 32FThe processing steps described are to form a backside blocking dielectric layer and to form conductive strips 46. A subset of conductive strips 46 may be formed in backside recesses laterally bounded by backside trenches 79 and isolation trenches 79. In addition, additional conductive strips may be formed in additional backside recesses formed by lateral recessing of dielectric material plate 42P.

[0309] Subsequently, you can execute the reference FIG. 13A to FIG. 13E The processing steps are described to form backside trench fill structures (74, 76) in backside trench 79 and isolation trench fill structures (174, 176) in isolation trench 179. Each of the backside trench fill structures (74, 76) may vertically extend from at least a first horizontal plane HP1 including a bottommost surface of the alternating stack {32, (46, 42C)} and at least to a second horizontal plane HP2 including a topmost surface of the alternating stack {32, (46, 42C)}.

[0310] The isolation trench filling structure (174, 176) may include an isolation trench spacer 174 formed simultaneously with the formation of the insulating spacer 74 and having the same material composition and the same thickness as the insulating spacer 74. In one embodiment, the isolation trench spacer 174 may include longitudinal sidewalls extending laterally along the second horizontal direction hd2 and laterally spaced apart from each other along the first horizontal direction hd1. In general, for any element having a lateral extent along at least two different horizontal directions, the longitudinal direction and the lateral direction may be defined such that the longitudinal direction has a greater lateral extent than the lateral direction.

[0311] The isolation trench filling structures (174, 176) may also include a conductive isolation trench filling structure 176 having the same material composition as the backside contact via structure 76. The isolation trench spacer 174 includes a dielectric material and provides electrical isolation between the conductive isolation trench filling structure 176 and elements located around the isolation trench spacer 174 and between elements located around the isolation trench spacer 174. Therefore, the isolation trench spacer 174 is also referred to as a dielectric isolation structure 174.

[0312] The dielectric etch stop structures 181 may be located outside of a corresponding one of the backside trenches 79. A first subset of the dielectric etch stop structures 181 includes a corresponding pair of dielectric sidewalls located within a pair of longitudinal sidewalls of a corresponding one of the backside trenches 79. A second subset of the dielectric etch stop structures 181 contacts the vertical alternating sequence of insulating plates 32P and dielectric material plates 42P.

[0313] Each of the conductive strips 46 may have a sidewall that is in direct contact with the dielectric isolation structure 174. The dielectric isolation structure 174 includes a longitudinal sidewall that extends laterally along the second horizontal direction hd2. Each insulating plate 32P in the vertically alternating sequence of insulating plates 32P and dielectric material plates 42P may be in contact with the dielectric isolation structure 174. Each dielectric material plate 42P in the vertically alternating sequence of insulating plates 32P and dielectric material plates 42P may be laterally spaced apart from the dielectric isolation structure 174 by a corresponding conductive strip 46 that has a greater lateral extent along the second horizontal direction hd2 than along the first horizontal direction hd1.

[0314] refer to Fig.37A , you can execute reference FIG. 14A to FIG. 21 The processing steps are described to provide an alternative configuration of the second exemplary structure.

[0315] refer to Fig.37B By filling the backside trench 79 with only the insulating spacer 74 and by filling the isolation trench 179 with only the isolation trench spacer 174, it is possible to Fig.37A The configuration of the second exemplary structure shown in derives an additional alternative configuration of the second exemplary structure. In this case, the isolation trench 179 can be completely filled with an insulating material (i.e., a dielectric material) that is an isolation trench spacer 174 of the dielectric isolation structure 174. Each of the conductive strips 46 can have a sidewall that is in direct contact with the dielectric isolation structure 174. The dielectric isolation structure 174 includes a longitudinal sidewall that extends laterally along the second horizontal direction hd2. Each insulating plate 32P in the vertical alternating sequence of insulating plates 32P and dielectric material plates 42P can be in contact with the dielectric isolation structure 174. Each dielectric material plate 42P in the vertical alternating sequence of insulating plates 32P and dielectric material plates 42P can be laterally spaced apart from the dielectric isolation structure 174 by a corresponding conductive strip 46, which has a larger lateral extent along the second horizontal direction hd2 than along the first horizontal direction hd1.

[0316] refer to Fig.38A and Fig.38B , available in Fig. 7E A third exemplary structure according to a third embodiment of the present disclosure is derived from the first exemplary structure after the processing steps of Fig.38A Some support pillar structures 20 are shown in FIG. It should be noted that additional support pillar structures 20 may be located below the process layer contact components 26, such as Fig. 7E as shown in .

[0317] refer to Fig.39A and Fig.39B , you can then perform a reference FIG. 35A to FIG. 35EThe processing steps described are used to form backside trenches 79 and isolation trenches 179. The patterns of backside trenches 79 and isolation trenches 179 can be similar to those of reference 1. FIG. 35A to FIG. 35E The back side trenches 79 are substantially the same as described above. Specifically, each back side trench 79 may extend laterally along the first horizontal direction hd1 between adjacent arrays of memory opening filling structures 58 and between adjacent arrays of in-process layer contact components 26, and may have respective end portions close to the boundary between the contact area 200 and the connection area 400. The isolation trench 179 is laterally spaced apart from the back side trenches 79 along the first horizontal direction hd1 and extends laterally along the second horizontal direction hd2. In one embodiment, the isolation trench 179 is located in an area without support post structures 20. At least one row of support post structures 20 may be present on either side of the isolation trench 179.

[0318] refer to Fig.40A and Fig.40B , sacrificial fill material may be deposited in the backside trenches 79 and the isolation trenches 179. Excess portions of the sacrificial fill material may be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 80. Each remaining portion of the sacrificial fill material within a corresponding backside trench 79 comprises a sacrificial backside trench fill structure 171. The sacrificial backside trench fill structure 171 may include a semiconductor material (such as amorphous silicon), a carbon-based material (such as spin-on carbon), an organosilicate glass, a polymer material, or a combination thereof.

[0319] A photoresist layer (not shown) may be applied over the contact level dielectric layer 80 and the sacrificial backside trench filling structure 171, and may be photolithographically patterned to form an elongated opening covering the entire area of ​​the isolation trench 179. The portion of the sacrificial filling material remaining in the isolation trench 179 may be removed by performing an etching process or an ashing process. The sacrificial filling material may be removed from the interior of the isolation trench 179. The photoresist layer may then be removed, for example, by ashing. Thus, the backside trench 79 is filled with the sacrificial backside trench filling structure 171, and the isolation trench 179 is not filled with any filling material.

[0320] refer to Fig.41A and Fig.41B An isotropic etching process may be performed to selectively etch the material of the sacrificial material layer 42 with respect to the material of the insulating layer 32, the sacrificial backside trench fill structure 171, and the support pillar structure 20. An isolation recess 143 is formed in the volume from which the material of the sacrificial material layer 42 is etched. An isolation cavity 177 may be formed, which includes Fig.39A and Fig.39B The volume of the isolation trench 179 formed in the process step of FIG. 1 and the volume of the isolation recess 143 formed by the isotropic etching process. Generally speaking, the isolation cavity 177 can be formed by lateral expansion of the isolation trench 179.

[0321] In one embodiment, the duration of the isotropic etching process can be selected so that the lateral recess distance of the sidewalls of the sacrificial material layer 42 is greater than the lateral spacing between the isolation trench 179 and the backside trench 79. In this case, when the isotropic etching process competes, the surface segment of the sacrificial backside trench filling structure 171 can be physically exposed to the isolation cavity 177 at each level of the sacrificial material layer 42. Each patterned portion of the sacrificial material layer 42 located between a corresponding adjacent pair of sacrificial backside trench filling structures 171 constitutes a sacrificial material strip 42S. The sacrificial material strips 42S are laterally spaced apart from each other by the sacrificial backside trench filling structures 171. Each portion of the insulating layer 32 located between the adjacent pairs of sacrificial backside trench filling structures 171 constitutes an insulating strip 32S. The insulating strips 32S located at the same level are laterally interconnected to each other by a portion of the corresponding insulating layer 32 adjacent to and / or exposed to the isolation cavity 177. The topmost insulating strip 32ST includes a portion of the topmost insulating layer 32T, and the bottommost insulating strip 32SB includes a portion of the bottommost insulating layer 32B.

[0322] An alternating stack (32S, 42S) of insulating strips 32S and sacrificial material strips 42S is formed between adjacent pairs of sacrificial backside trench filling structures 171. Insulating strips 32S are portions of insulating layer 32 located between respective adjacent pairs of backside trenches 79. Sacrificial material strips 42S are discrete remaining portions of sacrificial material layer 42. Each of the sacrificial material strips 42S is laterally spaced apart from all other sacrificial material strips 42S located at the same level by a combination of backside trenches 79 and isolation cavities 177. Isolation cavities 177 may be fin-shaped cavities including isolation grooves 143 that are fin-shaped voids of the fin-shaped cavities. Surface segments of support post structures 20 may be exposed to isolation grooves 143 of isolation cavities 177. A vertical alternating sequence of insulating plates 32P and dielectric material plates 42P may also be provided in connection area 400 and / or in contact area 200 adjacent to connection area 400. The vertical alternating sequence of insulating plates 32P and dielectric material plates 42P is laterally spaced apart from the alternating stack (32S, 42S) along a first horizontal direction hd1.

[0323] refer to Fig.42A and Fig.42B , a dielectric filling material, such as silicon oxide, may be deposited in the isolation cavity 177 by a conformal deposition process, such as a chemical vapor deposition process. Excess portions of the dielectric filling material may be removed by performing a recess etching process from above a horizontal plane including the top surface of the contact-level dielectric layer 80. The remaining portion of the dielectric filling material filling the isolation cavity 177 includes a dielectric isolation structure 276, which is a fin-shaped dielectric isolation structure 276 including a dielectric fin portion 276F located at the level of the sacrificial material strip 42S.

[0324] Generally speaking, the dielectric isolation structure 276 can be formed by depositing a dielectric material in the isolation cavity 177. The dielectric isolation structure 276 includes a dielectric wall portion 276W extending laterally along the second horizontal direction hd2 and laterally spaced apart from the backside trench 79, and a dielectric fin portion 276F protruding laterally from the dielectric wall portion 276W along the first horizontal direction hd1. The dielectric wall portion 276W is a portion of the dielectric isolation structure 276 that does not have any area overlap with the insulating strip 32S or with the insulating plate 32P in a plan view (such as a top view), and the dielectric fin portion 276F has an area overlap with the insulating strip 32S or with the insulating plate 32P in a plan view.

[0325] Each interface between the alternating stack (32S, 42S) and the dielectric isolation structure 276 extends vertically from a first horizontal plane HP1 including the bottommost surface of the alternating stack (32S, 42S) to a second horizontal plane HP2 including the topmost surface of the alternating stack (32S, 42S). Each interface between the alternating stack (32S, 42S) and the dielectric isolation structure 276 may have an undulating vertical cross-sectional profile along a direction perpendicular to the second horizontal direction hd2.

[0326] In one embodiment, the dielectric isolation structure 276 includes a dielectric wall portion 276W extending laterally along the second horizontal direction hd2 and laterally spaced apart from the backside trench 79, and a dielectric fin portion 276F protruding laterally from the dielectric wall portion 276W along the first horizontal direction hd1. In one embodiment, the dielectric fin portion 276F is located at the level of the sacrificial material strip 42S. In one embodiment, each of the dielectric fin portions 276F has a corresponding lateral dimension along the first horizontal direction hd1 that is greater than the lateral dimension of the dielectric wall portion 276W along the first horizontal direction hd1.

[0327] In one embodiment, the lateral distance between the dielectric wall portion 276W and one of the backside trenches 79 along the first horizontal direction hd1 is less than the lateral distance between the dielectric wall portion 276W and one of the sacrificial material strips 42S along the first horizontal direction hd1. In one embodiment, all interfaces between the insulating strips 32S and the dielectric isolation structure 276 are located within the sidewall surface segments of the dielectric wall portion 276W. In one embodiment, the support post structure 20 may extend vertically through a corresponding subset of the dielectric fin portions 276F and may extend vertically from a first horizontal plane HP1 including the bottommost surface of the alternating stack (32S, 42S) to a second horizontal plane HP2 including the topmost surface of the alternating stack (32S, 42S).

[0328] refer to Fig.43A and Fig.43B, the sacrificial backside trench filling structure 171 may be removed from the inside of the backside trench 79. For example, a selective etching process or an ashing process may be performed to selectively remove the sacrificial backside trench filling structure 171 from the materials of the insulating strips 32S, the sacrificial material strips 42S, and the dielectric isolation structures 276.

[0329] refer to Fig.44A and Fig.44B , you can execute reference FIG. 11A to FIG. 11E The processing steps described are to remove the sacrificial material strips 42S selective to the material of the insulating strips 32S and the dielectric isolation structures 276. The sidewalls of the dielectric isolation structures 276 may be physically exposed at each level of the backside recesses 43.

[0330] refer to FIG. 45A to FIG. 45C , you can execute reference FIG. 12A to FIG. 12F The processing steps are described to form an optional backside blocking dielectric layer and conductive strips 46 in backside recesses 43. Thus, sacrificial material strips 42S are replaced by conductive strips 46 to form alternating stacks (32S, 46) of corresponding subsets of insulating strips 32S and corresponding subsets of conductive strips 46.

[0331] The insulating strips 32S and the conductive strips 46 within each alternating stack (32S, 46) alternate in a vertical direction. Each of the alternating stacks (32S, 46) extends laterally along a first horizontal direction hd1, and the alternating stacks (32S, 46) in adjacent memory blocks are laterally spaced apart from each other by backside trenches 79 along a second horizontal direction hd2. An array of memory openings 49 extends vertically through the respective alternating stacks (32S, 46). A memory opening filling structure 58 may be located in the memory openings 49. Each of the memory opening filling structures 58 includes a respective vertical memory element stack located at the level of the conductive layer 46 and the vertical semiconductor channel 60.

[0332] A vertical alternating sequence of insulating plates 32P and dielectric material plates 42P may be provided, the vertical alternating sequence being laterally spaced apart from the alternating stack (32S, 46) along a first horizontal direction hd1. Each of the insulating plates 32P is located at the same level, has the same thickness, and has the same material composition as a corresponding subset of the insulating strips 32S within the alternating stack (32S, 46). The dielectric isolation structure 276 laterally contacts each of the insulating strips 32S within the alternating stack (32S, 46) and each insulating plate 32P and each dielectric material plate 42P within the vertical alternating sequence and extends laterally along a second horizontal direction hd2.

[0333] In one embodiment, each of the backside trenches 79 is filled with a respective backside trench filling structure (74, 76) having a respective pair of longitudinal sidewalls extending laterally along the first horizontal direction hd1. In one embodiment, each of the longitudinal sidewalls of the backside trench filling structures (74, 76) includes a respective surface segment in direct contact with the dielectric isolation structure 276.

[0334] refer to Fig.46A and Fig.46B , additional conductive via structures (88, 386) may be formed. The additional conductive via structures (88, 386) may include, for example, a drain contact via structure 88 formed directly on the top surface of a corresponding one of the drain regions 63 through the contact-level dielectric layer 80 and a connecting via structure 386 formed through the vertical alternating sequence of insulating plates 32P and dielectric material plates 42P.

[0335] refer to Fig.47 , you can execute reference FIG. 11A to FIG. 21 The processing steps described provide Fig.47 The third exemplary structure shown in .

[0336] refer to Fig.48A and Fig.48B , can be obtained by forming a patterned photoresist layer 377 above the contact level dielectric layer 80 Fig.40A and Fig.40B The third exemplary structure shown in derives a fourth exemplary structure according to a fourth embodiment of the present disclosure. The opening in the photoresist layer 377 may have an area including the entire area of ​​the isolation trench 179. The edge of the photoresist layer around the opening in the photoresist layer may be laterally offset outward from the top periphery of the isolation trench 179 by a lateral offset distance that is greater than the lateral offset distance between the isolation trench 179 and the backside trench 79. In one embodiment, the straight edge of the photoresist layer 377 (which extends along the second horizontal direction hd2) may span the end portion of each backside trench in the backside trench 79.

[0337] refer to Fig.49A and Fig.49BAt least one isotropic etching process may be performed to selectively recess the material of the insulating layer 32 for the sacrificial backside trench fill structure 171 located in the backside trench 79 and to recess the material of the sacrificial material layer 42 below the opening in the photoresist layer 377. The materials of the insulating layer 32 and the sacrificial material layer 42 may be recessed simultaneously using a single isotropic etching process, or may be recessed sequentially using a first isotropic etching process that selectively recesses the material of the sacrificial material layer 42 for the material of the insulating layer 32 and a second isotropic etching process that selectively recesses the material of the sacrificial material layer 42 for the material of the sacrificial material layer 42. For example, if the insulating layer 32 includes silicon oxide and the sacrificial material layer 42 includes silicon nitride, the first isotropic etching process may include a wet etching process using hot phosphoric acid, and the second isotropic etching process may include a wet etching process using dilute hydrofluoric acid. The second isotropic etching process may be performed after or before the first isotropic etching process. The duration of the first isotropic etching process and the duration of the second isotropic etching process may be selected so that the sidewalls of the sacrificial material layer 42 are laterally recessed by a greater than, less than, or the same distance as the sidewalls of the insulating material layer 32. An isolation cavity 177 is formed in the volume of the isolation trench 179 and the volume of the void formed by the first isotropic etching process and the second isotropic etching process.

[0338] In one embodiment, the lateral recess distance of the sidewalls of the sacrificial material layer 42 is greater than the lateral spacing between the isolation trench 179 and the backside trench 79. In this case, when the isotropic etching process competes, the surface segments of the sacrificial backside trench filling structure 171 can be physically exposed to the isolation cavity 177 at each level of the sacrificial material layer 42. Each patterned portion of the sacrificial material layer 42 located between a corresponding adjacent pair of sacrificial backside trench filling structures 171 constitutes a sacrificial material strip 42S. The sacrificial material strips 42S are laterally spaced apart from each other by the sacrificial backside trench filling structures 171.

[0339] In one embodiment, the lateral recess distance of the sidewalls of the insulating layer 32 is greater than the lateral spacing between the isolation trench 179 and the backside trench 79. In this case, when the isotropic etching process competes, the surface segments of the sacrificial backside trench filling structure 171 can be physically exposed to the isolation cavity 177 at each level of the insulating layer 32. Each patterned portion of the insulating layer 32 located between a corresponding adjacent pair of sacrificial backside trench filling structures 171 constitutes an insulating strip 32S. The insulating strips 32S are laterally spaced apart from each other by the sacrificial backside trench filling structures 171. The topmost insulating strip 32ST includes a portion of the topmost insulating layer 32T, and the bottommost insulating strip 32SB includes a portion of the bottommost insulating layer 32B.

[0340] An alternating stack (32S, 42S) of insulating strips 32S and sacrificial material strips 42S is formed in each memory block between adjacent pairs of sacrificial backside trench fill structures 171. Insulating strips 32S are portions of insulating layer 32 located between respective adjacent pairs of backside trenches 79. Sacrificial material strips 42S are discrete remaining portions of sacrificial material layer 42. Each of the sacrificial material strips 42S is laterally spaced apart from all other sacrificial material strips 42S located at the same level by a combination of backside trenches 79 and isolation cavities 177. Insulating strips 32S are discrete remaining portions of insulating layer 32. Each of the insulating strips 32S is laterally spaced apart from all other insulating strips 32S located at the same level by a combination of backside trenches 79 and isolation cavities 177. The isolation cavity 177 may have straight sidewalls extending vertically from the first horizontal plane HP1 to the second horizontal plane HP2 or may be a fin-shaped cavity including a fin-shaped void at the level of the sacrificial material strips 42S or at the level of the insulating strips 32S. The photoresist layer 377 may then be removed, for example by ashing.

[0341] refer to Fig.50A and Fig.50B , a dielectric filling material, such as silicon oxide, may be deposited in the isolation cavity 177 by a conformal deposition process, such as a chemical vapor deposition process. Excess portions of the dielectric filling material may be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 80 by performing a recess etching process. The remaining portion of the dielectric filling material filling the isolation cavity 177 includes a dielectric isolation structure 376, which may or may not be a fin-shaped dielectric isolation structure 376 including dielectric fins at the level of the sacrificial material strips 42S or at the level of the insulating strips 32S.

[0342] Generally speaking, the dielectric isolation structure 376 can be formed by depositing a dielectric material in the isolation cavity 177. The dielectric isolation structure 376 includes a dielectric wall portion 376W extending laterally along the second horizontal direction hd2 and laterally spaced apart from the backside trench 79, and a dielectric fin portion 376F protruding laterally from the dielectric wall portion 376W along the first horizontal direction hd1. The dielectric wall portion 376W is a portion of the dielectric isolation structure 376 that does not overlap with any area of ​​the insulating strip 32S or with the insulating plate 32P in a plan view (such as a top view), and the dielectric fin portion 376F does not overlap with any area of ​​the insulating strip 32S or with the insulating plate 32P in a plan view (such as a top view).

[0343] Each interface between the alternating stack (32S, 42S) and the dielectric isolation structure 376 extends vertically from a first horizontal plane HP1 including the bottommost surface of the alternating stack (32S, 42S) to a second horizontal plane HP2 including the topmost surface of the alternating stack (32S, 42S). Each interface between the alternating stack (32S, 42S) and the dielectric isolation structure 376 may have an undulating vertical cross-sectional profile along a direction perpendicular to the second horizontal direction hd2.

[0344] In one embodiment, the dielectric isolation structure 376 includes a dielectric wall portion 376W extending laterally along the second horizontal direction hd2 and laterally spaced apart from the backside trench 79, and may or may not include a dielectric fin portion 376F that protrudes laterally from the dielectric wall portion 376W along the first horizontal direction hd1. In one embodiment, the dielectric fin portion 376F may be located at the level of the sacrificial material strip 42S. Alternatively, the dielectric fin portion 376F may be located at the level of the insulating strip 32S. In one embodiment, each of the dielectric fin portions 376F has a corresponding lateral dimension along the first horizontal direction hd1 that is smaller than the lateral dimension of the dielectric wall portion 376W along the first horizontal direction hd1.

[0345] In one embodiment, the lateral distance along the first horizontal direction hd1 between the dielectric wall portion 376W and one of the backside trenches 79 is less than the lateral distance along the first horizontal direction hd1 between the dielectric wall portion 376W and the sacrificial material strip 42S and / or the lateral distance along the first horizontal direction hd1 between the dielectric wall portion 376W and the insulating strip 32S. In one embodiment, the support post structure 20 can be removed within the volume where the dielectric isolation structure 376 is located.

[0346] refer to Fig.51A and Fig.51B , the sacrificial backside trench filling structure 171 may be removed from the inside of the backside trench 79. For example, a selective etching process or an ashing process may be performed to selectively remove the sacrificial backside trench filling structure 171 from the materials of the insulating strips 32S, the sacrificial material strips 42S, and the dielectric isolation structures 376.

[0347] refer to FIG. 52A to FIG. 52C , each of the backside trenches 79 is filled with a corresponding backside trench filling structure (74, 76) having a corresponding pair of longitudinal sidewalls extending laterally along the first horizontal direction hd1. In one embodiment, each of the longitudinal sidewalls of the backside trench filling structures (74, 76) includes a corresponding surface segment that is in direct contact with the dielectric isolation structure 376.

[0348] refer to Fig.53A and Fig.53B, additional conductive via structures (88, 386) may be formed. The additional conductive via structures (88, 386) may include, for example, a drain contact via structure 88 formed directly on the top surface of a corresponding one of the drain regions 63 through the contact-level dielectric layer 80 and a connecting via structure 386 formed through the vertical alternating sequence of insulating plates 32P and dielectric material plates 42P.

[0349] refer to Fig.54 , you can execute reference FIG. 11A to FIG. 21 The processing steps described provide Fig.54 . The dielectric fin portion 376F may be located at the level of the conductive strip 46 and the dielectric material plate 42P, and may contact each of the conductive strip 46 and the dielectric material plate 42P. Alternatively, the dielectric fin portion 376F may also be located at the level of the insulating strip 32S and the insulating plate 32P, and may contact one of the insulating strip 32S and the insulating plate 32P.

[0350] Common Reference Figures 35A to 54 and related drawings, and according to various embodiments of the present disclosure, there is provided a three-dimensional memory device, the three-dimensional memory device comprising: alternating stacks (32S, 46) of insulating strips 32S and conductive strips 46, the insulating strips and the conductive strips alternating in a vertical direction, wherein each of the alternating stacks (32S, 46) extends laterally along a first horizontal direction hd1, and the alternating stacks (32S, 46) are laterally spaced apart from each other by backside grooves 79 along a second horizontal direction hd2; an array of memory openings 49, the array extending vertically through the alternating stacks (32S, 46); a memory opening filling structure 58, the memory opening filling structure being located in the memory opening 49, wherein each of the memory opening filling structures 58 comprises a vertical A vertical stack of semiconductor channels 60 and corresponding memory elements located at the level of conductive strips 46; and a vertical alternating sequence of insulating plates 32P and dielectric material plates 42P, which is laterally spaced apart from the alternating stack (32S, 46) along a first horizontal direction hd1, wherein each of the insulating plates 32P is located at the same level as a corresponding subset of insulating strips 32S within the alternating stack (32S, 46), has the same thickness and has the same material composition; and a dielectric isolation structure (174, 276, 376), which laterally contacts each of the insulating strips 32S within the alternating stack (32S, 46) and each insulating plate and each dielectric material plate 42P within the vertical alternating sequence and extends laterally along a second horizontal direction hd2.

[0351] In one embodiment, each of the backside trenches 79 is filled with a respective backside trench filling structure ( 74 , 76 ) having a respective pair of longitudinal sidewalls extending laterally along the first horizontal direction hd1 .

[0352] In one embodiment, each of the longitudinal sidewalls of the backside trench fill structure (74, 76) includes a respective surface segment that is in direct contact with the dielectric isolation structure (174, 276, 376).

[0353] In one embodiment, each interface between the alternating stack (32S, 46) and the dielectric isolation structure (174, 276, 376) extends vertically from a first horizontal plane HP1 including the bottommost surface of the alternating stack (32S, 46) to a second horizontal plane HP2 including the topmost surface of the alternating stack (32S, 46).

[0354] In one embodiment, each interface between the alternating stack (32S, 46) and the dielectric isolation structure (174, 276, 376) has an undulating vertical cross-sectional profile along a direction perpendicular to the second horizontal direction hd2.

[0355] In one embodiment, the dielectric isolation structure (174, 276, 376) includes a dielectric wall portion (276W, 376W) extending laterally along the second horizontal direction hd2 and laterally spaced apart from the backside trench 79; and a dielectric fin portion (276F, 376F) protruding laterally from the dielectric wall portion (276W, 376W) along the first horizontal direction hd1.

[0356] In one embodiment, the dielectric fin portions ( 276F, 376F) are located at the level of the conductive strips 46 , or at the level of the insulating tapes 32S.

[0357] In one embodiment, each of the dielectric fin portions (276F, 376F) has a respective lateral dimension along the first horizontal direction hd1 that is greater than a lateral dimension of the dielectric wall portion (276W, 376W) along the first horizontal direction hd1.

[0358] In one embodiment, a lateral distance between the dielectric wall portion (276W, 376W) and one of the backside trenches 79 along the first horizontal direction hd1 is less than a lateral distance between the dielectric wall portion (276W, 376W) and one of the conductive strips 46 along the first horizontal direction hd1.

[0359] In one embodiment, all interfaces between insulating strips 32S and dielectric isolation structures (174, 276, 376) are located within sidewall surface segments of dielectric wall portions (276W, 376W).

[0360] In one embodiment, a three-dimensional memory device includes a support post structure 20 that extends vertically through a corresponding subset of the dielectric fin portions (276F, 376F) and extends vertically from a first horizontal plane HP1 including the bottommost surface of the alternating stack (32S, 46) to a second horizontal plane HP2 including the topmost surface of the alternating stack (32S, 46).

[0361] In one embodiment, the three-dimensional memory device includes: an upper metal interconnect structure 380, which covers the alternating stack (32S, 46) and is embedded in the upper dielectric material layer 360; a memory side pad 388, which is electrically connected to the upper metal interconnect structure 380 and embedded in the upper dielectric material layer 360; and a logic die 700, which includes a logic side semiconductor device 720 and a logic side pad 788 electrically connected to the logic side semiconductor device 720 through the logic side metal interconnect structure 780, wherein the logic side pad 788 is bonded to the memory side pad 388.

[0362] In one embodiment, the three-dimensional memory device also includes a connecting via structure 386 that extends vertically through the vertical alternating sequence and provides electrical connection to the upper metal interconnect structure 380 .

[0363] In one embodiment, the three-dimensional memory device further includes a lateral insulated contact via structure (84, 86) extending vertically through a corresponding subset of the conductive strips located between corresponding adjacent pairs of backside trenches 79 and contacting a corresponding one of the conductive strips 46S. The lateral insulated contact via structure (84, 86) is located in a contact region that has no steps in the alternating stack of insulating strips and conductive strips. The alternating stack of insulating strips and conductive strips is located in different memory blocks that are electrically isolated from each other by the backside trenches and the dielectric isolation structure.

[0364] Various embodiments of the present disclosure may be used to form a three-dimensional memory device, wherein a contact via structure 86 is used to provide electrical contact to each of the conductive strips 46 while avoiding the formation of any trenches that intersect the backside trench 79. Generally speaking, two trenches that intersect each other result in a deeper bottom recess at the intersection region. The intersection region is prone to forming a downwardly protruding conductive structure and subsequent electrical short circuits. Various embodiments of the present disclosure use a dielectric etch stop structure (81, 181) or a dielectric isolation structure (174, 276, 376) to prevent electrical connection between word lines in laterally adjacent memory blocks while avoiding trench intersections during manufacturing process steps, thereby increasing yield and product reliability.

[0365] Although specific embodiments are mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional memory device, comprising: alternating stacks of insulating strips and conductive strips, the insulating strips and the conductive strips alternating in a vertical direction, wherein each of the alternating stacks extends laterally in a first horizontal direction, and the alternating stacks are laterally spaced apart from each other by backside trenches in a second horizontal direction; an array of memory openings extending vertically through the alternating stacks; memory opening filling structures located in the memory openings, wherein each of the memory opening filling structures comprises a vertical semiconductor channel and a respective vertical memory element stack at the level of the conductive strips; a vertical alternating sequence of insulating plates and plates of dielectric material, the vertical alternating sequence being laterally spaced from the alternating stack along the first horizontal direction, wherein each of the insulating plates is located at the same level, has the same thickness, and has the same material composition as a corresponding subset of the insulating strips within the alternating stack; and A dielectric isolation structure laterally contacts each of the insulating strips within the alternating stack and each insulating plate and each plate of dielectric material within the vertical alternating sequence and extends laterally along the second horizontal direction.

2. The three-dimensional memory device of claim 1, wherein each of the backside trenches is filled with a corresponding backside trench filling structure having a corresponding pair of longitudinal sidewalls extending laterally along the first horizontal direction. 3 . The three-dimensional memory device of claim 2 , wherein each of the longitudinal sidewalls of the backside trench filling structure comprises a respective surface segment in direct contact with the dielectric isolation structure.

4. The three-dimensional memory device of claim 1 , wherein each interface between the alternating stacks and the dielectric isolation structure extends vertically from a first horizontal plane including a bottommost surface of the alternating stacks to a second horizontal plane including a topmost surface of the alternating stacks. 5 . The three-dimensional memory device of claim 1 , wherein each interface between the alternating stacks and the dielectric isolation structure has an undulating vertical cross-sectional profile along the first horizontal direction perpendicular to the second horizontal direction.

6. The three-dimensional memory device according to claim 5, wherein the dielectric isolation structure comprises: a dielectric wall portion extending laterally along the second horizontal direction and laterally spaced from the backside trench; and A dielectric fin portion protrudes laterally from the dielectric wall portion along the first horizontal direction. 7 . The three-dimensional memory device of claim 6 , wherein the dielectric fin portions are located at the level of the conductive strips or at the level of the insulating strips. 8 . The three-dimensional memory device of claim 6 , wherein each of the dielectric fin portions has a respective lateral dimension along the first horizontal direction that is greater than a lateral dimension of the dielectric wall portion along the first horizontal direction.

9. The three-dimensional memory device of claim 6, wherein a lateral distance between the dielectric wall portion and one of the backside trenches along the first horizontal direction is smaller than a lateral distance between the dielectric wall portion and one of the conductive strips along the first horizontal direction.

10. The three-dimensional memory device of claim 6, wherein all interfaces between the insulating strips and the dielectric isolation structures are located within sidewall surface segments of the dielectric wall portions.

11. The three-dimensional memory device of claim 6 , further comprising a support post structure extending vertically through a corresponding subset of the dielectric fin portions and extending vertically from a first horizontal plane including a bottommost surface of the alternating stack to a second horizontal plane including a topmost surface of the alternating stack.

12. The three-dimensional memory device according to claim 1, further comprising: an upper metal interconnect structure overlying the alternating stack and embedded within an upper dielectric material layer; a memory side pad electrically connected to the upper metal interconnect structure and embedded within the upper dielectric material layer; and A logic die includes a logic-side semiconductor device and a logic-side pad electrically connected to the logic-side semiconductor device through a logic-side metal interconnect structure, wherein the logic-side pad is bonded to the memory-side pad.

13. The three-dimensional memory device of claim 12, further comprising a lateral insulated contact via structure extending vertically through a corresponding subset of the conductive strips between corresponding adjacent pairs of backside trenches and contacting a corresponding one of the conductive strips.

14. The three-dimensional memory device of claim 13, wherein the lateral insulated contact via structure is located in a contact region that has no steps in the alternating stacks of insulating and conductive strips.

15. The three-dimensional memory device of claim 1, wherein the alternating stacks of insulating and conductive strips are located in different memory blocks, the memory blocks being electrically isolated from each other by the backside trenches and the dielectric isolation structures.

16. A method comprising: forming a vertically alternating sequence of insulating layers and sacrificial material layers over the substrate, wherein the sacrificial material layers comprise a dielectric material; forming backside trenches and isolation trenches through the vertical alternating sequence, wherein the backside trenches extend laterally along the first horizontal direction and are laterally spaced apart along a second horizontal direction, and the isolation trenches extend laterally along the second horizontal direction and are laterally spaced apart from the backside trenches along the first horizontal direction; forming an isolation cavity by laterally extending the isolation trenches, wherein an alternating stack of insulating strips and sacrificial material strips is formed, wherein the insulating strips are portions of the insulating layer located between respective adjacent pairs of backside trenches, wherein the sacrificial material strips are discrete remaining portions of the sacrificial material layer, and wherein each of the sacrificial material strips is laterally spaced apart from all other sacrificial material strips located at the same vertical level by a combination of the backside trenches and the isolation cavity; forming a dielectric isolation structure in the isolation cavity; as well as The strips of sacrificial material are replaced with conductive strips to form alternating stacks of respective subsets of the insulating strips and respective subsets of the conductive strips.

17. The method according to claim 16, further comprising: forming a sacrificial backside trench fill structure in the backside trench; as well as performing an isotropic etching process, wherein the isotropic etching process selectively etches the material of the sacrificial material layer with respect to the material of the insulating layer and the sacrificial backside trench filling structure to form the isolation cavity, Wherein after the isotropic etching process, a surface segment of the sacrificial backside trench fill structure is physically exposed in the isolation cavity at each level of the sacrificial material layer.

18. The method of claim 16, wherein: forming the dielectric isolation structure by depositing a dielectric material in the isolation cavity; and The dielectric isolation structure comprises: a dielectric wall portion extending laterally along the second horizontal direction and laterally spaced from the backside trench; and A dielectric fin portion protrudes laterally from the dielectric wall portion along the first horizontal direction.

19. The method of claim 16, further comprising forming a lateral insulated contact via structure extending vertically through a respective subset of the conductive strips between respective adjacent pairs of backside trenches and contacting a respective one of the conductive strips.

20. The method according to claim 16, further comprising: forming an array of memory openings extending vertically through the vertical alternating sequence; as well as Memory opening filling structures are formed, the memory opening filling structures being located in the memory openings, wherein each of the memory opening filling structures comprises a vertical semiconductor channel and a respective vertical memory element stack at the level of the conductive strips.

21. A three-dimensional memory device, comprising: an alternating stack of insulating layers and composite layers, the insulating layers and composite layers alternating in a vertical direction, wherein each of the composite layers comprises a combination of a dielectric connecting plate and a plurality of conductive strips, the dielectric connecting plate and the plurality of conductive strips extending laterally in a first horizontal direction, being laterally spaced apart in a second horizontal direction by backside trenches extending laterally in the first horizontal direction and having respective sidewalls abutting respective sidewall surface segments of the dielectric connecting plate, wherein end portions of the backside trenches are laterally bounded by the dielectric connecting plates of the composite layers; an array of memory openings extending vertically through the alternating stacks; memory opening filling structures located in the memory openings, wherein each of the memory opening filling structures comprises a vertical semiconductor channel and a respective vertical memory element stack at the level of the conductive strips; a backside trench-fill structure located in the backside trench and extending vertically from at least a first horizontal plane including a bottommost surface of the alternating stack and extending at least to a second horizontal plane including a topmost surface of the alternating stack; and a dielectric etch stop structure located within or outside a corresponding one of the backside trenches, wherein each of the dielectric etch stop structures includes a corresponding pair of dielectric sidewalls located within a pair of longitudinal sidewalls of the corresponding one of the backside trenches, wherein the dielectric sidewalls of the dielectric etch stop structure extend laterally along the first horizontal direction and extend vertically from at least the first horizontal plane and extend at least to the second horizontal plane.

22. The three-dimensional memory device of claim 21, wherein each of the conductive strips has a respective lateral extent along the second horizontal direction that is no greater than a lateral spacing between a closest pair of the backside trenches.

23. The three-dimensional memory device of claim 22, wherein the lateral extent of each of the conductive strips is the same as the lateral spacing between the one of the closest pairs in the backside trenches throughout each of the conductive strips.

24. The three-dimensional memory device of claim 22, wherein: the lateral extent of each of the conductive strips being the same as the lateral spacing between the pair of closest pairs in the backside trenches within a first portion of each of the conductive strips, the first portion being distal from a dielectric connection plate contacted by the respective conductive strip; and The lateral extent of each of the conductive strips is less than the lateral spacing between the closest pair of backside grooves among the backside grooves within a second portion of each of the conductive strips, the second portion being proximal to the dielectric connection plate contacted by the corresponding conductive strip.

25. The three-dimensional memory device of claim 21 , wherein each of the dielectric etch stop structures comprises: a respective pair of inner longitudinal side walls, the respective pair of inner longitudinal side walls being parallel to the first horizontal direction and having a first transverse spacing therebetween; a corresponding pair of outer longitudinal side walls, the corresponding pair of outer longitudinal side walls being parallel to the first horizontal direction and having a second lateral spacing therebetween, the second lateral spacing being greater than the first lateral spacing; and A respective connecting side wall connects the respective pair of outer longitudinal side walls and contacts each of the dielectric connecting plates within the alternating stack.

26. The three-dimensional memory device of claim 25, wherein for each of the dielectric etch stop structures, the pair of dielectric sidewalls comprises a pair of the outer longitudinal sidewalls.

27. The three-dimensional memory device of claim 25, wherein for each of the dielectric etch stop structures, the pair of dielectric sidewalls comprises a pair of the inner longitudinal sidewalls.

28. The three-dimensional memory device of claim 21, wherein: each of the dielectric etch stop structures being located within the corresponding one of the backside trenches; and Each of the backside trench filling structures has a first portion having the same width as a corresponding one of the backside trenches and a second portion having a smaller width than the corresponding one of the backside trenches.

29. The three-dimensional memory device of claim 21, wherein: Each of the dielectric etch stop structures is located outside of the corresponding one of the backside trenches; and Each of the backside trench filling structures has a uniform width throughout, and the uniform width is the same as the width of the corresponding backside trench.

30. The three-dimensional memory device according to claim 21, further comprising: an upper metal interconnect structure overlying the alternating stack and embedded within an upper dielectric material layer; a memory side pad electrically connected to the upper metal interconnect structure and embedded within the upper dielectric material layer; and A logic die includes a logic-side semiconductor device and a logic-side pad electrically connected to the logic-side semiconductor device through a logic-side metal interconnect structure, wherein the logic-side pad is bonded to the memory-side pad.

31. The three-dimensional memory device of claim 30, further comprising a lateral insulated contact via structure extending vertically through a corresponding subset of the alternating stacks between corresponding adjacent pairs of backside trenches and contacting a corresponding one of the conductive strips.

32. The three-dimensional memory device of claim 31, wherein the lateral insulated contact via structure is located in a contact region, the contact region having no steps in the alternating stack.

33. The three-dimensional memory device of claim 30, further comprising a connecting via structure extending vertically through the dielectric connecting plates within the alternating stack and electrically connected to a corresponding one of the upper metal interconnect structures.

34. The three-dimensional memory device of claim 21, wherein the alternating stacks are in different memory blocks, the memory blocks being electrically isolated from each other by the backside trenches and the dielectric etch stop structures.

35. A method comprising: forming a vertically alternating sequence of insulating layers and sacrificial material layers over the substrate, wherein the sacrificial material layers comprise a dielectric material; forming backside grooves extending laterally across the vertical alternating sequence in a first horizontal direction, wherein the backside grooves are laterally spaced apart in a second horizontal direction, and stripe portions of the vertical alternating sequence between adjacent pairs of the backside grooves are interconnected to one another by connecting portions of the vertical alternating sequence, the connecting portions being connected to each of the stripe portions of the vertical alternating sequence; forming at least one dielectric etch stop structure before or after forming the backside trenches, such that the at least one dielectric etch stop structure vertically extends from at least a first horizontal plane including a bottommost surface of the vertical alternating sequence and extends to at least a second horizontal plane including a topmost surface of the vertical alternating sequence, and the at least one dielectric etch stop structure includes a pair of dielectric sidewalls located within a corresponding one of the backside trenches; forming the backside recess by performing an isotropic etching process that selectively removes a portion of the sacrificial material layer proximate the backside trench with respect to the material of the insulating layer and the at least one dielectric etch stop structure, wherein a remaining portion of the sacrificial material layer after the isotropic etching process includes a dielectric connecting plate contacting each of the dielectric etch stop structures; and A conductive strip is formed in the backside groove.

36. The method of claim 35, wherein: In forming the conductive strips, an alternating stack of respective portions of the insulating layer and respective subsets of the conductive strips is formed between each adjacent pair of the backside trenches; and The method also includes forming contact via structures through the alternating stack, wherein each of the contact via structures contacts a corresponding one of the conductive strips.

37. The method of claim 36, wherein: Each of the contact via structures is laterally surrounded by and contacted by a respective tubular insulating spacer; and Each of the contact via structures is electrically isolated from each conductive strip within the corresponding vertical stack of conductive strips except for the corresponding one of the conductive strips.

38. The method of claim 36, wherein the at least one dielectric etch stop structure is formed by depositing and patterning a conformal etch mask material layer within the backside trench after forming the backside trench.

39. The method of claim 36, wherein: forming the at least one dielectric etch stop structure prior to forming the backside trenches through the vertical alternating sequence; and Each of the backside trenches cuts into a peripheral portion of the at least one dielectric etch stop structure.

40. The method of claim 35, further comprising: forming an array of memory openings extending vertically through the vertical alternating sequence; as well as Memory opening filling structures are formed, the memory opening filling structures being located in the memory openings, wherein each of the memory opening filling structures comprises a vertical semiconductor channel and a respective vertical memory element stack at the level of the conductive strips.

Images