Ultra-low noise DC-DC voltage stabilizer method and circuit adopting current reference

Abstract

The invention discloses an ultra-low noise DC-DC voltage stabilizer circuit adopting a current reference. The ultra-low noise DC-DC voltage stabilizer circuit comprises a current sampling circuit, a high-side MOS tube, a low-side MOS tube, a PWM controller, a slope compensation circuit, a comparator and a compensation amplification circuit. The current sampling amplifier is used for sampling and outputting a signal to the comparator, and the comparator outputs the signal to the PWM controller; the compensation amplification circuit comprises an error amplifier, a type2 type compensation circuit and a reference voltage circuit, the in-phase input end of the error amplifier receives reference voltage, and the output end of the error amplifier is connected to the comparator and connected with the type2 type compensation circuit in parallel. In addition, the invention further discloses a method for the ultralow-noise DC-DC voltage stabilizer adopting the current reference, and the circuit is used for achieving the design of the ultralow-noise DC-DC voltage stabilizer. The ultra-low noise current source is used as the reference of the in-phase input end of the error amplifier, a voltage division network of the output end is omitted, and the noise of the output end is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of DC-DC regulators, and in particular to an ultra-low noise DC-DC regulator method and circuit using a current reference. Background Art

[0002] A DC-DC regulator is an electronic device that converts a fixed DC voltage to another fixed or adjustable DC voltage. They are widely used in various electronic systems to provide a stable power supply to ensure the normal operation of the circuit.

[0003] In DC-DC regulators, there are generally noise-sensitive devices such as phase-locked loops (PLLs), voltage-controlled oscillators (VCOs), and power amplifiers (PAs). Therefore, in the conversion process using DC-DC converters, it is necessary to pay attention to reducing noise to ensure the accuracy and reliability of the signal. In order to solve the noise problem in DC-DC regulators, the current optimization is mainly carried out by combining LDO low-dropout linear regulators and DC-DC converters. This is because the current mainstream DC-DC converters have a good suppression effect on high-frequency noise, but the low-frequency noise is large. The low-frequency noise is noise within 100kHz, while the LDO low-dropout linear regulator has a good low-frequency noise suppression effect but a poor high-frequency noise suppression effect. Therefore, the two are combined, and a combination of DC-DC converters + LDO low-dropout linear regulators is used to achieve full-band low-noise power supply, so that the final noise measurement value can also be controlled between hundreds of uV and several mV.

[0004] However, the measures currently taken contain at least the following three problems: 1) The layout area is increased and the efficiency is slightly lower than that of a single DC-DC converter; 2) It is necessary to consider the switching frequency of the DC-DC converter and the bandwidth limitations of the LDO low-dropout linear regulator. The actual design is subject to many device restrictions and needs to consider the compatibility of a large number of parameters, which is extremely cumbersome; 3) The suppression effect on low-frequency noise is still insufficient, which results in the final output noise being still relatively large. Summary of the invention

[0005] In view of the above three problems, the purpose of the present invention is to propose an ultra-low noise DC-DC regulator method and circuit using a current reference, using an ultra-low noise current source as the reference of the non-inverting input terminal of the error amplifier and eliminating the output terminal V OUT The voltage divider network effectively reduces the output V OUT The low-frequency noise is reduced and the overall circuit structure of the DC-DC regulator is optimized to obtain an ultra-low-noise DC-DC regulator, making the design simpler and more efficient.

[0006] This is achieved through the following technical solutions: First, an ultra-low noise DC-DC regulator method using a current reference is proposed, including the following steps: S1, setting a PWM controller, a high-side MOS tube Q1 and a low-side MOS tube Q2, connecting the high-side MOS tube Q1 and the low-side MOS tube Q2 to receive an input terminal V IN The power supply of the high-side MOS tube Q1 and the low-side MOS tube Q2 is controlled by the PWM controller at the same time; S2, a current sampling circuit, a comparator and a slope compensation circuit are set, and the drain of the high-side MOS tube Q1 in step S1 is sampled by the current sampling circuit, and the sampling result is output to the comparator and the sampling result is compensated by the slope compensation circuit; S3, a power inductor L and a compensation amplifier circuit are set, and the compensation amplifier circuit is connected to the output terminal V OUT and the comparator, and at the same time, the output terminal V is connected between the high-side MOS tube Q1 and the low-side MOS tube Q2 in step S1 through the power inductor L. OUT The compensation amplifier circuit includes an error amplifier EA, a type 2 compensation circuit, and a reference voltage circuit using a current reference. The inverting input terminal of the error amplifier EA is connected to the output terminal V OUT The non-inverting input terminal of the error amplifier EA receives the reference voltage of the reference voltage circuit, and the output terminal of the error amplifier EA is connected to the comparator and is connected in parallel to the type 2 compensation circuit.

[0007] In addition, an ultra-low noise DC-DC regulator circuit using a current reference is proposed, which is operated using the above method, including a current sampling circuit, a high-side MOS tube Q1, a low-side MOS tube Q2, a PWM controller, a slope compensation circuit, a comparator, a compensation amplifier circuit, an input terminal V IN and output terminal V OUT ; Wherein, the current sampling circuit includes a sampling resistor R4 and a current sampling amplifier; the input terminal V IN After passing through the sampling resistor R4, it enters the drain of the high-side MOS tube Q1. The source of the high-side MOS tube Q1 is connected to the drain of the low-side MOS tube Q2. The gates of the high-side MOS tube Q1 and the low-side MOS tube Q2 are both connected to the PWM controller. The two MOS tubes are connected to the output terminal V through the power inductor L. OUT , between the power inductor L and the output terminal V OUT A capacitor C connected to ground is also connected in parallel. OUTThe current sampling amplifier is used to sample the sampling resistor R4 and output the sawtooth wave signal to the non-inverting input terminal of the comparator, and the output terminal of the comparator is output to the PWM controller; the slope compensation circuit is used to perform slope compensation on the sawtooth wave signal; the compensation amplifier circuit includes an error amplifier EA, a type 2 compensation circuit and a reference voltage circuit, and the inverting input terminal of the error amplifier EA is connected to the output terminal V OUT The non-inverting input terminal of the error amplifier EA receives the reference voltage of the reference voltage circuit, and the output terminal of the error amplifier EA is connected to the inverting input terminal of the comparator and is connected in parallel to the type 2 compensation circuit.

[0008] At the output V OUT Abandoning the voltage divider network, an ultra-low noise current source is used as the reference for the non-inverting input of the error amplifier to achieve ultra-low noise. This not only facilitates adjustment, but also avoids the influence of thermal noise of the voltage divider network itself during operation, making the circuit design simpler and more efficient.

[0009] Preferably, the reference voltage circuit includes a capacitor C2, a resistor R4 and a current source I REF ; Capacitor C2 and resistor R4 are connected in parallel to the current source I REF Both ends are grounded to filter out the current source I REF The noise of the current source I REF The resistor R4 generates a stable voltage drop as the voltage of the non-inverting input terminal of the error amplifier EA. The current source generates a stable voltage drop through the resistor R4, which can effectively provide a reference voltage for the error amplifier EA and reduce noise.

[0010] Preferably, the type 2 compensation circuit includes a resistor R3, a grounded capacitor C1 and a grounded capacitor C3, the capacitor C3 is connected in parallel to the output end of the error amplifier EA, and the capacitor C1 is connected to the output end of the error amplifier EA through the resistor R3. Compensation using the type 2 compensation circuit can improve stability and achieve precise switch control.

[0011] Preferably, the current source I REF Use ultra-low noise current source. Using ultra-low noise current source can effectively reduce the final output V OUT noise.

[0012] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention uses an ultra-low noise current source as the reference of the in-phase input terminal of the error amplifier and eliminates the output terminal V OUT The voltage divider network effectively reduces the output V OUT The noise is reduced and the overall circuit structure of the DC-DC regulator is optimized to obtain an ultra-low noise DC-DC regulator, making the design simpler and more efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of the structure of an ultra-low noise DC-DC regulator circuit using a current reference; Figure 2 A schematic diagram of the loop structure of an ultra-low noise DC-DC regulator circuit using a current reference; Figure 3 It is an error amplifier connected to the output terminal V through a voltage divider network. OUT Schematic diagram of the structure. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0015] like Figure 1 As shown in FIG. 1 , it is a schematic diagram of the structure of an ultra-low noise DC-DC regulator circuit using a current reference, such as Figure 2 As shown, it is a loop structure diagram of an ultra-low noise DC-DC regulator circuit using a current reference; combined with Figure 1 and Figure 2 As shown, the circuit mainly includes a current sampling circuit, a high-side MOS tube Q1, a low-side MOS tube Q2, a PWM controller, a slope compensation circuit, a comparator, a compensation amplifier circuit, and an input terminal V IN and output terminal V OUT The high-side and low-side MOS tubes are controlled by the PWM controller, and the generated output voltage is fed back into the error amplifier to be compared with the reference voltage. The obtained output is then compensated and enters the comparator to be compared with the sawtooth wave signal after slope compensation. The signal generated after comparison enters the PWM controller to participate in the PWM signal control, thereby completing the construction of the ultra-low noise DC-DC regulator circuit.

[0016] In this embodiment, the current sampling circuit is used to sample the high-side MOS tube Q1, and specifically includes a sampling resistor R4 and a current sampling amplifier. IN Responsible for providing input voltage V IN , V IN After passing through the sampling resistor R4, it enters the drain of the high-side MOS tube Q1. The source of the high-side MOS tube Q1 is connected to the drain of the low-side MOS tube Q2. The gates of the high-side MOS tube Q1 and the low-side MOS tube Q2 are both connected to the PWM controller to receive the control of the PWM signal. The source of the low-side MOS tube Q2 is grounded. Between the two MOS tubes, it is also connected to the output terminal V through the power inductor L. OUT , between the power inductor L and the output terminal V OUT A capacitor C connected to ground is also connected in parallel. OUT , capacitor C OUTMainly used for filtering, the power inductor L uses the principle that the current flowing through the inductor cannot change suddenly. In a cycle, when the high-side MOS tube Q1 is turned on and the low-side MOS tube Q2 is turned off, the power inductor L plays the role of energy storage. At this time, the input voltage V IN Give the power inductor L and capacitor C OUT Charging; when the high-side MOS tube Q1 is turned off and the low-side MOS tube Q2 is turned on, the power inductor L serves as a power source to the capacitor C OUT Charging to maintain the output V OUT The output voltage remains unchanged. The two input terminals of the current sampling amplifier are connected to the two ends of the sampling resistor R4, which is used to sample the current of the sampling resistor R4 and output a sawtooth wave signal in the form of a voltage to the non-inverting input terminal of the comparator. This sawtooth wave signal participates in the operation of the loop after being compensated by the slope compensation circuit. It should be noted that the purpose of the slope compensation circuit is to provide a linearly increasing ramp signal to compensate the sawtooth wave signal, reduce the possibility of problems such as subharmonic oscillation, and improve stability. The circuit can use a conventional slope compensation circuit.

[0017] In this embodiment, the compensation amplifier circuit includes an error amplifier EA, a type 2 compensation circuit and a reference voltage circuit. The inverting input terminal of the error amplifier EA is connected to the output terminal V OUT The non-inverting input of the error amplifier EA receives the reference voltage of the reference voltage circuit, and the output of the error amplifier EA is connected to the inverting input of the comparator and is connected in parallel to the type 2 compensation circuit. The reference voltage circuit consists of capacitor C2, resistor R4 and current source I REF The capacitor C2 and the resistor R4 are connected in parallel to the current source I REF Both ends are grounded to filter out the current source I REF The noise of the current source I REF The stable voltage drop generated by resistor R4 is used as the reference voltage V at the non-inverting input of the error amplifier EA. ref By using the current source to generate a stable voltage drop through the resistor R4, a reference voltage can be effectively provided for the error amplifier EA and low-frequency noise can be reduced, that is, noise within 100kHz can be reduced, thereby effectively reducing the noise of the final output.

[0018] The type 2 compensation circuit compensates the output of the error amplifier EA. The type 2 compensation circuit includes a resistor R3, a grounded capacitor C1 and a grounded capacitor C3. The capacitor C3 is connected in parallel to the output of the error amplifier EA. The capacitor C1 is connected to the output of the error amplifier EA through the resistor R3. By using the type 2 compensation circuit to compensate the output of the error amplifier EA, new zeros and poles can be added to the loop, thereby affecting the bandwidth and phase of the entire loop. After the compensation, the loop stability and output transient response can be effectively improved.

[0019] like Figure 3 As shown, it is an error amplifier connected to the output terminal V through a voltage divider network. OUT The equivalent resistance of the error amplifier EA is recorded as R0. In the feedback loop, the resistors R1 and R2 are connected in series to form a voltage divider network. The resistor R1 is connected in parallel to the output terminal V OUT , resistor R2 is grounded. If the error amplifier EA is connected between resistors R1 and R2, that is, connected to the output terminal V through a voltage divider network OUT In this case, the output of the DC-DC regulator circuit is V OUT , input is formula (1): △V = , gm represents the transconductance parameter of the error amplifier EA.

[0020] Combination Figure 2 The loop shown, the output terminal V OUT The output voltage value is formula (2): , Gain represents the overall gain of the loop; similarly, the output V OUT The output noise is given by formula (3): , noise represents noise, △V （noise） It indicates the noise doped in the input. It can be seen that while keeping the output V OUT When the voltage remains unchanged, the larger the Gain, the greater the △V and △V （noise） The smaller it is, at the same time, due to V ref There is noise V noise1 , which will also introduce the noise V to the inverting input noise1 , which ultimately leads to the output V OUT The final noise is (V noise1 +△V （noise） )× .

[0021] Again Figure 2 By analyzing the loop shown in the figure, we can know that the transfer function is formula (4): ; The output of the error amplifier EA is formula (5): ,in, , V0 is V OUT ; The noise output by the error amplifier EA is given by formula (6): ; Output terminal V OUT The final noise is formula (7): Since sampling is current sampling, the output current remains unchanged, the sawtooth current remains unchanged, and the output of the error amplifier EA remains unchanged. Therefore, the higher the value of the transconductance parameter gm, the greater the amplitude of H (s). The smaller it is, Therefore, in order to effectively suppress the low-frequency noise of the DC-DC regulator circuit, it is necessary to design the voltage divider network and V ref Make optimizations.

[0022] When using a voltage divider network, The value of must be greater than 1. From formula (7), we can see that this will lead to increased noise. Only when it approaches 1 infinitely can the noise be reduced as much as possible. In addition, since the resistors R1 and R2 themselves generate heat during operation, this may introduce new thermal noise, further affecting the noise performance. Therefore, the present application directly cancels the voltage divider network, which is equivalent to making The value of is changed to 1, and the Figure 1 The structure shown is used to design the overall loop to simplify and optimize the circuit, and to eliminate the thermal noise introduced by the voltage divider network while realizing the DC-DC voltage regulator circuit conversion.

[0023] At the same time, an ultra-low noise current source I is selected at the non-inverting input of the error amplifier EA. REF To further reduce V ref The low-frequency noise in the output can effectively reduce the final output V OUT noise.

[0024] In addition, based on the ultra-low noise DC-DC regulator circuit using a current reference, an ultra-low noise DC-DC regulator method using a current reference is also proposed, including the following steps: S1, setting a PWM controller, a high-side MOS tube Q1 and a low-side MOS tube Q2, and connecting the high-side MOS tube Q1 and the low-side MOS tube Q2 to receive input terminals V IN The power supply of the high-side MOS tube Q1 and the low-side MOS tube Q2 is controlled by the PWM controller at the same time; S2, a current sampling circuit, a comparator and a slope compensation circuit are set, and the drain of the high-side MOS tube Q1 in step S1 is sampled by the current sampling circuit, and the sampling result is output to the comparator and the sampling result is compensated by the slope compensation circuit; S3, a power inductor L and a compensation amplifier circuit are set, and the compensation amplifier circuit is connected to the output terminal VOUT and the comparator, and at the same time, the output terminal V is connected between the high-side MOS tube Q1 and the low-side MOS tube Q2 in step S1 through the power inductor L. OUT The compensation amplifier circuit includes an error amplifier EA, a type 2 compensation circuit, and a reference voltage circuit using a current reference. The inverting input terminal of the error amplifier EA is connected to the output terminal V OUT The non-inverting input terminal of the error amplifier EA receives the reference voltage of the reference voltage circuit, and the output terminal of the error amplifier EA is connected to the comparator and connected in parallel to the type 2 compensation circuit. The advantages of this method can be referred to the relevant description in the ultra-low noise DC-DC regulator circuit using current reference, which will not be repeated here.

[0025] In summary, the present invention uses an ultra-low noise current source as the reference of the non-inverting input terminal of the error amplifier and eliminates the output terminal V OUT The voltage divider network effectively reduces the output V OUT The noise is reduced and the overall circuit structure of the DC-DC regulator is optimized to obtain an ultra-low noise DC-DC regulator, which makes the design simpler and more efficient, and is a significant improvement.

[0026] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. An ultra-low noise DC-DC regulator method using a current reference, characterized in that: The steps include: S1, set the PWM controller, high-side MOS tube Q1 and low-side MOS tube Q2, and connect the high-side MOS tube Q1 and the low-side MOS tube Q2 to the input terminal V IN The power supply is provided, and the PWM controller is used to control the switch of the high-side MOS tube Q1 and the low-side MOS tube Q2; S2, setting a current sampling circuit, a comparator and a slope compensation circuit, using the current sampling circuit to sample the drain of the high-side MOS tube Q1 in step S1, outputting the sampling result to the comparator and using the slope compensation circuit to compensate the sampling result; S3, set the power inductor L and the compensation amplifier circuit, and connect the compensation amplifier circuit to the output terminal V OUT and the comparator, and at the same time, the output terminal V is connected between the high-side MOS tube Q1 and the low-side MOS tube Q2 in step S1 through the power inductor L. OUT Complete external output; The compensation amplifier circuit includes an error amplifier EA, a type 2 compensation circuit, and a reference voltage circuit using a current reference. The inverting input terminal of the error amplifier EA is connected to the output terminal V OUT The non-inverting input terminal of the error amplifier EA receives the reference voltage of the reference voltage circuit, and the output terminal of the error amplifier EA is connected to the comparator and is connected in parallel to the type 2 compensation circuit.

2. An ultra-low noise DC-DC regulator circuit using a current reference, operating using an ultra-low noise DC-DC regulator method using a current reference as claimed in claim 1, characterized in that: It includes a current sampling circuit, a high-side MOS tube Q1, a low-side MOS tube Q2, a PWM controller, a slope compensation circuit, a comparator, a compensation amplifier circuit, an input terminal V IN and output terminal V OUT ; The current sampling circuit includes a sampling resistor R4 and a current sampling amplifier; the input terminal V IN After passing through the sampling resistor R4, it enters the drain of the high-side MOS tube Q1. The source of the high-side MOS tube Q1 is connected to the drain of the low-side MOS tube Q2. The gates of the high-side MOS tube Q1 and the low-side MOS tube Q2 are both connected to the PWM controller. The two MOS tubes are connected to the output terminal V through the power inductor L. OUT , between the power inductor L and the output terminal V OUT A capacitor C connected to ground is also connected in parallel. OUT The current sampling amplifier is used to sample the sampling resistor R4 and output the sawtooth wave signal to the non-inverting input terminal of the comparator, and the output terminal of the comparator is output to the PWM controller; the slope compensation circuit is used to perform slope compensation on the sawtooth wave signal; the compensation amplifier circuit includes an error amplifier EA, a type 2 compensation circuit and a reference voltage circuit, and the inverting input terminal of the error amplifier EA is connected to the output terminal V OUT The non-inverting input terminal of the error amplifier EA receives the reference voltage of the reference voltage circuit, and the output terminal of the error amplifier EA is connected to the inverting input terminal of the comparator and is connected in parallel to the type 2 compensation circuit.

3. The ultra-low noise DC-DC regulator circuit using a current reference according to claim 2, characterized in that: The reference voltage circuit includes capacitor C2, resistor R4 and current source I REF ; Capacitor C2 and resistor R4 are connected in parallel to the current source I REF Both ends are grounded to filter out the current source I REF The noise of the current source I REF A stable voltage drop is generated by the resistor R4 as the voltage at the non-inverting input terminal of the error amplifier EA.

4. The ultra-low noise DC-DC regulator circuit using a current reference according to claim 2, characterized in that: The type 2 compensation circuit includes a resistor R3, a grounded capacitor C1 and a grounded capacitor C3. The capacitor C3 is connected in parallel to the output end of the error amplifier EA. The capacitor C1 is connected to the output end of the error amplifier EA through the resistor R3.

5. The ultra-low noise DC-DC regulator circuit using a current reference according to claim 2, characterized in that: Current Source I REF Use ultra low noise current sources.

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