High throughput parallel architecture for recursive sine wave synthesizer

Abstract

Embodiments of the present disclosure relate to a high throughput parallel architecture for a recursive sine wave synthesizer. A first multiplier multiplies a first input with a first coefficient, and a first adder sums a second input with an output of the first multiplier to generate a first output. A second multiplier multiplies a third input by a second coefficient, a third multiplier multiplies a fourth input by a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. Second and third inputs are derived from the first output, and first and fourth inputs are derived from the second output. The first and second outputs generate digital values of the first and second digital sine waves, respectively.

Description

[0001] Divisional Application Instructions

[0002] This application is a divisional application of the Chinese patent application filed on September 17, 2020, with application number 202010978470.0 and invention name “High-throughput parallel architecture for recursive sine wave synthesizer”. Technical Field

[0003] The present invention relates generally to the generation of sine wave signals and, more particularly, to digital sine wave generators. Background Art

[0004] It is known in the art that the Chebyshev method can be used as a recursive algorithm for sine wave generation to find the nth angle formula from the (n-1)th angle formula and the (n-2)th angle formula. The formula is:

[0005] sin(nx)=2 cosx sin((n-1)x)-sin((n-2)x)

[0006] By replacing x with ω0, the above equation can be simplified mathematically to:

[0007] x1(n)=x1(n-1)+ψx2(n-1)Equation A

[0008] x2(n)=x2(n-1)-ψx1(n)Equation B

[0009] The multiplication coefficient

[0010] Therefore, the generated digital sinusoidal signal is:

[0011]

[0012] x2(n)=cos(ω0n)

[0013] Equations A and B can be simply used as Figure 1The addition, multiplication and delay elements shown are implemented in digital signal processing using the network diagram 10. The diagram 10 includes a first digital delay element 12 (e.g., in the form of a multi-bit data register including a D-type flip-flop) and a second digital delay element 14 (e.g., in the form of a multi-bit data register including a D-type flip-flop), the first digital delay element 12 being configured to receive the nth value of the first sinusoidal digital output x1 (and output the (n-1)th value of the first sinusoidal digital output x1), and the second digital delay element 14 being configured to receive the nth value of the second sinusoidal digital output x2 and output the (n-1)th value of the second sinusoidal digital output x2. The first and second sinusoidal digital outputs have the same frequency ω0, but have different phases (e.g., the phases differ from each other by 90 degrees). The D-type flip-flops of the registers including the first and second digital delay elements 12, 14 are composed of a plurality of digital delay elements 12 and 14 with a frequency f clock The operation is clock-controlled by a clock signal CK.

[0014] The first digital multiplier element 16 has a first input configured to receive the (n-1)th value of the second sinusoidal digital output x2 from the Q output of the second digital delay element 14, and a second input configured to receive the multiplication coefficient ψ. The output of the first digital multiplier element 16 is provided to a first input of a first digital summing element 18, which has a second input configured to receive the (n-1)th value of the first sinusoidal digital output x1 from the first digital delay element 12. The output of the first digital summing element 18 is the nth value of the first sinusoidal digital output x1 applied to the D input of the first delay element 12. The second digital multiplier element 22 has a first input configured to receive the nth value of the first sinusoidal digital output x1 (at the D input of the first delay element 12), and a second input configured to receive the multiplication coefficient -ψ. The output of the second digital multiplier element 22 is provided to a first input of a second digital summing element 24, which has a second input configured to receive the (n-1)th value of the second sinusoidal digital output x2 from the D output of the second digital delay element 14. A digital-to-analog (D / A) conversion circuit 28 sequentially receives the values ​​of the second sinusoidal digital output x2 and generates an analog sinusoidal wave output signal 30. The value of the first sinusoidal digital output x1 may also be converted to generate an analog sinusoidal wave output signal having the same frequency as the signal 30 but a different phase.

[0015] The critical timing path of the network 10 (referring to the longest path between any Q output of a flip-flop and any D input of a flip-flop) is represented by the path from the Q output of the flip-flop of the delay element 12 through the first digital summing element 18, the second digital multiplier element 22, and the second digital summing element 24 to the D input of the flip-flop of the delay element 14. This path represents the maximum logical delay of the digital signal processing operation, and this delay has a significant impact on the clock frequency f of the operation of the network 10. clock (i.e., the rate at which the digital values ​​of the sine wave are generated) can have a significant impact because all three mathematical operations must be completed between successive cycles of the clock. It would be advantageous to reduce the length of the critical path to support the flow of digital values ​​that generate the sinusoidal output at a higher clock frequency. Summary of the invention

[0016] In one embodiment, an apparatus includes a first core process and a second core process. The first core process includes: a first multiplier configured to multiply a first input by a first coefficient; a second multiplier configured to multiply a second input by a second coefficient; and a first adder configured to sum the outputs of the first multiplier and the second multiplier to generate a first output. The second core process includes: a third multiplier configured to multiply a third input by a third coefficient; a fourth multiplier configured to multiply a fourth input by a fourth coefficient; and a second adder configured to sum the outputs of the third multiplier and the fourth multiplier to generate a second output. Wherein the first and third inputs are derived from the second output, and wherein the second and fourth inputs are derived from the first output.

[0017] The first and second outputs provide digital values ​​for first and second digital sinusoidal signals, respectively, which have the same frequency but are offset in phase from each other.

[0018] In one embodiment, an apparatus comprises: a first multiplier configured to multiply a first input by a first coefficient; a first adder configured to generate a first output from a sum of an output of the first multiplier and a second input; a second multiplier configured to multiply a third input by the second coefficient; a third multiplier configured to multiply a fourth input by the third coefficient; a second adder configured to generate a second output from a sum of outputs of the second and third multipliers; wherein the second and third inputs are derived from the first output; and wherein the first and fourth inputs are derived from the second output.

[0019] The first and second outputs provide digital values ​​for first and second digital sinusoidal signals, respectively, which have the same frequency but are offset in phase from each other.

[0020] In one embodiment, a device includes a scalable processing architecture comprising multiple core processes, wherein each core process includes: a first multiplier configured to multiply a first input by a first coefficient; a second multiplier configured to multiply a second input by a second coefficient; and a first adder configured to sum the outputs of the first and second multipliers to generate a first output; wherein the first inputs of the core processes are coupled together to receive a signal derived from a first output of a first core process in the core processes; and wherein the second inputs of the core processes are coupled together to receive a signal derived from a first output of a second core process in the core processes, the second core process being different from the first core process. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0022] Figure 1 is a network diagram of the digital signal processing implementation of a recursive digital sine wave generator;

[0023] Figure 2 is a network diagram of the digital signal processing implementation of a recursive digital sine wave generator;

[0024] Figure 3 is a network diagram of a digital signal processing implementation of a recursive digital sine wave generator; and

[0025] Figure 4 is a network diagram of a digital signal processing implementation of a recursive digital sine wave generator. DETAILED DESCRIPTION

[0026] To reduce the critical path of network 10, start with equations A and B:

[0027] x1(n)=x1(n-1)+ψx2(n-1)

[0028] x2(n)=x2(n-1)-ψx1(n)

[0029] By substituting x1(n) into x2(n), we achieve the following:

[0030] x2(n)=x2(n-1)-ψ(x1(n-1)+ψx2(n-1))

[0031] which is rearranged to:

[0032] x2(n)=(1-ψ 2 )*x2(n-1)-ψx1(n-1)

[0033] Let K1 = 1-ψ 2

[0034] The result is:

[0035] x1(n)=x1(n-1)+ψx2(n-1)Equation C

[0036] x2(n)=K1*x2(n-1)-ψx1(n-1) Equation D

[0037] Equations C and D can be solved using only Figure 2 The addition, multiplication and delay elements shown in are implemented in digital signal processing using a network diagram 10'. Diagram 10' includes a first digital delay element 12 (e.g., in the form of a multi-bit data register including a D-type flip-flop) and a second digital delay element 14' (e.g., in the form of a multi-bit data register including a D-type flip-flop), the first digital delay element 12 being configured to receive the nth value of the first sinusoidal digital output x1 (and output the (n-1)th value of the first sinusoidal digital output x1), and the second digital delay element 14' being configured to receive the nth value of the second sinusoidal digital output x2 (and output the (n-1)th value of the second sinusoidal digital output x2). The first and second sinusoidal digital outputs have the same frequency ω0, but have different phases (e.g., the phases differ from each other by 90 degrees). The D-type flip-flops forming the registers of the first and second digital delay elements 12, 14' are composed of flip-flops having a frequency f clock The clock signal CK is used for clock control.

[0038] The first digital multiplier element 16 has a first input configured to receive the (n-1)th value of the second sinusoidal digital output x2 from the Q output of the second digital delay element 14', and a second input configured to receive the multiplication coefficient ψ. The output of the first digital multiplier element 16 is provided to the first input of the first digital summing element 18, which has a second input configured to receive the (n-1)th value of the first sinusoidal digital output x1 from the Q output of the first digital delay element 12. The output of the first digital summing element 18 is the nth value of the first sinusoidal digital output x1 to be stored in the first delay element 12. The second digital multiplier element 22' has a first input configured to receive the (n-1)th value of the first sinusoidal digital output x1 from the Q output of the first delay element 12, and a second input configured to receive the multiplication coefficient -ψ. The output of the second digital multiplier element 22' is provided to the first input of the second digital summing element 24'. The third digital multiplier element 26' has a first input configured to receive the (n-1)th value of the second sinusoidal digital output x2 from the Q output of the second digital delay element 14', and a second input configured to receive the multiplication coefficient K1. The output of the third digital multiplier element 26' is provided to the second input of the second digital summing element 24'. The output of the second digital summing element 24' is the nth value of the second sinusoidal digital output x2 to be stored in the second digital delay element 14'.

[0039] It should be noted that network 10' is Figure 1 Network 10 has a critical path advantage because the longest path between any Q output of a flip-flop and any D input of a flip-flop consists of only one digital multiplier element and one digital summing element, so the maximum logic delay here is less than Figure 1 Therefore, the network 10' can operate at a higher clock frequency.

[0040] Network 10' represents the core recursion of sine wave generation, which can be expressed as Figure 3 As shown, the core is replicated to generate multiple consecutive values ​​of the sine wave simultaneously so as to generate the digital value of the output sine wave at a higher effective clock frequency. For example, the goal would be to expand the core recursion four times so as to generate four consecutive digital values ​​of the sine wave (x2(n), x2(n+1), x2(n+2), x2(n+3)) simultaneously for each cycle of the clock CK, which would theoretically allow the digital value of the sine wave to be generated at a rate four times the actual clock frequency of the network 10'.

[0041] Each core recursion 10'(1) to 10'(4) includes a first digital summing element 18 having a first input configured to receive a first digital input signal 32. The first digital multiplier element 16 has: a first input configured to receive a second digital input signal 34, and a second input configured to receive a multiplication coefficient ψ. The output of the second digital multiplier element 16 is provided to the second input of the first digital summing element 18. The output of the first digital summing element 18 provides a first digital output signal 36. The second digital multiplier element 22' has: a first input configured to receive the first digital input signal 32, and a second input configured to receive the multiplication coefficient -ψ. The output of the third digital multiplier element 22' is provided to the first input of the second digital summing element 24'. The fourth digital multiplier element 26' has: a first input configured to receive the second digital input signal 34, and a second input configured to receive the multiplication coefficient K1. The output of the fourth digital multiplier element 26' is provided to the second input of the second digital summing element 24'. The output of the second digital summing element 24 ′ provides a second digital output signal 38 .

[0042] The core recursions 10'(1) to 10'(4) are connected in series (cascade) with feedback. The first and second digital output signals 36, 38 from the core recursion 10'(1) provide the first and second digital input signals 32, 34 for the core recursion 10'(2), respectively. The first and second digital output signals 36, 38 from the core recursion 10'(2) provide the first and second digital input signals 32, 34 for the core recursion 10'(3), respectively. The first and second digital output signals 36, 38 from the core recursion 10'(3) provide the first and second digital input signals 32, 34 for the core recursion 10'(4), respectively. The first digital output signal 36 from the core recursion 10'(4) is applied to the input of the first delay element 12 (for example, including a multi-bit register formed by a D-type flip-flop), which is configured to store the (n+3)th value of the first sinusoidal digital output x1, which is further provided from the Q output in feedback to the first digital input signal 32 for the core recursion 10'(1). The second digital output signal 38 from the core recursion 10'(4) is applied to the input of the second delay element 14(4) (e.g., including a multi-bit register formed by a D-type flip-flop), which is configured to store the (n+2)th value of the second sinusoidal digital output x2, which is further provided from the Q output in feedback to the second digital input signal 34 for the core recursion 10'(1). The second digital output signal 38 from the core recursion 10'(3) is applied to the input of the third delay element 14(3) (e.g., including a multi-bit register formed by a D-type flip-flop), which is configured to store the (n+2)th value of the second sinusoidal digital output x2. The second digital output signal 38 from the core recursion 10'(2) is applied to the input of the fourth delay element 14(2) (e.g., including a multi-bit register formed by a D-type flip-flop), which is configured to store the (n+1)th value of the second sinusoidal digital output x2. Finally, the second digital output signal 38 from the core recursion 10'(1) is applied to the input of a fifth delay element 14(1) (e.g., comprising a multi-bit register formed of D-type flip-flops), which is configured to store the (n)th value of the second sinusoidal digital output x2. The D-type flip-flops in the registers for the first to fifth digital delay elements 12, 14' are clocked by a clock frequency f clock The clock signal CK is used for clock control.

[0043] However, if Figure 3The recursive duplication of the core shown introduces a critical path problem. Here, it is noted that the longest path between any Q output of a flip-flop in a delay element and any D input of a flip-flop in a delay element includes four digital multiplier elements and four digital summing elements. Therefore, it is more difficult for network 100 to operate at the desired higher rate to generate digital values ​​of a sine wave (e.g., the network cannot operate efficiently to generate digital values ​​at the same frequency f clock ) generates four times Figure 2 samples per cycle of the clock of network 10').

[0044] To reduce the critical path of network 100, we start with equations C and D, which are the core recursion of network 10':

[0045] x1(n)=x1(n-1)+ψx2(n-1)

[0046] x2(n)=K1*x2(n-1)-ψx1(n-1)

[0047] Let m1 = -ψ and m2 = K1, which leads to:

[0048] x1(n)=x1(n-1)-m1*x2(n-1)Equation 1

[0049] x2(n)=m1*x1(n-1)+m2*x2(n-1)Equation 2

[0050] Now, we calculate the next three samples (x2(n+1), x2(n+2), x2(n+3)) of the sine output based on the current samples x1(n-1), x2(n-1). Let n=n+1, then:

[0051] x2(n+1)=m1(x1(n))+m2(x2(n))

[0052] The multiplication coefficient And the multiplication coefficient m2=2*cos(ω0)-1.

[0053] According to equations 1 and 2 above, then:

[0054] x2(n+1)=m1*(x1(n-1)-m1*x2(n-1))+m2(m2*x2(n-1)+m1*x1(n-1)).

[0055] Simplifying, this becomes:

[0056] x2(n+1)=(m1+m2*m1)x1(n-1)+(m2*m2-m1*m1)x2(n-1).

[0057] Let the multiplication coefficient

[0058] Let the multiplication coefficient m4=m2*m2-m1*m1=2(cos(2ω0)-cos(ω0))+1,

[0059] So:

[0060] x2(n+1)=m3*x1(n-1)+m4*x2(n-1) Equation 3

[0061] A similar process is then used to generate:

[0062] x2(n+2)=m5*x1(n-1)+m6*x2(n-1) Equation 4

[0063] in:

[0064] Multiplication coefficient

[0065] Multiplication coefficient m6 = 2(cos(3ω0)-cos(2ω0)+cos(ω0))-1

[0066] and:

[0067] x2(n+3)=m7*x1(n-1)+m8*x2(n-1)Equation 5

[0068] The multiplication coefficient

[0069] And the multiplication coefficient m8=2(cos(4ω0)-cos(3ω0)+cos(2ω0)-cos(ω0))+1.

[0070] Using a similar process, the next three samples of the sine output (x1(n+1), x1(n+2), x1(n+3) are calculated based on the current samples x1(n-1), x2(n-1) to produce:

[0071] x1(n+3)=m′7*x1(n-1)+m′8*x2(n-1) Equation 6

[0072] The multiplication coefficients are: m′0=1, m′1=-ψ, m′2=K1, and:

[0073] Multiplication coefficient m′3=m′0-m′1*m′1

[0074] Multiplication coefficient m′4=m′0*m′1+m′1*m′2

[0075] Multiplication coefficient m′5=m′3-m′4*m′1

[0076] Multiplication coefficient m'6 = m'3*m'1+m'4*m'2

[0077] The multiplication coefficient m′7=m′5-m′6*m′1, and

[0078] Multiplication coefficient m'8 = m'5*m'1+m'6*m'2

[0079] Equations 1 to 6 can be simply used as Figure 4 The addition, multiplication and delay elements shown in are implemented in digital signal processing using network diagram 200. It is noted that each of equations 1 to 6 shares a common processing operation in the form of x=a*x1(n-1)+b*x2(n-1), where a and b are constants (multiplication coefficients) having the above values. Therefore, for network diagram 200, core process 210 can be replicated multiple times. Core process 210 includes a first digital multiplier element 212, which has: a first input configured to receive a first digital input signal 214 corresponding to a value x1(n-1), and a second input configured to receive a multiplication coefficient a. The output of the first digital multiplier element 212 is provided to a first input of a digital summing element 218. The second digital multiplier element 220 has: a first input configured to receive a second digital input signal 222 corresponding to a value x2(n-1), and a second input configured to receive a multiplication coefficient b. The output of the second digital multiplier element 220 is provided to a second input of the digital summing element 218. The output of the digital summing element 218 provides a digital output signal 224.

[0080] In the first core process 210(1), the multiplication coefficients are a=m1 and b=m2. The digital output signal 224 from the first core process 210(1) is applied to the input of a delay element 230 (e.g., comprising a multi-bit register formed of D-type flip-flops) configured to store the (n)th value of the second sinusoidal digital output x2.

[0081] In the second core process 210(2), the multiplication coefficients are a=m3 and b=m4. The digital output signal 224 from the second core process 210(2) is applied to the input of a delay element 232 (e.g., comprising a multi-bit register formed of D-type flip-flops) configured to store the (n+1)th value of the second sinusoidal digital output x2.

[0082] In the third core process 210(3), the multiplication coefficients are a=m5 and b=m6. The digital output signal 224 from the third core process 210(3) is applied to the input of a delay element 234 (e.g., comprising a multi-bit register formed of D-type flip-flops) configured to store the (n+2)th value of the second sinusoidal digital output x2.

[0083] In the fourth core process 210 (4), the multiplication coefficients are a=m7 and b=m8. The digital output signal 224 from the fourth core process 210 (4) is applied to the input of a delay element 236 (e.g., including a multi-bit register formed by a D-type flip-flop), which is configured to store the (n+3)th value of the second sinusoidal digital output x2, wherein, in feedback, the Q output of the delay element 236 provides a digital signal applied to the input of a delay element 238 (e.g., including a multi-bit register formed by a D-type flip-flop), which is configured to store the (n-1)th value of the second sinusoidal digital output x2. The Q output of the delay element 238 provides the second digital input signal 222.

[0084] In the fifth core process 210(5), the multiplication coefficients are a=m'7 and b=m'8. The digital output signal 224 from the fifth core process 210(5) is applied to the input of a delay element 240 (e.g., comprising a multi-bit register formed by a D-type flip-flop), which is configured to store the (n+3)th value of the first sinusoidal digital output x1, and in feedback the Q output of the delay element 240 provides a digital signal applied to the input of a delay element 242 (e.g., comprising a multi-bit register formed by a D-type flip-flop), which is configured to store the (n-1)th value of the first sinusoidal digital output x1. The Q output of the delay element 242 provides the second digital input signal 214.

[0085] The D-type flip-flops used to form the registers of the digital delay elements 230 to 242 are composed of a clock frequency f clock The clock signal CK is used for clock control.

[0086] The Q outputs of digital delay elements 230 to 236 are applied to the input of multiplexer 250, which acts as a parallel-to-serial converter, producing a digital sine wave output signal 252 as a series of digital values ​​from the (n)th to the (n+3)th digital outputs generated in parallel from sine wave x2. The output data rate of signal 252 at the output of four-to-one multiplexer 250 is the clock frequency f clock The digital sine wave output signal 252 from the multiplexer 250 can be converted into an analog sine wave signal (for comparison, see Figure 1 ). Note also that the digital value of sine wave x2 produces a digital sine wave output signal which can also be converted to an analog signal (the two sine waves have the same frequency but are 90 degrees out of phase with each other).

[0087] Figure 4The advantage of the implementation is that it can be easily expanded by simply adding additional core processes 210, which have inputs connected in parallel with the other core processes. Each added core process requires the calculation of the appropriate multiplication coefficients a and b, and the output of the last core process included is coupled in feedback. As will be appreciated by those skilled in the art, the number of registers (flip-flops) does not increase dramatically with the increase in parallelism due to the increase in throughput.

[0088] A problem with the use of recursive functions such as those implemented with networks 10', 100, 200 is the accumulation of quantization errors with respect to the recursively generated data due to the finite word width. Consider in this regard the example of a multiplication and sum operation performed by each core process (see Figure 4 212 and 218 in the figure are used as examples). If the inputs are both five-digit numbers, then their product doubles the number of bits to ten, and their sum can produce an additional bit as a carry. However, if the delay element formed by the flip-flop is provided with the ability to store data in fewer bits (e.g., five bits) than produced, then the product or sum produced must be converted to five bits in some way. Many techniques for this conversion are known to those skilled in the art (rounding, floor, ceiling, etc.). This conversion process is called quantization, and the difference between the two values ​​is the quantization error. However, with each iteration of the recursive operation, there is an accumulation of quantization errors, and the accuracy of the signal output of the network becomes increasingly lower.

[0089] To address this problem, a refresh circuit 254 is used to periodically refresh the digital values ​​stored in the delay elements 238 and 242 with precise values, and the delay elements 238 and 242 provide the (n-1)th digital values ​​of the sine wave x1 and the sine wave x2. For example, the refresh circuit 254 may include a high-precision sine value generator that operates to generate a set of substitute values ​​256, which includes high-precision values ​​of the recursive data of the (n-1)th digital values ​​of the sine wave x1 and the sine wave x2. Periodically, the generated set of substitute values ​​256 is loaded into the delay elements 238 and 242, and additional recursive calculations will be derived from the newly loaded substitute values ​​256 (rather than the recursive values ​​previously calculated from the delay elements 236 and 240, including the accumulated errors). The rate at which the substitute values ​​256 are loaded into the delay elements 238 and 242 is a fraction of the frequency of the clock signal. For example, the rate may be f clock / M, where M is much greater than 1 and is typically an integer value in the range of hundreds to thousands. Therefore, every M clock cycles, the recursive digital sine wave generator 200 loads the set of replacement values ​​256, which are periodically generated by the high-precision sine value generator of the refresh circuit 254.

[0090] For example, substitution may be accomplished by refreshing and reloading the register formed by delay elements 238 and 242. By periodically updating the recursive data with a high precision substitute value, this operation will effectively eliminate finite precision errors that develop over time in the recursive calculation. The timing of the replacement every M clock cycles is configurable so that the specific sine angle at which the refresh and substitute operations occur is known in advance. A high precision sine value generator within refresh circuit 254 operates to pre-compute the correct (with high precision) value for the recursive data as a substitute value 256 for the specific sine angle that is loaded at the appropriate time so that the generation of the digital sine wave output is not interrupted.

[0091] The high precision sine value generator in the refresh circuit 254 can be implemented using a coordinate rotation digital computer (CORDIC). Those skilled in the art understand that CORDIC implements a hardware efficient iterative method for calculating various elementary functions using rotations. In this case, the elementary function calculated by the CORDIC is a sine wave function. The CORDIC can be used at the same frequency f as the recursive digital sine wave generator 200. clock operation. However, the throughput of the CORDIC is a few cycles less than the recursive digital sine wave generator 200 because many cycles of the clock signal are required to perform each calculation of the substitute value. The CORDIC can be highly hardware optimized because it operates at a slower speed than the recursive digital sine wave generator 200. This easy implementation allows the CORDIC to perform its operations sequentially, and this advantageously enables hardware reuse across iterations while saving occupied circuit area and power consumption.

[0092] The CORDIC of interest operates as a high precision sine angle calculator from which substitute values ​​associated with a particular sine angle of interest are generated. The particular sine angles of interest for which periodic correction operations are to be performed are known in advance to the CORDIC. For example, those angles of interest are selected so as to occur before an unacceptable degradation in the accuracy of the value of the digital sine wave output 252 occurs. During the M clock cycles before the next sine angle of interest occurs, the CORDIC operates to generate the upcoming substitute value associated with the next sine angle of interest. When the sample value n corresponding to the next sine angle of interest is reached, the CORDIC of the high precision sine value generator makes the substitute value available for loading into the delay elements 238 and 242 of the recursive digital sine wave generator 200.

[0093] The digital sine wave generator 200 includes a control circuit 260 that can specify the characteristics of the desired sine wave output to be generated by specifying the values ​​of the multiplication coefficients m1 to m8 and m'7 to m'8 and periodically providing the (n-1)th digital values ​​of the sine wave x1 and sine wave x2 to the delay elements 238 and 242. Appropriate control signals are applied to the refresh circuit 254 to cause the values ​​to be loaded initially (startup) and periodically to perform refreshes. The control circuit 260 tracks the digital sine wave output 252 and instructs the high-precision sine value generator within the refresh circuit 254 to identify the next sine angle of interest based on the value of M so as to pre-calculate a substitute value. At the appropriate time when the sample value n of the generated digital sine wave output 252 corresponding to the sine angle of interest is reached, the control circuit 160 instructs the refresh circuit 254 to cause the loading of the substitute value 256 pre-calculated by the high-precision sine value generator. The next more accurate value of the digital sine wave output 252 is then generated by the recursive digital sine wave generator 200. clock The product of the (n)th to (n+3)th values ​​of the digital sine wave output 252 in response to the clock CK is not interrupted by the process of loading the substitute value.

[0094] It is important to understand that although Figure 2 and Figure 3 Not explicitly shown, but control circuit 260 and refresh circuit 254 are also used.

[0095] Figures 2 to 4 The system may be implemented in any suitable hardware, software, firmware, or a combination thereof without departing from the scope of the present invention.

[0096] The system may include a processor and a memory having computer executable instructions for executing a process that implements recursive sine generation and CORDIC processing operations. The computer executable instructions may also be stored in whole or in part on a computer readable medium separate from the system on which the instructions are executed. The computer readable medium may include any volatile or non-volatile storage medium, such as flash memory, compact disk memory, etc. Although the present invention is described and described in detail in the drawings and the above specification, such description and description are considered to be illustrative or exemplary rather than restrictive; the present invention is not limited to the disclosed embodiments. By studying the drawings, the present disclosure and the appended claims, those skilled in the art can understand and implement other changes to the disclosed embodiments when implementing the claimed invention.

Claims

1. A device comprising: a first multiplier configured to multiply the first input by a first coefficient; a first adder configured to generate a first output from a summation of a second input and an output of the first multiplier; a second multiplier configured to multiply the third input by a second coefficient; a third multiplier configured to multiply the fourth input by a third coefficient; a second adder configured to generate a second output from a sum of an output of the second multiplier and an output of the third multiplier; wherein the second input and the third input are derived from the first output; and Wherein the first input and the fourth input are derived from the second output. The apparatus according to claim 1 , wherein the second coefficient is a negative value of the first coefficient.

3. The apparatus of claim 1, wherein the third coefficient is equal to one minus the square of the first coefficient.

4. The apparatus according to claim 1, further comprising: a first delay element configured to store the first output and generate the second input and the third input; and A second delay element is configured to store the second output and generate the first input and the fourth input. 5 . The apparatus of claim 4 , wherein each of the first delay element and the second delay element is a multi-bit digital register.

6. The apparatus of claim 5, wherein each multi-bit digital register is formed by a D-type flip-flop.

7. The apparatus of claim 6, wherein the D-type flip-flops are clocked by a same clock signal.

8. The apparatus of claim 4, wherein the first delay element and the second delay element store values ​​of the first output and the second output at a rate set by a clock signal, the apparatus further comprising: a sine wave value generator configured to generate substitute values ​​at a second rate that is less than the first rate; and The control circuit is configured to cause the values ​​of the first output and the second output stored in the first delay element and the second delay element to be periodically replaced by the generated replacement value.

9. The apparatus of claim 8, wherein the sine wave value generator comprises a coordinate rotation digital computer (CORDIC) configured to generate the substitute values ​​for certain angles of the desired sine wave.

10. The apparatus of claim 1, wherein the second output is a digital value of a digital sine wave signal.

11. The apparatus of claim 10, wherein the first output is a digital value of another digital sine wave signal having the same frequency as the digital sine wave signal but shifted in phase.

12. An apparatus comprising: Multiple signal processing networks; Each signal processing network includes: a first multiplier configured to multiply the first input by a first coefficient; a first adder configured to generate a first output from a summation of a second input and an output of the first multiplier; a second multiplier configured to multiply the third input by a second coefficient; a third multiplier configured to multiply the fourth input by a third coefficient; a second adder configured to generate a second output from a sum of an output of the second multiplier and an output of the third multiplier; wherein the plurality of signal processing networks are arranged in series, wherein: The first output of one signal processing network in the series is used as the second input and the third input of a subsequent signal processing network in the series; the second output of the one signal processing network in the series being used as the first input and the fourth input of the subsequent signal processing network in the series; The second input and the third input of the first signal processing network in the series are derived from the first output of the last signal processing network in the series; and The first input and the fourth input of the first signal processing network in the series are derived from the second output of the last signal processing network in the series. The apparatus of claim 12 , wherein the second coefficient is a negative value of the first coefficient. The apparatus of claim 12 , wherein the third coefficient is equal to one minus the square of the first coefficient.

15. The apparatus according to claim 12, further comprising: a first delay element configured to store the first output of the last signal processing network in the series and to generate an output that is applied to the second input and the third input of the first signal processing network in the series; as well as A second delay element is configured to store the second output of the last signal processing network in the series and to generate an output that is applied to the first input and the fourth input of the first signal processing network in the series.

16. The apparatus of claim 15, wherein each of the first delay element and the second delay element is a multi-bit digital register.

17. The apparatus of claim 16, wherein each multi-bit digital register is formed by a D-type flip-flop.

18. The apparatus of claim 17, wherein the D-type flip-flops are clocked by a same clock signal.

19. The apparatus of claim 15, wherein the first delay element and the second delay element store values ​​of the first output and the second output at a first rate set by a clock signal, the apparatus further comprising: a sine wave value generator configured to generate substitute values ​​at a second rate less than the first rate; and The control circuit is configured to cause the values ​​of the first output and the second output stored in the first delay element and the second delay element to be periodically replaced by the generated replacement value.

20. The apparatus of claim 19, wherein the sine wave value generator comprises a coordinate rotation digital computer (CORDIC) configured to generate the substitute values ​​for certain angles of a desired sine wave.

21. The apparatus of claim 12, wherein the second output of each signal processing network is a digital value of a digital sine wave signal.

22. The apparatus of claim 21, wherein the first output of each signal processing network is a digital value of another digital sine wave signal having the same frequency as the digital sine wave signal but offset in phase.

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