Built-in self-test repair method for ai accelerator chip pe matrix

Abstract

The application discloses an AI accelerator chip PE matrix built-in self-test repair method, and relates to the technical field of AI accelerator chip circuit structure design. The built-in self-test method generates a scan test excitation by using a scan test generator, transmits and outputs a response through a configurable PE operation unit, judges whether the output response is correct or not by using an output response comparator, and judges the row and column addresses of a faulty PE unit by using a fault PE diagnostic device. The built-in self-repair method replaces and repairs the faulty PE unit by using an RPE redundant operation unit, and distributes the corresponding data bus to the RPE redundant operation unit according to the row and column addresses by activating the data bus and the weight data bus distributor. The application realizes the self-test of the PE operation unit and the self-repair of the faulty PE operation unit with a small additional circuit area ratio, thereby improving the yield of the AI accelerator chip and reducing the chip manufacturing cost.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of AI accelerator chip circuit structure design, in particular to an AI accelerator chip PE matrix built-in self-test repair method. BACKGROUND

[0002] The impulse matrix composed of the multiply-accumulate units can greatly improve the efficiency of the deep learning algorithm and is widely applied to the tensor processor, the neural network processor and other AI accelerator chips. The design technology of the testability and the fault tolerance of the emerging high-performance AI accelerator chips has begun to attract widespread attention.

[0003] Structure diagram of the multiply-accumulate operation unit PE Figure 1 Structure diagram of the multiply-accumulate operation unit PE Figure 2 Each PE operation unit includes a weight register, a data register and an accumulation register, and the weight and the activation data are loaded into the weight register and the data register in each row and each column of the PE operation unit in the form of serial scanning. The weight and the activation data latched by the register are multiplied by a multiplier, and the multiplication result and the accumulation result latched by the accumulation register in the previous PE operation unit are added by an adder, and the addition result is saved in the accumulation register and transmitted to the next PE operation unit. The final result of the multiply-accumulate operation of each column of the PE operation unit is saved to the accumulation result memory. When tested, the accumulation register needs to be configured into a shift register through a two-way selector, and the output response of the multiplier and the adder can be serially derived from the scan chain circuit composed of the shift register for comparison.

[0004] However, since each PE operation unit contains a plurality of bit registers, the accumulation register needs to be configured into a larger scan register, that is, a two-way selector needs to be added to each bit register to form a scan chain, and the structure diagram is as follows Figure 2 This will greatly increase the area ratio of the entire impulse matrix module, eventually leading to a significant increase in the area of the entire AI chip. The current test method can only diagnose the faulty PE operation unit through external software, and the faulty unit diagnosed can only be shielded and discarded. If the number of discarded PE operation units is too large or the weight is too large, the operation accuracy of the AI chip will be significantly reduced, the AI chip will become a waste chip, the yield of the chip will be reduced, and the manufacturing cost of the chip will be increased. SUMMARY

[0005] In order to overcome the problems of the prior art, such as the large area ratio of the test circuit module in the circuit design, the significant increase of the area of the whole AI accelerator chip, the need of diagnosing the faulty PE operation unit through external software, the decrease of the chip yield rate caused by the faulty PE operation unit, and the increase of the chip manufacturing cost, the application provides an AI accelerator chip PE matrix built-in self-test repair method, which can effectively reduce the large area ratio of the circuit module, thereby reducing the area of the AI accelerator chip, without the need of diagnosing the faulty PE operation unit through external software, improving the chip yield rate, and reducing the chip manufacturing cost.

[0006] In order to achieve the object of the application, the application adopts the following technical solutions:

[0007] One of the objects of the application is:

[0008] An AI accelerator chip PE matrix built-in self-test method, the method comprising the following steps:

[0009] S11: a scan test generator imports scan test excitation serial data into PE weight registers and PE activation registers in a configurable PE operation unit;

[0010] S12: after the test excitation is subjected to multiplication and addition operation, the output response is latched to the PE accumulation register in the configurable PE operation unit;

[0011] S13: the PE accumulation register of the configurable PE operation unit is configured as a scan register, and the output response is serially exported;

[0012] S14: an output response comparator compares the output response with the stored correct response, if the output response is consistent with the stored correct response, it is checked whether all test excitation serial data have been applied, if not, it returns to step S11, if yes, the test is ended; if the output response is not consistent with the stored correct response, step S15 is executed;

[0013] S15: a faulty PE diagnostic device diagnoses the faulty configurable PE operation unit according to the comparison result of the output response comparator, saves the address information of the faulty PE operation unit to a faulty PE address storage, and checks whether all test excitations have been applied, if not, it returns to step S11, if yes, the test is ended.

[0014] According to the technical solution, the AND gate circuit at the output end of the output response comparator can be controlled by an external signal, and whether the lowest bits of the output response are included in the comparison range is determined according to the operation precision requirement of the AI chip. If the operation precision requirement is not high, the fault that the lowest bits of the output response are wrong can be ignored, and at this time, the AND gate circuit can shield the comparison result of the output response of the bits to ensure that the PE operation matrix passes the test.

[0015] The second object of the present application is to:

[0016] A built-in self-repairing method of an AI accelerator chip PE matrix, the method comprising the following steps:

[0017] S21: reading the address information of the faulty configurable PE operation unit row from the faulty PE address memory;

[0018] S22: checking whether the RPE redundant operation unit in the row is unused according to the column address information, if unused, assigning the corresponding active data bus to the RPE redundant operation unit and executing step S25, if used, executing step S23;

[0019] S23: checking whether the RPE redundant operation unit in the column is unused according to the row address information, if unused, assigning the corresponding weight data bus to the RPE redundant operation unit and executing step S25, if used, executing step S24;

[0020] S24: checking whether there is an additional RPE redundant operation unit row, if yes, executing step S22, otherwise executing step S25;

[0021] S25: checking whether all the faulty configurable PE operation unit addresses are traversed, if yes, executing step S26, otherwise executing step S21;

[0022] S26: shielding all the faulty configurable PE operation units by configuring the AND gate circuit through the register;

[0023] S27: preloading the weight data stream of the RPE redundant operation unit, using the counter in the RPE redundant operation unit to latch the corresponding weight data to the RPE weight register of the RPE redundant operation unit according to the column address, and ending the repair.

[0024] According to the technical solution, in the actual operation process of the repaired PE unit matrix, the RPE operation units participating in the replacement repair in the RPE unit row and the RPE unit column and other normal PE operation units perform multiplication operation synchronously, but the RPE units in the RPE unit column latch the operation results in the RPE units and continuously perform self-accumulation with the multiplication results generated in the next clock cycle, that is, the multiplication and accumulation results in the whole operation period are always stored in a single RPE unit.

[0025] After the operation period is completed, the operation results of each RPE in the RPE unit column and the corresponding column addresses are read in a serial scanning manner by the RPE operation result scanning accumulators, the RPE unit operation results with the same column addresses as the RPE operation result scanning accumulators are continuously accumulated, and the final accumulation results are distributed to the accumulators below the PE operation unit matrix to complete the final accumulation operation.

[0026] For the RPE unit row and the RPE unit column, if the corresponding RPE units in the current RPE unit row and the RPE unit column have been used, the RPE units in the remaining RPE unit row or the RPE unit column can be called to replace, so that the repair probability of the chip PE matrix can be greatly improved on the premise of slightly increasing the circuit area.

[0027] After the test and repair are completed, the number of faulty PEs and the row and column address data thereof can also be exported to the external test equipment software through the scan chain, for chip design and manufacturing process maturity analysis and optimization, to determine the optimized RPE unit number and row and column arrangement.

[0028] Compared with the prior art, the beneficial effects of the present application are that:

[0029] The present application provides a built-in self-test repair circuit for an AI accelerator chip PE matrix, which comprises a scan test generator, a configurable PE operation unit, an output response comparator, a faulty PE diagnostic device in the built-in self-test circuit, and an activation data bus distributor and an RPE redundant operation unit in the built-in self-repair circuit, and is combined with a test repair controller and an accumulation memory, which can effectively reduce the area occupancy of the circuit module, thereby reducing the area of the AI acceleration chip, and without the need for external software to diagnose the faulty PE operation unit, the circuit can be self-tested through the built-in self-test circuit, and the circuit can be self-repaired through the built-in self-repair circuit, the number of discarded PE operation units in the test process is reduced, the operation accuracy of the PE operation unit is improved, and the yield of the chip is improved, thereby reducing the manufacturing cost of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 It is a schematic diagram of the PE pulsation matrix structure inside the existing AI accelerator chip.

[0031] Figure 2 A circuit structure schematic diagram of a PE operation unit under the existing test is provided.

[0032] Figure 3 A step flow chart for implementing built-in self-test is provided for the embodiment of the present application.

[0033] Figure 4 A structure schematic diagram of a built-in self-test repair circuit of an AI accelerator chip PE matrix is provided for the embodiment of the present application.

[0034] Figure 5 A circuit structure schematic diagram of a configurable PE operation unit is provided for the embodiment of the present application.

[0035] Figure 6 A step flow chart for implementing built-in self-repair is provided for the embodiment of the present application.

[0036] Figure 7 A circuit structure schematic diagram of an RPE redundant operation unit is provided for the embodiment of the present application.

[0037] Figure 8 An RPE unit arrangement schematic diagram for a PE operation unit being a 64x64 matrix is provided for the embodiment of the present application.

[0038] Figure 9 An RPE unit arrangement schematic diagram for a PE operation unit being a 128x128 matrix is provided for the embodiment of the present application.

[0039] Figure 10 An RPE unit arrangement schematic diagram for a PE operation unit being a 256x256 matrix is provided for the embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to facilitate the understanding of the present application, a more comprehensive description of the present application will be given below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0041] It should be noted that when an element is referred to as being "fixed" to another element, it can be directly on the other element or there can be a middle element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or there can be a middle element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] Embodiment one:

[0044] The embodiment provides a built-in self-test method for an AI accelerator chip PE matrix, referring to Figure 3 , the method comprises the following steps:

[0045] S11: The scan test generator imports the scan test excitation serial data into the PE weight register and the PE activation register in the configurable PE operation unit; specifically: the scan test excitation serial is imported into the weight and activation data register in the PE operation unit, since the activation data register in the same row PE operation unit and the weight data register in the same column PE operation unit naturally form a complete scan chain circuit, the scan test generator reads the saved test excitation, and transmits the test excitation to the input end of the multiplier and the adder of each PE operation unit in the form of serial shift through the two scan chain circuits;

[0046] S12: The output response after the test excitation is subjected to multiplication and addition operation is latched to the PE accumulation register in the configurable PE operation unit;

[0047] S13: The PE accumulation register of the configurable PE operation unit is configured as a scan register, and the output response is transmitted to the output response comparator through the serial shift of the scan chain register composed of the PE accumulation registers in the same column of configurable PE operation units;

[0048] S14: The output response comparator compares the output response with the stored correct response, if the output response is consistent with the stored correct response, it is checked whether all test excitation serial data has been applied, if not, it returns to step S11, if yes, the test is ended; if the output response is not consistent with the stored correct response, step S15 is executed;

[0049] S15: The faulty PE diagnostic apparatus diagnoses the row and column address of the configurable PE operation unit with faults according to the comparison result of the output response comparator, and saves the address information to the faulty PE address storage, checks whether all test excitations have been applied, if not, it returns to step S11, if yes, the test is ended;

[0050] In this embodiment, an AND gate circuit is inserted between the multiplier and the adder in the PE operation unit, becoming a configurable PE operation unit, the circuit structure of which is shown in Figure 5 Each bit output of the multiplier is connected to one input of each AND gate circuit, and the output of each AND gate circuit is connected to each input of the adder. The other input of the AND gate circuit can be controlled by the zero setting register or the scan test control signal.

[0051] When the zero setting register or the scan test control signal is set to 0, the output of the AND gate circuit is 0, and the result of the multiplier is set to 0. At this time, the result output by the previous PE unit is not changed after being added with 0, so the result latched by the accumulation register follows the output of the previous PE unit, thereby realizing the scan shift function of the register.

[0052] When the zero setting control register and the scan test control signal are 1, the AND gate circuit can be regarded as transparent, and the operation function of the PE unit is unchanged.

[0053] As a preferred embodiment, referring to Figure 4 The output of the scan test generator is connected to the input of the configurable PE operation unit, the output of the configurable PE operation unit is connected to the input of the output response comparator, and the output of the output response comparator is connected to the input of the faulty PE diagnostic device.

[0054] The input of the faulty PE address memory is connected to the output of the faulty PE diagnostic device;

[0055] The output of the test repair controller is connected to the input of the scan test generator, the output response comparator, the faulty PE diagnostic device, the test excitation memory, and the faulty PE address memory, respectively.

[0056] As a preferred embodiment, referring to Figure 4 It further includes a two-way selector, the data input of the two-way selector is connected to the output of the scan test generator, the control input of the two-way selector is connected to the output of the test repair controller, and the output of the two-way selector is connected to the data input of the configurable PE operation unit in the first column of the PE matrix.

[0057] As a preferred embodiment, referring to Figure 5The configurable PE operation unit is characterized in that the PE operation unit comprises a PE weight register, a PE data register, a PE zero register, a PE accumulation register, a PE multiplier, a PE adder and a PE AND gate circuit, the input end of the PE multiplier is connected with the output end of the PE weight register and the output end of the PE data register, the input end of the PE AND gate circuit is connected with the output end of the PE data register, the output end of the PE multiplier and the output end of the PE zero register, the output end of the PE AND gate circuit is connected with the input end of the PE adder, and the output end of the PE adder is connected with the input end of the PE accumulation register.

[0058] In the embodiment, the AND gate circuit added at the output end of the lowest bits of the output response comparator can be controlled by an external signal, and whether the lowest bits of the output response are included in the comparison range is determined according to the operation precision requirement of the AI chip. If the operation precision requirement is not high, the fault of the lowest bits of the output response can be ignored, and at this time, the AND gate circuit can shield the comparison result of the output response of the bits to ensure that the PE operation matrix passes the test.

[0059] Embodiment two:

[0060] In the embodiment, a plurality of redundant RPE operation units that can be used to replace the faulty PE operation unit are arranged, the structure of the row and column of the redundant RPE operation unit is arranged around the configurable PE operation unit matrix, and a plurality of RPE redundant unit rows and a plurality of RPE redundant unit columns are formed. The embodiment provides a built-in self-repairing method for the PE matrix of the AI accelerator chip, as shown in Figure 6 , comprising the following steps:

[0061] S21: reading the row and column address information of the configurable PE operation unit with faults from the fault PE address memory;

[0062] S22: checking whether the RPE redundant operation unit in the RPE redundant operation unit row is unused according to the column address information, if the RPE redundant operation unit is unused, the corresponding active data bus is allocated to the RPE redundant operation unit and step S25 is executed, if the RPE redundant operation unit is used, step S23 is executed;

[0063] S23: Check whether the RPE redundant operation unit in the row according to the row address information is unused, if not, allocate the corresponding weight data bus to the RPE redundant operation unit and execute step S25, if yes, execute step S24; (Specifically: check whether the RPE redundant operation unit in the row according to the row address information is unused, if the RPE unit is not used, the weight data bus distributor allocates the weight data bus corresponding to the column to the RPE unit according to the column address of the faulty PE, to ensure that the weight data stream obtained by the RPE unit is the same as the weight data stream obtained by the faulty PE unit, and then execute S25, if the RPE redundant operation unit is used, execute S24);

[0064] S24: Check whether there is an additional RPE redundant operation unit row, if yes, execute step S22, otherwise execute step S25;

[0065] S25: Check whether all faulty configurable PE operation unit addresses are traversed, if yes, execute step S26, otherwise execute step S21;

[0066] S26: Mask all faulty configurable PE operation units by configuring the AND gate circuit through the register; (Specifically: set the zero register of the faulty PE unit to 0 by configuring the AND gate circuit through the register, at this time the output of the AND gate circuit is 0, the multiplier result is masked to 0, and the adder of the faulty PE unit directly transmits the operation result of the previous PE unit connected in series to the next PE unit connected in series, so that the faulty PE operation unit is shielded and does not participate in the actual operation.);

[0067] S27: RPE redundant operation unit preloads weight data stream, uses the counter in the RPE redundant operation unit to lock the corresponding weight data to the weight register of the RPE redundant operation unit according to the column address, and the repair is completed. (Specifically: serially preloads the weight data of the RPE unit row and the RPE unit column, according to the column address information of the faulty PE locked by each RPE unit, uses the counter in the RPE unit to lock the weight data corresponding to the column address to the weight register of the RPE, to ensure that the weight data used by the RPE unit is the same as the weight data of the faulty PE unit, and the repair process is completed.)

[0068] The repaired PE unit matrix performs multiplication operation in the process of actual operation, the RPE unit row and the RPE unit column which participate in replacement repair and other normal PE operation units perform multiplication operation synchronously, but the RPE unit in the RPE unit column latches the operation result in the RPE unit and continuously performs self-accumulation with the multiplication result generated in the next clock cycle, that is, the multiplication and accumulation result in the whole operation period is always stored in a single RPE unit. After the operation period is completed, the RPE operation result scanning accumulator reads the operation result of each RPE in the RPE unit column and the corresponding column address in a serial scanning manner, continuously accumulates the RPE unit operation result with the same RPE operation result scanning accumulator column address, and distributes the final accumulation result to the accumulator below the PE operation unit matrix to complete the final accumulation operation.

[0069] For multiple RPE unit rows and RPE unit columns, if the corresponding RPE unit in the current RPE unit row and RPE unit column has been used, the RPE unit in the remaining RPE unit row or RPE unit column can be called to replace it, so that the repair probability of the chip PE matrix can be greatly improved under the premise of slightly increasing the circuit area.

[0070] The RPE redundant operation unit adopted also contains a counter circuit compared with the configurable PE operation unit, which counts according to the serial import of the weight data stream, and locks the corresponding weight data in the weight register according to the column address information, so as to ensure that the RPE and the replaced faulty PE have the same weight data. There is also a two-input AND gate in the RPE unit to support the scan chain circuit configuration of the accumulation register.

[0071] As a preferred embodiment, refer to Figure 4 , including weight FIFO memory, test repair controller, accumulation memory, activation data bus distributor, weight data bus distributor, RPE redundant operation unit row and RPE redundant operation unit column;

[0072] The output end of the fault PE address memory is connected with the address input end of the activation data bus distributor and the weight data bus distributor respectively; the output end of the weight FIFO memory is connected with the weight data input end of the RPE unit in the RPE redundant operation unit row, the output end of the activation data bus distributor is connected with the activation data input end of the RPE unit in the RPE redundant operation unit row, the accumulation output end of the RPE unit in the RPE redundant operation unit row is connected with the accumulation input end of the configurable PE operation unit in the first row of the PE matrix respectively, the accumulation output end of the configurable PE operation unit in the last row of the PE matrix is connected with the input end of the accumulation memory; the output end of the weight data bus distributor is connected with the weight data input end of the RPE redundant operation unit in the RPE redundant operation unit column; the output end of the test repair controller is connected with the input end of the fault PE address memory, the activation data bus distributor and the weight data bus distributor respectively.

[0073] As a preferred embodiment, refer to Figure 4 The RPE operation result scanning accumulator is further connected with the data output end of the RPE unit in the RPE redundant operation unit column and the output end of the test repair controller respectively, and the output end of the RPE operation result scanning accumulator is connected with the input end of the accumulation memory.

[0074] As a preferred embodiment, refer to Figure 4 The adder, the two-way selector and the activation data memory are further included, the input end of the adder is connected with the output end of the configurable PE operation unit in the last row of the PE matrix and the output end of the RPE operation result scanning accumulator respectively, the output end of the adder is connected with the input end of the accumulation memory;

[0075] The data input end of the two-way selector is connected with the output end of the activation data memory, the control input end of the two-way selector is connected with the output end of the test repair controller, and the output end of the two-way selector is connected with the data input end of the configurable PE operation unit in the first column of the PE matrix;

[0076] The input end of the activation data memory is connected with the output end of the test repair controller.

[0077] As a preferred embodiment, refer to Figure 7The RPE redundant operation unit comprises an RPE weight counter, an RPE weight register, an RPE data register, an RPE multiplier, an RPE AND gate circuit, an RPE adder and an RPE accumulation register. The output end of the counter is connected with the input end of the RPE weight register. The input ends of the RPE multiplier are connected with the output ends of the RPE weight register and the RPE data register respectively. The output end of the RPE multiplier is connected with the input end of the RPE AND gate circuit. The output end of the RPE AND gate circuit is connected with the input end of the RPE adder. The output end of the RPE adder is connected with the input end of the RPE accumulation register.

[0078] In the repair mode, the weight data input end of the RPE unit in the RPE operation unit row is connected with the weight FIFO memory, and the activation data input end of the RPE unit is connected with the activation data bus distributor. The activation data bus distributor distributes the corresponding activation data bus from the activation data buffer to the RPE unit according to the row address information of the faulty PE. The activation data input end of the RPE operation unit in the RPE operation unit column is connected with the activation data output end of the PE operation unit in the rightmost PE operation unit column of the PE operation unit matrix, and the weight data input end of the RPE operation unit is connected with the weight data bus distributor. The weight data bus distributor distributes the corresponding weight bus from the weight FIFO memory to the RPE operation unit according to the column address information of the faulty PE operation unit. The accumulator output end of the RPE unit in the RPE redundant operation unit column is connected with the input end of the column RPE operation result scan accumulator, the output end of the RPE operation result scan accumulator is connected with the adder above the accumulation memory, and the output end of the adder is connected with the data input end of the accumulation memory.

[0079] In the repair mode, the weight data input end of the RPE unit in the RPE operation unit row is connected with the weight FIFO memory, and the activation data input end of the RPE unit is connected with the activation data bus distributor. The activation data bus distributor distributes the corresponding activation data bus from the activation data buffer to the RPE unit according to the row address information of the faulty PE. The activation data input end of the RPE operation unit in the RPE operation unit column is connected with the activation data output end of the PE operation unit in the rightmost PE operation unit column of the PE operation unit matrix, and the weight data input end of the RPE operation unit is connected with the weight data bus distributor. The weight data bus distributor distributes the corresponding weight bus from the weight FIFO memory to the RPE operation unit according to the column address information of the faulty PE operation unit. The accumulator output end of the RPE unit in the RPE redundant operation unit column is connected with the input end of the column RPE operation result scan accumulator, the output end of the RPE operation result scan accumulator is connected with the adder above the accumulation memory, and the output end of the adder is connected with the data input end of the accumulation memory.

[0080] Embodiment three:

[0081] The embodiment is directed to embodiments one and two, and provides built-in self-test method and built-in self-repair method of AI accelerator chip PE matrix based on built-in self-test and built-in self-repair of AI accelerator chip PE matrix.

[0082] As a preferred embodiment, refer to Figure 5 and Figure 8 , the 64x64 matrix composed of PE operation units is arranged with two rows of RPE redundant units at the upper part of the matrix and one column of RPE redundant units at the right side of the matrix.

[0083] Refer to Figure 6 , the RPE counter is used to lock the corresponding weight data in the weight register according to the column address information, so as to ensure that the RPE and the replaced faulty PE have the same weight data. There is also a two-input AND gate in the RPE unit to support the scan chain circuit configuration of the accumulation register.

[0084] The RPE operation unit in the same column as the faulty PE operation unit in the first row of RPE redundant operation units is selected for replacement, and the corresponding activation data bus is distributed to the RPE operation unit using the activation data bus distributor.

[0085] If the RPE operation unit has been used, the RPE operation unit in the same row as the faulty PE operation unit in the RPE operation unit column is selected for replacement, and the corresponding weight data bus is distributed to the RPE unit using the weight data bus distributor. Meta If the RPE unit has also been used, the RPE operation unit in the second row of RPE operation units is continuously selected for replacement and repair.

[0086] Monte Carlo simulation is used to verify the actual repair effect of the embodiment. Assuming that each PE operation unit has a certain probability of failure, 10000 64x64 PE matrices composed of such PE units are randomly generated, and the probability of complete repair of the PE unit matrix with the addition of two rows and one column of RPE units under different failure probabilities is verified.

[0087] The simulation results are shown in Table 1. It can be seen that the configuration of two rows and one column of RPE operation units has a repair rate of 100% when the failure rate is 0.5% or less, and the repair rate can still reach 97.3% when the failure rate is 1%.

[0088] Table 1:

[0089]

[0090] As a preferred embodiment, refer to

[0091] Figure 9 ​For 128x128 PE matrix, two RPE operation unit rows and two RPE operation unit columns are arranged to improve the repair rate.

[0092] Due to the addition of one RPE operation unit column, the repair process adds the operation step of selecting RPE operation units from the second RPE operation unit column for replacement repair.

[0093] Monte Carlo simulation is performed on the repair result, and the simulation result is shown in Table 2. It can be seen that the configuration of two rows and two columns of RPE units still achieves 100% repair rate at a fault rate of 0.4% and below, and still achieves 93.2% repair rate at a high fault rate of 0.8%.

[0094] Table 2:

[0095]

[0096] As a preferred embodiment, refer to Figure 10 For 256x256 PE operation unit matrix, four RPE operation unit rows and two RPE operation unit columns are arranged.

[0097] Due to the addition of two RPE unit rows and one RPE unit column, the repair process adds the operation step of selecting RPE units from the second RPE unit column, the third and fourth RPE unit rows for replacement repair.

[0098] The Monte Carlo simulation result of this configuration is shown in Table 3. It can be seen that even for a super large PE operation unit matrix of 256x256, when the fault rate is 0.6% and below, the repair rate still reaches 100%, when the fault rate is 0.8%, the repair rate is 97.4%, and at a high fault rate of 1%, the repair rate still reaches 61.5%. If the fault rate continues to increase, the repair rate will exponentially decay. At this time, to further improve the repair rate, one more RPE unit column can be added.

[0099] Table 3:

[0100]

[0101] The invention adds RPE redundant operation units and other logic circuits and on-chip memories for testing and repair, which slightly increases the area of the entire PE operation unit matrix circuit.

[0102] The RTL design of each circuit structure is logically synthesized by using the synthesis tool Design Compiler of Synopsys, and the circuit area analysis result is shown in Table 4 and Table 5.

[0103] Table 4:

[0104]

[0105] Table 4 is the area increment of the PE matrix of the existing test technology relative to the area of the PE matrix without adding the test technology. It can be seen that the area increment of the existing scan chain test technology using a two-way selector is 5.24%.

[0106] Table 5:

[0107]

[0108] Table 5 is the area increment of each different circuit structure of the present application relative to the area of the PE matrix without adding the test technology. The area increment of the configurable PE unit circuit using an AND gate circuit is only 0.52%.

[0109] Table 5 shows that for the above three different PE matrices, the area increment caused by adding different numbers of RPE redundant operation unit rows and columns, assuming that a single RPE operation unit has an area similar to that of a PE operation unit, the RPE redundant operation unit area increment of Embodiment 1 is 4.68%, the RPE redundant operation unit area increment of Embodiment 2 is 2.47%, and the RPE redundant operation unit area increment of Embodiment 3 is 2.34%. It can be seen that as the size of the PE matrix increases, the RPE redundant operation unit area increment ratio gradually decreases.

[0110] It can also be seen from Table 5 that the area increment of the built-in self-test circuit is very small, but because the weight data bus distributor and the activation data bus distributor in the built-in self-repair circuit occupy a large area, the area increment of the built-in self-repair circuit is relatively large. Perhaps the area ratio of the built-in self-repair circuit can be further optimized to reduce the area ratio of the built-in self-repair circuit.

[0111] It should be noted that this area ratio is only relative to the PE matrix circuit area without adding the test technology. Relative to the entire AI chip area, the PE matrix circuit area only accounts for about 30-40%. Therefore, the total area of the present application scheme relative to the entire AI chip area generally does not exceed 5%. The yield of the AI chip using the present application technology is far more than 5%.

[0112] The above is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent flow transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A built-in self-test method for the PE matrix of an AI accelerator chip, characterized in that, The method includes the following steps: S11: The scan test generator imports the serial test stimulus data stored in the test stimulus memory into the PE weight register and PE activation register in the configurable PE operation unit; S12: Latch the output response after the test stimulus is multiplied and added to the PE accumulator register in the configurable PE arithmetic unit; S13: Configure the PE accumulator register of the configurable PE operation unit as a scan register and serially export the output response; S14: The output response comparator compares the output response with the stored correct response. If the output response matches the stored correct response, it checks whether all test stimulus serial data has been applied. If not, it feeds back to step S11. If completed, the test ends. If the output response does not match the stored correct response, it executes step S15. S15: The fault PE diagnostic unit diagnoses the row and column address of the faulty configurable PE operation unit based on the comparison result of the output response comparator, saves the address information to the faulty PE address memory, and checks whether all test stimuli have been applied. If not, it returns to step S11; if completed, the test ends.

2. The built-in self-test method for the PE matrix of an AI accelerator chip according to claim 1, characterized in that, The output of the scan test generator is connected to the input of the configurable PE operation unit located in the first row of the PE matrix, the output of the configurable PE operation unit located in the last row of the PE matrix is ​​connected to the input of the output response comparator, and the output of the output response comparator is connected to the input of the fault PE diagnostic device.

3. The built-in self-test method for the PE matrix of an AI accelerator chip according to claim 1, characterized in that, It includes a fault PE address memory and a test repair controller. The output of the test stimulus memory is connected to the input of the scan test generator, and the output of the scan test generator is connected to the input of the configurable PE operation unit. The input terminal of the fault PE address memory is connected to the output terminal of the fault PE diagnostic tool; The output of the test and repair controller is connected to the input of the scan test generator, the output response comparator, the fault PE diagnostic unit, the test stimulus memory, and the fault PE address memory, respectively.

4. The built-in self-test method for the PE matrix of an AI accelerator chip according to claim 3, characterized in that, It also includes a two-way selector, the data input terminal of which is connected to the output terminal of the scan test generator, the control input terminal of which is connected to the output terminal of the test repair controller, and the output terminal of which is connected to the data input terminal of the configurable PE operation unit in the first column of the PE matrix.

5. The built-in self-test method for the PE matrix of an AI accelerator chip according to any one of claims 1-4, characterized in that, The configurable PE operation unit includes a PE weight register, a PE data register, a zeroing register, a PE accumulator register, a PE multiplier, a PE adder, and a PE AND gate. The input of the PE multiplier is connected to the output of the PE weight register and the output of the PE data register. The input of the PE AND gate is connected to the output of the PE data register, the output of the PE multiplier, and the output of the zeroing register. The output of the PE AND gate is connected to the input of the PE adder, and the output of the PE adder is connected to the input of the PE accumulator register.

6. A built-in self-healing method for the PE matrix of an AI accelerator chip, characterized in that, The method includes the following steps: S21: Read the row and column address information of the faulty configurable PE operation unit from the faulty PE address memory; S22: Check whether the RPE redundant operation unit in the column of the RPE redundant operation unit row is unused according to the column address information. If it is unused, allocate the corresponding active data bus to the RPE redundant operation unit and execute step S25. If it has been used, execute step S23. S23: Check whether the RPE redundant operation unit in the row of the RPE redundant operation unit column is unused according to the row address information. If it is unused, allocate the corresponding weight data bus to the RPE redundant operation unit and execute step S25. If it has been used, execute step S24. S24: Check if there are any additional RPE redundant operation unit rows. If they exist, proceed to step S22; otherwise, proceed to step S25. S25: Check if all configurable PE operation unit addresses with faults have been traversed. If yes, proceed to step S26; otherwise, proceed to step S21. S26: By configuring the AND gate circuit through the register, all configurable PE operation units with faults are shielded; S27: The RPE redundancy operation unit preloads the weight data stream, uses the counter in the RPE redundancy operation unit to latch the corresponding weight data into the RPE weight register of the RPE redundancy operation unit according to the column address, and the repair ends.

7. The built-in self-healing method for the PE matrix of an AI accelerator chip according to claim 6, characterized in that, It includes a weighted FIFO memory, a test and repair controller, an accumulation memory, an activation data bus distributor, a weighted data bus distributor, and rows and columns of RPE redundant operation units; The output of the fault PE address memory is connected to the address input of the activation data bus allocator and the weight data bus allocator, respectively; the output of the weight FIFO memory is connected to the weight data input of the RPE unit in the RPE redundancy operation unit row; the output of the activation data bus allocator is connected to the activation data input of the RPE unit in the RPE redundancy operation unit row; the accumulation output of the RPE unit in the RPE redundancy operation unit row is connected to the accumulation input of the configurable PE operation unit located in the first row of the PE matrix; the accumulation output of the configurable PE operation unit located in the last row of the PE matrix is ​​connected to the input of the accumulation memory; the output of the weight data bus allocator is connected to the weight data input of the RPE redundancy operation unit in the RPE redundancy operation unit column; the output of the test repair controller is connected to the input of the fault PE address memory, the activation data bus allocator, and the weight data bus allocator, respectively.

8. The built-in self-healing method for the PE matrix of an AI accelerator chip according to claim 7, characterized in that, It also includes an RPE operation result scanning accumulator, the input of which is connected to the data output of the RPE unit in the RPE redundant operation unit column and the output of the test and repair controller, respectively, and the output of which is connected to the input of the accumulator memory.

9. The built-in self-healing method for the PE matrix of an AI accelerator chip according to claim 8, characterized in that, It also includes an adder, a two-way selector, and an active data memory. The input of the adder is connected to the output of the configurable PE operation unit and the output of the RPE operation result scanning accumulator, respectively. The output of the adder is connected to the input of the accumulator memory. The data input terminal of the two-way selector is connected to the output terminal of the activated data memory, the control input terminal of the two-way selector is connected to the output terminal of the test and repair controller, and the output terminal of the two-way selector is connected to the data input terminal of the configurable PE operation unit in the first column of the PE matrix. The input terminal of the activation data storage is connected to the output terminal of the test and repair controller.

10. The built-in self-healing method for the PE matrix of an AI accelerator chip according to any one of claims 6-9, characterized in that, The RPE redundancy operation unit includes an RPE weight counter, an RPE weight register, an RPE data register, an RPE multiplier, an RPE AND gate, an RPE adder, and an RPE accumulator register. The output of the RPE weight counter is connected to the input of the RPE weight register. The input of the RPE multiplier is connected to the output of the RPE weight register and the output of the RPE data register, respectively. The output of the RPE multiplier is connected to the input of the RPE AND gate. The output of the RPE AND gate is connected to the input of the RPE adder. The output of the RPE adder is connected to the input of the RPE accumulator register.

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