Field programmable gate array (FPGA) test method for multi-chip shared single input / output (IO) port of single-bus temperature sensor
The FPGA testing method for multiple single-bus temperature sensors sharing a single IO port addresses the challenge of limited FPGA resources by allowing simultaneous temperature measurement through a unique address algorithm, reducing hardware changes and costs.
Patent Information
- Application Number
- CN202411278888.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-12
- Publication Date
- 2025-01-03
AI Technical Summary
In modern electronic systems, particularly in aviation and aerospace, the limited FPGA IO port resources are strained when multiple temperature sensors need to be measured at different locations, necessitating additional hardware changes to accommodate multiple sensors.
An FPGA testing method that allows multiple single-bus temperature sensors to share a single IO port by using a specific algorithm to identify and communicate with each sensor individually, utilizing a unique 64-bit ROM-encoded address and a wired AND function to manage conflicts, enabling simultaneous temperature measurement without additional hardware.
This method enables simultaneous temperature measurement of multiple sensors using a single IO port, requiring only software upgrades, thus reducing hardware modifications and costs, and maintaining a short development cycle.
Smart Images
Figure CN119248689A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of temperature measurement of temperature sensors, and in particular relates to an FPGA testing method for multiple single-bus temperature sensors sharing a single IO port. Background Art
[0002] In modern electronic systems, temperature sensors have always been a very important component, especially in the hardware design and system operation process, their role is increasingly valued. Figure 1 The single bus temperature sensor shown in (a) is a digital temperature sensor. It has been widely used in various IoT and embedded systems due to its high accuracy, small size, low power consumption and simple required circuits. This temperature sensor uses a control bus to realize command input and data output, with a high accuracy of ±0.5℃ and a wide range from -55℃ to +125℃. It is easy to use, with only power supply, ground and a data input and output port. It only needs to control the data input and output ports through MCU or FPGA to achieve temperature measurement.
[0003] In existing test systems, one IO port is often used to control a temperature sensor, and each temperature sensor's input and output ports need to be connected to a pull-up resistor. This has the following drawbacks in modern aviation or aerospace electronic systems: FPGA IO port resources are precious, but temperature values need to be measured at multiple locations, that is, multiple temperature sensors need to be added for measurement with minimal hardware changes. Summary of the invention
[0004] The purpose of the present invention is to provide an FPGA testing method for multiple single-bus temperature sensors sharing a single IO port, using FPGA to realize one IO port to simultaneously control multiple temperature sensors and measure the temperature at different positions.
[0005] In order to solve the above technical problems, the present invention provides an FPGA testing method for multiple single-bus temperature sensors sharing a single IO port, comprising the following steps:
[0006] Step 1: Start and initialize the temperature sensor and ensure that the temperature sensor is connected to the single bus;
[0007] Step 2: Send a search ROM code address instruction. If there are different ROM code addresses on the single bus, the number of temperature sensors will increase by 1, and N different ROM code addresses will be stored in the corresponding registers.
[0008] Step 3: Send the matching ROM code address instruction and temperature conversion instruction to make the corresponding temperature sensor respond and start converting the temperature;
[0009] Step 4: Wait for 1 second for the temperature conversion to complete, send a temperature reading command, read the digital temperature data and convert it into a temperature value;
[0010] Step 5: Send the current ROM encoding address and converted temperature value to the serial port and print them out;
[0011] Step 6: Repeat steps 3 to 5, send the second to Nth matching ROM code address instructions in sequence, convert and print them;
[0012] Step 7: Repeat steps 1 to 6 to search, match, convert and display the temperature again.
[0013] Preferably, the algorithm for sending the instruction to search the ROM encoding address in step 2 specifically includes the following steps:
[0014] Step 21: The bus host FPGA issues a search ROM encoding address instruction on the single bus;
[0015] Step 22: Each temperature sensor simultaneously transmits the address from the 0th bit to the Mth bit back to the bus host FPGA, that is, first transmits the original code of the bit, and then transmits the inverse code of the bit;
[0016] Step 23: When the bus host FPGA reads the original code and the inverse code of the bit from the single bus process, the two bits are stored, and there are four results of 00, 01, 10 and 11 respectively, and each result is judged. If there is a conflicting bit, it means that there are multiple temperature sensors on the single bus;
[0017] Step 24: If there is a conflicting bit, when the currently stored M bits are processed as 0, the number of stored bits is increased by 1; when the currently stored M bits are processed as 1, the number of stored bits is decreased by 1;
[0018] Step 25: When the currently stored M bit is processed as 0, repeat steps 22 to 24, send the M+1th bit to the 64th bit address in sequence, and obtain the ROM encoding address of the first temperature sensor;
[0019] Step 26: When the currently stored M bit is processed as 1, repeat steps 22 to 24, send the M+1th bit to the 64th bit address in sequence, and obtain the ROM encoding address of the second temperature sensor;
[0020] Step 27: Repeat steps 21 to 26 above to search out the ROM code address of the Nth temperature sensor in turn and store it. When the number of conflicting bit registers is reduced to 0, the search is terminated.
[0021] Preferably, in step 22, the single bus has a wired AND function, and when multiple temperature sensors simultaneously return 1 and 0, the level on the single bus is 0.
[0022] Preferably, in step 23:
[0023] 00 means that there is a bus master FPGA connected to the single bus, and their values conflict at this data bit;
[0024] 01 means that there is a bus master FPGA connected to the single bus, and their values are all 0 at this data bit;
[0025] 10 means that there is a bus master FPGA connected to the single bus, and their values are all 1 at this data bit;
[0026] 11 means there is no bus master FPGA connected to the single bus.
[0027] Preferably, each of the temperature sensors has a unique 64-bit ROM encoded address.
[0028] Preferably, the connection circuit between the temperature sensor and the bus host FPGA is as follows: the DQ ends of the plurality of temperature sensors are connected in parallel to the IO ports of one bus host FPGA.
[0029] Compared with the prior art, the present invention has the following beneficial effects:
[0030] The present invention discloses an FPGA testing method and method for multiple single-bus temperature sensors sharing a single IO port. The present invention can simultaneously measure the temperature of multiple single-bus temperature sensors without increasing the IO ports of the FPGA. Only software upgrade is required, which meets the need of not changing the circuit board during the development of aerospace systems and has the advantages of short modification cycle, low cost, etc. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 The figure is a circuit diagram for connecting a temperature sensor to an FPGA; wherein (a) is a common one-to-one hardware connection diagram in the prior art, and (b) is a one-to-many hardware connection diagram of the present invention.
[0032] Figure 2 This is a flow chart of the FPGA testing multiple temperature sensors of the present invention.
[0033] Figure 3 A flowchart of the algorithm for searching multiple ROM encoding addresses for the FPGA of the present invention. DETAILED DESCRIPTION
[0034] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0035] like Figure 2As shown, the embodiment of the present invention provides an FPGA testing method for multiple single-bus temperature sensors sharing a single IO port, comprising the following steps:
[0036] Step 1: Start and initialize the temperature sensor and ensure that the temperature sensor is connected to the single bus;
[0037] Step 2: Send a search ROM code address instruction. If there are different ROM code addresses on the single bus, the number of temperature sensors will increase by 1, and N different ROM code addresses will be stored in the corresponding registers.
[0038] Step 3: Send the matching ROM code address instruction and temperature conversion instruction to make the corresponding temperature sensor respond and start converting the temperature;
[0039] Step 4: Wait for 1 second for the temperature conversion to complete, send a temperature reading command, read the digital temperature data and convert it into a temperature value;
[0040] Step 5: Send the current ROM encoding address and converted temperature value to the serial port and print them out;
[0041] Step 6: Repeat steps 3 to 5, send the second to Nth matching ROM code address instructions in sequence, convert and print them;
[0042] Step 7: Repeat steps 1 to 6 to search, match, convert and display the temperature again.
[0043] like Figure 3 As shown, the algorithm for sending the search ROM code address instruction in step 2 specifically includes the following steps:
[0044] Step 21: The bus host FPGA issues a search ROM encoding address instruction on the single bus;
[0045] Step 22: Each temperature sensor simultaneously transmits the address from the 0th bit to the Mth bit back to the bus host FPGA, that is, first transmits the original code of the bit, and then transmits the inverse code of the bit;
[0046] Step 23: When the bus host FPGA reads the original code and the inverse code of the bit from the single bus process, the two bits are stored, and there are four results of 00, 01, 10 and 11 respectively, and each result is judged. If there is a conflicting bit, it means that there are multiple temperature sensors on the single bus;
[0047] Step 24: If there is a conflicting bit, when the currently stored M bits are processed as 0, the number of stored bits is increased by 1; when the currently stored M bits are processed as 1, the number of stored bits is decreased by 1;
[0048] Step 25: When the currently stored M bit is processed as 0, repeat steps 22 to 24, send the M+1th bit to the 64th bit address in sequence, and obtain the ROM encoding address of the first temperature sensor;
[0049] Step 26: When the currently stored M bit is processed as 1, repeat steps 22 to 24, send the M+1th bit to the 64th bit address in sequence, and obtain the ROM encoding address of the second temperature sensor;
[0050] Step 27: Repeat steps 21 to 26 above to search out the ROM code address of the Nth temperature sensor in turn and store it. When the number of conflicting bit registers is reduced to 0, the search is terminated.
[0051] In step 22, the single bus has a wired AND function. When multiple temperature sensors send back 1 and 0 at the same time, the level on the single bus is 0.
[0052] like Figure 3 As shown, in step 23:
[0053] 00 means that there is a bus master FPGA connected to the single bus, and their values conflict at this data bit;
[0054] 01 means that there is a bus master FPGA connected to the single bus, and their values are all 0 at this data bit;
[0055] 10 means that there is a bus master FPGA connected to the single bus, and their values are all 1 at this data bit;
[0056] 11 means there is no bus master FPGA connected to the single bus.
[0057] Each temperature sensor has a unique 64-bit ROM-encoded address.
[0058] like Figure 1 As shown in (b), the connection circuit between the temperature sensor and the bus host FPGA is as follows: the DQ ends of multiple temperature sensors are connected in parallel to the IO port of one bus host FPGA.
[0059] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A FPGA testing method for multiple single-bus temperature sensors sharing a single IO port, characterized in that: The steps include: Step 1: Start and initialize the temperature sensor and ensure that the temperature sensor is connected to the single bus; Step 2: Send a search ROM code address instruction. If there are different ROM code addresses on the single bus, the number of temperature sensors will increase by 1, and N different ROM code addresses will be stored in the corresponding registers. Step 3: Send the matching ROM code address instruction and temperature conversion instruction to make the corresponding temperature sensor respond and start converting the temperature; Step 4: Wait for 1 second for the temperature conversion to complete, send a temperature reading command, read the digital temperature data and convert it into a temperature value; Step 5: Send the current ROM encoding address and converted temperature value to the serial port and print them out; Step 6: Repeat steps 3 to 5, send the second to Nth matching ROM code address instructions in sequence, convert and print them; Step 7: Repeat steps 1 to 6 to search, match, convert and display the temperature again.
2. The FPGA testing method for multiple single-bus temperature sensors sharing a single IO port as claimed in claim 1, characterized in that: The algorithm for sending the search ROM code address instruction in step 2 specifically includes the following steps: Step 21: The bus host FPGA issues a search ROM encoding address instruction on the single bus; Step 22: Each temperature sensor simultaneously transmits the address from the 0th bit to the Mth bit back to the bus host FPGA, that is, first transmits the original code of the bit, and then transmits the inverse code of the bit; Step 23: When the bus host FPGA reads the original code and the inverse code of the bit from the single bus process, the two bits are stored, and there are four results of 00, 01, 10 and 11 respectively, and each result is judged. If there is a conflicting bit, it means that there are multiple temperature sensors on the single bus; Step 24: If there is a conflicting bit, when the currently stored M bits are processed as 0, the number of stored bits is increased by 1; when the currently stored M bits are processed as 1, the number of stored bits is decreased by 1; Step 25: When the currently stored M bit is processed as 0, repeat steps 22 to 24, send the M+1th bit to the 64th bit address in sequence, and obtain the ROM encoding address of the first temperature sensor; Step 26: When the currently stored M bit is processed as 1, repeat steps 22 to 24, send the M+1th bit to the 64th bit address in sequence, and obtain the ROM encoding address of the second temperature sensor; Step 27: Repeat steps 21 to 26 above to search out the ROM code address of the Nth temperature sensor in turn and store it. When the number of conflicting bit registers is reduced to 0, the search is terminated.
3. The FPGA testing method for multiple single-bus temperature sensors sharing a single IO port as claimed in claim 2, characterized in that: In step 22, the single bus has a wired AND function. When multiple temperature sensors send back 1 and 0 at the same time, the level on the single bus is 0.
4. The FPGA testing method for multiple single-bus temperature sensors sharing a single IO port as claimed in claim 2, characterized in that: In step 23: 00 means that there is a bus master FPGA connected to the single bus, and their values conflict at this data bit; 01 means that there is a bus master FPGA connected to the single bus, and their values are all 0 at this data bit; 10 means that there is a bus master FPGA connected to the single bus, and their values are all 1 at this data bit; 11 means there is no bus master FPGA connected to the single bus.
5. The FPGA testing method for multiple single-bus temperature sensors sharing a single IO port as claimed in claim 1, characterized in that: Each of the temperature sensors has a unique 64-bit ROM encoded address.
6. The FPGA testing method for multiple single-bus temperature sensors sharing a single IO port as claimed in claim 1, characterized in that: The connection circuit between the temperature sensor and the bus host FPGA is as follows: the DQ ends of multiple temperature sensors are connected in parallel to the IO port of one bus host FPGA.