Pixel circuit and driving method thereof, display panel and display device

Abstract

The invention provides a pixel circuit and a driving method thereof, a display panel and a display device, and the pixel circuit comprises a light-emitting element which is electrically connected to a first power signal end; the driving sub-circuit generates a driving current from the first power supply signal end to the second power supply signal end through the light-emitting element; the compensation control sub-circuit transmits a first power supply signal of a first power supply signal end to a first node based on a signal of a compensation control end; the compensation sub-circuit is electrically connected with the third node and the fourth node, and is used for electrically connecting the third node with the fourth node based on a signal of a compensation control end; the write-in sub-circuit is electrically connected with a data signal end and a fourth node, and transmits a data signal of the data signal end to the fourth node based on a signal of a data control end; and the first light-emitting control sub-circuit transmits the driving current from the third node to the second power supply signal end based on the signal of the first light-emitting control end. According to the embodiment provided by the invention, the threshold compensation range is expanded.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display panel, and a display device. Background Art

[0002] In the field of display technology, active switching devices based on oxide technology are often used because of their high uniformity. In current display panels, transistors at different positions in the pixel circuit have different display contents, and the threshold voltages of the driving transistors in each circuit have different offset states, resulting in poor uniformity of the display panel. Summary of the invention

[0003] In order to solve at least one of the above problems, the present disclosure provides a pixel circuit according to a first aspect, comprising:

[0004] A light emitting element, electrically connected to the first power signal terminal;

[0005] A driving subcircuit, including a driving transistor, electrically connected between a first node and a second node, and configured to generate a driving current from a first power signal terminal to a second power signal terminal via a light emitting element;

[0006] a compensation control subcircuit, electrically connected between the first power signal terminal and the first node, and configured to transmit the first power signal of the first power signal terminal to the first node based on the signal of the compensation control terminal;

[0007] a compensation subcircuit, electrically connected to the third node and the fourth node, and configured to electrically connect the third node to the fourth node based on a signal at the compensation control terminal;

[0008] a writing subcircuit, electrically connected to the data signal terminal and the fourth node, and configured to transmit the data signal of the data signal terminal to the fourth node based on the signal of the data control terminal;

[0009] The first light emitting control subcircuit is electrically connected to the third node and is configured to transmit the driving current from the third node to the second power signal terminal based on the signal of the first light emitting control terminal.

[0010] Optionally, the pixel circuit further includes: a first capacitor, wherein a first electrode of the first capacitor is electrically connected to the fourth node, and a second electrode of the first capacitor is electrically connected to a fifth node corresponding to the control electrode of the driving transistor.

[0011] Optionally, the compensation control subcircuit includes a first transistor, a first electrode of the first transistor is electrically connected to the first power signal terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the compensation control terminal.

[0012] The compensation sub-circuit includes a second transistor, a first electrode of the second transistor is electrically connected to the third node, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the compensation control terminal.

[0013] Optionally, the pixel circuit also includes: a reference subcircuit, electrically connected between the reference voltage terminal and the fifth node, configured to transmit the first reference voltage of the reference voltage terminal to the fifth node based on the signal of the reference control terminal, and the reference control terminal and the compensation control terminal are electrically connected to the same signal line.

[0014] Optionally, the pixel circuit further includes: a second capacitor, a first electrode of the second capacitor is electrically connected to the second reference voltage terminal, and a second electrode of the second capacitor is electrically connected to the fourth node.

[0015] Optionally, the second reference voltage terminal and the first reference voltage terminal are electrically connected to the same signal line, or

[0016] The second reference voltage terminal and the first power signal terminal are electrically connected to the same signal line.

[0017] Optionally, the pixel circuit further includes: a second light emitting control subcircuit,

[0018] The second light emitting control subcircuit is electrically connected between the first node and the first electrode of the driving transistor, and is configured to electrically connect the first node to the first electrode of the driving transistor based on a signal of the second light emitting control terminal, or

[0019] The second light emitting control subcircuit is electrically connected between the second node and the third node, and is configured to electrically connect the second node and the third node based on a signal of the second light emitting control terminal.

[0020] Optionally, there is an overlapping period between the effective levels of the access signal of the second light-emitting control terminal and the effective level of the signal accessed by the compensation control terminal.

[0021] Optionally, the writing sub-circuit includes a third transistor, a first electrode of the third transistor is electrically connected to the data signal terminal, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the data control terminal.

[0022] The first light emitting control subcircuit includes a fourth transistor, a first electrode of the fourth transistor is electrically connected to the third node, a second electrode is electrically connected to the second power signal terminal, and a control electrode is electrically connected to the first light emitting control terminal.

[0023] A second aspect of the present disclosure provides a display panel, comprising the pixel circuit described above.

[0024] A third aspect of the present disclosure provides a display device, comprising the display panel described above.

[0025] A fourth aspect of the present disclosure provides a driving method of the pixel circuit as described above, comprising:

[0026] In the compensation stage, based on the signal at the compensation control terminal being at an effective level, the first power supply signal is transmitted to the first node and the third node and the fourth node are electrically connected, so as to perform threshold compensation on the driving transistor using the first power supply signal;

[0027] In the writing phase, the data signal is transmitted to the fourth node based on the signal at the data control terminal being at a valid level; and

[0028] In the light emitting stage, based on the signal at the first light emitting control terminal being at an effective level, the driving current is transmitted from the third node to the second power signal terminal, so that the light emitting element emits light.

[0029] The beneficial effects of the present disclosure are as follows:

[0030] In response to the existing problems, the present disclosure develops a pixel circuit and a driving method thereof, a display panel, and a display device. By providing a compensation control subcircuit and a compensation subcircuit, and the two are controlled by the same control signal, a first power supply signal as a driving power supply signal is used to provide a compensation potential for a driving transistor, thereby increasing the range of threshold compensation and improving the display effect. In addition, the circuit timing is simple, which is conducive to narrow frame, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 A schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure is shown;

[0033] Figure 2 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present disclosure;

[0034] Figure 3 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present disclosure;

[0035] Figure 4 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present disclosure;

[0036] Figure 5 A signal timing diagram of key ports of a pixel circuit according to an embodiment of the present disclosure is shown;

[0037] Figures 6 to 9 A working principle diagram of a pixel circuit according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0038] In order to more clearly illustrate the present disclosure, the present disclosure is further described below in conjunction with preferred embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content described below is illustrative rather than restrictive, and should not be used to limit the scope of protection of the present disclosure.

[0039] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate a quantitative limitation, but rather indicate the existence of at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. In addition, in the present disclosure, the electrical connection can be a direct connection or a connection separated by a certain conductive transistor.

[0040] The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, since all transistors are N-type transistors, in order to distinguish the source and drain of the transistor, the drain is called the first electrode, the source is called the second electrode, and the gate is called the control electrode. When the gate inputs a high level, the source and drain are turned on. In addition, when the gate and the source are both at a high level with equal potential, the source and drain are not turned on.

[0041] At present, with the increase in the size of display products, for example, display products gradually change from a few inches to more than ten inches, and from 12.9 inches (2048 rows of pixels) to, for example, more than 18 inches (3296 rows of pixels), the display screen changes from a horizontal screen to a vertical screen, which causes the time for the row scanning signal to scan one row of pixels per 1H to be reduced from 3.6μs to 1.9μs, where 1 second is divided by the number of rows and then divided by the refresh rate of 1H. The threshold compensation of the traditional pixel driving circuit is carried out synchronously with the writing of data, and the sampling time is also less than 1H, resulting in insufficient compensation time at high frequency or high resolution, resulting in affected image quality. At present, in order to solve the problem of insufficient compensation time under high frequency or high refresh rate, a solution of separating the compensation time from the data writing time is usually adopted.

[0042] However, in the related art, in the scheme of performing compensation and data writing separately, it is necessary to provide bias for the source of the driving transistor through a bias voltage, and write a reference voltage to the gate of the driving transistor to keep the driving transistor turned on during compensation. For the pixel circuit of the oxide process, if the driving transistor is an N-type transistor, that is, a driving transistor with a positive threshold voltage, the reference voltage and the bias voltage are usually fixed values, and in order to ensure that the driving transistor is turned on, the bias voltage is less than the reference voltage. In the case where the threshold voltage is still positive after drift, compensation can be achieved as long as a sufficient bias voltage is set. If the threshold voltage drifts negatively, the bias voltage is still less than the reference voltage at this time, which is insufficient to change it from leakage to charging, and compensation cannot be achieved, and the compensation range and effect are limited.

[0043] In order to achieve at least one of the above objectives, an embodiment of the present disclosure provides a pixel circuit, including:

[0044] A light emitting element, electrically connected to the first power signal terminal;

[0045] A driving subcircuit, comprising a driving transistor, electrically connected between a first node and a second node, and configured to generate a driving current from the first power signal terminal to the second power signal terminal via a light emitting element;

[0046] a compensation control subcircuit, electrically connected between the first power signal terminal and the first node, and configured to transmit the first power signal of the first power signal terminal to the first node based on a signal of the compensation control terminal;

[0047] a compensation subcircuit, electrically connected to a third node and a fourth node, and configured to electrically connect the third node with the fourth node based on a signal of the compensation control terminal;

[0048] a writing subcircuit, electrically connected to the data signal terminal and the fourth node, and configured to transmit the data signal of the data signal terminal to the fourth node based on the signal of the data control terminal;

[0049] The first light emitting control subcircuit is electrically connected to the third node and is configured to transmit the driving current from the third node to the second power signal terminal based on the signal of the first light emitting control terminal.

[0050] In this embodiment, by providing a compensation control sub-circuit and a compensation sub-circuit, and the two are controlled by the same control signal, the first power supply signal as the driving power supply signal is used to provide a compensation potential for the driving transistor, thereby increasing the range of threshold compensation, improving the display effect, and simplifying the circuit timing, which is conducive to narrowing the frame.

[0051] In order to explain in detail the structure and functional advantages of the pixel circuit in the embodiment of the present disclosure, a specific circuit structure is described in detail below in combination with specific examples.

[0052] In a specific example, refer to Figure 1 As shown, the pixel circuit includes: a light emitting element 10, a driving sub-circuit 20, a compensation control sub-circuit 30, a compensation sub-circuit 40, a writing sub-circuit 50 and a first light emitting control sub-circuit 60.

[0053] Specifically, the light emitting element 10 includes a first electrode (i.e., an anode) and a second electrode (i.e., a cathode), wherein the first electrode is electrically connected to a first power signal terminal VDD, and the second electrode is electrically connected to a pixel driving circuit, wherein the potential of the first power signal terminal VDD is positive, and a first power signal as a driving potential of the pixel circuit is provided. That is, in the embodiment of the present disclosure, the light emitting element 10 is set to an inverted structure.

[0054] The light emitting element 10 may be an organic light emitting diode, or may be a quantum dot light emitting diode (QLED) or a micro light emitting diode (Micro LED).

[0055] Continue to refer to Figure 1 As shown, the driving subcircuit 20 includes a driving transistor DTFT. The driving subcircuit 20 is electrically connected between the first node N1 and the second node N2, and is configured to generate a driving current from the first power signal terminal to the second power signal terminal via the light emitting element 10. Specifically, the first electrode of the driving transistor DTFT is electrically connected to N1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the fifth node N5, that is, the control electrode corresponds to the third node N5. When the potential of the fifth node N5 is at an effective level and the potential difference between the fifth node N5 and the second node N2 is greater than the threshold voltage of the driving transistor DTFT, the driving transistor DTFT is turned on.

[0056] The compensation control subcircuit 30 is electrically connected between the first power signal terminal VDD and the first node N1 , and is configured to transmit the first power signal of the first power signal terminal VDD to the first node N1 based on the signal of the compensation control terminal Gate2 .

[0057] The compensation sub-circuit 40 is electrically connected to the third node N3 and the fourth node N4 , and is configured to electrically connect the third node N3 and the fourth node N4 based on a signal of the compensation control terminal Gate2 .

[0058] In the embodiment of the present disclosure, the compensation control subcircuit 30 and the compensation subcircuit 40 are controlled by a signal at the same signal terminal, and under the control of the signal, the first power signal terminal VDD and the first node N1 and the third node N3 and the fourth node N4 are simultaneously turned on, so that in the compensation stage, the signal at the first power signal terminal VDD can be used to provide a compensation potential for the driving transistor DTFT, so that with the cooperation of the two, compensation can be achieved regardless of whether the threshold voltage of the driving transistor DTFT drifts positively or negatively.

[0059] Continue to refer to Figure 1 As shown, the write sub-circuit 50 is electrically connected to the data signal terminal DATA and the fourth node N4, and is configured to transmit the data signal of the data signal terminal DATA to the fourth node N4 based on the signal of the data control terminal Gate1. The data signal Gate1 and the compensation control terminal Gate2 receive different signals and are not effective at the same time, realizing a structure of threshold compensation and data writing separation.

[0060] The first light emitting control subcircuit 60 is electrically connected to the third node N3 and is configured to transmit the driving current from the third node N3 to the second power signal terminal VSS based on the signal of the first light emitting control terminal Gate(n), and the second power signal terminal VSS is connected to a negative voltage.

[0061] Specifically, refer to Figure 1 As shown, the compensation control subcircuit 30 includes a first transistor T1, a first electrode of the first transistor T1 is electrically connected to the first power signal terminal VDD, a second electrode is electrically connected to the first node N1, and a control electrode is electrically connected to the compensation control terminal Gate2, and the compensation subcircuit 40 includes a second transistor T2, a first electrode of the second transistor T2 is electrically connected to the third node N3, a second electrode is electrically connected to the fourth node N4, and a control electrode is electrically connected to the compensation control terminal Gate2. When the signal connected to the compensation control terminal Gate2 is at an effective level, the first transistor T1 is turned on to electrically connect the first power signal terminal VDD to the first node N1, and the second transistor T2 is turned on to electrically connect the third node N3 and the fourth node N4. The compensation control terminal Gate2 can be electrically connected to a row output terminal of the second group of scan signal lines.

[0062] Continue to refer to Figure 1 As shown, the writing sub-circuit 50 includes a third transistor T3, a first electrode of the third transistor T3 is electrically connected to the data signal terminal DATA, a second electrode is electrically connected to the fourth node N4, and a control electrode is electrically connected to the data control terminal Gate1. When the signal connected to the data control terminal Gate1 is at an effective level, the third transistor T3 is turned on, the data signal terminal DATA is turned on with the fourth node N4, and the data signal is transmitted to the fourth node N4. The data control terminal Gate1 can be electrically connected to a row output terminal of the first group of scan signal lines.

[0063] The first light-emitting control subcircuit 60 includes a fourth transistor T4, a first electrode of the fourth transistor T4 is electrically connected to the third node N3, a second electrode is electrically connected to the second power signal terminal VSS, and a control electrode is electrically connected to the first light-emitting control terminal Gate3(n). When the signal connected to the first light-emitting control terminal Gate3(n) is at an effective level, the fourth transistor T4 is turned on to electrically connect the third node N3 to the first power signal terminal VSS. When a driving current exists from the first power signal terminal VDD to the third node N3 via the light-emitting element 10, the driving current is transmitted from the third node N3 to the second power signal terminal VSS. The first light-emitting control terminal Gate3(n) can be electrically connected to a row output terminal of the third group of scanning signal lines, and n represents the current moment, that is, it represents the row output terminal electrically connected to the current row.

[0064] Continue to refer to Figure 1 As shown, the pixel circuit further includes a first capacitor C1, a first electrode of the first capacitor C1 is electrically connected to the fourth node N4, a second electrode of the first capacitor C1 is electrically connected to the fifth node N5, and is used to store a voltage difference between the fourth node N4 and the fifth node N5.

[0065] Continue to refer to Figure 1 As shown, the pixel circuit further includes a reference subcircuit 70, which is electrically connected between the reference voltage terminal Vef and the fifth node N5, and is configured to transmit the first reference voltage of the reference voltage terminal REF to the fifth node N5 based on the signal of the reference control terminal Gate2. The reference control terminal and the compensation control terminal are electrically connected to the same signal line, so they have the same reference number. The reference subcircuit 70 includes a fifth transistor T5, a first electrode of the fifth transistor T5 is electrically connected to the reference voltage terminal REF, a second electrode is electrically connected to the fifth node N5, and a control electrode is electrically connected to the reference control terminal Gate2. When the signal connected to the reference control terminal Gate2 is at an effective level, the first reference voltage of the reference voltage terminal REF is transmitted to the fifth node N5. That is, in this embodiment, the first reference voltage can be provided to the fifth node N5 through the fifth transistor T5.

[0066] Continue to refer to Figure 1 As shown, the pixel circuit may further include a second capacitor C2, a first electrode of the second capacitor C2 being electrically connected to the second reference voltage terminal, and a second electrode being electrically connected to the fourth node N4. The second capacitor C2 is used to maintain the potential of the fourth node N4. Specifically, the second capacitor C2 can maintain the potential of the fourth node N4 after the data signal is written into the fourth node N4.

[0067] Optionally, refer to Figure 1As shown, the second reference voltage terminal can be connected to the same signal line as the first reference voltage terminal REF, so that the label of the second reference voltage terminal is the same as the label of the reference voltage terminal REF. At this time, the first electrode of the second capacitor C2 is connected to the first reference voltage, and the second electrode of the second capacitor C2 is maintained at the voltage level provided by the fourth node N4.

[0068] Alternatively, refer to Figure 2 As shown, the second reference voltage terminal can be connected to the same signal line as the first power signal terminal VDD, so that the number of the second reference voltage terminal is the same as the number of the first power signal terminal VDD. At this time, the first electrode of the second capacitor C2 is connected to the first power signal, and the second electrode of the second capacitor C2 is maintained at the voltage level provided by the fourth node N4.

[0069] Optionally, continue to refer to Figure 1 As shown, the pixel circuit further includes a second light-emitting control subcircuit 80, which is electrically connected between the second node N2 and the third node N3, and is configured to drive the current to electrically connect the second node N2 and the third node N3 based on the signal of the second light-emitting control terminal Gate3(n+1). Specifically, the second light-emitting control subcircuit 80 includes a sixth transistor T6, a first electrode of the sixth transistor T6 is electrically connected to the second node N2, a second electrode is electrically connected to the third node N3, and a control electrode is electrically connected to the second light-emitting control terminal Gate3(n+1). When the signal received by the second light-emitting control terminal Gate3(n+1) is at an effective level, the sixth transistor T6 is turned on to electrically connect the second node N2 and the third node N3. In the light-emitting stage, the drive current can be transmitted from the second node N2 to the third node N3.

[0070] In addition, more preferably, in the present embodiment, there is an overlapping period between the signal received by the second light-emitting control terminal Gate3(n+1) and the signal received by the compensation control terminal Gate2, so that in the compensation stage, the second light-emitting control terminal Gate3(n+1) receives a signal of an effective level to provide the first power signal of the first power signal terminal to the third node N3, thereby forming a path from the first power signal terminal VDD to the fourth node N4 for threshold compensation of the driving transistor DTFT.

[0071] The second light emitting control terminal Gate3 (n+1) can be electrically connected to a row output terminal of the third group of scanning signal lines, and n+1 represents the next moment, that is, it represents being electrically connected to the row output terminal of the next row.

[0072] visible, Figure 1The pixel circuit shown uses only three groups of row scanning signal lines, that is, only three groups of gate drive circuits are required in the display panel to realize the pixel driving function of the light-emitting unit in the display area. The circuit timing is simple and can greatly simplify the circuit structure in the peripheral area of ​​the display panel, which is conducive to the narrow frame design.

[0073] Alternatively, refer to Figure 3 As shown, the second light-emitting control subcircuit 80 may also be arranged between the first node N1 and the first electrode of the driving transistor DTFT. That is, the second light-emitting control subcircuit 80 is electrically connected between the first node N1 and the first electrode of the driving transistor DTFT, and is configured to electrically connect the first node N1 to the first electrode of the driving transistor DTFT based on the signal of the second light-emitting control terminal Gate3(n+1). Specifically, the second light-emitting control subcircuit 80 includes a sixth transistor T6, the first electrode of the sixth transistor T6 is electrically connected to the first node N1, the second electrode is electrically connected to the first electrode of the driving transistor DTFT, and the control electrode is electrically connected to the second light-emitting control terminal Gate3(n+1). When the signal received by the second light-emitting control terminal Gate3(n+1) is at an effective level, the sixth transistor T6 is turned on to electrically connect the first node N1 and the first electrode of the driving transistor DTFT. In the light-emitting stage, the driving current can be transmitted from the first node N1 to the first electrode of the driving transistor DTFT.

[0074] In addition, more preferably, in the present embodiment, there is an overlapping period between the signal received by the second light-emitting control terminal Gate3(n+1) and the signal received by the compensation control terminal Gate2, so that in the compensation stage, the second light-emitting control terminal Gate3(n+1) receives a signal of an effective level to provide the first power signal of the first power signal terminal to the third node N3, thereby forming a path from the first power signal terminal VDD to the fourth node N4 for threshold compensation of the driving transistor DTFT.

[0075] The second light emitting control terminal Gate3 (n+1) can be electrically connected to a row output terminal of the third group of scanning signal lines, and n+1 represents the next moment, that is, it represents being electrically connected to the row output terminal of the next row.

[0076] Of course, it should be noted that, referring to Figure 4As shown, the pixel circuit may not include the second light-emitting control subcircuit. In this case, as long as the signal received by the compensation control terminal Gate2 is at an effective level, a conductive path from the first power signal terminal VDD to the fourth node N4 can be formed, so that the threshold voltage of the driving transistor DTFT is compensated by the first power signal. At the same time, in the light-emitting stage, when the first light-emitting control unit 60 receives the effective level signal of the first light-emitting control terminal, a signal path from the first power signal terminal via the light-emitting element 10 to the second power signal terminal VSS can be formed. In addition, in this case, the second node N2 and the third node N3 are equivalent to the same node.

[0077] In order to further understand the structure and function of the shift register circuit of the embodiment of the present disclosure, Figure 5 The timing diagram within one frame of image is shown, combined with Figures 6 to 9 describe Figure 1 The circuit structure shown works in different time periods.

[0078] It should be noted that in the figure, a slash is used to indicate that the transistor is turned off, and a solid line with an arrow indicates a current path. In addition, the data signal connected to the data signal terminal DATA is represented as Vdata, the first reference voltage connected to the reference voltage terminal REF is represented as Vref, the first power signal is represented as VDD, and the second power signal is represented as VSS.

[0079] Reference Figure 5 As shown, the process of the pixel circuit driving the light-emitting element 10 includes a first period T1, a second period T2, a third period T3 and a fourth period T4, wherein the first period T1 is a reset stage, the second period T2 is a compensation stage, the third period T3 is a writing period, and the fourth period T4 is a light-emitting stage.

[0080] In the first time period T1, that is, in the reset stage, the signal of the data control terminal Gate1 is at a low level, the signal of the compensation control terminal Gate2 is at a high level, the reference control terminal and the compensation control terminal are connected to the same signal, which is also at a high level, the first light-emitting control terminal Gate3(n) is at a high level, and the second light-emitting control terminal Gate3(n+1) is at a low level.

[0081] Therefore, the first transistor T1 is turned on, and the potential of the second electrode of the light emitting element 10 is reset to VDD using the first power signal VDD of the first power signal terminal VDD; the second transistor T2 is turned on, and the potential of the fifth node N5 is reset to Vref using the first reference voltage Vref; the fourth transistor T4 and the fifth transistor T5 are turned on, and the fourth node N4 and the third node N3 are reset to VSS using the second power signal VSS. At the same time, the third transistor T3 and the sixth transistor T6 are turned off.

[0082] In the second time period T2, that is, in the compensation stage, the signal of the data control terminal Gate1 is at a low level, the signal of the compensation control terminal Gate2 is at a high level, the reference control terminal and the compensation control terminal are connected to the same signal, which is also at a high level, the first light-emitting control terminal Gate3(n) is at a low level, and the second light-emitting control terminal Gate3(n+1) is at a high level, that is, the signal of the second light-emitting control terminal Gate3(n+1) is in an overlapping period of high level with the compensation control terminal Gate2 during the compensation stage.

[0083] At this time, the fifth transistor T5 is turned on, the potential of the fifth node N5 is maintained at Vref, the sixth transistor T6 is turned on, and at the beginning of the second time period T2, the source voltage Vs of the driving transistor DTFT is less than the first reference voltage Vref, the driving transistor DTFT is turned on, and at the same time, because the first transistor T1 is turned on, the second transistor T2 is turned on, thereby forming a path from the first power signal terminal VDD to the first node N1 to the second node N2 to the third node N3 and then to the fourth node N4, and the potentials of the third node N3 and the fourth node N4 gradually increase from VSS to Vref-Vth, where Vth represents the threshold voltage of the driving transistor DTFT. At the same time, when the potential of the fourth node N4 becomes Vref-VSS, the compensation is ended.

[0084] In addition, from Figure 5 It can be seen that in the compensation stage, the third transistor T3 and the fourth transistor T4 are turned off, which will not be described in detail here.

[0085] It is worth mentioning that in the embodiment of the present disclosure, by setting the compensation control subcircuit 30 and the compensation subcircuit 40 to be controlled by the compensation control terminal Gate2, when the second light-emitting control subcircuit 80 is included, the second light-emitting control terminal Gate3(n+1) of the second light-emitting control subcircuit 80 set on the path from the first power signal terminal VDD to the fourth node N4 and the compensation control terminal Gate2 have an overlapping period of effective level in the compensation stage, thereby forming a conductive path from the first power signal terminal VDD to the fourth node N4, so that the threshold compensation level for the driving transistor DTFT can be provided by using the first power signal VDD. Therefore, in the embodiment of the present disclosure, the threshold voltage Vth of the driving transistor DTFT can be compensated regardless of positive drift or negative drift, thereby increasing the range of threshold compensation and improving display quality.

[0086] In the third time period T3, that is, in the writing stage, the signal of the data control terminal Gate1 becomes a high level, the signal of the compensation control terminal Gate2 is a low level, the reference control terminal and the compensation control terminal are connected to the same signal, which is also a low level, the first light-emitting control terminal Gate3(n) is a high level, and the second light-emitting control terminal Gate3(n+1) is a low level.

[0087] Therefore, only the third transistor T3 and the fourth transistor T4 are turned on, and the other transistors are turned off. After the third transistor T3 is turned on, the data signal Vdata connected to the data signal terminal DATA is transmitted to the fourth node N4. After the fourth transistor T4 is turned on, the second power signal terminal VSS is transmitted to the third node N3, and the potential of the third node N3 is VSS.

[0088] In addition, after the data signal Vdata is written into the fourth node N4, the potential of the fourth node N4 becomes Vdata and is maintained under the action of the second capacitor C2. The potential of the first electrode of the first capacitor C1 changes from the original Vref-Vth to Vdata, and the voltage change amount ΔV=Vdata-(Vref-Vth)=Vdata-Vref+Vth. Under the bootstrap action of the first capacitor C1, the potential change amount of the second electrode of the first capacitor C1 changes by ΔV at the same time, and the potential of the fifth node N5 should be Vref+ΔV=Vref+Vdata-Vref+Vth=Vdata+Vth.

[0089] In the fourth time period T4, that is, in the light-emitting stage, the signal of the data control terminal Gate1 becomes a low level, the signal of the compensation control terminal Gate2 is a low level, the reference control terminal and the compensation control terminal are connected to the same signal, which is also a low level, the first light-emitting control terminal Gate3(n) is a high level, and the second light-emitting control terminal Gate3(n+1) becomes a high level.

[0090] At this time, the driving transistor DTFT is turned on and generates a driving current. The potential of the fifth node N5 is the control electrode potential Vg=Vdata+Vth of the driving transistor DTFT, and the potential of the second node N2 is the second electrode potential Vs=VSS of the driving transistor DTFT. Vgs=Vdata+Vth-VSS, and the driving current I=k×(Vgs-Vth) 2 =k×(Vgs+VSS) 2 , where k represents the gain parameter of the driving transistor.

[0091] It can be seen that after the above process, the threshold compensation of the driving transistor DTFT is completed. In addition, because the first transistor T1 is turned off, the current path from the first power signal terminal VDD to the first node N1 is the first power signal terminal VDD through the light emitting element 10 to the first node N1, and the sixth transistor T6 and the fourth transistor T4 are turned on, thereby forming a path from the first power signal terminal VDD through the light emitting element 10 to the first node N1 to the second node N2 and then to the third node N3 and then to the second power signal terminal VSS, and the driving current I drives the light emitting element 10 to emit light.

[0092] Through the above arrangement, a pixel circuit of an inverted light-emitting element is provided, and this circuit structure can prevent the source potential of the driving transistor DTFT from being affected by the anode potential of the degraded light-emitting element 10, and the display stability is better; at the same time, the time separation of the compensation phase and the writing phase of the pixel circuit of the embodiment of the present disclosure can provide sufficient data adoption and data writing time, and is more suitable for display products with high refresh rate or high resolution; at the same time, the pixel circuit of the embodiment of the present disclosure, while realizing the above functions, can provide positive or negative threshold voltage compensation for the driving transistor, especially the circuit in which the N-type oxide transistor is the driving transistor, to ensure that the threshold compensation range can cover various changes, thereby ensuring display uniformity and stability; in addition, only three groups of scanning signal line groups are required in the pixel circuit, that is, at least only three groups of gate drive circuits are required to complete pixel driving, which is conducive to narrow frame design.

[0093] A second aspect of the present disclosure provides a display panel including the pixel circuit of an embodiment of the present disclosure.

[0094] In this embodiment, by including the above-mentioned pixel circuit, an inverted light-emitting element pixel driving design with a wide range of threshold compensation can be implemented with a simple circuit layout, which can improve the display quality for high refresh rate and high resolution products.

[0095] The third aspect of the present disclosure provides a display device, including the display panel of the embodiment of the present disclosure. The display device can be a display product or component including any of the above display panels, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc., which is not limited in the present embodiment.

[0096] The specific structure and function of the above display panel and the pixel circuit included in the display panel have been described in detail in the above embodiments and will not be repeated here.

[0097] In this embodiment, an inverted pixel circuit of a light-emitting element with separate compensation and writing is provided in a real panel through a display panel, and the compensation control subcircuit and the compensation subcircuit in the pixel circuit cooperate with each other, and a first power supply signal as a driving power supply signal is used to provide a compensation potential for the driving transistor, thereby increasing the range of threshold compensation, improving the display effect, and simplifying the circuit timing, which is conducive to narrowing the frame.

[0098] A fourth aspect of the present disclosure provides a driving method of a pixel circuit using an embodiment of the present disclosure, comprising:

[0099] In the compensation stage, based on the signal at the compensation control terminal being at an effective level, the first power supply signal is transmitted to the first node and the third node and the fourth node are electrically connected, so as to perform threshold compensation on the driving transistor using the first power supply signal;

[0100] In the writing phase, the data signal is transmitted to the fourth node based on the signal at the data control terminal being at a valid level; and

[0101] In the light emitting stage, based on the signal at the first light emitting control terminal being at an effective level, the driving current is transmitted from the third node to the second power signal terminal, so that the light emitting element emits light.

[0102] The above method provides positive or negative threshold voltage compensation, ensures that the threshold compensation range can cover various changes, and ensures display uniformity and stability; in addition, only three groups of scanning signal line groups are required in the pixel circuit, that is, at least only three groups of gate drive circuits are required to complete pixel driving, which is conducive to narrow frame design. The specific implementation of this embodiment is the same as the previous embodiment, and will not be repeated here.

[0103] In response to the existing problems, the present disclosure develops a pixel circuit and a driving method thereof, a display panel, and a display device. By providing a compensation control subcircuit and a compensation subcircuit, and the two are controlled by the same control signal, a first power supply signal as a driving power supply signal is used to provide a compensation potential for a driving transistor, thereby increasing the range of threshold compensation and improving the display effect. In addition, the circuit timing is simple, which is conducive to narrow frame, and has broad application prospects.

[0104] Obviously, the above embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, and are not limitations on the implementation methods of the present disclosure. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made on the basis of the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present disclosure are still within the protection scope of the present disclosure.

Claims

1. A pixel circuit, characterized in that: include: A light emitting element, electrically connected to the first power signal terminal; A driving subcircuit, comprising a driving transistor, electrically connected between a first node and a second node, and configured to generate a driving current from the first power signal terminal to the second power signal terminal via a light emitting element; a compensation control subcircuit, electrically connected between the first power signal terminal and the first node, and configured to transmit the first power signal of the first power signal terminal to the first node based on a signal of the compensation control terminal; a compensation subcircuit, electrically connected to a third node and a fourth node, and configured to electrically connect the third node with the fourth node based on a signal of the compensation control terminal; a writing subcircuit, electrically connected to the data signal terminal and the fourth node, and configured to transmit the data signal of the data signal terminal to the fourth node based on the signal of the data control terminal; The first light emitting control subcircuit is electrically connected to the third node and is configured to transmit the driving current from the third node to the second power signal terminal based on the signal of the first light emitting control terminal.

2. The pixel circuit according to claim 1, characterized in that: Also includes: A first capacitor, wherein a first electrode of the first capacitor is electrically connected to the fourth node, and a second electrode of the first capacitor is electrically connected to a fifth node corresponding to the control electrode of the driving transistor.

3. The pixel circuit according to claim 1, characterized in that: The compensation control subcircuit comprises a first transistor, wherein a first electrode of the first transistor is electrically connected to the first power signal terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the compensation control terminal. The compensation subcircuit includes a second transistor, a first electrode of the second transistor is electrically connected to the third node, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the compensation control terminal.

4. The pixel circuit according to claim 2, characterized in that: Also includes: A reference subcircuit is electrically connected between a first reference voltage terminal and the fifth node, and is configured to transmit a first reference voltage of the reference voltage terminal to the fifth node based on a signal of a reference control terminal, wherein the reference control terminal and the compensation control terminal are electrically connected to the same signal line.

5. The pixel circuit according to claim 1, characterized in that: Also includes: A second capacitor, wherein a first electrode of the second capacitor is electrically connected to the second reference voltage terminal, and a second electrode of the second capacitor is electrically connected to the fourth node.

6. The pixel circuit according to claim 5, characterized in that: The second reference voltage terminal and the first reference voltage terminal are electrically connected to the same signal line, or The second reference voltage terminal and the first power signal terminal are electrically connected to the same signal line.

7. The pixel circuit according to claim 1, characterized in that: Also includes: The second light emitting control sub-circuit, The second light emitting control subcircuit is electrically connected between the first node and the first electrode of the driving transistor, and is configured to electrically connect the first node to the first electrode of the driving transistor based on a signal of the second light emitting control terminal, or The second light emitting control subcircuit is electrically connected between the second node and the third node, and is configured to electrically connect the second node and the third node based on a signal of a second light emitting control terminal.

8. The pixel circuit according to claim 1, characterized in that: There is an overlapping period between the effective levels of the access signal of the second light-emitting control terminal and the signal accessed by the compensation control terminal.

9. The pixel circuit according to claim 1, characterized in that: The writing sub-circuit comprises a third transistor, a first electrode of the third transistor is electrically connected to the data signal terminal, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the data control terminal. The first light emitting control subcircuit includes a fourth transistor, a first electrode of the fourth transistor is electrically connected to the third node, a second electrode is electrically connected to the second power signal terminal, and a control electrode is electrically connected to the first light emitting control terminal.

10. A display panel, characterized in that: The method comprises a pixel circuit as claimed in any one of claims 1 to 9.

11. A display device, characterized in that: Comprising the display panel as claimed in claim 10.

12. A driving method for a pixel circuit according to any one of claims 1 to 9, characterized in that: include: In the compensation stage, based on the signal at the compensation control terminal being at a valid level, the first power signal is transmitted to the first node and the third node and the fourth node are electrically connected, so as to perform threshold compensation on the driving transistor using the first power signal; In the writing phase, the data signal is transmitted to the fourth node based on the signal at the data control terminal being at a valid level; as well as In the light emitting stage, the driving current is transmitted from the third node to the second power signal terminal based on the signal at the first light emitting control terminal being at an effective level, so that the light emitting element emits light.

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