Display panel

Abstract

The invention provides a display panel. The display panel comprises a plurality of cascaded gate driving units and a pixel driving circuit. The gate driving unit comprises an input control module used for outputting a driving signal in a display scanning period; the compensation detection control module is used for outputting a compensation detection driving signal in a scanning blank period; the output module is connected with the input control module and the compensation detection control module, and is used for responding to the driving signal in a display scanning period to output a display scanning signal and responding to the compensation detection driving signal in a scanning blank period to output a compensation detection scanning signal; the pixel driving circuit is connected with the gate driving unit and is used for receiving a display scanning signal in a display scanning period and receiving a compensation detection scanning signal in a scanning blank period.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] Currently, display panels are widely used in different fields, such as smart mobile terminals, notebooks, and augmented reality displays, etc. However, the display panel may have a problem of uneven display brightness during the display process.

[0003] Therefore, how to improve the uneven brightness of the display panel is a technical problem that needs to be solved. Summary of the invention

[0004] The purpose of the present application is to provide a display panel to improve the problem of uneven brightness display of the display panel.

[0005] In a first aspect, the present application provides a display panel, wherein one frame time of the display panel includes a display scanning period and a scanning blank period, and the display panel includes:

[0006] A plurality of cascaded gate driving units, wherein the gate driving units include:

[0007] An input control module, used for outputting a driving signal during the display scanning period;

[0008] A compensation detection control module, configured to output a compensation detection drive signal during the scanning blank period; and

[0009] an output module connected to the input control module and the compensation detection control module, and configured to respond to the drive signal to output a display scanning signal during the display scanning period, and respond to the compensation detection drive signal to output a compensation detection scanning signal during the scanning blank period; and

[0010] The pixel driving circuit is connected to the gate driving unit and is used for receiving the display scanning signal during the display scanning period and receiving the compensation detection scanning signal during the scanning blank period.

[0011] Beneficial effects of some embodiments of the present application: Due to the newly provided compensation detection control module, the output module is connected to the input control module and the compensation detection control module. The output module responds to the drive signal to output the display scanning signal during the display scanning period, and responds to the compensation detection drive signal to output the compensation detection scanning signal during the scanning blank period. The pixel driving circuit is used to receive the display scanning signal during the display scanning period, and to receive the compensation detection scanning signal during the scanning blank period. Through this design, during the display scanning period, the pixel driving circuit receives the display scanning signal to provide conditions for the display panel to display, and during the blank period, the pixel driving circuit receives the compensation detection scanning signal to provide conditions for realizing random compensation detection. While realizing the display in one frame time, the compensation of the pixel driving circuit is realized, thereby improving the problem of uneven brightness display of the display panel during the display process. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 Schematic diagram of a display panel according to some embodiments of the present application;

[0013] Figure 2 A schematic diagram of a pixel driving circuit according to some embodiments of the present application;

[0014] Figure 3 Schematic diagram of a gate driving circuit of some embodiments of the present application;

[0015] Figure 4 Schematic diagram of a circuit of the (3n-1)th gate driving unit GOA (3n-1) in some embodiments of the present application;

[0016] Figure 5 This is a driving timing diagram of the gate driving circuit of some embodiments of the present application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0018] See also Figures 1 to 5 As shown, Figure 1 is a schematic diagram of a display panel according to some embodiments of the present application, Figure 2 is a schematic diagram of a pixel driving circuit of some embodiments of the present application, Figure 3 is a schematic diagram of a gate driving circuit of some embodiments of the present application, Figure 4is a circuit diagram of the (3n-1)th gate driving unit GOA(3n-1) in some embodiments of the present application, Figure 5 This is a driving timing diagram of the gate driving circuit of some embodiments of the present application.

[0019] The display panel 100 is an organic light emitting diode display panel, but is not limited thereto. The display panel 100 may also be a liquid crystal display panel, a micro light emitting diode display panel, a sub-millimeter light emitting diode display panel, or a quantum dot display panel.

[0020] Please refer to Figure 1 As shown, the display panel 100 includes a display area 100a and a non-display area 100b disposed around the display area 100a. The display panel 100 includes a pixel driving circuit 200 located in the display area 100a, and the pixel driving circuit 200 is connected to the data signal line DL and the scanning signal line GL.

[0021] The display panel 100 further includes a gate driving circuit 20 disposed in the non-display area 100b. The gate driving circuit 20 includes a first gate driving circuit 201 and a second gate driving circuit 202, which are respectively located at opposite sides of the display area 100a.

[0022] It is understandable that the gate driving circuit 20 may also be located at only one side of the display area 100a. At least a portion of the gate driving circuit 20 may also be disposed in the display area 100a.

[0023] See also Figure 2 As shown, the pixel driving circuit 200 includes a data writing transistor K1, a driving transistor DT, a compensation control transistor K2 and a storage capacitor Cst.

[0024] Among them, the driving transistor DT includes an N-type transistor. The data writing transistor K1 and the compensation control transistor K2 both include P-type transistors, which is convenient for reducing the size of the data writing transistor K1 and the compensation control transistor K2 while meeting the charging requirements of the data writing transistor K1, so as to facilitate the display panel to achieve high-frequency driving. Moreover, the size of the data writing transistor K1 and the compensation control transistor K2 is reduced, which is conducive to reducing the area occupied by the pixel driving circuit, thereby increasing the number of pixel driving circuits and pixels, and meeting the display panel's demand for high-resolution display.

[0025] It is understandable that the data writing transistor K1 and the compensation control transistor K2 may also include N-type transistors. In the case where both the data writing transistor K1 and the compensation control transistor K2 include N-type transistors, since the charging current of the N-type transistor is relatively small, the charging time of the N-type transistor needs to be increased, and the increase in the charging time limits the increase in the driving frequency of the display panel. In addition, in order to achieve a better charging effect for the N-type transistor, it is necessary to increase the ratio of the channel width to the channel length of the N-type transistor, and the increase in the ratio limits the increase in the resolution of the display panel.

[0026] The gate of the data writing transistor K1 is connected to the scanning signal line GL, one of the source and the drain of the data writing transistor K1 is connected to the data signal line DL, and the other of the source and the drain of the data writing transistor K1 is connected to the gate of the driving transistor DT.

[0027] One of the source and drain of the driving transistor DT receives a first power signal VDD, and the other of the source and drain of the driving transistor DT receives a second power signal VSS, wherein the first power signal VDD is a high level signal, and the second power signal VSS is a low level signal.

[0028] The gate of the compensation control transistor K2 is connected to a compensation control signal line (not shown) located in the display area 100a, one of the source and the drain of the compensation control transistor K2 is connected to the other of the source and the drain of the driving transistor DT and receives the second power signal VSS, and the other of the source and the drain of the compensation control transistor K2 is connected to the detection chip 30.

[0029] The storage capacitor Cst is connected between the other of the source and the drain of the data write transistor K1 and the other of the source and the drain of the drive transistor DT.

[0030] The light emitting device OLED is connected between the other of the source and the drain of the driving transistor DT and the second power signal VSS.

[0031] See also Figure 3 As shown, the gate driving circuit 20 includes a plurality of gate driving units. The plurality of gate driving units include a first-stage gate driving unit GOA (1), a second-stage gate driving unit GOA (2), a third-stage gate driving unit GOA (3) and a (3n-1)th-stage gate driving unit GOA (3n-1), where n is an integer greater than or equal to 2.

[0032] A plurality of gate driving units are cascaded. Each gate driving unit outputs a level transmission signal to the gate driving unit of the next level. Specifically, the first-level gate driving unit GOA (1) receives the start signal STV and outputs a first-level level transmission signal ST (1) to the second-level gate driving unit GOA (2). The second-level gate driving unit GOA (2) receives the first-level level transmission signal ST (1) and outputs a second-level level transmission signal ST (2). The third-level gate driving unit GOA (3) receives the second-level level transmission signal ST (2) and outputs a third-level level transmission signal ST (3). The (3n-1)th-level gate driving unit GOA (3n-1) receives the (3n-2)th-level level transmission signal ST (3n-2) and outputs the (3n-1)th-level level transmission signal ST (3n-1).

[0033] Each gate driving unit is connected to the first clock signal line CKL1 to receive the first clock signal CK1. Each gate driving unit is connected to the second clock signal line CKL2 to receive the second clock signal CK2. Each gate driving unit is connected to the reset signal line Reset to receive the output control signal RE. Each gate driving unit is connected to the switching control signal line CKBL to receive the switching control signal CKB. Each gate driving unit is connected to the first level signal line VL to receive the first level VGL, which is a low level signal. Each gate driving unit is connected to the second level signal line VL to receive the second level VGH, which is a high level signal. The (3n-2)th gate driving unit (not shown) is connected to the first compensation detection selection signal line LSPL1 to receive the first compensation detection selection signal LP1. For example, the first gate driving unit GOA(1) receives the first compensation detection selection signal LP1. The (3n-1)th gate driving unit GOA(3n-1) is connected to the second compensation detection selection signal line LSPL2 to receive the second compensation detection selection signal LP2, for example, the second gate driving unit GOA(2) receives the second compensation detection selection signal LP2. The (3n)th gate driving unit (not shown) is connected to the third compensation detection selection signal line LSPL3 to receive the third compensation detection selection signal LP3, for example, the third gate driving unit GOA(3) receives the third compensation detection selection signal LP3.

[0034] The output end of the first-stage gate driving unit GOA (1) is connected to the first scanning signal line GL1. The output end of the second-stage gate driving unit GOA (2) is connected to the second scanning signal line GL2. The output end of the third-stage gate driving unit GOA (3) is connected to the third scanning signal line GL3. The output end of the (3n-1)th-stage gate driving unit GOA (3n-1) is connected to the (3n-1)th-stage scanning signal line GL (3n-1).

[0035] Please refer to Figure 5 As shown, one frame time of the display panel 100 includes a display scanning period S1 and a scanning blank period S2, and the scanning blank period S2 is located between the display scanning periods S1 of two adjacent frames. For example, when the refresh rate of the display panel 100 is 120Hz, one frame time is 8.3ms, the display scanning period S1 corresponds to 8ms, and the scanning blank period S2 corresponds to 0.3ms.

[0036] In the display scanning period S1, the gate driving circuit 20 sequentially outputs the display scanning signal WR1 to the multiple rows of pixel driving circuits 200. The data writing transistor K1 is turned on in response to the display scanning signal WR1, and stores the display data signal transmitted by the data signal line DL in the storage capacitor Cst for display.

[0037] During the scanning blank period S2, one gate driving unit GOA among all the gate driving units in the gate driving circuit 20 is randomly controlled to output the compensation detection scanning signal WR2. The data writing transistor K1 receiving the compensation detection scanning signal WR2 is turned on in response to the compensation detection scanning signal WR2, and the compensation control transistor K2 is also turned on, and the detection chip 30 detects the initial threshold voltage of the driving transistor DT. After completing the detection of the initial threshold voltage, the initial threshold voltage of the driving transistor DT is externally compensated, so that the display panel can solve the problem of uneven brightness display during the display process.

[0038] Therefore, in addition to outputting the display scanning signal WR1 during the display scanning period S1, the gate driving circuit 20 can also randomly control a gate driving unit GOA in the gate driving circuit 20 to output a compensation detection scanning signal WR2 during the scanning blank period S2 to detect the initial threshold voltage of the driving transistor DT, which is beneficial to realize external compensation of the driving voltage of the driving transistor DT while realizing display in one frame time, thereby improving the problem of uneven brightness display of the display panel during the display process.

[0039] In addition, since the data writing transistor K1 is a P-type transistor, when the display scanning signal WR1 and the compensation detection scanning signal WR2 are both low-level signals, the data writing transistor K1 is turned on.

[0040] The following is a detailed description of the low-level display scan signal WR1 (3n-1) and the compensation detection scan signal WR2 (3n-1) output by the (3n-1)th gate drive unit GOA (3n-1). The other gate drive units GOA in the gate drive circuit 20 can be deduced in the same manner, and this application will not provide a detailed description.

[0041] Please refer to Figure 4As shown, the (3n-1)th gate driving unit GOA(3n-1) includes an input control module 11, a stage transmission module 12, a compensation detection control module 13, an output module 14, a switching module 15 and a pull-down module 18.

[0042] The input control module 11 is used to output a driving signal in the display scanning period S1 , where the driving signal includes a first driving signal P and a second driving signal D.

[0043] Specifically, the input control module 11 includes a thirteenth transistor T3 and a fourteenth transistor T4. The gate of the thirteenth transistor T3 receives the first clock signal CK1, one of the source and the drain of the thirteenth transistor T3 receives the previous stage transfer signal ST(3n-2), and the other of the source and the drain of the thirteenth transistor T3 outputs the second drive signal D. The gate of the fourteenth transistor T4 receives the first clock signal CK1, one of the source and the drain of the fourteenth transistor T4 receives the first level VGL, and the other of the source and the drain of the fourteenth transistor T4 outputs the first drive signal P.

[0044] The previous stage transmission signal ST(3n-2) is a stage transmission signal output by the gate driving unit of the (3n-2)th stage, but is not limited thereto. When n is equal to 1, one of the source and the drain of the thirteenth transistor T3 receives the start signal STV.

[0045] The level transmission module 12 is connected to the input control module 11. The level transmission module 12 is used to respond to the driving signal in the display scanning period S1 to output the current level transmission signal ST (3n-1). The current level transmission signal ST (3n-1) includes a high-level current level transmission signal and a low-level current level transmission signal that is less than the high-level current level transmission signal.

[0046] The level transmission module 12 includes a fourth transistor T10 and a fifth transistor T9. The gate of the fourth transistor T10 receives the first drive signal P, and one of the source and drain of the fourth transistor T10 receives the second level VGH. The gate of the fifth transistor T9 receives the second drive signal D, and one of the source and drain of the fifth transistor T9 receives the first level VGL. The other of the source and drain of the fifth transistor T9 is connected to the other of the source and drain of the fourth transistor T10. Among them, the other of the source and drain of the fourth transistor T10 outputs a high-level level transmission signal. The other of the source and drain of the fifth transistor T9 outputs a low-level level transmission signal.

[0047] Therefore, the level transmission module 12 selectively outputs one of the second level VGH and the first level VGL according to the second driving signal D and the first driving signal P. The level transmission module 12 outputs the second level VGH as a high level level transmission signal according to the first driving signal P. The level transmission module 12 outputs the first level VGL as a low level level transmission signal according to the second driving signal D.

[0048] The (3n-1)th gate driving unit GOA (3n-1) further includes a third capacitor C3, which is used to stabilize the voltage value of the first driving signal P to ensure that the other of the source and the drain of the fourth transistor T10 can stably output a high-level current transmission signal.

[0049] A first electrode of the third capacitor C3 receives the first driving signal P, and a second electrode of the third capacitor C3 receives the second level VGH. Specifically, the third capacitor C3 is connected between the gate of the fourth transistor T10 and the second level VGH.

[0050] The compensation detection control module 13 is used to output a compensation detection driving signal during the scanning blank period S2 . Specifically, the compensation detection control module 13 includes a detection selection circuit 131 and a detection control circuit 132 .

[0051] The detection selection circuit 131 is used for outputting a detection selection control signal in response to the previous stage transmission signal ST(3n-2) and the compensation detection selection signal during the display scanning period S1.

[0052] Further, the front stage transmission signal ST(3n-2) includes a low level front stage transmission signal and a high level front stage transmission signal greater than the low level front stage transmission signal. The detection selection circuit 131 is used to respond to the low level front stage transmission signal and the low level compensation detection selection signal in the display scanning period S1 to output the detection selection control signal.

[0053] Specifically, the detection selection circuit 131 includes a first transistor T18. During the display scanning period S1, the gate of the first transistor T18 receives the compensation detection selection signal. For example, for the (3n-1)th gate driving unit GOA(3n-1), the gate of the first transistor T18 receives the second compensation detection selection signal LP2. One of the source and the drain of the first transistor T18 receives the previous stage transfer signal ST(3n-2), and the other of the source and the drain of the first transistor T18 outputs the detection selection control signal M.

[0054] When the previous stage transmission signal ST(3n-2) is at a low level, the second compensation detection selection signal LP2 is also controlled to be a low level signal, so that the first transistor T18 outputs a low level detection selection control signal.

[0055] It should be noted that, for the second-stage gate driving unit GOA(2), the first transistor T18 also receives the second compensation detection selection signal LP2. For the first-stage gate driving unit GOA(1) and the (3n-2)-stage gate driving unit, the first transistor T18 receives the first compensation detection selection signal LP1. For the third-stage gate driving unit GOA(3) and the (3n)-stage gate driving unit, the first transistor T18 receives the third compensation detection selection signal LP3. Therefore, the three adjacent gate driving units GOA receive the first compensation detection selection signal LP1, the second compensation detection selection signal LP2 and the third compensation detection selection signal LP3, respectively, but are not limited thereto.

[0056] The detection control circuit 132 is connected to the detection selection circuit 131 and the output module 14. The detection control circuit 132 is used to respond to the detection selection control signal and the output control signal RE during the scanning blank period S2 to output the compensation detection driving signal.

[0057] Specifically, the detection control circuit 132 includes a second transistor T19 , a first capacitor C4 , and a third transistor T20 .

[0058] In the display scanning period S1 , the gate of the second transistor T19 receives the detection selection control signal, and one of the source and the drain of the second transistor receives the first level VGL.

[0059] The first capacitor C4 is used to store the detection selection control signal M outputted by the detection selection circuit 131 in the display scanning period S1. In the display scanning period S1, the first electrode of the first capacitor C4 receives the detection selection control signal M, and the second electrode of the first capacitor C4 receives the first level VGL.

[0060] Specifically, the first capacitor C4 is connected to the gate of the second transistor T19 and one of the source and the drain of the second transistor T19.

[0061] One of the source and drain of the third transistor T20 is connected to the other of the source and drain of the second transistor T19. During the scanning blank period S2, the gate of the third transistor T20 receives the output control signal RE, and the other of the source and drain of the third transistor outputs the compensation detection driving signal.

[0062] The output module 14 is connected to the input control module 11 and the compensation detection control module 13. The output module 14 is used to respond to the driving signal to output the display scanning signal WR1 (3n-1) during the display scanning period S1, and respond to the compensation detection driving signal to output the compensation detection scanning signal WR2 (3n-1) during the scanning blank period S2.

[0063] The display scan signal WR1 (3n-1) includes a valid display scan signal and an invalid display scan signal. The data writing transistor K1 is turned on after receiving the valid display scan signal, and remains turned off after receiving the invalid display scan signal.

[0064] The output module 14 includes a sixth transistor T24 and a seventh transistor T25. In the display scanning period S1, the gate of the sixth transistor T24 receives the first drive signal P, one of the source and the drain of the sixth transistor T24 receives the second level VGH, and the other of the source and the drain of the sixth transistor T24 outputs an invalid display scanning signal. In the display scanning period S1, the gate of the seventh transistor T25 receives the second drive signal D, one of the source and the drain of the seventh transistor T25 receives the first level VGL, and the other of the source and the drain of the seventh transistor T25 outputs a valid display scanning signal.

[0065] Since the second level VGH is a high level, the invalid display scanning signal is a high level signal. The first level VGL is a low level, and the valid display scanning signal is a low level signal.

[0066] During the scanning blank period S2, the seventh transistor T25 receives the compensation detection driving signal, one of the source and the drain of the seventh transistor T25 receives the first level VGL, and the other of the source and the drain of the seventh transistor T25 outputs the compensation detection scanning signal WR2 (3n-1). Since the first level VGL is a low level signal, the compensation detection scanning signal WR2 (3n-1) is also a low level signal.

[0067] In some embodiments, the (3n-1)th gate driving unit GOA(3n-1) further includes a fifth capacitor C5, and the fifth capacitor C5 is used to stabilize the voltage value of the first driving signal P. A first electrode of the fifth capacitor C5 receives the first driving signal P, and a second electrode of the fifth capacitor C5 receives the second level VGH.

[0068] Specifically, the fifth capacitor C5 is connected between the second level VGH and the gate of the sixth transistor T24.

[0069] In some embodiments, the (3n-1)th gate driving unit GOA(3n-1) further includes a switching module 15 connected between the input control module 11 and the output module 14. The switching module 15 is used to connect the input control module 11 and the output module 14 during the display scanning period S1, and to disconnect the input control module 11 and the output module 14 during the scanning blank period S2.

[0070] The switching module 15 includes an eleventh transistor T22 and a twelfth transistor T21. The gate of the eleventh transistor T22 receives the switching control signal CKB, and the source and drain of the eleventh transistor T22 are connected between the gate of the sixth transistor T24 and the input control module 11. The gate of the twelfth transistor T21 receives the switching control signal CKB, and the source and drain of the twelfth transistor T21 are connected between the gate of the seventh transistor T25 and the input control module 11. The eleventh transistor T22 is turned on and transmits the first drive signal P during the display scanning period S1, and is turned off during the scanning blank period S2. The twelfth transistor T21 is turned on and transmits the second drive signal D during the display scanning period S1, and is turned off during the scanning blank period S2.

[0071] Specifically, the gate of the eleventh transistor T22 receives the switching control signal CKB, one of the source and the drain of the eleventh transistor T22 is connected to the other of the source and the drain of the fourteenth transistor T4, and the other of the source and the drain of the eleventh transistor T22 is connected to the gate of the sixth transistor T24. The gate of the twelfth transistor T21 receives the switching control signal CKB, one of the source and the drain of the twelfth transistor T21 is connected to the other of the source and the drain of the thirteenth transistor T3, and the other of the source and the drain of the twelfth transistor T21 is connected to the gate of the seventh transistor T25 and the other of the source and the drain of the third transistor T20.

[0072] In some embodiments, the (3n-1)th gate driving unit GOA (3n-1) further includes a first feedback module 21 and a pull-down module 18 connected to the first feedback module 21. The first feedback module 21 receives the first driving signal P and outputs a feedback signal. The pull-down module 18 receives the feedback signal and outputs a pull-down signal Q1 to pull down the second driving signal D.

[0073] The pull-down module 18 includes an eighth transistor T16. In the display scanning period S1, the gate of the eighth transistor T16 and one of the source and the drain of the eighth transistor T16 receive the feedback signal, and the other of the source and the drain of the eighth transistor T16 outputs a pull-down signal Q1 to the gate of the seventh transistor T25, and the pull-down signal Q1 pulls down the second driving signal D to ensure that the seventh transistor T25 stably outputs a valid display scanning signal in the display scanning period S1.

[0074] The pull-down module 18 further includes a fifteenth transistor T14 and a sixteenth transistor T15. The gate of the fifteenth transistor T14 receives the first clock signal CK1, and one of the source and the drain of the fifteenth transistor T14 receives the previous stage transfer signal ST(3n-2). The gate of the sixteenth transistor T15 receives the first level VGL, and the source and the drain of the fifteenth transistor T14 are connected between the other of the source and the drain of the fifteenth transistor T14 and the gate of the eighth transistor T16.

[0075] The first feedback module 21 includes a ninth transistor T1, a tenth transistor T2, and a second capacitor C1. During the display scan period S1, the gate of the ninth transistor T1 receives the first drive signal P, and one of the source and drain of the ninth transistor T1 receives the second level VGH. During the display scan period S1, one of the source and drain of the tenth transistor T2 receives the second clock signal CK2. The first electrode of the second capacitor C1 is connected to the other of the source and drain of the ninth transistor T1 and the other of the source and drain of the tenth transistor T2. The second electrode of the second capacitor C1 is connected to the gate of the tenth transistor T2 and the gate of the eighth transistor T16.

[0076] The (3n-1)th gate driving unit GOA(3n-1) further includes a second feedback module 22, which receives the first driving signal P, the second driving signal D and the first clock signal CK1. In the display scanning period S1, the second feedback module 22 is used to control the potentials of the first driving signal P and the second driving signal to be opposite.

[0077] Specifically, the second feedback module 22 includes a seventeenth transistor T51 and an eighteenth transistor T52. The gates of the seventeenth transistor T51 and the eighteenth transistor T52 receive the second drive signal D. One of the source and the drain of the eighteenth transistor T52 receives the first clock signal CK1, one of the source and the drain of the eighteenth transistor T52 is connected to one of the source and the drain of the seventeenth transistor T51, and the other of the source and the drain of the seventeenth transistor T51 receives the first drive signal P1.

[0078] The (3n-1)th gate driving unit GOA(3n-1) further includes a third feedback module 26, which receives the second driving signal D, the first driving signal P and the second level VGH. The third feedback module 26 is used to pull up the first driving signal P according to the second driving signal D. The third feedback module 26 includes a nineteenth transistor T8, a gate of the nineteenth transistor T8 receives the second driving signal D, one of a source and a drain of the nineteenth transistor T8 receives the second level VGH, and the other of a source and a drain of the nineteenth transistor T8 receives the first driving signal P.

[0079] The (3n-1)th gate driving unit GOA(3n-1) further includes a fourth feedback module 16, which receives the second driving signal D, the first driving signal P and the second level VGH. The fourth feedback module 16 includes a twentieth transistor T26, the gate of the twentieth transistor T26 receives the second driving signal D, one of the source and the drain of the twentieth transistor T26 receives the second level VGH, and the other of the source and the drain of the twentieth transistor T26 receives the first driving signal P.

[0080] The (3n-1)th level gate driving unit GOA (3n-1) further includes a first voltage stabilizing module 23. The first voltage stabilizing module 23 includes a 21st transistor T6 and a 4th capacitor C2. The gate of the 21st transistor T6 is connected to the first electrode of the 4th capacitor C2, one of the source and the drain of the 21st transistor T6 receives the second clock signal CK2, and the other of the source and the drain of the 21st transistor T6 is connected to the second electrode of the 4th capacitor C2.

[0081] The (3n-1)th level gate driving unit GOA(3n-1) further includes a second voltage stabilizing module 24, which includes a twenty-second transistor T11, the gate of which receives the first level VGL, and the source and drain of which are connected between the gate of the twenty-first transistor T6 and the other of the source and drain of the fourteenth transistor T4.

[0082] The (3n-1)th stage gate driving unit GOA(3n-1) further includes a third voltage stabilizing module 25. The third voltage stabilizing module 25 includes a twenty-third transistor T7, a gate of the twenty-third transistor T7 receives the second clock signal CK2, and a source and a drain of the twenty-third transistor T7 are connected between the other of the source and the drain of the twenty-first transistor T6 and the gate of the fourth transistor T10.

[0083] The (3n-1)th level gate driving unit GOA(3n-1) also includes a fourth voltage stabilizing module 19, which includes a twenty-fourth transistor T12, the gate of which receives the first level VGL, and the source and drain of which are connected between the gate of the fifth transistor T9 and the other of the source and drain of the thirteenth transistor T3.

[0084] The (3n-1)th level gate driving unit GOA(3n-1) also includes a fifth voltage stabilizing module 17, which includes a twenty-fifth transistor T23, the gate of which receives the first level VGL, and the source and drain of which are connected between the gate of the seventh transistor T25 and the other of the source and drain of the third transistor T20.

[0085] It should be noted that the first transistor T18 to the twenty-fifth transistor T23 are all P-type transistors. The fourth transistor T10 and the fifth transistor T9 are all P-type transistors.

[0086] Please refer again Figure 5 As shown, the second gate driving unit GOA (2) is selected as an example for explanation. The selection of the second gate driving unit GOA (2) means that the second gate driving unit GOA (2) outputs the display scanning signal WR1 (2) in the display scanning period S1, and the second gate driving unit GOA (2) is selected in the display scanning period S1, and the second gate driving unit GOA (2) outputs the compensation detection scanning signal WR1 (2) in the scanning blank period S2.

[0087] In the first period t1 of the display scanning period S1 , the first compensation detection selection signal LP1 , the second compensation detection selection signal LP2 , and the third compensation detection selection signal LP3 are all low level signals to initialize the position of the second transistor T19 of each gate driving unit.

[0088] In the second period t2 of the display scanning period S1, the first compensation detection selection signal LP1 and the third compensation detection selection signal LP2 are both high level signals, and the second compensation detection selection signal LP2 is a low level signal. When the first stage transmission signal ST(1) is a low level signal, the first transistor T18 of the second stage gate driving unit GOA(2) is turned on, the first transistor T18 outputs a low level detection selection control signal M(2), and the first capacitor C4 stores the detection selection control signal M(2).

[0089] In the third period t3 of the display scanning period S1 , the switching control signal CKB is switched from the low level to the high level, the eleventh transistor T22 and the twelfth transistor T21 are turned off, and the input control module 11 is disconnected from the output module 14 .

[0090] In the fourth period t4 of the scanning blank period S2, the second transistor T19 of the second-stage gate driving unit GOA (2) is turned on, the output control signal RE is switched to a low level, the third transistor T20 of the second-stage gate driving unit GOA (2) is turned on, the third transistor T20 outputs a low-level compensation detection driving signal, and the seventh transistor T25 outputs a low-level compensation detection scanning signal WR1 (2) according to the low-level compensation detection driving signal. The second scanning signal line GL2 connected to the second-stage gate driving unit GOA (2) outputs the low-level compensation detection scanning signal WR1 (2) to the corresponding data writing transistor K1 of the pixel driving circuit 200, the data writing transistor K1 is turned on, the compensation control transistor K2 is also turned on, and the detection chip 30 detects the initial threshold voltage of the data writing transistor K1.

[0091] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: One frame time of the display panel includes a display scanning period and a scanning blank period, and the display panel includes: A plurality of cascaded gate driving units, each gate driving unit comprising: An input control module, used for outputting a driving signal during the display scanning period; A compensation detection control module, configured to output a compensation detection drive signal during the scanning blank period; and an output module connected to the input control module and the compensation detection control module, and configured to respond to the drive signal to output a display scanning signal during the display scanning period, and respond to the compensation detection drive signal to output a compensation detection scanning signal during the scanning blank period; and The pixel driving circuit is connected to the gate driving unit and is used for receiving the display scanning signal during the display scanning period and receiving the compensation detection scanning signal during the scanning blank period.

2. The display panel according to claim 1, characterized in that: The gate driving unit further comprises: a level transmission module for outputting a level transmission signal of the current level in response to the driving signal during the display scanning period; The compensation detection control module includes: a detection selection circuit for responding to a previous stage transmission signal and a compensation detection selection signal to output the detection selection control signal during the display scanning period; and The detection control circuit is used for responding to the detection selection control signal and the output control signal to output the compensation detection driving signal during the scanning blank period.

3. The display panel according to claim 2, characterized in that: The detection selection circuit comprises: A first transistor, during the display scanning period, a gate of the first transistor receives the compensation detection selection signal, one of a source and a drain of the first transistor receives the previous stage transmission signal, and the other of a source and a drain of the first transistor outputs the detection selection control signal.

4. The display panel according to claim 2 or 3, characterized in that: The detection control circuit comprises: a second transistor, wherein a gate of the second transistor receives the detection selection control signal during the display scanning period, and one of a source and a drain of the second transistor receives a first level; a first capacitor, wherein a first electrode of the first capacitor receives the detection selection control signal during the display scanning period, and a second electrode of the first capacitor receives the first level; and A third transistor, one of the source and the drain of the third transistor is connected to the other of the source and the drain of the second transistor, during the scan blank period, the gate of the third transistor receives the output control signal, and the other of the source and the drain of the third transistor outputs the compensation detection drive signal.

5. The display panel according to claim 2, characterized in that: The driving signal includes a first driving signal and a second driving signal, the current level transmission signal includes a high level current level transmission signal and a low level current level transmission signal which is lower than the high level current level transmission signal, and the level transmission module includes: a fourth transistor, wherein a gate of the fourth transistor receives the first driving signal, one of a source and a drain of the fourth transistor receives a second level, and the other of a source and a drain of the fourth transistor outputs the high-level current-stage transmission signal; A fifth transistor, wherein the gate of the fifth transistor receives the second driving signal, one of the source and the drain of the fifth transistor receives the first level, and the other of the source and the drain of the fifth transistor outputs the low-level current-stage transmission signal.

6. The display panel according to claim 5, characterized in that: The preceding stage transmission signal comprises a low-level preceding stage transmission signal, and the detection selection circuit is used for responding to the low-level preceding stage transmission signal and the compensation detection selection signal to output the detection selection control signal during the display scanning period.

7. The display panel according to claim 5, characterized in that: The display scan signal includes a valid display scan signal and an invalid display scan signal, and the output module includes: a sixth transistor, wherein during the display scanning period, a gate of the sixth transistor receives the first driving signal, one of a source and a drain of the sixth transistor receives a second level, and the other of the source and the drain of the sixth transistor outputs the invalid display scanning signal; and A seventh transistor, in the display scanning period, the gate of the seventh transistor receives the second driving signal, one of the source and the drain of the seventh transistor receives the first level, and the other of the source and the drain of the seventh transistor outputs the effective display scanning signal.

8. The display panel according to claim 7, characterized in that: The gate driving unit further includes: a feedback module, the feedback module being configured to receive the first drive signal and the clock signal during the display scanning period, and output a feedback signal; and A pull-down module is used to receive the feedback signal during the display scanning period to pull down the second driving signal received by the gate of the seventh transistor.

9. The display panel according to claim 8, characterized in that: The pull-down module comprises: An eighth transistor, in the display scanning period, one of the gate, source and drain of the eighth transistor receives the feedback signal, and the other of the source and drain of the eighth transistor is connected to the gate of the seventh transistor.

10. The display panel according to claim 9, characterized in that: The feedback module comprises: a ninth transistor, wherein during the display scanning period, a gate of the ninth transistor receives the first driving signal, and one of a source and a drain of the ninth transistor receives a second level; a tenth transistor, wherein one of a source and a drain of the tenth transistor receives the clock signal during the display scanning period; and a second capacitor, a first electrode of the second capacitor being connected to the other of the source and the drain of the ninth transistor and the other of the source and the drain of the tenth transistor, and a second electrode of the second capacitor being connected to the gate of the tenth transistor and the gate of the eighth transistor.

11. The display panel according to claim 7, characterized in that: The gate driving unit further includes: a switching module, which is used to connect the input control module and the output module during the display scanning period, and is used to disconnect the input control module and the output module during the scanning blank period.

12. The display panel according to claim 11, characterized in that: The switching module comprises: an eleventh transistor, a gate of the eleventh transistor receiving a switching control signal, a source and a drain of the eleventh transistor being connected between the gate of the sixth transistor and the input control module; and A twelfth transistor, a gate of the twelfth transistor receives a switching control signal, and a source and a drain of the twelfth transistor are connected between the gate of the seventh transistor and the input control module.

13. The display panel according to claim 1, characterized in that: The pixel driving circuit comprises: a data writing transistor, a gate of the data writing transistor receives the display scanning signal in the display scanning period and receives the compensation detection scanning signal in the scanning blank period, and one of the source and the drain of the data writing transistor receives the data signal; a driving transistor, wherein a gate of the driving transistor is connected to the other of a source and a drain of the data writing transistor, and one of the source and the drain of the driving transistor receives a first power supply signal; a compensation control transistor, wherein a gate of the compensation control transistor receives a compensation control signal, one of a source and a drain of the compensation control transistor and the other of a source and a drain of the driving transistor receive a second power supply signal, and the other of a source and a drain of the compensation control transistor is connected to a detection chip; and A storage capacitor is connected between the other of the source and the drain of the data write transistor and the other of the source and the drain of the drive transistor.

14. The display panel according to claim 13, characterized in that: The data writing transistor and the compensation control transistor each include a P-type transistor.

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