A gallium nitride semiconductor wafer on a silicon substrate, its preparation method and applications

Abstract

The present invention discloses a silicon substrate gallium nitride semiconductor wafer, a preparation method thereof and an application thereof, relating to the technical field of semiconductor materials. The silicon substrate gallium nitride semiconductor wafer is successively stacked by a silicon single crystal substrate, a silicon carbide single crystal thin film barrier layer, an ultra-thin porous titanium nitride weak bonding decoupling layer, an aluminum nitride single crystal thin film nucleation layer template layer and a gallium nitride single crystal thin film quality improvement layer. The present invention realizes the regulation of the weak bonding decoupling effect of the aluminum nitride single crystal thin film nucleation layer template layer thereon by regulating the pore size and pore density in the ultra-thin porous titanium nitride weak bonding decoupling layer, and further realizes the regulation of the large misfit stress of the silicon substrate gallium nitride material and the improvement of the crack-free thickness, material crystallization quality and preparation efficiency. The silicon substrate gallium nitride semiconductor wafer of the present invention can be applied to the research and production of gallium nitride-based power electronic devices, microwave radio frequency devices and optoelectronic devices.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor materials, and particularly relates to a silicon substrate gallium nitride semiconductor wafer, a preparation method thereof, and an application thereof. Background Art

[0002] Silicon (Si) single crystal substrate has a cubic diamond crystal structure with a lattice constant of 0.5341 nm. The in-plane lattice constant of the Si(111) crystal plane is 0.383 nm, and the in-plane thermal expansion coefficient is 3.59×10 -6 K -1 ; Gallium nitride (GaN) has a hexagonal wurtzite crystal structure with lattice constants a = 0.31885 nm and c = 0.5185 nm. The thermal expansion coefficient of the a-axis is 5.59×10 -6 K -1 and the thermal expansion coefficient of the c-axis is 3.17×10 -6 K -1 . When using a silicon single crystal substrate to prepare and grow gallium nitride (GaN), there will be relatively large lattice mismatch (mismatch degree -16.9%) and thermal mismatch (mismatch degree 56%), and the interface reaction and interface composition interdiffusion problems are also very prominent. Especially when using the conventional high-temperature (such as higher than 1000 °C) low-pressure metalorganic chemical vapor deposition (MOCVD) process for preparation and growth, a large number of silicon (Si) atoms generated by the high-temperature decomposition of the silicon (Si) substrate surface diffuse into the gallium nitride (GaN) epitaxial layer, resulting in uncontrollable n-type heavy doping of the doping concentration. Diffusing upward along the line dislocations will also form silicon (Si) spots and leakage channels, making it difficult to improve the breakdown voltage performance of the silicon (Si) substrate gallium nitride (GaN) power electronic devices. To overcome the typical large-mismatch heteroepitaxy problem in the preparation of silicon (Si) substrate gallium nitride (GaN), on a large-size silicon single crystal substrate, usually, a single crystal aluminum nitride (AlN) thin film with a thickness of at least 100 nm is first prepared as a barrier layer and a buffer layer, and then multiple layers of aluminum gallium nitride (AlGaN) single crystal thin films or multi-period aluminum nitride / gallium nitride (AlN / GaN) superlattices are inserted to form a large-mismatch stress regulation structure to regulate the large-mismatch stress and inhibit the upward extension of line dislocations. However, it is still very difficult to increase the crack-free thickness of the gallium nitride (GaN) single crystal thin film quality improvement layer to more than 5 μm and reduce the dislocation density to 1×10 8 cm -2 or less. Among them, aluminum nitride (AlN) has a hexagonal wurtzite structure with lattice constants a = 0.3112 nm and c = 0.4882 nm; the thermal expansion coefficient of the a-axis is 4.15×10 -6 K -1 and the thermal expansion coefficient of the c-axis is 5.27×10 -6 K -1Commonly, single-crystalline aluminum nitride (AlN) thin films are used as the barrier layer. However, due to the large number of grain boundaries and line dislocations still existing in the single-crystalline aluminum nitride thin films, the effect of blocking silicon (Si) diffusion is limited. Moreover, the effect of introducing multi-layer thin aluminum gallium nitride (AlGaN) or multi-period AlN / GaN superlattices to regulate the large lattice mismatch stress will be weakened as the size of the silicon (Si) substrate increases. The larger the size of the silicon (Si) substrate, the smaller the crack-free thickness of the gallium nitride (GaN) epitaxial layer. Therefore, it is necessary to greatly increase the thickness of aluminum gallium nitride (AlGaN) or the number of periods of the multi-period AlN / GaN superlattices, which greatly reduces the growth efficiency of gallium nitride epitaxial wafers on large-size silicon substrates. This is also one of the reasons why it is difficult to increase the crack-free thickness of the gallium nitride (GaN) epitaxial layer on 6-inch and 8-inch silicon substrates to more than 5 μm and it is difficult to improve the production capacity. Therefore, it is necessary to design a new structure for regulating the large lattice mismatch stress of gallium nitride (GaN) on a silicon (Si) substrate to more effectively block silicon diffusion and improve the crystallization quality, crack-free thickness and material preparation efficiency of the gallium nitride (GaN) epitaxial material on the silicon substrate. Summary of the Invention

[0003] The technical problem to be solved by the present invention is that there is a large lattice mismatch stress in the preparation and growth of gallium nitride materials on a silicon substrate, which is difficult to effectively regulate, and it is difficult to further improve the crystallization quality, crack-free thickness and material preparation efficiency of gallium nitride materials on a silicon substrate. To more effectively block silicon diffusion and reduce the influence of large lattice mismatch stress on the quality of material preparation and growth, a silicon substrate gallium nitride semiconductor wafer including a large lattice mismatch stress regulation structure is provided.

[0004] To solve the above problems, the present invention proposes the following technical solutions:

[0005] In a first aspect, the present invention provides a silicon substrate gallium nitride semiconductor wafer, including:

[0006] A silicon single-crystal substrate with a thickness of 500 - 1000 μm;

[0007] A single-crystalline silicon carbide thin film barrier layer with a thickness of 200 - 500 nm and a 3C-SiC structure, disposed on the silicon single-crystal substrate;

[0008] An ultra-thin porous titanium nitride weak-bonding decoupling layer with a thickness of 10 - 30 nm, disposed on the single-crystalline silicon carbide thin film barrier layer;

[0009] A single-crystalline aluminum nitride thin film nucleation layer template layer with a thickness of 500 - 1000 nm, disposed on the ultra-thin porous titanium nitride weak-bonding decoupling layer;

[0010] A gallium nitride single-crystalline thin film quality improvement layer with a thickness of not less than 5 μm, disposed on the single-crystalline aluminum nitride thin film nucleation layer template layer.

[0011] Understandably, in the gallium nitride semiconductor wafer on a silicon substrate according to the present invention, a large misfit stress regulation structure is added between the silicon single crystal substrate and the gallium nitride epitaxial layer, and through this large misfit stress regulation structure, silicon diffusion is blocked and the influence of the large misfit stress on the material preparation and growth quality is reduced. In the present invention, the large misfit stress regulation structure is composed of a silicon carbide single crystal thin film barrier layer, an ultra-thin porous titanium nitride weak bonding decoupling layer, and an aluminum nitride single crystal thin film nucleation layer template layer stacked in sequence.

[0012] Further, the size of the silicon single crystal substrate includes but is not limited to 1 inch, 2 inches, 4 inches, 6 inches, 8 inches, and 12 inches in diameter.

[0013] The gallium nitride single crystal thin film quality improvement layer has no cracks and the dislocation density is not higher than 1×10 8 cm -2 .

[0014] Further, the porosity of the ultra-thin porous titanium nitride weak bonding decoupling layer is 35-75%.

[0015] Further, the dislocation density of the aluminum nitride single crystal thin film nucleation layer template layer is not higher than 1×10 7 cm -2 and the surface roughness is not higher than 0.5 nm.

[0016] In a second aspect, the present invention provides a method for preparing the gallium nitride semiconductor wafer on a silicon substrate described in the first aspect, including the following steps:

[0017] S1. Prepare a silicon single crystal substrate, and perform high-temperature and high-vacuum baking on the surface of the silicon single crystal substrate to remove the residual oxide layer and adsorbed impurities;

[0018] S2. Form a silicon carbide single crystal thin film barrier layer with a 3C-SiC structure on the silicon single crystal substrate;

[0019] S3. Form an ultra-thin indium titanium nitride single crystal thin film layer with a single C-axis preferred orientation on the silicon carbide single crystal thin film barrier layer;

[0020] S4. Form an aluminum nitride single crystal thin film layer with a single C-axis preferred orientation on the ultra-thin indium titanium nitride single crystal thin film layer with a single C-axis preferred orientation;

[0021] S5. Perform high-temperature and high-vacuum annealing in a hydrogen atmosphere so that the indium component in the ultra-thin indium titanium nitride single crystal thin film layer is completely thermally decomposed and precipitates from the grain gaps in the aluminum nitride single crystal thin film layer with a single C-axis preferred orientation, to obtain the ultra-thin porous titanium nitride weak bonding decoupling layer;

[0022] S6. Perform high-temperature and high-vacuum annealing in an ammonia atmosphere, where the grains in the aluminum nitride single-crystal thin film layer with a single preferred orientation in the C direction fuse, merge, and recrystallize to obtain the aluminum nitride single-crystal thin film nucleation layer template layer;

[0023] S7. Form a gallium nitride single-crystal thin film quality improvement layer on the aluminum nitride single-crystal thin film nucleation layer template layer.

[0024] Further, in step S5, the conditions for high-temperature and high-vacuum annealing in a hydrogen atmosphere are: the hydrogen atmosphere pressure is 30 - 50 Pa, the annealing temperature is 650 - 850 °C, and the high-temperature and high-vacuum annealing is carried out for 1.0 - 3.0 hours.

[0025] Further, in step S6, the conditions for high-temperature and high-vacuum annealing in an ammonia atmosphere are: the ammonia atmosphere pressure is 50 - 100 Pa, the annealing temperature is 1000 - 1200 °C, and the high-temperature and high-vacuum annealing is carried out for 1.0 - 5.0 hours.

[0026] The present invention also provides the silicon substrate gallium nitride semiconductor wafer described above, or the silicon substrate gallium nitride semiconductor wafer prepared by the method can be applied to the research and production of gallium nitride-based power electronic devices, gallium nitride-based microwave radio frequency devices, gallium nitride-based light-emitting diode devices, gallium nitride-based laser diode devices, and gallium nitride-based ultraviolet detection devices.

[0027] Compared with the prior art, the technical effects that the present invention can achieve include:

[0028] The silicon substrate gallium nitride semiconductor wafer provided by the present invention is composed of a silicon single-crystal substrate, a silicon carbide (3C-SiC) single-crystal thin film barrier layer, an ultrathin porous titanium nitride (TiN) weak-bond decoupling layer, an aluminum nitride (AlN) single-crystal thin film nucleation layer template layer, and a gallium nitride (GaN) single-crystal thin film quality improvement layer stacked in sequence. Among them, the silicon carbide single-crystal thin film barrier layer with a 3C-SiC structure is denser than the conventional aluminum nitride (AlN) single-crystal thin film barrier layer, can better block the thermal diffusion of silicon (Si) atoms generated by the high-temperature decomposition of the silicon (Si) substrate surface into the gallium nitride (GaN) epitaxial layer, and provides a good template for the single-crystal preparation and growth of subsequent other structural layers; the a-axis thermal expansion coefficient of titanium nitride (TiN) is 9.5×10 -6 K -1, larger than that of silicon (Si), gallium nitride (GaN), aluminum nitride (AlN), and aluminum oxide (Al2O3). The ultra-thin porous titanium nitride weak-bonding decoupling layer of the present invention can more effectively coordinate the thermal stress generated during the large-scale cooling process and is not affected by the expansion of the size of the silicon (Si) single crystal substrate. The aluminum nitride (AlN) single crystal thin film nucleation layer template layer of the present invention has a higher crystal quality than the conventional aluminum nitride (AlN) single crystal thin film barrier layer buffer layer and the multi-layer aluminum gallium nitride (AlGaN) single crystal thin film composition gradient buffer layer. It can not only provide a single crystal thin film template with better crystal quality but also more effectively reduce the lattice mismatch stress and dislocation density of the gallium nitride (GaN) single crystal thin film quality improvement layer. By controlling the thickness and porosity of the ultra-thin porous titanium nitride (TiN) weak-bonding decoupling layer, not only can the large mismatch stress and dislocation density of the gallium nitride (GaN) single crystal thin film quality improvement layer be further reduced, but also the crack-free thickness and yield of the gallium nitride (GaN) single crystal thin film quality improvement layer can be significantly improved.

[0029] Further, according to the method for preparing a gallium nitride semiconductor wafer on a silicon substrate of the present invention, the ultra-thin porous titanium nitride (TiN) weak-bonding decoupling layer is formed by subjecting an indium titanium nitride (InTiN) ultra-thin single crystal layer containing indium (In) components to a high-temperature and high-vacuum annealing process in a hydrogen atmosphere to completely thermally decompose and precipitate the indium (In) components. Among them, the indium titanium nitride (InTiN) single crystal thin film material with a high content of indium (In) components has strong polarity and is easy to achieve the single-crystal growth of the hexagonal crystal structure with a single preferred orientation of the C-axis of regularly arranged grains on the surface of the silicon carbide (3C-SiC) single crystal thin film barrier layer. Taking the ultra-thin indium titanium nitride (InTiN) layer with a single preferred orientation of the C-axis of the hexagonal crystal structure as a template, the single-crystal growth of aluminum nitride (AlN) with regularly arranged grains and a single preferred orientation of the C-axis of the hexagonal crystal structure can also be achieved. After the high-temperature and high-vacuum annealing treatment in a hydrogen atmosphere, the indium (In) components in the ultra-thin indium titanium nitride (InTiN) single crystal layer will completely decompose and precipitate along the grain gaps of the upper aluminum nitride (AlN) single crystal thin film layer, thereby forming an ultra-thin porous titanium nitride (TiN) weak-bonding decoupling layer. The ultra-thin porous titanium nitride (TiN) weak-bonding decoupling layer can further achieve weak bonding and decoupling between the aluminum nitride (AlN) single crystal thin film nucleation layer template layer thereon and the bottom silicon (Si) substrate and the silicon carbide (3C-SiC) single crystal thin film barrier layer. The aluminum nitride (AlN) single crystal thin film nucleation layer template layer with weak bonding and decoupling is then subjected to a high-temperature and high-vacuum annealing process in an ammonia atmosphere. Only by annealing at a high temperature of 1000 - 1200 °C and high vacuum can the grains in the aluminum nitride (AlN) single crystal thin film fuse and merge and then recrystallize to form an aluminum nitride (AlN) single crystal thin film nucleation layer template layer with higher crystal quality, which has a lower recrystallization temperature (1400 - 1600 °C) than that of the conventional aluminum nitride thin film on a sapphire substrate.

[0030] Furthermore, the structure of the silicon substrate gallium nitride semiconductor wafer provided by the present invention can realize the large mismatch stress regulation of silicon substrate gallium nitride. The "unsupported substrate" model design based on the flexible substrate is compared with the existing flexible substrate preparation technology, such as sacrificial layer bonding technology, ion implantation buried layer technology and few-layer two-dimensional material technology, etc., in which the weak bond decoupling effect is difficult to control. The pore size and pore density in the film layer after high-temperature and high-vacuum annealing can be controlled by regulating the indium (In) component concentration and layer thickness in the ultra-thin indium titanium nitride (InTiN) film, thereby achieving the effect regulation of the weak bond decoupling of the aluminum nitride (AlN) single crystal thin film nucleation layer template layer thereon. Ultra-thin porous titanium nitride (TiN) weakly bonded decoupling layers with different thicknesses, pore sizes, and densities are designed and prepared on silicon (Si) single crystal substrates of different sizes. This can not only significantly improve the crystalline quality of the aluminum nitride (AlN) single crystal thin film nucleation layer and template layer thereon, but also significantly reduce the stress and dislocation density of the subsequent epitaxially grown thicker gallium nitride (GaN) single crystal thin film quality improvement layer, and significantly improve the crack-free thickness and material preparation growth efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 This is a schematic diagram of the structure of a silicon substrate gallium nitride semiconductor wafer according to Example 1 of the present invention. Reference numeral 100 represents a silicon substrate, comprising a silicon single crystal substrate 101; reference numeral 200 represents a large mismatch stress control structure, comprising a silicon carbide single crystal thin film barrier layer 201, an ultra-thin porous titanium nitride weakly bonded decoupling layer 202, and an aluminum nitride single crystal thin film nucleation layer template layer 203, stacked in sequence; and reference numeral 300 represents a gallium nitride epitaxial layer, comprising a gallium nitride single crystal thin film quality enhancement layer 301.

[0033] Figure 2 This is a schematic diagram of the structure of an ultrathin InTiN single crystal thin film layer and an aluminum nitride single crystal thin film layer having a single preferred C-direction orientation formed on the silicon carbide single crystal thin film barrier layer 201 in the method for preparing a gallium nitride semiconductor wafer on a silicon substrate according to Example 1 of the present invention. Reference numeral 2021 represents the ultrathin InTiN single crystal thin film layer, and reference numeral 2031 represents the aluminum nitride single crystal thin film layer.

[0034] Figure 3In the method for preparing a silicon substrate gallium nitride semiconductor wafer according to Embodiment 1 of the present invention, after high-temperature and high-vacuum annealing, a schematic structural diagram of an ultrathin porous titanium nitride weakly bonded decoupling layer 202 and an aluminum nitride single-crystal thin film nucleation layer template layer 203 is formed on the silicon carbide single-crystal thin film barrier layer 201. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the embodiments described below are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0036] It should be understood that when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0037] It should also be understood that the terms used in the specification of the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present invention. As used in the specification of the embodiments of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms.

[0038] Embodiment 1

[0039] This embodiment discloses a 6-inch silicon substrate gallium nitride semiconductor wafer, and its structure is as Figure 1 shown. Among them, 100 is a silicon substrate, which is composed of a silicon single-crystal substrate 101, 200 is a large misfit stress regulation structure, which is composed of a silicon carbide single-crystal thin film barrier layer 201, an ultrathin porous titanium nitride weakly bonded decoupling layer 202, and an aluminum nitride single-crystal thin film nucleation layer template layer 203 stacked in sequence, and 300 is a gallium nitride epitaxial layer, which is composed of a gallium nitride single-crystal thin film quality improvement layer 301.

[0040] Further referring to Figure 2 and Figure 3 , the structure and preparation method of the silicon substrate gallium nitride semiconductor wafer in this embodiment are introduced as follows:

[0041] A 6-inch thick 1000 μm thick silicon single-crystal substrate (101).

[0042] A silicon carbide single crystal thin film barrier layer (201) with a thickness of 200 nm and a 3C-SiC structure is formed on a 6-inch silicon single crystal substrate (101) with a thickness of 1000 μm by using a high-temperature chemical vapor deposition (HTCVD) process at 1100°C.

[0043] A 30-nm-thick ultra-thin porous titanium nitride weakly bonded decoupling layer (202) and a 500-nm-thick aluminum nitride single crystal thin film nucleation layer template layer (203). In this embodiment, the above structure is prepared by using a medium-high temperature plasma-enhanced chemical vapor deposition (PECVD) process at 650°C on a 200-nm-thick silicon carbide single crystal thin film barrier layer (101) to sequentially form a 30-nm-thick ultra-thin indium titanium nitride (InTiN) single crystal layer (2021) with a C-axis single preferred orientation and an indium component atomic percentage concentration of 75% and a 500-nm-thick aluminum nitride single crystal thin film layer (2031) with a C-axis single preferred orientation. First, a high-temperature and high-vacuum annealing is performed for 0.5 hours at a hydrogen atmosphere pressure of 30 Pa and an annealing temperature of 900°C, so that the indium (In) component in the ultra-thin indium titanium nitride (InTiN) single crystal layer (2021) is completely thermally decomposed and precipitates from the grain gaps and grain boundaries in the aluminum nitride single crystal thin film layer (2031) to form the ultra-thin porous titanium nitride weakly bonded decoupling layer (202); then, a high-temperature and high-vacuum annealing is performed for 1 hour at an ammonia atmosphere pressure of 50 Pa and an annealing temperature of 1100°C, so that the grains in the aluminum nitride single crystal thin film layer (2031) merge and recrystallize to form the aluminum nitride single crystal thin film nucleation layer template layer (203); in this embodiment, the indium (In) component atomic percentage concentration in the ultra-thin indium titanium nitride (InTiN) single crystal layer (2021) is 75%, the porosity of the ultra-thin porous titanium nitride weakly bonded decoupling layer (202) is 75%, and the dislocation density of the aluminum nitride single crystal thin film nucleation layer template layer (203) is not higher than 1×10 7 cm -2 and the surface roughness is not higher than 0.5 nm.

[0044] In other embodiments, a medium-high temperature plasma-enhanced chemical vapor deposition (PECVD) process at 550 - 750°C can be used to sequentially form an ultra-thin indium titanium nitride (InTiN) single crystal layer (2021) with a C-axis single preferred orientation and an aluminum nitride single crystal thin film layer with a C-axis single preferred orientation.

[0045] A gallium nitride single crystal thin film quality improvement layer (301) without cracks and with a thickness of not less than 10 μm is grown on the above 500-nm-thick aluminum nitride single crystal thin film nucleation layer template layer (203) by using a conventional metalorganic chemical vapor deposition (MOCVD) process at 1050°C; in this embodiment, the dislocation density of the gallium nitride single crystal thin film quality improvement layer (301) is not higher than 5×10 7 cm -2 .

[0046] The 6-inch gallium nitride semiconductor wafer on silicon substrate prepared by the above embodiment can be used for developing and producing high-frequency high-power gallium nitride-based microwave radio frequency devices.

[0047] Example 2

[0048] Further refer to Figures 1-3 This embodiment provides an 8-inch gallium nitride semiconductor wafer on silicon substrate. The structure of the 8-inch gallium nitride semiconductor wafer on silicon substrate sequentially includes from bottom to top:

[0049] An 8-inch silicon single crystal substrate (101) with a thickness of 1500 μm;

[0050] A silicon carbide single crystal thin film barrier layer (201) with a thickness of 300 nm;

[0051] An ultrathin porous titanium nitride weak bonding decoupling layer (202) with a thickness of 20 nm;

[0052] A nucleation layer template layer (203) of aluminum nitride single crystal thin film with a thickness of 1000 nm;

[0053] A gallium nitride single crystal thin film quality improvement layer (301) with a crack-free thickness of not less than 7 μm.

[0054] The preparation method of the above 8-inch gallium nitride semiconductor wafer on silicon substrate includes the following:

[0055] S1. Prepare an 8-inch silicon single crystal substrate (101), and perform surface high-temperature and high-vacuum baking on the silicon single crystal substrate (101) at a hydrogen atmosphere pressure of 20 Pa and a substrate heating temperature of 1100 °C to remove the residual oxide layer and adsorbed impurities.

[0056] S2. On the 8-inch silicon single crystal substrate (101), a silicon carbide single crystal thin film barrier layer (201) with a 3C-SiC structure is prepared by low-energy ion beam deposition process at a medium-high temperature of 750 - 850 °C. In this embodiment, a silicon carbide single crystal thin film barrier layer (201) with a 3C-SiC structure is prepared by low-energy ion beam deposition process at a medium-high temperature of 750 °C.

[0057] S3. On the silicon carbide single crystal thin film barrier layer (201), an ultrathin indium titanium nitride single crystal thin film layer (2021) with a single preferred orientation in the C direction is prepared by pulsed DC magnetron sputtering process at a medium-high temperature of 550 - 750 °C. The atomic percentage concentration of indium component in the ultrathin indium titanium nitride single crystal layer (2021) in this embodiment is 65%; in this embodiment, an ultrathin indium titanium nitride single crystal thin film layer (2021) with a single preferred orientation in the C direction is prepared by pulsed DC magnetron sputtering process at a medium-high temperature of 750 °C.

[0058] S4. On the ultra-thin indium titanium nitride single-crystalline thin film layer (2021) with a single preferred orientation in the C direction, an aluminum nitride single-crystalline thin film layer (2031) with a single preferred orientation in the C direction is formed by using a pulsed magnetron sputtering process at a medium-high temperature of 550 - 750 °C; in this embodiment, an aluminum nitride single-crystalline thin film layer (2031) with a single preferred orientation in the C direction is formed by using a pulsed magnetron sputtering process at a medium-high temperature of 750 °C.

[0059] S5. Under the conditions of a hydrogen atmosphere pressure of 50 Pa and a high temperature of 850 °C, high-temperature and high-vacuum annealing is carried out for 1.0 hour to completely thermally decompose the indium component in the ultra-thin indium titanium nitride single-crystalline thin film layer (2021) and precipitate it from the grain gaps and grain boundaries in the aluminum nitride single-crystalline thin film layer (2031) with a single preferred orientation in the C direction, obtaining the ultra-thin porous titanium nitride weakly bonded decoupling layer (202). The porosity of the ultra-thin porous titanium nitride weakly bonded decoupling layer (202) in this embodiment is 65%.

[0060] S6. Under the conditions of an ammonia atmosphere pressure of 100 Pa and a high temperature of 1150 °C, high-temperature and high-vacuum annealing is carried out for 2 hours to fuse, merge, and recrystallize the grains in the aluminum nitride single-crystalline thin film layer (2031) with a single preferred orientation in the C direction, obtaining the aluminum nitride single-crystalline thin film nucleation layer template layer (203). In this embodiment, the dislocation density of the aluminum nitride single-crystalline thin film nucleation layer template layer (203) is not higher than 2×10 7 cm -2 and the surface roughness is not higher than 0.6 nm.

[0061] S7. On the aluminum nitride single-crystalline thin film nucleation layer template layer (203), a gallium nitride single-crystalline thin film quality improvement layer (301) with a thickness of not less than 7 μm is formed by using a metalorganic chemical vapor deposition process at a high temperature of 1050 °C. In this embodiment, the gallium nitride single-crystalline thin film quality improvement layer (301) has no cracks and the dislocation density is not higher than 6×10 7 cm -2 。

[0062] The 8-inch silicon substrate gallium nitride semiconductor wafer prepared by using the above embodiment can be used to develop and produce gallium nitride-based power electronic devices with a breakdown voltage of not less than 1200 V.

[0063] The gallium nitride semiconductor wafer on a silicon substrate provided by an embodiment of the present invention uses a large misfit stress regulation structure composed of a single-crystal thin film barrier layer of silicon carbide (3C-SiC), an ultra-thin porous titanium nitride (TiN) weak-bond decoupling layer, and a single-crystal thin film nucleation layer template layer of aluminum nitride (AlN) to regulate the large misfit stress of gallium nitride on a silicon substrate. It can not only further improve the crystallization quality, crack-free thickness, and material preparation efficiency of the gallium nitride material on a silicon substrate, but also more effectively block silicon diffusion and reduce the influence of large misfit stress on the growth quality of material preparation.

[0064] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0065] The above is the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A gallium nitride semiconductor wafer on a silicon substrate, characterized in that, Comprising: A silicon single crystal substrate with a thickness of 500 - 1000 µm; A silicon carbide single crystal thin film barrier layer with a 3C - SiC structure and a thickness of 200 - 500 nm, disposed on the silicon single crystal substrate; An ultra - thin porous titanium nitride weak - bonding decoupling layer with a thickness of 10 - 30 nm, disposed on the silicon carbide single crystal thin film barrier layer; An aluminum nitride single crystal thin film nucleation layer template layer with a thickness of 500 - 1000 nm, disposed on the ultra - thin porous titanium nitride weak - bonding decoupling layer; A gallium nitride single crystal thin film quality improvement layer with a thickness of not less than 5 µm, disposed on the aluminum nitride single crystal thin film nucleation layer template layer; The ultra - thin porous titanium nitride weak - bonding decoupling layer is formed by subjecting an indium - titanium - nitrogen ultra - thin single crystal layer containing indium components to a high - temperature and high - vacuum annealing process in a hydrogen atmosphere, so that the indium components are completely thermally decomposed and precipitated.

2. The gallium nitride semiconductor wafer on a silicon substrate according to claim 1, wherein The size of the silicon single crystal substrate includes diameters of 1 inch, 2 inches, 4 inches, 6 inches, 8 inches, and 12 inches.

3. The gallium nitride semiconductor wafer on a silicon substrate according to claim 2, characterized in that, The gallium nitride single crystal thin film quality improvement layer has no cracks and the dislocation density is not higher than 1×10 8 cm -2 .

4. The gallium nitride semiconductor wafer on a silicon substrate according to claim 1, wherein, The porosity of the ultra - thin porous titanium nitride weak - bonding decoupling layer is 35 - 75%.

5. The gallium nitride semiconductor wafer on a silicon substrate according to claim 1, wherein The dislocation density of the nucleation layer template layer of the aluminum nitride single crystal thin film is not higher than 1×10 7 cm -2 and the surface roughness is not higher than 0.5 nm.

6. A method for preparing a gallium nitride semiconductor wafer on a silicon substrate according to any one of claims 1-5, characterized in that, Including the following steps: S1. Prepare a silicon single crystal substrate, and perform high - temperature and high - vacuum baking on the surface of the silicon single crystal substrate to remove the residual oxide layer and adsorbed impurities; S2. Form a silicon carbide single crystal thin film barrier layer with a 3C - SiC structure on the silicon single crystal substrate; S3. Form an ultra - thin indium - titanium - nitrogen single crystal thin film layer with a single preferred orientation in the C - direction on the silicon carbide single crystal thin film barrier layer; S4. Form an aluminum nitride single crystal thin film layer with a single preferred orientation in the C - direction on the ultra - thin indium - titanium - nitrogen single crystal thin film layer with a single preferred orientation in the C - direction; S5. Perform high - temperature and high - vacuum annealing in a hydrogen atmosphere, so that the indium components in the ultra - thin indium - titanium - nitrogen single crystal thin film layer are completely thermally decomposed and precipitated from the grain boundaries of the aluminum nitride single crystal thin film layer with a single preferred orientation in the C - direction, obtaining the ultra - thin porous titanium nitride weak - bonding decoupling layer; S6. Perform high - temperature and high - vacuum annealing in an ammonia atmosphere, and the grains in the aluminum nitride single crystal thin film layer with a single preferred orientation in the C - direction are fused and recrystallized, obtaining the aluminum nitride single crystal thin film nucleation layer template layer; S7. Form a gallium nitride single crystal thin film quality improvement layer on the aluminum nitride single crystal thin film nucleation layer template layer.

7. The method for preparing the gallium nitride semiconductor wafer on the silicon substrate as claimed in claim 6, wherein In step S5, the high - temperature and high - vacuum annealing conditions in a hydrogen atmosphere are: hydrogen atmosphere pressure 30 - 50 Pa, annealing temperature 650 - 850 °C, and high - temperature and high - vacuum annealing time 1.0 - 3.0 hours.

8. The method for preparing the gallium nitride semiconductor wafer on a silicon substrate according to claim 6, wherein, In step S6, the high - temperature and high - vacuum annealing conditions in an ammonia atmosphere are: ammonia atmosphere pressure 50 - 100 Pa, annealing temperature 1000 - 1200 °C, and high - temperature and high - vacuum annealing time 1.0 - 5.0 hours.

9. The method for preparing the gallium nitride semiconductor wafer on a silicon substrate as claimed in claim 6, wherein, The atomic percentage concentration of indium components in the ultra - thin indium - titanium - nitrogen single crystal thin film layer is 35 - 75%.

10. The gallium nitride semiconductor wafer on a silicon substrate according to any one of claims 1-5, or the gallium nitride semiconductor wafer on a silicon substrate prepared by the method according to any one of claims 6-9 is applied to the research, development and production of gallium nitride-based power electronic devices, gallium nitride-based microwave radio frequency devices, gallium nitride-based light-emitting diode devices, gallium nitride-based laser diode devices, and gallium nitride-based ultraviolet detection devices.

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