A kind of micro low-sensitivity double-sided heat dissipation semiconductor power discrete device and preparation method

Abstract

This application belongs to the technical field of semiconductor devices, and discloses a miniature low-inductance double-sided heat dissipation type semiconductor power discrete device and a preparation method thereof, which includes a TEC substrate, a chip, a plurality of molybdenum grains and a plastic package. The TEC substrate includes a heat dissipation plate, a PN junction layer and a heat collecting plate. The chip is mounted on the bottom of the heat collecting plate. The plurality of molybdenum grains are welded and connected to each electrode of the chip. The plastic package wraps the TEC substrate, the chip and the molybdenum grains, and the top of the heat dissipation plate and the bottom of the molybdenum grains are exposed. This structural design realizes active heat dissipation through the TEC substrate, and at the same time uses molybdenum grains to replace traditional pins and cancels internal leads or conductive sheets, reducing parasitic parameters, and has the advantages of good heat dissipation performance, excellent electrical characteristics and small volume.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more particularly, to a micro low-inductance double-sided heat dissipation type semiconductor power discrete device and a manufacturing method thereof. Background Art

[0002] The structure of a traditional power discrete device is as Figure 14 shown, including a heat sink 1', a chip 2', a conductive sheet 3' or bonding wire, pins 4', and a plastic package (not shown in the figure). The chip 2' is mounted on the heat sink 1' and electrically connected to the pins 4' through the conductive sheet 3' or bonding wire. Among them, the heat sink 1' is usually a simple plate-like structure (such as a copper plate, a copper-clad ceramic plate, etc.).

[0003] When such a power discrete device is working, heat is generated inside the chip 2'. Relying on the characteristic of heat conduction from high temperature to low temperature, the heat is diffused to the heat sink 1' and then dissipated to the external heat dissipation structure by the heat sink 1'. This heat dissipation method completely relies on passive heat conduction by contact and is limited by the specific heat capacity of the heat sink 1' inside the device. When the heat fills the heat sink 1' inside the device, a thermal equilibrium will be formed between the internal heat and the outside, restricting the continuous dissipation of heat and resulting in poor heat dissipation performance.

[0004] In addition, due to the existence of the pins 4' and the conductive sheet 3' or bonding wire between the pins 4' and the chip 2', parasitic parameters such as parasitic inductance, parasitic resistance, and parasitic capacitance will be generated. These parasitic parameters will cause problems such as a decrease in device stability, an increase in power consumption, noise interference, and a reduction in switching speed.

[0005] The power discrete devices in the prior art also have disadvantages such as large volume, low heat dissipation efficiency, and poor electrical performance. With the development of electronic products towards miniaturization and high performance, the requirements for the heat dissipation performance, electrical characteristics, and size of power discrete devices are getting higher and higher.

[0006] In view of the above problems, the prior art urgently needs to be improved. Summary of the Invention

[0007] The purpose of the present application is to provide a micro low-inductance double-sided heat dissipation type semiconductor power discrete device and a manufacturing method thereof, which have the advantages of good heat dissipation performance, excellent electrical characteristics, and small size.

[0008] In a first aspect, the present application provides a micro low-inductance double-sided heat dissipation type semiconductor power discrete device, including:

[0009] TEC substrate, the TEC substrate includes a heat dissipation plate, a PN junction layer, and a heat collection plate stacked in sequence from top to bottom; a first copper clad layer is provided on the lower surface of the heat collection plate; a positive electrode pad and a negative electrode pad are also provided downward on the TEC substrate, and the positive electrode pad and the negative electrode pad are respectively electrically connected to the positive and negative current input ends of the PN junction layer;

[0010] A chip, the chip is mounted on the bottom of the heat collection plate, a drain is provided on the top of the chip, a gate, a Kelvin source electrode, and a source electrode are provided on the bottom of the chip, and the drain is soldered and connected to the first copper clad layer;

[0011] Multiple molybdenum grains, including a gate molybdenum grain soldered and connected to the gate, a Kelvin source electrode molybdenum grain soldered and connected to the Kelvin source electrode, a source electrode molybdenum grain soldered and connected to the source electrode, a drain molybdenum grain soldered and connected to the first copper clad layer, a positive electrode molybdenum grain soldered and connected to the positive electrode pad, and a negative electrode molybdenum grain soldered and connected to the negative electrode pad; the molybdenum grains are used for electrical connection with an external circuit;

[0012] A plastic package body, the plastic package body wraps the TEC substrate, the chip, and the molybdenum grains, and the top of the heat dissipation plate and the bottom of each molybdenum grain are exposed.

[0013] This structural design realizes active heat dissipation through the TEC substrate. At the same time, by using molybdenum grains to replace traditional pins and canceling internal leads or conductive sheets, the parasitic parameters are reduced, and it has the advantages of good heat dissipation performance, excellent electrical characteristics, and small volume.

[0014] Preferably, the chip is a silicon carbide MOSFET chip.

[0015] The silicon carbide MOSFET chip can work stably at a higher temperature, which complements the double-sided heat dissipation design of the device and further improves the heat dissipation efficiency. At the same time, the silicon carbide MOSFET chip has a faster switching speed and lower switching loss, which helps to reduce the overall power consumption of the device and improve the energy conversion efficiency. In addition, the silicon carbide MOSFET chip has a higher breakdown voltage, enabling the device to withstand a higher operating voltage and expanding the application range.

[0016] Preferably, the positive electrode pad is provided on the lower surface of the heat dissipation plate or the lower surface of the heat collection plate; the negative electrode pad is provided on the lower surface of the heat dissipation plate or the lower surface of the heat collection plate.

[0017] Preferably, one side of the heat dissipation plate extends beyond the range of the heat collection plate, and the positive electrode pad and the negative electrode pad are provided on the lower surface of the part where the heat dissipation plate extends beyond the range of the heat collection plate.

[0018] This arrangement provides additional mounting space for the positive and negative pads by extending one side of the heat dissipation plate beyond the range of the heat collection plate. Placing these two pads on the lower surface of the extended part of the heat dissipation plate can effectively utilize the space of the device without affecting the installation and heat dissipation effect of the chip. This design solves the problem of arranging pads in a limited space, enabling the positive and negative pads to be conveniently connected to the external circuit without interfering with the installation and function of the chip. In addition, since the positive and negative pads are located on the extended part of the heat dissipation plate, they are at a certain distance from the chip, which can reduce electromagnetic interference and improve the overall performance of the device.

[0019] Preferably, one gate and one gate molybdenum particle are provided, two Kelvin source electrodes and two Kelvin source molybdenum particles are provided, two source electrodes and two source molybdenum particles are provided, and two drain molybdenum particles are provided; the centers of the gate and the gate molybdenum particle are located on a symmetry plane perpendicular to the bottom surface of the chip, and the two Kelvin source electrodes, the two Kelvin source molybdenum particles, the two source electrodes, the two source molybdenum particles, the two drain molybdenum particles, and between the positive molybdenum particle and the negative molybdenum particle are symmetrically arranged with respect to the symmetry plane.

[0020] Preferably, a second copper-clad layer is provided on the top of the heat dissipation plate; a third copper-clad layer is provided at the bottom of each molybdenum particle.

[0021] Preferably, the area ratio of the chip at the bottom of the heat collection plate is more than 95%.

[0022] In a second aspect, the present application provides a preparation method for preparing the above-mentioned micro low-inductance double-sided heat dissipation type semiconductor power discrete device, including the steps:

[0023] A1. Place the TEC substrate face down in the positioning jig.

[0024] A2. Stack a first solder chip on the first copper-clad layer on the bottom surface of the TEC substrate.

[0025] A3. Stack the chip face down on the first solder chip, making the drain at the top of the chip contact the first solder chip, and the first solder chip partially exposed outside the range of the chip.

[0026] A4. Stack second solder chips on the gate, Kelvin source electrode, and source electrode at the bottom of the chip respectively, and on the positive and negative pads of the TEC substrate.

[0027] A5. Stack the corresponding molybdenum particles on each of the second solder chips and at the positions where the first solder chip is exposed outside the range of the chip to obtain a first semi-finished product.

[0028] While applying downward pressure to the first semi-finished product, perform reflow soldering on the first semi-finished product using vacuum reflow soldering technology to obtain a second semi-finished product;

[0029] A7. Perform plastic encapsulation molding on the second semi-finished product to obtain a finished product;

[0030] A8. Perform test taping and packaging on the finished product.

[0031] Preferably, step A6 includes:

[0032] Stack the auxiliary counterweight on the first semi-finished product to apply pressure to the first semi-finished product;

[0033] Send the auxiliary counterweight, the first semi-finished product, and the positioning fixture into a vacuum reflow soldering device for reflow soldering to obtain a second semi-finished product.

[0034] Preferably, step A7 includes:

[0035] Perform plastic encapsulation on the second semi-finished product so that the plastic encapsulation body completely wraps the second semi-finished product;

[0036] Etch the plastic encapsulation body on the top of the second semi-finished product to expose the top of the TEC substrate;

[0037] Etch the plastic encapsulation body on the bottom of the second semi-finished product to expose the bottoms of the molybdenum grains.

[0038] Beneficial effects: The micro low-inductance double-sided heat dissipation type semiconductor power discrete device and preparation method provided by this application include a TEC substrate, a chip, a plurality of molybdenum grains, and a plastic encapsulation body. The TEC substrate includes a heat dissipation plate, a PN junction layer, and a heat collection plate. The chip is mounted on the bottom of the heat collection plate. The plurality of molybdenum grains are welded and connected to the respective electrodes of the chip. The plastic encapsulation body wraps the TEC substrate, the chip, and the molybdenum grains, and the top of the heat dissipation plate and the bottoms of the molybdenum grains are exposed. This structural design realizes active heat dissipation through the TEC substrate, and at the same time uses molybdenum grains to replace traditional pins and eliminates internal leads or conductive sheets, reducing parasitic parameters, and having the advantages of good heat dissipation performance, excellent electrical characteristics, and small volume. Description of the Drawings

[0039] Figure 1 It is a cross-sectional view of the micro low-inductance double-sided heat dissipation type semiconductor power discrete device provided by the embodiment of this application.

[0040] Figure 2 It is a perspective view of the micro low-inductance double-sided heat dissipation type semiconductor power discrete device provided by the embodiment of this application in the upright state.

[0041] Figure 3 It is a perspective view of the micro low-inductance double-sided heat dissipation type semiconductor power discrete device provided by the embodiment of this application in the inverted state.

[0042] Figure 4 This is a three-dimensional internal structure diagram of the micro low-inductance double-sided heat dissipation semiconductor power discrete device provided by the embodiment of the present application.

[0043] Figure 5 This is a side view of the internal structure of the micro low-inductance double-sided heat dissipation semiconductor power discrete device provided by the embodiment of the present application.

[0044] Figure 6 This is a flowchart of the preparation method provided by the embodiment of the present application.

[0045] Figure 7 This is a state diagram before the TEC substrate is placed in the positioning fixture.

[0046] Figure 8 This is a state diagram after the TEC substrate is placed in the positioning fixture.

[0047] Figure 9 This is a state diagram after the first solder pad is stacked.

[0048] Figure 10 This is a state diagram after the chip is stacked.

[0049] Figure 11 This is a state diagram after the second solder pad is stacked.

[0050] Figure 12 This is a state diagram after the molybdenum particles are stacked.

[0051] Figure 13 This is a state diagram after the auxiliary counterweight is stacked.

[0052] Figure 14 This is a schematic structural diagram of the existing power discrete device.

[0053] Label description: 1. TEC substrate; 101. Heat dissipation plate; 102. PN junction layer; 103. Heat collecting plate; 104. First copper-clad layer; 105. Second copper-clad layer; 2. Chip; 201. Gate; 202. Kelvin source; 203. Source; 3. Molybdenum particles; 301. Gate molybdenum particles; 302. Kelvin source molybdenum particles; 303. Source molybdenum particles; 304. Drain molybdenum particles; 305. Positive electrode molybdenum particles; 306. Negative electrode molybdenum particles; 307. Third copper-clad layer; 4. Plastic package; 5. First solder pad; 6. Second solder pad; 90. Positioning fixture; 91. Positioning groove; 92. Auxiliary counterweight. Detailed implementation manners

[0054] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and illustrated herein can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0055] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, the terms "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0056] In power discrete devices, heat dissipation performance and parasitic parameters are key factors affecting their performance and reliability. Traditional power discrete devices adopt passive heat dissipation methods, relying on the natural conduction of heat from the chip to the heat sink for heat dissipation. However, this method is limited by the specific heat capacity of the heat sink. When the heat of the heat sink reaches saturation and the internal and external heat reaches equilibrium, the continuous heat dissipation ability is limited. In addition, the pins, conductive sheets or bonding wires used in traditional designs introduce significant parasitic parameters, including parasitic inductance, resistance and capacitance, which have a negative impact on the stability, power consumption, noise characteristics and switching speed of the device.

[0057] When facing the problems of the influence of heat dissipation performance and parasitic parameters of power discrete devices, several possible solutions have been considered. One idea is to improve the traditional passive heat dissipation structure by increasing the surface area of the heat sink or using materials with higher thermal conductivity to improve the heat dissipation efficiency. However, although this method can improve the heat dissipation performance to a certain extent, it is still limited by the inherent defects of passive heat dissipation and cannot completely solve the heat dissipation problem in high power density applications. Another idea is to introduce a liquid cooling system to quickly remove heat by using circulating liquid. This method can significantly improve the heat dissipation efficiency, but it will greatly increase the complexity and cost of the system, and may also introduce new reliability problems. For the problem of parasitic parameters, methods of optimizing the circuit layout and reducing the connection wire length have been considered. However, the improvement space of this method is limited under the traditional packaging structure and it is difficult to meet the requirements of high-frequency and high-power applications.

[0058] In order to solve the two key problems of heat dissipation and parasitic parameters simultaneously, the present application proposes a scheme for a miniature low-inductance double-sided heat dissipation semiconductor power discrete device.

[0059] Please refer to Figures 1 - 5 In some embodiments of the present application, a micro low-inductance double-sided heat dissipation semiconductor power discrete device includes:

[0060] A TEC substrate 1 (i.e., a thermoelectric cooling substrate), which includes a heat dissipation plate 101, a PN junction layer 102, and a heat collecting plate 103 stacked in sequence from top to bottom; a first copper-clad layer 104 is provided on the lower surface of the heat collecting plate 103; on the TEC substrate 1, a positive electrode pad and a negative electrode pad are also provided downward, and the positive electrode pad and the negative electrode pad are respectively electrically connected to the positive and negative current input ends of the PN junction layer 102;

[0061] A chip 2, which is mounted on the bottom of the heat collecting plate 103. A drain is provided on the top of the chip 2, and a gate 201, a Kelvin source 202, and a source 203 (as shown in Figure 10 ) are provided on the bottom of the chip 2. The drain is welded and connected to the first copper-clad layer 104;

[0062] A plurality of molybdenum grains 3, including a gate molybdenum grain 301 welded and connected to the gate 201, a Kelvin source molybdenum grain 302 welded and connected to the Kelvin source 202, a source molybdenum grain 303 welded and connected to the source 203, a drain molybdenum grain 304 welded and connected to the first copper-clad layer 104, a positive electrode molybdenum grain 305 welded and connected to the positive electrode pad, and a negative electrode molybdenum grain 306 welded and connected to the negative electrode pad; the molybdenum grains 3 are used for electrical connection with an external circuit;

[0063] A plastic package 4, which wraps the TEC substrate 1, the chip 2, and the molybdenum grains 3, and the top of the heat dissipation plate 101 and the bottom of each molybdenum grain 3 are exposed.

[0064] This structural design realizes active heat dissipation through the TEC substrate 1. At the same time, by using molybdenum grains 3 to replace traditional pins and canceling internal leads or conductive sheets, the parasitic parameters are reduced, and it has the advantages of good heat dissipation performance, excellent electrical characteristics, and small volume.

[0065] It should be noted that the up and down directions in the present application are based on the placement direction of Figure 1 (therefore, the descriptions of top and bottom are also based on the placement direction of Figure 1 ). It is only for convenience of description and does not limit the orientation during actual use. During use, the side where the molybdenum grains 3 are exposed can be mounted on the PCBA circuit board (thus eliminating the need for additional leads for circuit connection), and a heat sink can be mounted on the side where the heat dissipation plate 101 is exposed. Further, another heat sink can be mounted on the side of the PCBA circuit board facing away from the micro low-inductance double-sided heat dissipation semiconductor power discrete device to further improve the heat dissipation effect; however, the installation method of the micro low-inductance double-sided heat dissipation semiconductor power discrete device is not limited to this.

[0066] Among them, the TEC substrate 1 is one of the core components of this solution. The PN junction layer 102 generates a temperature difference through current input, actively transferring heat from the heat collection plate 103 to the heat dissipation plate 101. This structure can adjust the heat dissipation efficiency according to actual needs. For example, when working at high power, the current input is increased to improve the heat dissipation capacity. The heat dissipation plate 101 and the heat collection plate 103 can be made of ceramic materials with moderate thermal conductivity but good insulation performance. The chip 2 is directly mounted on the bottom of the heat collection plate 103. This design eliminates the thermal interface material between the chip 2 and the radiator in traditional packaging, greatly reducing the thermal resistance. The drain is set at the top of the chip 2, and the gate 201, Kelvin source 202, and source 203 are set at the bottom. This layout can optimize the current distribution and reduce the hot spots inside the chip 2.

[0067] Among them, the application of the molybdenum particles 3 is another key innovation point. Multiple molybdenum particles 3 are used to replace the traditional pins and leads, including the gate molybdenum particle 301, Kelvin source molybdenum particle 302, source molybdenum particle 303, drain molybdenum particle 304, positive electrode molybdenum particle 305, and negative electrode molybdenum particle 306. The molybdenum particles 3 are directly welded and connected to the respective electrodes of the chip 2, significantly shortening the current path. Molybdenum has excellent electrical conductivity, which can effectively reduce the resistance loss. At the same time, the size and shape of the molybdenum particles 3 can be precisely controlled, helping to reduce the parasitic inductance. Generally, the length and width dimensions of the molybdenum particles 3 are the same as those of the corresponding electrodes or pads (for the drain molybdenum particle 304, its length and width dimensions can be adjusted according to the space size for the drain molybdenum particle 304 to connect on the first copper-clad layer 104). For the thickness, the thickness of the molybdenum particles 3 can be controlled within the range of 1 mm - 5 mm. In this way, not only can electrical connection be achieved, parasitic parameters be reduced, but also it can act as a radiator to help dissipate the heat of the chip 2.

[0068] The first copper-clad layer 104 provided on the lower surface of the heat collection plate 103 serves a dual purpose: on the one hand, it improves the heat conduction efficiency, and on the other hand, it serves as a medium for electrical connection. The thickness of the first copper-clad layer 104 can be adjusted as needed, preferably greater than 200 μm. The encapsulant 4 wraps the TEC substrate 1, the chip 2, and the molybdenum particles 3, but the top of the heat dissipation plate 101 and the bottoms of the respective molybdenum particles 3 are exposed. This design realizes double-sided heat dissipation, greatly increasing the heat dissipation area. The exposed heat dissipation plate 101 can be directly in contact with the external heat dissipation system, and the exposed molybdenum particles 3 are not only convenient for electrical connection but also can serve as additional heat dissipation channels.

[0069] There is a close association and interaction among these features. The TEC substrate 1 provides the basis for active heat dissipation for the entire structure. The direct mounting of the chip 2 on the heat collection plate 103 maximizes the heat transfer efficiency. The application of the molybdenum particles 3 not only reduces the parasitic parameters but also makes double-sided heat dissipation possible. The first copper-clad layer 104 plays a bridging role between heat conduction and electrical connection.

[0070] Among them, multiple P-type semiconductor devices and N-type semiconductor devices are arranged in the PN junction layer 102. These P-type semiconductor devices and N-type semiconductor devices are alternately connected in series in sequence to form multiple PN junctions connected in series with each other. Preferably, these semiconductor devices are arranged in a meandering pattern (such as an S-shaped arrangement or a serpentine arrangement, etc.) to form more PN junctions within a certain space and improve the heat dissipation efficiency.

[0071] Among them, the type of the chip 2 can be selected according to actual needs. Preferably, the chip 2 is a silicon carbide MOSFET chip.

[0072] Selecting a silicon carbide MOSFET chip as the core component of the micro low-inductance double-sided heat dissipation type semiconductor power discrete device has many advantages. The silicon carbide material has characteristics such as a wide bandgap, a high breakdown electric field, and a high thermal conductivity, making the MOSFET chip based on silicon carbide perform excellently in high-temperature, high-frequency, and high-voltage applications. Specifically, the silicon carbide MOSFET chip can operate stably at a higher temperature, which complements the double-sided heat dissipation design of the device and further improves the heat dissipation efficiency. At the same time, the silicon carbide MOSFET chip has a faster switching speed and lower switching losses, which helps to reduce the overall power consumption of the device and improve the energy conversion efficiency. In addition, the silicon carbide MOSFET chip has a higher breakdown voltage, enabling the device to withstand a higher operating voltage and expanding the application range. Adopting a silicon carbide MOSFET chip, combined with the double-sided heat dissipation structure of the TEC substrate 1, the low-inductance design of multiple molybdenum grains 3, and the protection of the plastic package 4, together constitute a micro low-inductance double-sided heat dissipation type semiconductor power discrete device with excellent performance. This design not only improves the power density and reliability of the device but also reduces the parasitic inductance and improves the switching characteristics of the device, making it have significant advantages in high-frequency, high-temperature, and high-voltage applications.

[0073] Among them, the performance and size of the chip 2 can be set according to actual needs. For example, a silicon carbide MOSFET chip with a rated voltage of 650V, a on-resistance of 32mΩ, and a size of 3.1mm * 2.3mm is selected (selecting this chip 2 can obtain a micro low-inductance double-sided heat dissipation type semiconductor power discrete device with a size of 3.3mm * 2.5mm), but it is not limited thereto.

[0074] Among them, the positive electrode pad is arranged on the lower surface of the heat dissipation plate 101 or the lower surface of the heat collecting plate 103; the negative electrode pad is arranged on the lower surface of the heat dissipation plate 101 or the lower surface of the heat collecting plate 103.

[0075] Arranging the positive electrode pad and the negative electrode pad on the lower surface of the heat dissipation plate 101 or the lower surface of the heat collecting plate 103 can make full use of the structural characteristics of the TEC substrate 1 to optimize the electrical performance and thermal performance, providing new ideas for the development of high-performance semiconductor power devices.

[0076] In this application, the positive electrode pad and the negative electrode pad can be arranged in various ways. One way is to arrange both pads on the lower surface of the heat dissipation plate 101, another way is to arrange both pads on the lower surface of the heat collection plate 103, and it is also possible to arrange the positive electrode pad on the lower surface of the heat dissipation plate 101 while arranging the negative electrode pad on the lower surface of the heat collection plate 103, or vice versa. These different arrangement methods can be selected according to the specific device structure and application requirements.

[0077] In some preferred embodiments, see Figure 4 , Figure 5 , one side of the heat dissipation plate 101 extends beyond the range of the heat collection plate 103, and the positive electrode pad and the negative electrode pad are arranged at the lower surface of the part where the heat dissipation plate 101 extends beyond the range of the heat collection plate 103.

[0078] This arrangement provides additional installation space for the positive electrode pad and the negative electrode pad by extending one side of the heat dissipation plate 101 beyond the range of the heat collection plate 103. Arranging these two pads on the lower surface of the extended part of the heat dissipation plate 101 can effectively utilize the space of the device, and at the same time does not affect the installation and heat dissipation effect of the chip 2. This design solves the problem of arranging pads in a limited space, enabling the positive electrode pad and the negative electrode pad to be conveniently connected to the external circuit without interfering with the installation and function of the chip 2. In addition, since the positive electrode pad and the negative electrode pad are located at the extended part of the heat dissipation plate 101, they are kept at a certain distance from the chip 2, which can reduce electromagnetic interference and improve the overall performance of the device.

[0079] This design cooperates with the layout of the TEC substrate 1, the chip 2, and the molybdenum grains 3 to form a compact and efficient structure. The extension of the heat dissipation plate 101 not only provides installation space for the pads but also increases the heat dissipation area and improves the overall heat dissipation efficiency. At the same time, since the positive electrode pad and the negative electrode pad are located at the extended part of the heat dissipation plate 101, the distance between them and the chip 2 is optimized, which helps to reduce parasitic inductance and improve the switching speed of the device.

[0080] In practical applications, this layout enables the micro low-inductance double-sided heat dissipation type semiconductor power discrete device to better adapt to various complex circuit environments. The positions of the positive electrode pad and the negative electrode pad are convenient for connecting to the external circuit without interfering with the normal operation of the chip 2. This design also improves the reliability of the device because the appropriate distance between the positive electrode pad and the negative electrode pad and the chip 2 can reduce the influence of thermal stress on the connection.

[0081] Among them, the number and layout of the gate 201, the Kelvin source 202, and the source 203 on the chip 2 and the corresponding molybdenum grains 3 can be adjusted according to actual needs, and the number and layout of the drain molybdenum grains 304 can also be adjusted according to actual needs.

[0082] In a possible implementation, see Figure 4 , Figure 10 , both the gate 201 and the gate molybdenum grain 301 are provided with one, both the Kelvin source 202 and the Kelvin source molybdenum grain 302 are provided with two, both the source 203 and the source molybdenum grain 303 are provided with two, and the drain molybdenum grain 304 is provided with two; the centers of the gate 201 and the gate molybdenum grain 301 are located on a symmetry plane perpendicular to the bottom surface of the chip 2, and between the two Kelvin sources 202, between the two Kelvin source molybdenum grains 302, between the two sources 203, between the two source molybdenum grains 303, between the two drain molybdenum grains 304, and between the positive electrode molybdenum grain 305 and the negative electrode molybdenum grain 306 are symmetrically arranged with respect to this symmetry plane.

[0083] This layout design realizes the symmetry of the device structure by precisely controlling the quantity and positions of each electrode and the molybdenum grains 3. The centers of the gate 201 and the gate molybdenum grain 301 are located on the symmetry plane, ensuring the uniform distribution of the gate signal. The symmetrical arrangement of the two Kelvin sources 202, the sources 203 and their corresponding molybdenum grains 3 helps to reduce the parasitic inductance and improve the switching speed of the device. The symmetrical setting of the two drain molybdenum grains 304 is conducive to uniform heat dissipation and current distribution. The symmetrical arrangement of the positive electrode molybdenum grain 305 and the negative electrode molybdenum grain 306 helps to reduce the parasitic inductance of the device and improve the electrical performance. Through this symmetrical layout, this technical solution effectively solves the problems of uneven current distribution, uneven heat dissipation and large parasitic inductance inside the device. The symmetrical structure enables the current and heat to be more evenly distributed inside the device, reduces the generation of local hot spots, and improves the heat dissipation efficiency of the device. At the same time, the symmetrical layout also helps to reduce the parasitic inductance of the device, improve the switching speed and the overall electrical performance. This design not only optimizes the electrical characteristics of the device, but also improves its reliability and service life, making this micro low-inductance double-sided heat dissipation semiconductor power discrete device have better performance in high-frequency and high-power applications.

[0084] Furthermore, see Figure 4 , Figure 10 , the molybdenum grains 3 and the corresponding electrodes or pads on one side of the above-mentioned symmetry plane are arranged in sequence along a straight line direction parallel to this symmetry plane, and the molybdenum grains 3 and the corresponding electrodes or pads on the other side of the above-mentioned symmetry plane are arranged in sequence along another straight line direction parallel to this symmetry plane; thus, it is more conducive to improving the structural compactness and more conducive to reducing the product size.

[0085] It should be noted that the bottom surfaces of all the molybdenum grains 3 are flush (in the same plane) to ensure that each molybdenum grain 3 can be reliably attached to the PCBA circuit board during use to achieve good electrical connection.

[0086] Preferably, see Figure 1, a second copper cladding layer 105 is provided on the top of the heat dissipation plate 101; a third copper cladding layer 307 is provided at the bottom of each molybdenum particle 3.

[0087] By providing the second copper cladding layer 105 and the third copper cladding layer 307, it is convenient to solder and connect with external devices (radiator or PCBA circuit board), improving the connection reliability. In addition, better heat conduction and electrical connection can also be achieved. The thicknesses of the second copper cladding layer 105 and the third copper cladding layer 307 can be adjusted as needed, preferably greater than 200 μm.

[0088] In practical applications, the heat dissipation efficiency of the TEC substrate 1 is positively correlated with the contact area between the chip 2 and the TEC substrate 1. The larger this contact area is, the higher the heat dissipation efficiency. Therefore, the area ratio of the chip 2 at the bottom of the heat collecting plate 103 is preferably above 95%.

[0089] By setting the area ratio of the chip 2 at the bottom of the heat collecting plate 103 above 95%, the heat dissipation area of the heat collecting plate 103 is fully utilized. This design can significantly improve the heat dissipation efficiency of the chip 2 because the larger the contact area between the chip 2 and the heat collecting plate 103, the better the heat conduction effect. At the same time, this design also helps to achieve miniaturization of the device. Since the chip 2 almost occupies the entire area at the bottom of the heat collecting plate 103, unnecessary space waste is reduced, making the size of the entire device more compact. In addition, the large-area contact between the chip 2 and the heat collecting plate 103 may also bring other benefits, such as reducing thermal resistance, improving the reliability and service life of the device, etc. This design fully considers the balance between heat dissipation requirements and space utilization rate, and is an optimized solution. Compared with the traditional design, this high-ratio layout method may have significant improvements in both heat dissipation efficiency and space utilization rate, reflecting the innovation and practical value of this technical solution.

[0090] Since the area ratio of the chip 2 at the bottom of the heat collecting plate 103 is set above 95%, the size of the chip 2 is not much different from the size of the packaged product. The area ratio of the chip 2 is also similar to that of the WLCSP package (i.e., wafer-level chip package), but compared with the WLCSP package, the manufacturing process is simpler and the cost is lower; moreover, the product of this application can achieve double-sided heat dissipation, greatly improving the heat dissipation ability. The use of silicon carbide MOSFET chips provides very important support for the realization of ultra-high power density.

[0091] Among them, the connection between the chip 2 and the heat collecting plate 103 and between each molybdenum particle 3 and the corresponding electrode (or pad, or the first copper cladding layer 104) can be carried out in various ways, such as welding, crimping or conductive adhesive bonding, etc.

[0092] In some preferred embodiments, the connection is made by using a solder tab welding method, which is conducive to ensuring the consistency of the bottom surface heights of the molybdenum grains 3 and ensuring that the bottom surfaces of the molybdenum grains 3 are in the same plane. For example Figure 1 , Figure 5 in, between the chip 2 and the first copper-clad layer 104 at the bottom of the heat collecting plate 103 and between the drain molybdenum grain 304 and the first copper-clad layer 104, they are welded and connected by the same first solder tab 5, and the other molybdenum grains 3 are respectively welded and connected to the corresponding electrodes or pads through the corresponding second solder tabs 6. Among them, the materials of the first solder tab 5 and the second solder tab 6 are preferably tin or silver.

[0093] Referring Figure 6 , the present application provides a preparation method for preparing the above-mentioned micro low-inductance double-sided heat dissipation type semiconductor power discrete device, including the steps:

[0094] A1. Place the TEC substrate 1 face down in the positioning jig 90 (as Figure 7 , Figure 8 shown);

[0095] A2. Stack the first solder tab 5 on the first copper-clad layer 104 at the bottom of the TEC substrate 1 (as Figure 9 shown);

[0096] A3. Stack the chip 2 face down on the first solder tab 5, making the drain at the top of the chip 2 contact the first solder tab 5, and a part of the first solder tab 5 is exposed outside the range of the chip 2 (as Figure 10 shown);

[0097] A4. Stack the second solder tabs 6 on the gate 201, Kelvin source 202 and source 203 at the bottom of the chip 2 respectively, and on the positive electrode pad and negative electrode pad of the TEC substrate 1 (as Figure 11 shown);

[0098] A5. Stack the corresponding molybdenum grains 3 on each second solder tab 6 and at the position where the first solder tab 5 is exposed outside the range of the chip 2 to obtain a first semi-finished product (as Figure 12 shown);

[0099] A6. While applying pressure downward to the first semi-finished product, perform reflow soldering on the first semi-finished product by using the vacuum reflow soldering technology to obtain a second semi-finished product;

[0100] A7. Perform plastic encapsulation on the second semi-finished product to obtain a finished product;

[0101] A8. Test, tape and package the finished product.

[0102] This preparation method manufactures a miniature low-sensitivity double-sided heat-dissipating semiconductor power discrete device through a series of precise steps. First, the TEC substrate 1 is placed in the positioning fixture 90 to ensure the accuracy of subsequent operations. Then, by stacking solder pads and chips 2, an electrical connection and a heat conduction path are established. Next, molybdenum grains 3 are placed at key positions to provide an interface for external circuit connection. Vacuum reflow soldering technology is used for soldering, and this step is crucial for ensuring reliable connection between components. The vacuum environment can reduce oxidation during the soldering process and improve the soldering quality. At the same time, applying pressure to the semi-finished product can ensure close contact between components and further improve the soldering effect. Using solder pads for soldering can better ensure the height consistency of each molybdenum grain 3 compared with using solder paste, and there is no need for vacuum sintering and cleaning after sintering, which can reduce the cleaning and wire bonding processes and avoid quality problems brought by these processes, greatly simplifying the manufacturing process and improving product reliability. The plastic encapsulation molding step provides protection for the device and also fixes the internal structure. The final testing and packaging steps ensure the quality and reliability of the product.

[0103] Among them, see Figure 7 , a plurality of positioning grooves 91 adapted to the TEC substrate 1 are provided on the positioning fixture 90. In step A1, a plurality of TEC substrates 1 are placed face down in these positioning grooves 91 for positioning, and multiple products can be prepared simultaneously, improving the preparation efficiency. The positioning fixture 90 can be made of precisely machined metal or ceramic materials, with high dimensional accuracy to ensure the position stability of the TEC substrate 1 in subsequent steps.

[0104] Preferably, step A6 includes:

[0105] Stack the auxiliary counterweight 92 on the first semi-finished product to apply pressure to the first semi-finished product (as Figure 13 shown);

[0106] Send the auxiliary counterweight 92, the first semi-finished product, and the positioning fixture 90 together into the vacuum reflow soldering device for reflow soldering to obtain the second semi-finished product.

[0107] The auxiliary counterweight 92 is used to apply pressure to the first semi-finished product to ensure close contact between components during the reflow soldering process. The vacuum reflow soldering device provides a vacuum environment for the soldering process, which helps reduce soldering defects. These two features cooperate with each other to effectively solve the key problems in the preparation process.

[0108] The auxiliary counterweight 92 can be implemented in various forms. For example, it can be a metal plate with a moderate weight, whose size is slightly larger than that of the first semi-finished product to ensure uniform pressure. It can also be designed as a pressing plate with multiple protrusions, which correspond to the key welding points on the first semi-finished product to achieve local pressurization. In addition, pneumatic or hydraulic devices with adjustable pressure can be used to flexibly control the pressure according to the requirements of different products.

[0109] A layer of high-temperature resistant and non-sticky isolation material, such as polytetrafluoroethylene film, can be added between the auxiliary counterweight 92 and the first semi-finished product to prevent adhesion during the high-temperature welding process.

[0110] The vacuum degree of the vacuum reflow soldering device can be adjusted according to the product requirements, usually in the range of 1×10 -2 to 1×10 -4 Pa. A temperature gradient can also be set inside the device to achieve more precise control of the welding temperature. For example, the temperature can be slowly increased from 150°C to a maximum of 320°C and then gradually cooled, and the whole process may last for 5 minutes - 10 minutes.

[0111] Through the pressing action of the auxiliary counterweight 92, this technical solution effectively prevents the displacement or deformation of each component at high temperature, ensures the close contact of the welding surface, and thus significantly improves the welding quality. The vacuum environment greatly reduces the oxidation risk, reduces the generation of bubbles and impurities, and further enhances the welding effect. This combination not only improves the welding quality and reliability of the product, but also helps to improve the overall performance and service life of the device.

[0112] Among them, the weight of the auxiliary counterweight 92 can be adjusted according to actual needs. Since solder chips are used for welding in this solution, solder overflow will not occur due to excessive pressure (this would happen if solder paste were used, resulting in the need for cleaning after welding and it being difficult to control the thickness of the remaining solder, thus making it difficult to ensure that the bottom surfaces of each molybdenum particle 3 are at the same height). Therefore, the pressure range is less restricted, as long as the structure and function of each component are not damaged. For example, when the size of the chip 2 is 3.1mm * 2.3mm and the size of the finished product after plastic encapsulation is 3.3mm * 2.5mm, the weight of the auxiliary counterweight 92 can be set according to the product size and the required pressure (ensuring that the pressure received by the product is the required pressure), where the required pressure is generally 10MPa - 25MPa, which can not only ensure the close contact of the welding surface but also not damage the structure and function of each component.

[0113] Further, step A7 includes:

[0114] Plastic encapsulating the second semi-finished product so that the plastic encapsulation body 4 completely wraps the second semi-finished product;

[0115] Etch the plastic package 4 on the top of the second semi-finished product to expose the top of the TEC substrate 1;

[0116] Etch the plastic package 4 on the bottom of the second semi-finished product to expose the bottom of each molybdenum particle 3.

[0117] This solution solves the problem of how to precisely control the exposed parts during the plastic packaging process. By first completely wrapping and then etching, it avoids the problems of incomplete coverage or inaccurate exposed parts that may occur during direct plastic packaging. This method not only improves the manufacturing precision and consistency but also enhances the overall structural strength and sealing performance of the device. At the same time, the exposure of the top of the TEC substrate 1 is beneficial for heat dissipation, and the exposure of the bottom of the molybdenum particle 3 facilitates electrical connection with the external circuit, thus meeting the functional requirements of the micro low-inductance double-sided heat dissipation semiconductor power discrete device.

[0118] In specific implementation, various methods can be used to plastic package the second semi-finished product. For example, injection molding technology can be used to inject the molten plastic packaging material into the mold to completely wrap the second semi-finished product. Another method is compression molding technology, where the preheated plastic packaging material is placed in the mold and then made to flow and wrap the second semi-finished product by applying pressure. Both of these methods can ensure that the plastic package 4 evenly covers the entire second semi-finished product, providing a good basis for the subsequent etching step.

[0119] The etching process can use dry etching or wet etching. Dry etching usually uses plasma or ion beam and can achieve high-precision etching effects. Wet etching uses chemical solutions, which, although slightly lower in precision, have lower costs and are suitable for large-scale production. Regardless of which etching method is selected, the key lies in precisely controlling the etching depth and range to ensure that the top of the TEC substrate 1 and the bottom of the molybdenum particle 3 are exactly exposed without over-etching to affect the device performance.

[0120] It should be noted that during the etching process, the material properties of the TEC substrate 1 and the molybdenum particle 3 need to be considered, and appropriate etching parameters and protection measures should be selected. For example, photoresist or other protective layers can be coated on the areas that need to be protected before etching to prevent over-etching. The control of the etching rate is also crucial. Usually, a step-by-step etching method is adopted, and detection is carried out after etching a certain depth each time to ensure that the etching effect meets the requirements.

[0121] Among them, the second copper-clad layer 105 and the third copper-clad layer 307 can be prepared in advance on the corresponding parts or can be prepared in step A7. For the latter case, step A7 also includes:

[0122] Prepare the second copper-clad layer 105 on the top of the TEC substrate 1;

[0123] Prepare the third copper-clad layer 307 on the bottom of each molybdenum particle 3.

[0124] For example, the second copper-clad layer 105 and the third copper-clad layer 307 can be prepared by chemical vapor deposition or physical vapor deposition, but are not limited thereto.

[0125] In step A8, the finished product can be tested, taped, and packaged using existing technologies, which are not limited herein.

[0126] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0127] The above description is only for the embodiments of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A miniature low-inductance double-sided heat dissipation semiconductor power discrete device, characterized in that: include: A TEC substrate (1), the TEC substrate (1) comprising a heat sink (101), a PN junction layer (102) and a heat collecting plate (103) stacked in sequence from top to bottom; a first copper cladding layer (104) is provided on the lower surface of the heat collecting plate (103); a positive electrode pad and a negative electrode pad are also provided downwardly on the TEC substrate (1), the positive electrode pad and the negative electrode pad being electrically connected to the positive and negative current input terminals of the PN junction layer (102) respectively; A chip (2), the chip (2) being mounted on the bottom of the heat collecting plate (103), the top of the chip (2) being provided with a drain electrode, the bottom of the chip (2) being provided with a gate electrode (201), a Kelvin source electrode (202) and a source electrode (203), the drain electrode being connected to the first copper cladding layer (104) by soldering; A plurality of molybdenum particles (3), including a gate molybdenum particle (301) connected to the gate (201) solder paste, a Kelvin source molybdenum particle (302) connected to the Kelvin source (202) solder paste, a source molybdenum particle (303) connected to the source (203) solder paste, a drain molybdenum particle (304) connected to the first copper cladding layer (104) solder paste, a positive electrode molybdenum particle (305) connected to the positive electrode pad solder paste, and a negative electrode molybdenum particle (306) connected to the negative electrode pad solder paste; the molybdenum particles (3) are used to be electrically connected to an external circuit; A plastic packaging body (4), wherein the plastic packaging body (4) wraps the TEC substrate (1), the chip (2) and the molybdenum particles (3), and the top of the heat sink (101) and the bottom of each of the molybdenum particles (3) are exposed.

2. The miniature low-inductance double-sided heat dissipation semiconductor power discrete device according to claim 1, characterized in that: The chip (2) is a silicon carbide MOSFET chip.

3. The miniature low-inductance double-sided heat dissipation semiconductor power discrete device according to claim 1, characterized in that: The positive electrode welding pad is arranged on the lower surface of the heat dissipation plate (101) or the lower surface of the heat collecting plate (103); and the negative electrode welding pad is arranged on the lower surface of the heat dissipation plate (101) or the lower surface of the heat collecting plate (103).

4. The miniature low-inductance double-sided heat dissipation semiconductor power discrete device according to claim 3, characterized in that: One side of the heat dissipation plate (101) extends out of the range of the heat collecting plate (103), and the positive electrode pad and the negative electrode pad are arranged on the lower surface of the portion of the heat dissipation plate (101) extending out of the range of the heat collecting plate (103).

5. The miniature low-inductance double-sided heat dissipation semiconductor power discrete device according to claim 1, characterized in that: The gate electrode (201) and the gate electrode platinum particle (301) are each provided with one, the Kelvin source electrode (202) and the Kelvin source electrode platinum particle (302) are each provided with two, the source electrode (203) and the source electrode platinum particle (303) are each provided with two, and the drain electrode platinum particle (304) is provided with two; the center of the gate electrode (201) and the center of the gate electrode platinum particle (301) are located on a symmetric plane perpendicular to the bottom surface of the chip (2); the two Kelvin source electrodes (202), the two Kelvin source electrode platinum particles (302), the two source electrodes (203), the two source electrode platinum particles (303), the two drain electrode platinum particles (304), and the positive electrode platinum particles (305) and the negative electrode platinum particles (306) are all symmetrically arranged about the symmetric plane.

6. The miniature low-inductance double-sided heat dissipation semiconductor power discrete device according to claim 1, characterized in that: A second copper-clad layer (105) is provided on the top of the heat dissipation plate (101); and a third copper-clad layer (307) is provided on the bottom of each of the molybdenum particles (3).

7. The miniature low-inductance double-sided heat dissipation semiconductor power discrete device according to claim 1, characterized in that: The chip (2) accounts for more than 95% of the area of ​​the bottom of the heat collecting plate (103).

8. A method for preparing a miniature low-inductive double-sided heat dissipation semiconductor power discrete device, characterized in that: The method for preparing the miniature low-inductive double-sided heat dissipation semiconductor power discrete device according to any one of claims 1 to 7 comprises the following steps: A1. Place the TEC substrate (1) with the top surface facing downward into the positioning fixture (90); A2. stacking a first solder sheet (5) on the first copper-clad layer (104) on the bottom surface of the TEC substrate (1); A3. stacking the chip (2) with the top facing downward on the first soldering pad (5), so that the drain electrode on the top of the chip (2) contacts the first soldering pad (5), and the first soldering pad (5) is partially exposed outside the range of the chip (2); A4. stacking a second soldering sheet (6) on the gate (201), the Kelvin source (202) and the source (203) at the bottom of the chip (2) and on the positive electrode pad and the negative electrode pad of the TEC substrate (1); A5. stacking corresponding molybdenum particles (3) on each of the second soldering sheets (6) and at positions of the first soldering sheets (5) protruding outside the range of the chip (2) to obtain a first semi-finished product; A6. While applying pressure downward to the first semi-finished product, the first semi-finished product is reflowed using a vacuum reflow technique to obtain a second semi-finished product; A7. Plastic-sealing the second semi-finished product to obtain a finished product; A8. Test taping and packaging of the finished products.

9. The method for preparing a miniature low-inductive double-sided heat dissipation semiconductor power discrete device according to claim 8, characterized in that: Step A6 includes: superimposing an auxiliary counterweight (92) on the first semi-finished product to apply pressure to the first semi-finished product; The auxiliary counterweight (92), the first semi-finished product and the positioning jig (90) are sent together into a vacuum reflow soldering device for reflow soldering to obtain a second semi-finished product.

10. The method for preparing a miniature low-inductance double-sided heat dissipation semiconductor power discrete device according to claim 8, characterized in that: Step A7 includes: Plastic-sealing the second semi-finished product so that the plastic-sealed body (4) completely wraps the second semi-finished product; Etching the plastic packaging body (4) at the top of the second semi-finished product so as to expose the top of the TEC substrate (1); The plastic sealing body (4) at the bottom of the second semi-finished product is etched to expose the bottom of each of the molybdenum particles (3).

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