Maximum on-time control circuit capable of adaptively changing along with frequency
The frequency-adaptive maximum on-time control circuit addresses insufficient bootstrap charging in Buck converters by using an IBIAS reference current and logic module to manage power tube on-time, ensuring stable operation and reduced power consumption.
Patent Information
- Application Number
- CN202411436199.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-01-03
AI Technical Summary
Existing Buck-type switching converters face issues with abnormal operation due to insufficient charging time of the bootstrap capacitor, particularly at high clock frequencies, leading to abnormal output states and increased power consumption.
A maximum on-time control circuit that adapts with frequency is implemented, using an IBIAS reference current module, capacitor, and logic control module to manage the maximum on-time of the power tube, ensuring normal operation by controlling the charging and discharging of the capacitor.
The solution ensures normal operation of the Buck circuit across varying frequencies, reduces circuit complexity and power consumption, and minimizes the impact of process and temperature variations.
Smart Images
Figure CN119253984A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of electronic circuits, in particular to a maximum on-time control circuit that changes adaptively with frequency. Background Art
[0002] In the field of power electronics, Buck-type switching converters are widely used in the power conversion process to reduce the input voltage to the required output voltage. The voltage driven by the upper power tube of the Buck-type switching converter needs to be higher than the power supply voltage in order to turn on the upper power tube. This voltage is usually achieved through a bootstrap circuit. The bootstrap circuit charges the bootstrap capacitor when the lower power tube is turned on, and supplies power to the upper power tube when the upper power tube is turned on. Therefore, in each switching cycle, the bootstrap capacitor needs enough time to be fully charged to drive the upper power tube normally. When the input voltage is slightly higher than the output voltage or the input voltage is turned off very slowly, the output voltage duty cycle is very high. When the clock frequency is high, the conduction time of the lower power tube will become very short, and the bootstrap capacitor will not be fully charged, causing the Buck circuit to work abnormally, further affecting various circuits in the subsequent stage.
[0003] In the prior art, three solutions are usually used to deal with the problem of abnormal output state caused by insufficient charging time of the bootstrap capacitor. The first solution is to change the power supply mode of the driving power supply. For example, the upper power tube is replaced with PMOS, but because the current driving capability of PMOS is lower than that of NMOS, several times the area is required to achieve the same current driving capability. A charge pump circuit can also be used to power the upper power tube. The charge pump can always provide a stable high voltage higher than the power supply voltage to the driving circuit, so that the operation of the driving circuit is independent of the switch state. The charge pump circuit increases the complexity of the circuit, and the charge pump voltage is higher than the power supply voltage, which will limit the maximum value of the power supply voltage under the same process. The second solution is to monitor the voltage of the bootstrap capacitor. When the capacitor voltage is lower than a certain threshold, the switch node voltage is forced to be lowered. When the normal state is a large duty cycle, the voltage on the bootstrap capacitor drops to a lower position and is supplemented by the additional lower tube MOS being turned on, resulting in a low average voltage, thereby increasing the on-resistance of the MOS tube and increasing the power consumption. The third solution is to design a fixed maximum on-time. When the on-time exceeds the preset time, the upper power tube will be automatically turned off and the lower power tube will be turned on. Since the device is greatly affected by process and temperature, the maximum on-time fluctuation is also large. In addition, when the internal oscillator frequency increases, the maximum on-time may exceed the time of one cycle and will no longer have a limiting function. Summary of the invention
[0004] The purpose of the present invention is to provide a maximum on-time control circuit that changes adaptively with frequency to limit the maximum on-time of the power tube in the Buck circuit, ensuring that the Buck circuit can work normally when the input voltage is slightly higher than the output voltage or the input voltage is turned off very slowly.
[0005] In order to achieve the above-mentioned purpose, the technical methods adopted by the present invention are as follows: A maximum on-time control circuit that changes adaptively with frequency is used in a Buck circuit. An upper power tube and a lower power tube in the Buck circuit are connected in series and their connection points generate an output voltage through a power inductor. The control ends of the upper power tube and the lower power tube are controlled to be turned on and off through a power tube drive control circuit. The maximum on-time control circuit comprises an IBIAS reference current module, a capacitor and a logic control module. The output end of the IBIAS reference current module is respectively connected to one end of the capacitor and the input end of the logic control circuit, and the other end of the capacitor is grounded. The logic control module comprises a D trigger, and the output end of the D trigger is connected to the input end of the power tube drive control circuit in the Buck circuit. The IBIAS reference current module comprises a shutdown signal control end for inputting a shutdown signal and a charge and discharge control end for controlling the charging and discharging of the capacitor.
[0006] As a limitation: the logic control module also includes a first inverter, a second inverter and a NAND gate, the output end of the IBIAS reference current module is connected to the input end of the first inverter, the output end of the first inverter is connected to the first input end of the NAND gate, the second input end of the NAND gate inputs the upper power tube gate signal, the output end of the NAND gate is connected to the D input end of the D flip-flop, the clock signal input end of the D flip-flop inputs the clock signal, the reset signal input end of the D flip-flop is connected to the output end of the second inverter, and the input end of the second inverter is connected to the charge and discharge control end of the BIAS reference current module.
[0007] As a further limitation: the maximum on-time control circuit also includes a PMOS tube, the source of the PMOS tube is connected to the power supply, the drain of the PMOS tube is connected to the input end of the first inverter, and the gate of the PMOS tube is connected to the output end of the first inverter.
[0008] As a further limitation: a resistor is connected between the output terminal of the IBIAS reference current module and the capacitor.
[0009] Due to the adoption of the above scheme, the present invention has the following beneficial effects compared with the prior art: The present invention provides a maximum on-time control circuit that changes adaptively with frequency. By setting an IBIAS reference current module, a capacitor and a logic control module, the IBIAS reference current module charges the capacitor, provides a flip voltage for the logic control module, and then controls the maximum on-time of the power tube on the Buck circuit through the potential output by the logic control module, ensuring that when the input voltage of the Buck circuit is slightly higher than the output voltage or the input voltage is turned off very slowly, the Buck circuit can also work normally. In addition, the present invention has a simple structure, reduces the occupied area, and reduces the cost; the charging capacitor is reduced, and the current of the IBIAS reference current module can be limited to a very low level, reducing power consumption; the maximum on-time of the upper power tube changes adaptively with the clock frequency, and can work normally within the operating frequency range of the Buck circuit, and the maximum on-time will not be affected by the charging current and the size of the charging capacitor, and is less affected by the process and temperature.
[0010] The present invention is suitable for controlling a Buck circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0012] Figure 1 A circuit diagram of a maximum on-time control circuit that adaptively changes with frequency according to an embodiment of the present invention; Figure 2 The figure is a waveform relationship diagram of the charge and discharge control terminal CTRL, the clock signal input terminal CLK and the output terminal VOUT signal of the maximum on-time control circuit of the embodiment of the present invention when the clock frequency is 1 MHz and the ratio of the output voltage to the input voltage of the Buck circuit is lower than 95%; Figure 3 The figure is a waveform relationship diagram of the charge and discharge control terminal CTRL, the clock signal input terminal CLK and the output terminal VOUT signal of the maximum on-time control circuit of the embodiment of the present invention when the clock frequency is 1 MHz and the ratio of the output voltage to the input voltage of the Buck circuit exceeds 95%; Figure 4 The figure is a waveform relationship diagram of the charge and discharge control terminal CTRL, the clock signal input terminal CLK and the output terminal VOUT signal of the maximum on-time control circuit of the embodiment of the present invention when the clock frequency is 2MHz and the ratio of the output voltage to the input voltage of the Buck circuit is lower than 95%; Figure 5 The figure is a waveform relationship diagram of the charge and discharge control terminal CTRL, the clock signal input terminal CLK and the output terminal VOUT signal of the maximum on-time control circuit of the embodiment of the present invention when the clock frequency is 500kHz and the ratio of the output voltage to the input voltage of the Buck circuit exceeds 95%; In the figure: 1. Logic control module. DETAILED DESCRIPTION
[0013] The present invention is further described below in conjunction with embodiments, but those skilled in the art should understand that the present invention is not limited to the following embodiments, and any improvements and equivalent changes made based on the specific embodiments of the present invention are within the scope of protection of the claims of the present invention.
[0014] Embodiment A maximum on-time control circuit adaptively changing with frequency A maximum on-time control circuit that changes adaptively with frequency is used in a Buck circuit. In the Buck circuit, an upper power tube and a lower power tube are connected in series and their connection points are filtered by an inductor and a capacitor to generate a stable output voltage. The control ends of the upper power tube and the lower power tube are controlled to be turned on and off by a power tube drive control circuit. The circuit diagram of the maximum on-time control circuit is shown in FIG. Figure 1 As shown, it includes an IBIAS reference current module, a resistor R, a capacitor C, a PMOS tube and a logic control module 1, the IBIAS reference current module includes a shutdown signal control terminal SHDN for inputting a shutdown signal and a charge and discharge control terminal CTRL for controlling the charging and discharging of the capacitor, the logic control module 1 includes a first inverter INV1, a second inverter INV2, a NAND gate NAND and a D trigger, the output end of the IBIAS reference current module is respectively connected to one end of the resistor R, the drain of the PMOS tube and the input end of the first inverter INV1, the other end of the resistor R is connected to one end of the capacitor C, the other end of the capacitor C is grounded, the source of the PMOS tube is connected to the power supply, and the PMOS tube The gate is connected to the output end of the first inverter INV1, the output end of the first inverter INV1 is connected to the first input end of the NAND gate NAND, the second input end of the NAND gate NAND inputs the power tube gate signal VGH, the output end of the NAND gate NAND is connected to the D input end of the D flip-flop, the clock signal input end CLK of the D flip-flop inputs the clock signal, the reset signal input end Reset of the D flip-flop is connected to the output end of the second inverter INV2, the output end VOUT of the D flip-flop is connected to the input end of the power tube drive control circuit in the Buck circuit, and the input end of the second inverter INV2 is connected to the charge and discharge control end CTRL of the BIAS reference current module.
[0015] The IBIAS reference current module provides charging current for capacitor C, and the resistor R plays a role in reducing transient current. IBIAS is controlled by two control signals. The shutdown signal control terminal SHDN inputs the shutdown signal of the Buck circuit. When the Buck circuit is turned off, the IBIAS reference current module is also turned off, that is, when the shutdown signal control terminal SHDN of the IBIAS reference current module inputs a high level, the IBIAS reference current module is turned off, saving power consumption; the charge and discharge control terminal CTRL of the IBIAS reference current module inputs a high level to charge capacitor C, and the capacitor C is discharged when the input is a low level. The PMOS tube is connected to the first inverter INV1 to form a positive feedback, which can increase the flip speed of the voltage at node B. With the arrival of the falling edge of the clock signal, the input of the charge and discharge control terminal CTRL of the IBIAS reference current module becomes a high level, the upper power tube of the Buck circuit is turned on, and the IBIAS reference current module charges capacitor C. When the voltage at node A reaches the flip voltage of the first inverter INV1, the voltage at node B will become a low level, and the voltage at node C will become a high level. If the input voltage of the Buck circuit is slightly higher than the output voltage or the input voltage is turned off very slowly, the output voltage duty cycle is very high, the upper power tube is turned on for a long time, the charge and discharge control terminal CTRL of the BIAS reference current module is at a high level for a long time, and the BIAS reference current module will always charge the capacitor C. When the next clock rising edge comes, the node C maintains a high level, the output terminal VOUT of the D flip-flop outputs a high level, and then controls the upper power tube of the Buck circuit to turn off. The maximum on-time control circuit of this embodiment sets the maximum on-time of the upper power tube of the Buck circuit, and the time is the width of the pulse on the clock. When the Buck circuit is in a normal working state, the upper power tube is turned off before the next clock rising edge comes, so the charge and discharge control terminal CTRL of the IBIAS reference current module will become a low level in advance, the node A starts to discharge, and the node E becomes a high level, the output of the D flip-flop is set to 0, and the output terminal VOUT outputs a low level, and the upper power tube of the Buck circuit will not be turned off.
[0016] The maximum on-time control circuit of this embodiment is designed using 0.18μm BCD technology. The circuit is integrated in a Buck chip. The pulse width of the clock signal square wave preset in the chip is 50ns, so the maximum on-time is 1 time period minus 50ns. When the clock frequency is 1MHz, Figure 2 As shown, when the ratio of the output voltage to the input voltage of the Buck circuit is lower than 95%, the on-time is lower than 950ns, and the maximum on-time control circuit of this embodiment will not function; Figure 3As shown in FIG. 1 , when the ratio of the output voltage to the input voltage exceeds 95%, the conduction time exceeds 950ns. The maximum conduction time control circuit of this embodiment will take effect when the conduction time is 950ns, and the upper power tube will be turned off. When the clock frequency is 2MHz, Figure 4 As shown in FIG. 1 , when the ratio of the output voltage to the input voltage of the Buck circuit exceeds 90%, the conduction time exceeds 450ns. The maximum conduction time control circuit of this embodiment will take effect when the conduction time is 450ns, and the upper power tube will be turned off. When the clock frequency is 500kHz, Figure 5 As shown, when the ratio of the output voltage to the input voltage of the Buck circuit exceeds 97.5%, the conduction time exceeds 1950ns, and the maximum conduction time control circuit of this embodiment will take effect when the conduction time is 1950ns, turning off the upper power tube. The maximum conduction time control circuit of this embodiment can control the maximum conduction time of the upper power tube in the Buck circuit to change adaptively with the clock frequency, and limit the maximum conduction time of the upper power tube, ensuring that the Buck circuit can work normally when the input voltage is slightly higher than the output voltage.
Claims
1. A maximum on-time control circuit that changes adaptively with frequency, used in a Buck circuit, in which an upper power tube and a lower power tube are connected in series and their connection points are filtered by an inductor and a capacitor to generate a stable output voltage, and the control ends of the upper power tube and the lower power tube are controlled to be turned on and off by a power tube drive control circuit, characterized in that: The maximum on-time control circuit includes an IBIAS reference current module, a capacitor and a logic control module. The output end of the IBIAS reference current module is respectively connected to one end of the capacitor and the input end of the logic control circuit, and the other end of the capacitor is grounded. The logic control module includes a D trigger. The output end of the D trigger is connected to the input end of the power tube drive control circuit in the Buck circuit. The IBIAS reference current module includes a shutdown signal control end for inputting a shutdown signal and a charge and discharge control end for controlling the charging and discharging of the capacitor.
2. The maximum on-time control circuit that changes adaptively with frequency according to claim 1, characterized in that: The logic control module also includes a first inverter, a second inverter and a NAND gate. The output end of the IBIAS reference current module is connected to the input end of the first inverter, the output end of the first inverter is connected to the first input end of the NAND gate, the second input end of the NAND gate inputs the upper power tube gate signal, the output end of the NAND gate is connected to the D input end of the D flip-flop, the clock signal input end of the D flip-flop inputs the clock signal, the reset signal input end of the D flip-flop is connected to the output end of the second inverter, and the input end of the second inverter is connected to the charge and discharge control end of the BIAS reference current module.
3. The maximum on-time control circuit that changes adaptively with frequency according to claim 2, characterized in that: The maximum on-time control circuit also includes a PMOS tube, a source of the PMOS tube is connected to a power supply, a drain of the PMOS tube is connected to an input end of the first inverter, and a gate of the PMOS tube is connected to an output end of the first inverter.
4. A maximum on-time control circuit that changes adaptively with frequency according to any one of claims 1 to 3, characterized in that: A resistor is connected between the output of the IBIAS reference current module and the capacitor.