A wide frequency conversion three-phase AC input preprocessing method and system

Abstract

The present invention relates to the technical field of new energy storage systems, and specifically to a wide frequency conversion three-phase AC input preprocessing method and system. An overall operating architecture is designed, and based on the transient and steady-state judgment identifier output by the frequency processing function, low-pass and band-pass filtering are switched to achieve transient fast frequency switching tracking effect and better steady-state filtering effect. The present invention adopts discretization to implement the filtering algorithm, especially for the orthogonal coupling quantity in the two-phase stationary coordinate system, a band-pass complex coefficient sequence filter based on the ROGI structure is adopted. The present invention performs high-pass and de-jitter filtering on the zero-crossing detection ZCD-FLL frequency locking result, designs a steady-state criterion, and determines the steady-state conditions to adapt to different changes in the input frequency. The present invention designs a transient criterion by analyzing the frequency feedback coefficient, and quantitatively analyzes its threshold value reference, so that the system can recognize the fact of frequency change as quickly as possible during steady-state operation, return the frequency lock to zero, and restart the transient frequency lock.

Description

Technical Field

[0001] The present invention relates to the technical field of new energy storage systems, and in particular to a wide frequency conversion three-phase AC input preprocessing method and system. Background Art

[0002] With the continuous development of power electronics technology, wide frequency conversion AC power supply systems are widely used in aerospace, medical equipment, special power supplies and other fields due to their relatively low cost, high energy conversion efficiency and strong adaptability. The input AC power supply operating frequency range is usually 50-800Hz, and the power density of electrical equipment can be further improved at medium and high frequencies, which is conducive to the miniaturization and integration of equipment.

[0003] Based on this background, in the hardware design of actual projects, the circuit design layout is becoming more and more compact, which makes the sampling circuit extremely susceptible to interference from the power circuit. In addition, due to the size, the performance of the low-end digital control chip that can be selected is insufficient, which further limits the system's ability to process AC. In particular, for wide frequency three-phase AC, unlike the traditional 50Hz industrial frequency, there are steady-state uncertainties, including various disturbances in amplitude and phase, as well as rapid and large transient frequency shears. Therefore, it is necessary to study a preprocessing method to quickly track transient frequency shears under performance constraints, and improve the waveform quality in the steady state by accurately locking the frequency, while reducing the amount of calculation and reducing the average execution time of preprocessing, and optimizing the overall execution efficiency.

[0004] From the implementation point of view, for AC signals, the current filtering processing methods mainly rely on low-pass filter (LPF) or band-pass filter (BPF). Band-pass filtering relies on accurate frequency locking. Currently, there are mainly open-loop zero-cross detection (ZCD) algorithms, as well as closed-loop phase-locked loops (PLL) and frequency-locked loops (FLL). As for the specific implementation of band-pass filtering, in the past two decades, complex coefficient sequence filters based on reduced-order generalized integrators (ROGI) have been increasingly widely used.

[0005] Literature Li Mingyu. Research on control strategy of wide-range input three-phase Buck PFC rectifier [D]. Southwest Jiaotong University, 2020. The processing method is to directly couple the sampled three-phase AC signal with the control signal and input the modulation drive. This method does not require any phase-locked and frequency-locked links, which reduces the amount of calculation, but the THD of its AC power frequency signal depends entirely on the ability of the hardware sampling circuit to shield electromagnetic interference. The DC bias and harmonic components cannot be effectively filtered out in the software; or a low-pass filter with a lower cutoff frequency is used, which will bring a larger steady-state phase delay over a wide frequency band.

[0006] Literature Meng Yucheng. Research on wide frequency conversion aviation power grid AC-DC power supply based on digital control [D]. Nanjing University of Science and Technology, 2023. The double hysteresis loop zero-crossing detection frequency locking method is adopted. This method uses the zero-crossing detection algorithm to obtain the frequency of the AC quantity, and the corresponding filtering algorithm can be designed based on this frequency. The zero-crossing detection algorithm is very fast, but the accuracy of zero-crossing detection is limited by the corresponding interrupt processing frequency. It will bring large steady-state errors at medium and high frequencies above 400Hz, especially around 800Hz. If no further correction is made, the frequency directly obtained based on zero-crossing detection cannot be used for the accurate design of the bandpass filter.

[0007] Literature Golestan S, Guerrero JM, Vasquez JC, et al. A Study on Three-Phase FLLs [J]. IEEE Transactions on Power Electronics, 2018. The FLL frequency-locked loop structure is a relatively simple frequency information extractor developed in recent years, which combines a ROGI-based sequence filter with a frequency-locked integrator. However, for the frequency step shear conditions that may occur in wide-band input AC power supplies, no matter which frequency locking method is used, the transient process of frequency locking tracking cannot be avoided. This transient process cannot be ignored within a time that is not shorter than a certain threshold. Using a bandpass filter with an error will cause the modulation drive to give an erroneous signal, resulting in a large distortion of the system's output voltage and current, reducing the power factor, increasing THD, and in severe cases damaging the device. Summary of the invention

[0008] In view of this, an object of the present invention is to provide a wide frequency conversion three-phase AC input preprocessing method and system to solve the problem of large distortion of the output voltage and current of the system.

[0009] Based on the above purpose, the present invention provides a wide frequency conversion three-phase AC input preprocessing method, comprising the following steps:

[0010] Perform Clark transformation on the three-phase AC input data to obtain two-phase AC input datav iα and v iβ , for two-phase AC data v iα and v iβ Perform filtering to obtain two-phase AC output data v oα and v oβ , where the filtering process includes bandpass filtering and low-pass filtering. Bandpass filtering uses a complex coefficient filter based on ROGI, and like low-pass filtering, it uses a bilinear transformation method for discretization. v oα The process of frequency processing and filtering includes:

[0011] The frequency locking is completed through the designed steady-state criterion, that is, when entering the steady state, the bandpass filter is entered to improve the waveform quality;

[0012] The frequency shear is determined by the designed transient criterion, the frequency is reset to zero, the frequency lock is restarted, and a low-pass filter is used to track the waveform after the frequency update;

[0013] In view of the small disturbances in the frequency during steady-state operation, or the frequency error caused by the frequency locking accuracy, a fixed-period steady-state frequency compensation function is designed to automatically adjust the frequency fluctuation within the acceptable range.

[0014] Preferably, the frequency is locked using the zero-crossing detection method, and the obtained frequency is an approximate frequency f cg , design the steady-state frequency criterion, suppress the steady-state DC component of the frequency through a high-pass filter, and eliminate the influence of the unknown frequency and its changes on the steady-state judgment of the locked frequency.

[0015] Preferably, the frequency feedback error coefficient is designed to satisfy

[0016]

[0017] in t It is a time variable. Its steady-state value is verified by calculation to be independent of the operating frequency of the input AC signal and only related to the difference of the change:

[0018]

[0019] in V is the frequency of the alternating current, k is the cut-off angular frequency, and the transient criterion is designed. When the frequency is locked in a steady state, the system performs bandpass filtering to process the AC quantity. If the input AC quantity is relative to the current locked frequency, a large range of frequency shear ∆ oh G = oh g - oh og ,in oh g is the actual working frequency of the AC quantity, oh og The frequency of the frequency-locked system outputs. To ensure rapidity, low-pass filtering is not considered or a cutoff angle frequency is given that is much larger than k The low-pass e q (t)Satisfy:

[0020]

[0021] in e Q is the steady-state error before and after the input frequency is sheared, set at n Within the control cycle, the frequency is greater than ∆ oh min The transformation makes a shear response, that is, when t q = nT s of e q ( t q ) as the threshold for instability judgment e q_set ,at this time:

[0022] .

[0023] Preferably, in the steady-state execution stage, the inherent error of zero-crossing detection frequency locking and the small shear of the frequency signal are corrected through a fixed-cycle steady-state compensation. Suppose the frequency value to be corrected is equal to ∆ oh C , then the frequency feedback error coefficient that needs to be corrected in steady state is:

[0024]

[0025] The accurate output frequency can be obtained by correcting the following formula f og ,

[0026] .

[0027] The present invention also provides a wide frequency conversion three-phase AC input preprocessing system for executing the wide frequency conversion three-phase AC input preprocessing method.

[0028] Beneficial effects of the present invention:

[0029] 1. The wide frequency conversion three-phase AC input preprocessing method proposed in the present invention can simultaneously meet the transient fast frequency cutting tracking effect and the steady-state good filtering effect, and can cope with wide range frequency changes while achieving the improvement of steady-state AC waveform quality;

[0030] 2. The wide frequency conversion three-phase AC input preprocessing method proposed in the present invention is based on uneven interrupt processing time allocation, which greatly reduces the average execution time and reserves more resources for other processing tasks. While accurately locking the frequency and achieving the filtering effect, it reduces the resource consumption and calculation time of the algorithm as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only for the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 It is a schematic diagram of the overall architecture of the wide frequency conversion three-phase AC input preprocessing method adopted by the present invention.

[0033] Figure 2 The low-pass filter and its discrete implementation method used in the present invention, wherein Figure (a) is a frequency schematic diagram, and Figure (b) is a bilinear differential discrete implementation schematic diagram.

[0034] Figure 3 This is a ROGI-based bandpass complex coefficient sequence filter and its discrete implementation method adopted by the present invention, wherein Figure (a) is a frequency schematic diagram, and Figure (b) is a bilinear differential discretization implementation schematic diagram.

[0035] Figure 4 This is a logic block diagram of the ZCD-FLL zero-crossing detection method adopted by the present invention.

[0036] Figure 5 Schematic diagram of steady-state judgment operation waveform used in the analysis of the present invention, wherein Figure (a) is a schematic diagram of step cutting response, and Figure (b) is a schematic diagram of slope cutting response.

[0037] Figure 6 This is an overall logic block diagram of the wide frequency conversion three-phase AC input preprocessing method adopted by the present invention.

[0038] Figure 7 This is a schematic diagram of the 50Hz frequency locking verification used in the analysis of the present invention, wherein Figure (a) is, from top to bottom, a schematic diagram of the steady-state criterion based on the changes of the frequency locking low-pass filter and the high-pass filter, a schematic diagram of the control cycle count and the operation stage, and a schematic diagram of the frequency feedback error; Figure (b) is a waveform schematic diagram and a local enlarged diagram.

[0039] Figure 8 This is a schematic diagram of the 400Hz frequency locking verification used in the analysis of the present invention, wherein Figure (a) is, from top to bottom, a schematic diagram of the steady-state criterion based on the changes of the frequency locking low-pass filter and the high-pass filter, a schematic diagram of the control cycle count and the operation stage, and a schematic diagram of the frequency feedback error; Figure (b) is a waveform schematic diagram and a local enlarged diagram.

[0040] Figure 9 This is a schematic diagram of the 800Hz frequency locking verification used in the analysis of the present invention, wherein Figure (a) is, from top to bottom, a schematic diagram of the steady-state criterion based on the changes of the frequency locking low-pass filter and the high-pass filter, a schematic diagram of the control cycle count and the operation stage, and a schematic diagram of the frequency feedback error; Figure (b) is a waveform schematic diagram and a local enlarged diagram.

[0041] Figure 10 This is a schematic diagram of the verification of steady-state compensation for a small-range disturbance of 50-52Hz frequency used in the analysis of the present invention, wherein Figure (a) is, from top to bottom, a schematic diagram of compensation based on frequency locking, a schematic diagram of control cycle counting and operation phase, and a schematic diagram of frequency feedback error; Figure (b) is a waveform schematic diagram and a local enlarged diagram.

[0042] Figure 11 This is a schematic diagram of the verification of steady-state compensation for a small-range disturbance of 400-405Hz frequency used in the analysis of the present invention, wherein Figure (a) is, from top to bottom, a schematic diagram of compensation based on frequency locking, a schematic diagram of control cycle counting and operation phase, and a schematic diagram of frequency feedback error; Figure (b) is a waveform schematic diagram and a local enlarged diagram.

[0043] Figure 12 This is a schematic diagram of the verification of steady-state compensation for a small-range disturbance of 800-795Hz frequency used in the analysis of the present invention, wherein Figure (a) is, from top to bottom, a diagram of compensation based on frequency locking, a diagram of control cycle counting and operation stages, and a diagram of frequency feedback error; Figure (b) is a waveform diagram and a local enlarged diagram.

[0044] Figure 13 This is a schematic diagram of the 50-400-800-50Hz frequency wide range fast switching verification used in the analysis of the present invention, wherein Figure (a) is a waveform schematic diagram, a frequency locking schematic diagram, and a frequency feedback error schematic diagram from top to bottom; Figure (b) is a local enlarged diagram of Figure (a) at the moment of frequency cutting from top to bottom.

[0045] Figure 14 This is a schematic diagram of the 800-400-50-800Hz frequency wide range fast switching verification used in the analysis of the present invention, wherein Figure (a) is a waveform schematic diagram, a frequency locking schematic diagram, and a frequency feedback error schematic diagram from top to bottom; Figure (b) is a local enlarged diagram of Figure (a) at the moment of frequency cutting from top to bottom.

[0046] Figure 15 The following are histograms of the operating time of different methods used in the analysis of the present invention, wherein Figure (a) is the method based on zero-crossing detection and periodic delay compensation proposed by the present invention, Figure (b) is the transient steady-state switching method based on the ROGI-FLL frequency-locked loop, and Figure (c) is the frequency processing method based on the SRF-PLL phase-locked loop. DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments.

[0048] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0049] The present invention provides a method for preprocessing a wide frequency three-phase AC input, which is as follows:

[0050] 1. Overall architecture

[0051] In the overall design, low-pass filtering with a higher cutoff frequency can track the input sampling waveform faster, but the waveform quality is poor, which is not conducive to the modulation output of the steady-state waveform; while band-pass filtering can achieve good steady-state filtering effects, but cannot track quickly when the frequency is switched. Therefore, in order to simultaneously meet the transient fast frequency cutting tracking effect and the steady-state good filtering effect, the low-pass and band-pass switching method is adopted. The Clark transform of the three-phase data is obtained v iα and v iβ , filter it and get v oα and v oβ .right v oα Frequency processing is performed to obtain a frequency transient state identifier, which is used to feed back to the filter gate; and the AC signal frequency locked after steady state is used to fit the bandpass filter coefficient, such as Figure 1 shown.

[0052] For the assignment of frequency transient and steady state identifiers, design appropriate steady state criteria and transient state criteria.

[0053] For the steady-state criterion, it is mainly used in the frequency locking process. For frequency locking, since the calculation time of the trigonometric function of the phase-locked loop is relatively long, the frequency-locked loop relies on the error feedback of the bandpass sequence filter, and the filter parameters need to be refitted in each interrupt cycle. The above two closed-loop methods are relatively complex. Therefore, it is planned to lock the frequency through the zero-crossing detection method. The frequency locking is completed through the steady-state criterion, that is, the frequency has stabilized within a certain range, and the bandpass filter can be entered to improve the waveform quality.

[0054] For transient judgment, it is mainly used in steady-state operation. After the frequency shear, the fact of frequency change is recognized as quickly as possible, the frequency lock is reset to zero, the frequency lock is restarted, and a low-pass filter with a higher cutoff frequency is used to track the waveform after the frequency update at the expense of the quality of the transient output waveform.

[0055] Furthermore, in response to the conditions such as small disturbances in the frequency during steady-state operation, or frequency errors caused by frequency locking accuracy, a periodic steady-state frequency compensation function is designed to automatically adjust the frequency fluctuation within an acceptable range, so as not to frequently trigger the transient judgment, causing the frequency lock to return to zero, and then use low-pass filtering to reduce the waveform quality. At the same time, the periodic steady-state compensation calculation can reduce the average execution time of the steady-state frequency processing, while accurately locking the frequency, and reducing the resource consumption and calculation time of the frequency locking algorithm as much as possible.

[0056] 2. Filter discretization implementation

[0057] 2.1 Transient-Low-Pass Filter

[0058] Low-pass filtering is used in transient state, and its transfer function is

[0059] (1)

[0060] in oh c is the cutoff angular frequency, which is discretized into the following after bilinear transformation:

[0061] (2)

[0062] in T s is the filter sampling calculation period, and the coefficients are:

[0063] (3)

[0064] In order to ensure a certain clutter suppression capability and minimize phase delay, the cutoff frequency is designedf c =12kHz. Its time domain schematic diagram and discrete domain structure block diagram are as follows Figure 2 shown.

[0065] 2.2 Steady-state bandpass complex coefficient sequence filtering

[0066] The reduced-order generalized integrator ROGI is used to form a bandpass complex coefficient sequence filter, and its transfer function is:

[0067] (4)

[0068] in oh g is the resonant angular frequency where the passband gain is 1, k is the gain control parameter, which is generally equal to the power frequency angular frequency of the AC signal. After the bilinear transformation is discretized, it is:

[0069] (5)

[0070] The coefficients are:

[0071] (6)

[0072] The complex number j is realized using AC coupling terms. Its time domain schematic diagram and discrete domain structure block diagram are as follows Figure 3 shown.

[0073] 3. Zero-crossing detection and steady-state judgment

[0074] 3.1 ZCD-FLL Zero Crossing Detection Frequency Lock

[0075] The logic block diagram of the zero-crossing detection algorithm is as follows: Figure 4 As shown. Set two count values ​​tc_cont and st_cont, which are the sampling control count when the AC signal does not cross zero continuously, and the de-jitter filter count used to determine the zero crossing of the AC signal. Set the global variable state to record the positive and negative polarity of the current AC signal, positive is 1, and negative is 0. When the program enters the zero crossing detection frequency lock ZCD-FLL (Zero Crossing Detection FLL, ZCD-FLL), first tc_cont is incremented by 1, the polarity of the current sampling value is determined, and the current recorded state is XORed. If it is 1, the signal is detected to be zero crossing. At this time, in order to prevent the signal from being noise, the de-jitter filter processing is entered, and st_cont is incremented by 1; if it is detected that it is not zero crossing, it is directly reduced to 0. When st_cont exceeds a certain threshold, it is guaranteed that the signal crosses zero, and the current tc_cont value is recorded and the relevant count value is cleared. The frequency can be calculated using the following formula:

[0076] (7)

[0077] The locked frequency needs to be further low-pass filtered, and then enter the band-pass filter. After the band-pass filter, if the frequency remains stable, there is no need to execute the zero-crossing detection program to reduce resource consumption. Therefore, it is necessary to determine the moment when the locked frequency enters the steady state.

[0078] 3.2 Steady-state judgment

[0079] Since the frequency is unknown, and for zero-crossing detection, the larger the input AC frequency, the smaller the number of control count points, and the larger the frequency lock error, it is impossible to determine whether it has entered a steady state by the absolute value of the error or the frequency difference. If the direct delay method is used, since the change in the input AC signal frequency is not necessarily a step shear, it is impossible to guarantee that the input AC signal will reach stability after a certain period of time, so it is also impossible to directly determine whether it has entered a steady state by giving a given delay time.

[0080] In order to solve the influence of the unknown frequency and its change on the frequency-locked steady-state judgment, the sampling high-pass filter processes the output frequency and suppresses the DC component of the frequency. Its transfer function is as follows.

[0081] (8)

[0082] in oh h is the high-pass filter cutoff angular frequency. At this time, when the AC signal frequency is locked and stabilized, its value must tend to 0. Compared with differential, the use of high-pass filtering will not amplify the disturbance caused by high-frequency noise.

[0083] After the frequency is sheared, the high-frequency component is suppressed by the low-pass filter, and the DC component is suppressed by the high-pass filter. The curve is as follows: Figure 5 As shown. The curve is divided into an ascending phase and a descending phase, and there is a maximum point. Therefore, in each interrupt, the high-throughput calculated this time is compared with the maximum value obtained previously, and the maximum value can be iteratively obtained. The maximum value is calculated at a certain ratio to obtain a stable threshold. When the curve decreases over time and is less than the threshold, de-jitter filtering is performed. That is, if the high-pass judgment value calculated by the interrupt control is less than the stable threshold, the count is automatically increased by 1, otherwise it is automatically decreased by 1. When the count accumulates to a certain amount, the de-jitter delay is completed, and it is judged to enter a steady state.

[0084] Since the accuracy of zero-crossing detection depends on the size of the control frequency, it is impossible to achieve complete accuracy. For example, at 800Hz, if a control frequency of 40kHz is used, the half-cycle sampling points of the input AC signal are only 25 points. When the counting error differs by ±1 point, the obtained frequency error can reach +33.3Hz or -30.8Hz, and this error cannot be completely eliminated by low-pass. In particular, for some frequencies, the number of half cycles cannot be completely divided by 40kHz. At this time, the obtained frequency will show periodic fluctuations. Under the condition of satisfying steady-state conditions, it still has a certain error with the actual frequency, that is, the obtained frequency is an approximate frequency f cg .

[0085] 4. Transient judgment and steady-state frequency error compensation

[0086] 4.1 Frequency feedback error analysis

[0087] Set frequency feedback error e q satisfy:

[0088] (9)

[0089] Depend on Figure 3 (a), we can get the system equation:

[0090] (10)

[0091] In the formula oh og is the current angular frequency obtained by locking. Considering the case of amplitude quasi-locking, the input and output AC amplitudes are equal, that is, V o ≈ V i = V ,analyze e q Differentiating (t) with respect to time yields:

[0092] (11)

[0093] in v iα v oα + v iβ v oβ = V 2 , which can be obtained by Laplace transform e q About the angular frequency difference ∆ oh g = oh g - oh og The transfer function of (12) satisfies the first-order system, and its cutoff angular frequency is k , e q It has nothing to do with the operating frequency of the input AC signal, but only with the difference of the change:

[0094] (12)

[0095] 4.2 Transient judgment

[0096] When the frequency is locked in steady state, the system performs bandpass filtering to process the AC. If the input AC quantity is relative to the current locked frequency, a large range of frequency shear ∆ oh G = oh g - oh og To ensure rapidity, low-pass filtering is not considered or a cutoff frequency is given that is much greater than k Low pass, such as 0.2~0.5 f s Then according to formula (12), e q ( t )satisfy:

[0097] (13)

[0098] in e Q is the steady-state error before and after the input frequency is sheared. n Within the control cycle, the frequency is greater than ∆ oh min The transformation makes a shear response, that is, when t q = nT s of e q ( t q ) as the threshold for instability judgment e q_set .at this time:

[0099] (14)

[0100] like e q_setIf the value is too large, the shear response time will increase, bringing unstable impact. If the value is too small, the transient criterion will be frequently triggered, entering the transient state and performing low-pass filtering, resulting in a waste of computing resources and reduced waveform quality. Therefore, the threshold should be reasonably adjusted based on the above calculation according to the actual working conditions. However, the steady-state value of the frequency feedback error exists and must exist e Q < e q_set In this case, the transient discriminant cannot be used for judgment. In this case, the frequency needs to be corrected through steady-state frequency error compensation.

[0101] 4.3 Steady-state frequency error compensation

[0102] Calculating the bandpass coefficient using frequency parameters with errors will cause deviations in the amplitude and phase of the AC data after filtering, thus affecting the waveform quality. During operation, there are two possible conditions that require steady-state error compensation:

[0103] (1) After the transient frequency locking is completed, it can be obtained from the previous section that when the frequency locking is performed through zero-crossing detection and enters the steady-state bandpass filter, the locked frequency is limited by accuracy and has errors;

[0104] (2) During the steady-state execution process, the frequency of the input AC signal undergoes a small shear, and the steady-state value of the frequency feedback error is less than the threshold of the transient criterion;

[0105] In the above two cases, the cut-off frequency is set to be equal to ∆ oh C = oh g - oh cg , which can be regarded as a step response. Since steady-state compensation requires more accurate e q value, so e q Perform low-pass filtering to obtain e qL , assuming the low-pass cutoff frequency is oh εq , this frequency is small and cannot be ignored, then:

[0106] (15)

[0107] Its step response time domain expression is:

[0108] (16)

[0109] in e C is the steady-state error of frequency correction, take e q =0.95 e C Time point t 0 is used as the correction starting point, which satisfies:

[0110] (17)

[0111] t 0 time has nothing to do with the input power frequency and amplitude of the AC quantity. The above transcendental equation can be solved by Newton iteration method and other related numerical analysis methods. t 0 basic delay t 1, which ensures that the frequency feedback error at this point e q In steady state e C , the accurate output frequency can be obtained by the following correction f og :

[0112] (18)

[0113] Therefore, in the steady-state execution phase, the fixed cycle T tc = t 0+ t 1. Steady-state compensation is performed without the need for constant feedback correction to reduce the overall resource consumption rate of the frequency processing algorithm.

[0114] 5. Implementation and Verification

[0115] 5.1 Parameter setting and calculation

[0116] From the above, the frequency switching processing algorithm logic block diagram is as follows: Figure 6 As shown, Fin_FLL_flag is the frequency lock identifier: when Fin_FLL_flag=0, it is a transient frequency lock state, executing zero-crossing detection → steady-state judgment, including high-pass filtering and de-jittering delay; when Fin_FLL_flag=1, it is a steady-state execution state, executing frequency feedback error calculation → transient judgment → steady-state compensation, including low-pass filtering and delay.

[0117] Design control frequency f s =40kHz, that is T s =25us. Design LPF low-pass filter cutoff frequency f c If the frequency is 20kHz, the parameters of LPF are:

[0118]

[0119] For BPF, considering the filtering effect, it is set to have a -10dB amplitude gain suppression effect at the triple frequency of any power frequency of 50-800Hz, that is:

[0120]

[0121] It can be deduced that:

[0122]

[0123] Pick k =197, and the polynomial fitting is performed by the least square method through MATLAB. Then the BPF coefficients can be calculated by the following polynomials in the range of 50-800Hz:

[0124]

[0125] For steady-state judgment, the high-pass cutoff frequency is set to 20 Hz and the debouncing delay threshold is designed to 1600.

[0126] For the steady-state compensation part, design e q Too low pass e qL Cut-off frequency f εq is 32Hz. The approximate solution of equation (17) is obtained by numerical calculation: t 0=0.024s, take t 1=8ms, then the delay period of steady-state compensation T tc A total of 32ms, that is, the delay period T tc The corresponding control cycle count threshold is 1280.

[0127] For transient judgment, for the working condition where the effective value of the phase voltage is 115V and the absolute value of the switching frequency is 50Hz, it is designed to be within 1ms, that is, n = The frequency switching is reflected within 40 control cycles. At this time, the transient instability judgment threshold is 7540 according to formula (18), that is, e q_set Must not be less than this value.

[0128] The above-mentioned related setting values ​​need to be adjusted according to actual working conditions and response speed requirements.

[0129] 5.2 Frequency Processing Algorithm Simulation Implementation

[0130] The given noise composition is set as follows: white noise power 1e-3, and fundamental wave superimposed 100kHz amplitude 0.01 mixing noise. After adjustment, eq It needs to pass through a higher cutoff frequency of 0.5 f s =20kHz low-pass filtering, preliminary processing, and use backward difference discretization to save computing power; transient instability judgment threshold e q_set The given value needs to be increased to 10k.

[0131] First, verify the frequency locking process, mainly verify the steady-state criterion and frequency locking error compensation process. Perform frequency locking on 50Hz, 400Hz, and 800Hz respectively. Figure 7 ,8,9Result diagram. The control cycle count is superimposed after the frequency-locked high-pass flux is less than the stable threshold, and reaches the de-jitter delay count threshold to enter the steady state. At this time, the frequency feedback error begins to be calculated. After the compensation delay time, the current feedback error after low-pass filtering is detected and read, and compensated by (18). After compensation, the frequency feedback error gradually returns to zero. Observing the waveform diagram, it can be seen that in the frequency-locked transient LPF stage, the quality of the filtered output waveform is poor. In the BPF but frequency uncalibrated compensation stage, the waveform noise is filtered out, but there is an obvious phase difference with the original curve. After compensation calibration, the phase error is eliminated.

[0132] Secondly, verify the steady-state compensation effect of small-range frequency disturbance. Add small disturbances to 50Hz, 400Hz, and 800Hz respectively, so that their frequencies are switched to 52Hz, 405Hz, and 795Hz at 0.5s. Figure 10 ,11,12 Result diagram. Frequency feedback error coefficient e q The absolute value rises but does not reach the transient judgment condition, and the waveform has a phase error. When the control cycle count reaches the steady-state compensation delay period, the system compensates the frequency. e q The phase error is eliminated, indicating that the frequency has been accurately compensated.

[0133] Finally, verify the processing effect of fast switching over a wide frequency range. Observe the control parameter waveform at the moment of switching. e q Absolute value greater than e q_set When the frequency is locked and returns to zero, it means that the frequency has been switched. The time from input frequency cutting to frequency locking and returning to zero is the response time of the transient criterion.

[0134] Set the frequency conversion to 50 → 400 → 800 → 50Hz, and the shear nodes to 0.5s, 1.0s and 1.5s. The result is as follows Figure 13As shown, the three frequency cutting moments are magnified. At this time, the response times of the transient criteria of the three nodes are 223.9μs, 226.8μs and 123.1μs respectively, and the required control cycles n are 9, 9 and 6 respectively, which meet the design requirements.

[0135] Set the frequency conversion to 800 → 400 → 50 → 800Hz, and the shear nodes to 0.5s, 1.0s and 1.5s. The result is as follows Figure 14 As shown, the three frequency cutting moments are magnified. At this time, the response times of the transient criteria of the three nodes are 199.2μs, 224.9μs and 125.5μs respectively, and the required control cycles n are 8, 9 and 5 respectively, which meet the design requirements.

[0136] 5.3 Comparison of Algorithm Resources on DSP Platform

[0137] An experimental platform was built based on Ti's TMS320F28035, and a program was written on the embedded integrated addition coprocessor (CLA) to implement the zero-crossing detection and periodic delay compensation method proposed by the present invention, the transient steady-state switching method based on the ROGI-FLL frequency-locked loop, and the frequency processing method based on the SRF-PLL phase-locked loop. The execution time of each program was measured by outputting high and low levels at the I / O port, and the following data was obtained:

[0138] Table 1 Execution time measurement of different algorithms

[0139]

[0140] Based on the above data, a time bar graph is drawn as shown in Figure 15, where the horizontal axis is designed as the timing process from transient to steady state. As can be seen from the figure, the phase-locked and frequency-locked SRF-PLL consumes a lot of time due to the design of trigonometric function calculations. For the method proposed in this article and the ROGI-FLL algorithm, the time taken is relatively less. In the transient stage, the ZCD-FLL (a.1) used in the present invention only takes 1.089μs, which is less than the 2.547μs required for ROGI-FLL to execute (b.1), so it has an advantage in the total transient time. In the steady-state stage, ROGI-FLL itself includes BPF filtering, which reduces the time consumption; while the method proposed in the present invention requires additional delay compensation. Every certain delay period, an interruption (a.5) is required to re-compensate the frequency and fit the parameters. This time is slightly longer than the time required for ROGI-FLL in the steady state (b.4).

[0141] However, in the steady-state phase, the proposed method only takes 1.123 μs in the rest of the interrupt processing process (a.4) of the entire delay cycle, which is only half of the time required for ROGI-FLL steady-state execution. This method greatly reduces the average execution time. By allocating the uneven interrupt processing time for the frequency processing algorithm, the system can retain enough instruction storage and time resources to process additional complex algorithms such as state machines, control, modulation, etc. in most control interrupts, optimizing the overall execution efficiency and enhancing the flexibility of resource scheduling in a multi-tasking environment.

[0142] Those skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the present invention is limited to these examples; under the concept of the present invention, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity. Any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A wide frequency conversion three-phase AC input preprocessing method, characterized in that: The following steps are involved: Perform Clark transformation on the three-phase AC input data to obtain the two-phase AC input data v iα and v iβ , for two-phase AC data v iα and v iβ Perform filtering to obtain two-phase AC output data v oα and v oβ , where the filtering process includes bandpass filtering and low-pass filtering. Bandpass filtering uses a complex coefficient filter based on ROGI, and like low-pass filtering, it uses a bilinear transformation method to discretize v oα The process of frequency processing and filtering includes: The frequency locking is completed through the designed steady-state criterion, that is, when entering the steady state, the bandpass filter is entered to improve the waveform quality; The frequency shear is determined by the designed transient criterion, the frequency is reset to zero, the frequency lock is restarted, and a low-pass filter is used to track the waveform after the frequency update; In case of small disturbances in the frequency during steady-state operation or frequency errors caused by frequency locking accuracy, a fixed-period steady-state frequency compensation function is designed to automatically adjust the frequency fluctuation within an acceptable range. Design the frequency feedback error coefficient to meet ε q (t)=v iβ (t)·v oα (t)-v iα (t)·v oβ (t); Where t is a time variable, and its steady-state value is verified by calculation to be independent of the operating frequency of the input AC signal and only related to the difference in change: Where V is the frequency of the AC quantity, k is the cutoff angular frequency, and the transient criterion is designed. When the frequency is locked in a steady state, the system performs bandpass filtering to process the AC quantity. If the input AC quantity is relative to the current locked frequency, a large range of frequency shear Δω is generated. G =ω g -ω og , where ω g is the actual working frequency of the AC quantity, ω og is the output frequency of the frequency-locked system. To ensure rapidity, low-pass filtering is not considered or a low-pass filter with a cutoff angular frequency much greater than k is given. According to the following formula ε q (t)Satisfy: where ε Q is the steady-state error before and after the input frequency is sheared, set within n control cycles, for frequencies greater than Δω min The transformation makes a shear response, that is, when t q =nT s ε q (t q ) as the threshold value ε for instability judgment q_set ,at this time:

2. The wide frequency conversion three-phase AC input preprocessing method according to claim 1, characterized in that: The frequency is locked by using the zero-crossing detection method, and the obtained frequency is an approximate frequency f cg , design the steady-state frequency criterion, suppress the steady-state DC component of the frequency through a high-pass filter, and eliminate the influence of the unknown frequency and its changes on the steady-state judgment of the locked frequency.

3. The wide frequency conversion three-phase AC input preprocessing method according to claim 1, characterized in that: In the steady-state execution stage, the inherent error of zero-crossing detection frequency locking and the shear of the frequency signal are corrected through the fixed-cycle steady-state compensation. Suppose the corrected frequency value is equal to Δω C , then the frequency feedback error coefficient that needs to be corrected in steady state is: The accurate output frequency f is obtained by correcting the following formula og , 4. A wide frequency conversion three-phase AC input preprocessing system, characterized in that: Used to execute the wide frequency conversion three-phase AC input preprocessing method as described in any one of claims 1-3.

Images