A voltage balancing control method and controller for a three-level circuit converter

Abstract

The present application is applicable to the field of electric energy conversion technology, and provides a voltage equalization control method and controller for a three-level circuit converter. The method includes: obtaining the average value of the half-bus bias and the inductor current of the current switching cycle and the previous switching cycle of the three-level circuit converter; determining the duty cycle compensation amount based on the half-bus bias of the current switching cycle; judging the corresponding compensation direction, target compensation tube and integral parameters for eliminating static errors based on the average value of the half-bus bias and the inductor current of the current switching cycle and the previous switching cycle; performing voltage equalization control on the target compensation tube based on the duty cycle compensation amount, compensation direction, target compensation tube and integral parameters for eliminating static errors to perform voltage correction. The method of the present application can avoid the debugging personnel from repeatedly debugging the parameters of the voltage equalization ring due to changes in the equipment application scenario, improve the correction speed and accuracy, and improve the output voltage and current control accuracy.

Description

Technical Field

[0001] The present application belongs to the technical field of electric energy conversion, and in particular relates to a voltage equalization control method and controller for a three-level circuit converter. Background Art

[0002] Converters, such as DC-DC and DC-AC converters, are primarily used to convert one form of electrical energy into another. This process may involve changes in electrical parameters such as voltage, current, frequency, phase number, or power factor. Converter control circuits include, but are not limited to, open-loop and closed-loop control. Open-loop control circuits are typically used in applications where output accuracy is not a priority. Their control strategies are relatively simple and do not rely on output feedback. Closed-loop control circuits, on the other hand, utilize output feedback signals to precisely control and adjust output parameters. They are widely used in power electronics devices requiring high precision, high stability, and dynamic response.

[0003] In three-level circuit converters and other related devices, voltage balancing of the voltage-dividing capacitors is a critical issue that must be addressed. Ideally, the voltage-dividing capacitors should maintain voltage balance and be half the output voltage. However, in practical circuits, since the driver circuits and switching characteristics of the switches cannot be exactly the same, the duty cycles of the two switches will inevitably vary. This results in the energy provided by the two voltage-dividing capacitors within a cycle not being completely equal, resulting in uneven voltage balancing. Therefore, voltage balancing control technology is needed to address this issue.

[0004] Existing three-level converter voltage balancing control technology typically uses a PI controller for the balancing loop, with fixed control parameters. To avoid overshoot and oscillation, the proportional parameters are often set too low when the parameters are fixed, resulting in relatively slow control speed during power conversion. When power is switched rapidly, the transition process in the string equipment may cause uneven current distribution, preventing the equipment from operating normally. Some designs do not include an integral parameter, resulting in a static error in the half-bus voltage, causing certain ripple in the output voltage and current, and reducing output power performance. In designs that do include an integral parameter, debugging the integral parameter is often related to the equipment's hardware specifications and application. An excessively strong integral link can cause response lag and even trigger equipment failures and control instability. An excessively weak integral link reduces dynamic response speed, requiring the commissioning personnel to rely on their experience. Improper commissioning can easily lead to bias and prevent the equipment from operating normally. Summary of the Invention

[0005] In order to overcome the problems existing in the related technology, the embodiment of the present application provides a voltage equalization control method and controller for a three-level circuit converter, which can avoid the debugging personnel from repeatedly debugging the voltage equalization ring parameters due to changes in the equipment application scenario, improve the correction speed and accuracy, and improve the output voltage and current control accuracy.

[0006] This application is achieved through the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a voltage balancing control method for a three-level circuit converter, comprising:

[0008] Obtaining a half bus bias voltage of a current switching cycle of the three-level circuit converter, an average value of the inductor current of the current switching cycle, a half bus bias voltage of a previous switching cycle, and an average value of the inductor current of the previous switching cycle;

[0009] Determine the duty cycle compensation amount based on the half bus bias voltage of the current switching cycle;

[0010] Based on the half-bus bias voltage of the current switching cycle, the average value of the inductor current of the current switching cycle, the half-bus bias voltage of the previous switching cycle, and the average value of the inductor current of the previous switching cycle, the corresponding compensation direction, the target compensation tube, and the integral parameter for eliminating static error are determined;

[0011] Based on the duty cycle compensation amount, compensation direction, target compensation tube and integral parameters for eliminating static error, the target compensation tube is subjected to voltage equalization control to perform voltage correction.

[0012] In a possible implementation of the first aspect, determining the duty cycle compensation amount based on the half bus bias of the current switching cycle includes:

[0013] Determining the conversion relationship between the duty cycle compensation amount and time based on the carrier period value and the switching frequency of the time reference module of the three-level circuit converter;

[0014] The duty cycle compensation amount is determined based on the conversion relationship between the half bus bias voltage and the duty cycle compensation amount and time in the current switching cycle.

[0015] In a possible implementation of the first aspect, the duty cycle compensation amount Expressed as:

[0016]

[0017] in, is the absolute value of the half bus bias voltage of the current switching cycle; is the half bus capacitance value; is the switching frequency; is the carrier period value of the time base module of the three-level circuit converter; is the average value of the inductor current in the current switching cycle.

[0018] In a possible implementation of the first aspect, after determining the duty cycle compensation amount based on the half-bus bias of the current switching cycle, the voltage sharing control method for the three-level circuit converter further includes:

[0019] Setting a preset value for a maximum adjustment bias voltage in a single switching cycle, and determining a limit value for a duty cycle compensation amount based on the preset value for the maximum adjustment bias voltage in a single switching cycle; the limit value for the duty cycle compensation amount is used to limit the duty cycle compensation amount; wherein, when the average value of the inductor current in the current switching cycle is less than 2 A, the limit value for the duty cycle compensation amount is 0;

[0020] The duty cycle compensation amount is updated based on the limit value of the duty cycle compensation amount to obtain an updated duty cycle compensation amount.

[0021] In a possible implementation of the first aspect, determining a corresponding compensation direction, a target compensation tube, and an integral parameter for eliminating static error based on a half-bus bias voltage of a current switching cycle, an average value of an inductor current of the current switching cycle, a half-bus bias voltage of a previous switching cycle, and an average value of an inductor current of the previous switching cycle includes:

[0022] Determine a change trend of the half-bus bias based on the half-bus bias of the current switching cycle and the half-bus bias of the previous switching cycle;

[0023] Determine a change trend of the inductor current based on an average value of the inductor current in the current switching cycle and an average value of the inductor current in the previous switching cycle;

[0024] Determine the compensation direction based on the changing trend of the half-bus bias voltage and the changing trend of the inductor current;

[0025] Determine the target compensation tube in the compensation direction;

[0026] For the target compensation tube, determine the corresponding integral parameters for eliminating static error.

[0027] In a possible implementation of the first aspect, determining a corresponding integral parameter for eliminating static error includes:

[0028] determining a rate of change of the inductor current based on an average value of the inductor current in a current switching cycle and an average value of the inductor current in a previous switching cycle;

[0029] An integral parameter for eliminating static error is determined based on the rate of change of the inductor current and the half-bus bias voltage of the current switching cycle.

[0030] In a possible implementation of the first aspect, the rate of change of the inductor current is Expressed as:

[0031]

[0032] in, is the average value of the inductor current in the current switching cycle; is the average value of the inductor current in the previous switching cycle; is the switching frequency;

[0033] Integral parameter to eliminate static error Expressed as:

[0034]

[0035] in, is the initial integration parameter, ; k is the current switching cycle; is the half bus bias voltage of the current switching cycle; t For time.

[0036] In a possible implementation of the first aspect, the voltage sharing control method for a three-level circuit converter further includes:

[0037] During the commutation process of voltage-equalizing control of the target compensation tube, a commutation digital logic is set; the commutation digital logic includes clearing the integral parameter for eliminating the static error when the positive or negative polarity of a single quantity in the average value of the half-bus bias voltage or the inductor current changes between the current moment and the previous moment.

[0038] In a possible implementation of the first aspect, obtaining an average value of a half-bus bias voltage and an average value of an inductor current in a current switching cycle of a three-level circuit converter includes:

[0039] Obtaining a capacitance value of a half busbar of a three-level circuit converter in a current switching cycle and an inductor current in a current switching cycle;

[0040] Determine an average value of the inductor current in the current switching cycle based on the inductor current in the current switching cycle;

[0041] A half bus bias voltage of the current switching cycle is determined based on the capacitance value of the current switching cycle and the inductor current of the current switching cycle.

[0042] In a second aspect, the present application provides a controller, which is used to execute the voltage balancing control method for a three-level circuit converter as described in the first aspect.

[0043] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0044] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0045] In the embodiment of the present application, the integral parameter for eliminating static error is determined based on the average value of the half-bus bias and the inductor current of the current and previous switching cycles. This dynamic adjustment based on real-time data can avoid response lag and control instability caused by an overly strong integral link, while also reducing the problem of reduced dynamic response speed caused by a too weak integral link, thereby avoiding the lack of reliance on personnel experience during the debugging process and reducing the risk of bias and equipment failure caused by improper debugging. In addition, based on the data of the current and previous switching cycles to determine the compensation direction, target compensation tube, and duty cycle compensation amount, and to perform voltage equalization control on the compensation tube, it can ensure the accuracy and timeliness of compensation, thereby effectively performing voltage correction, effectively solving the problems caused by an integral link that is too strong or too weak, reducing the workload of equipment maintenance and technical support, reducing output voltage and current ripple, improving output control accuracy, and also improving the overall performance and stability of the system, providing a strong guarantee for the normal operation of the equipment.

[0046] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0048] Figure 1 1 is a flow chart of a voltage balancing control method for a three-level circuit converter provided in one embodiment of the present application;

[0049] Figure 2 This is a topological diagram of a single-channel bidirectional DC converter provided in one embodiment of the present application;

[0050] Figure 3 This is a block diagram of a voltage balancing ring provided in one embodiment of the present application;

[0051] Figure 4 This is a schematic diagram of the relationship between the duty cycle compensation amount of the voltage-sharing control and the output PWM waveform in the three-level phase-shifted wave generation mode provided in one embodiment of the present application;

[0052] Figure 5 This is a duty cycle compensation calculation block diagram provided by an embodiment of the present application;

[0053] Figure 6 This is a block diagram of a direction identification module provided in one embodiment of the present application;

[0054] Figure 7It is a structural diagram of a controller provided in one embodiment of the present application. DETAILED DESCRIPTION

[0055] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0056] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0057] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0058] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0059] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0060] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0061] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0062] Figure 1 This is a flow chart of a voltage balancing control method for a three-level circuit converter provided by an embodiment of the present application, with reference to Figure 1 The voltage balancing control method of the three-level circuit converter is described in detail as follows:

[0063] An embodiment of the present application provides a method for controlling voltage sharing of a three-level circuit converter, the method comprising:

[0064] Step 101: Obtain a half bus bias voltage of a current switching cycle, an average value of an inductor current of the current switching cycle, a half bus bias voltage of a previous switching cycle, and an average value of an inductor current of the previous switching cycle of a three-level circuit converter.

[0065] Exemplary, half bus bias Refers to the difference between the half bus voltage at the input and output ends. Taking a single-channel bidirectional DC converter as an example, Figure 2 As shown, the half-bus bias is the voltage of capacitor C2 minus the voltage of capacitor C1, and the average value of the inductor current in the current switching cycle is Refers to the average value of the current through the inductor L1 in the current switching cycle. Or half bus bias The voltage of capacitor C3 minus the voltage of capacitor C1, the average value of the inductor current in the current switching cycle Refers to the average value of the current passing through the inductor L2 in the current switching cycle.

[0066] Step 102: Determine a duty cycle compensation amount based on a half bus bias voltage of a current switching cycle.

[0067] For example, Figure 3 The block diagram of the voltage balancing loop is shown in Figure 2. The voltage balancing loop includes a compensation calculation module and a direction detection module. The compensation calculation module obtains the half bus bias voltage of the current switching cycle. Determine the duty cycle compensation amount , the compensation calculation module calculates the duty cycle compensation Passed to the identification module.

[0068] Step 103: Determine the corresponding compensation direction, target compensation tube, and integral parameter for eliminating static error based on the half-bus bias of the current switching cycle, the average value of the inductor current of the current switching cycle, the half-bus bias of the previous switching cycle, and the average value of the inductor current of the previous switching cycle.

[0069] For example, use k Represents the current switching cycle, then k -1 indicates the last switching cycle, such as Figure 3As shown, the direction detection module is based on the half bus bias voltage of the current switching cycle. , the average value of the inductor current in the current switching cycle , half bus bias voltage of the previous switching cycle and the average value of the inductor current in the previous switching cycle Determine the changing trends of the bus voltage and inductor current. Based on the changing trends of the bus voltage and inductor current, the current compensation direction and the switch tube that needs to be compensated can be determined. The corresponding compensation direction, target compensation tube and integral parameters for eliminating static error can be determined, so that the corresponding duty cycle compensation value can be output to the target compensation tube to adjust the bias.

[0070] Step 104 : Based on the duty cycle compensation amount, the compensation direction, the target compensation tube, and the integral parameter for eliminating static error, voltage equalization control is performed on the target compensation tube to perform voltage deviation correction.

[0071] For example, when the no-load / light-load voltage deviation is large, the inductor current increases and reaches the control threshold, and control begins. According to the determined compensation direction (positive or negative) and the determined target compensation tube (G1, G2, G3 or G4), on the basis of the original duty cycle of the target compensation tube, voltage equalization control is performed according to the duty cycle compensation amount and the integral parameter for eliminating static error to perform voltage correction.

[0072] This embodiment determines the integral parameter for eliminating static error by taking the average values ​​of the half-bus bias and inductor current from the current and previous switching cycles. This dynamic adjustment based on real-time data can avoid response lag and control instability caused by an overly strong integral link, while also reducing the potential for reduced dynamic response speed caused by a too weak integral link. This avoids the lack of reliance on human experience during debugging and reduces the risk of bias and equipment failure caused by improper debugging. Furthermore, based on the data from the current and previous switching cycles, the compensation direction, target compensation tube, and duty cycle compensation amount are determined, and voltage balancing control is performed on the compensation tube, ensuring the accuracy and timeliness of compensation, thereby effectively performing voltage correction and resolving the issues caused by an overly strong or weak integral link.

[0073] In one embodiment, a specific process of obtaining the average value of the half bus bias voltage and the inductor current of the current switching cycle of the three-level circuit converter is specifically described. Then, step 101 includes:

[0074] First, obtain the capacitance value C of the half busbar of the three-level circuit converter in the current switching cycle and the inductor current of the current switching cycle. .

[0075] Then, based on the inductor current of the current switching cycle, , determine the average value of the inductor current in the current switching cycle .

[0076] For example, since the capacitor current cannot be sampled directly, the current loop can be used to , use the inductor current instead of the capacitor current in the calculation. Figure 4 The figure shows the relationship between the duty cycle compensation of the voltage-sharing control and the output PWM waveform under the three-level phase-shifted wave mode. In a single switching cycle, the sawtooth wave Figure 4 As shown in the figure, the shaded part of the compensation tube G2 PWM is the effective time of the voltage balance control. According to the effective time of the bias control, the rising edge and falling edge of CMP+DutyComp correspond to the peak value of the inductor current. t / 2 time. The inductor current acts near the valley value ∆ t / 2 time. It is approximately considered that the peak value acts on ∆ t / 2 time, the valley value acts on ∆ t / 2 time, that is Action time ∆t, that is .

[0077] Finally, based on the capacitance value C of the current switching cycle and the inductor current of the current switching cycle , determine the half bus bias voltage of the current switching cycle .

[0078] For example, since the half bus voltage control time is in microseconds, the inductor can be approximated as a constant current source. According to the constant current source charging formula for the capacitor, the voltage deviation of a single switching cycle can be obtained. , we can get the half bus bias The expression is:

[0079]

[0080] in, is the voltage-sharing control time, C is the half-bus capacitor value, is the half bus capacitance current, t For time.

[0081] In one embodiment, see Figure 5 , introduces the specific process of determining the duty cycle compensation amount. Step 102 includes:

[0082] Firstly, based on the carrier cycle value and the switching frequency of the time reference module of the three-level circuit converter, the conversion relationship between the duty cycle compensation amount and time is determined.

[0083] Exemplarily, the conversion relationship between the duty cycle compensation amount and time is expressed as:

[0084]

[0085] The duty cycle compensation amount is determined based on the conversion relationship between the half bus bias voltage and the duty cycle compensation amount and time in the current switching cycle.

[0086] For example, the half bus bias voltage is regulated Duty cycle compensation required Expressed as:

[0087]

[0088] in, is the absolute value of the half bus bias voltage of the current switching cycle; is the half bus capacitance value; is the switching frequency; is the carrier period value of the time base module of the three-level circuit converter; is the average value of the inductor current in the current switching cycle. You can select the carrier period value of the TB (time base) module of the DSP TMS320F28335 chip.

[0089] In addition, to prevent calculation errors and overshoot, the duty cycle compensation Therefore, after determining the duty cycle compensation amount based on the half bus bias voltage of the current switching cycle, the voltage balancing control method of the three-level circuit converter further includes:

[0090] A preset value of a maximum adjustment bias voltage in a single switching cycle is set, and a limit value of a duty cycle compensation amount is determined based on the preset value of the maximum adjustment bias voltage in a single switching cycle; the limit value of the duty cycle compensation amount is used to limit the duty cycle compensation amount; the duty cycle compensation amount is updated based on the limit value of the duty cycle compensation amount to obtain an updated duty cycle compensation amount.

[0091] For example, the preset value of the maximum adjustment bias voltage in a single switching cycle is set to 10V, that is, when When , substitute into formula (3) to get the limit value of duty cycle compensation, and update after limit .

[0092] Among them, when the average value of the inductor current in the current switching cycle is less than 2A, the limit value of the duty cycle compensation is 0. When the inductor current is close to 0A under no-load / light load, the bias compensation error may be caused by the noise of the previous stage or the sampling deviation. Therefore, when hour, ,otherwise DutyComp = DutyComp .

[0093] In one embodiment, see Figure 6The process of determining the corresponding compensation direction, the target compensation tube and the integral parameter for eliminating static error by the direction detection module is specifically introduced. Step 103 includes:

[0094] Based on the half-bus bias of the current switching cycle and the half-bus bias of the previous switching cycle, the changing trend of the half-bus bias is determined; based on the average value of the inductor current of the current switching cycle and the average value of the inductor current of the previous switching cycle, the changing trend of the inductor current is determined; based on the changing trend of the half-bus bias and the changing trend of the inductor current, the compensation direction is determined; the target compensation tube is determined in the compensation direction; for the target compensation tube, the corresponding integral parameter for eliminating static error is determined.

[0095] For example, the direction identification module mainly calculates the current cycle voltage compensation direction, compensation tube, and control static error elimination based on the physical quantity of the current switching cycle combined with the physical quantity state of the previous switching cycle. When calculating the current cycle voltage compensation direction and compensation tube, according to the current moment 、 , last moment 、 The combination logic relationship determines the compensation direction and compensation switch tube.

[0096] For example, if the bus voltage decreases and the inductor current increases, reactive power needs to be injected into the circuit, meaning the compensation direction is positive. If the bus voltage increases and the inductor current decreases, reactive power needs to be absorbed from the circuit, meaning the compensation direction is negative. Based on the compensation direction, the switches to be turned on or off are determined. If the compensation direction is positive, reactive power needs to be injected into the circuit, so the upper set of switches needs to be turned on to increase the inductor current. If the compensation direction is negative, reactive power needs to be absorbed from the circuit, so the lower set of switches needs to be turned on to reduce the inductor current.

[0097] Among them, determining the corresponding integral parameters for eliminating static errors includes:

[0098] The rate of change of the inductor current is determined based on an average value of the inductor current in the current switching cycle and an average value of the inductor current in the previous switching cycle.

[0099] For example, when eliminating static error, bias the half busbar Introduce integration and judge the current steady state and transient state according to the rate of change of inductor current. Calculate the rate of change of inductor current. Expressed as:

[0100]

[0101] in, is the average value of the inductor current in the current switching cycle; is the average value of the inductor current in the previous switching cycle; is the switching frequency.

[0102] Next, an integral parameter for eliminating static error is determined based on the rate of change of the inductor current and the half bus bias voltage of the current switching cycle.

[0103] like Figure 6 1 / S in the equation represents the half bus bias voltage of the current switching cycle. The integral parameter to eliminate static error Expressed as:

[0104]

[0105] in, is the initial integration parameter, ; k is the current switching cycle; is the half bus bias voltage of the current switching cycle; t is time. Integral compensation direction and duty cycle compensation amount Consistent, after entering the steady state, half bus bias When it is small, it automatically recognizes and improves the integral ratio to reduce the static error in steady state.

[0106] It should be noted that when determining the integral parameter to eliminate static error In the process of calculating the duty cycle, the duty cycle compensation amount still needs to be limited.

[0107] In addition, a special design is made for the commutation. When the no-load / light-load voltage deviation is large, the inductor current increases and reaches the control threshold to start control. The voltage lags behind the current, and there is a period of integral accumulation of the initial half-bus voltage bias. When the power is reversed, the response will lag due to the large hysteresis, which may cause the compensation direction to be wrong. When the power is reversed, the dominant position of the dominant tube remains unchanged. The sign will change when the average value of the inductor current When the reverse threshold is reached, the initial value of the average value of the inductor current is the forward commutation error value, and the integral output needs to be cleared to improve the direction recognition speed. Then, the voltage equalization control method of the three-level circuit converter also includes:

[0108] During the commutation process of performing voltage-sharing control on the target compensation tube, the commutation digital logic is set.

[0109] The commutation digital logic includes clearing the integral parameter for eliminating static error when the positive or negative polarity of a single quantity of the half-bus bias voltage or the average value of the inductor current changes between the current moment and the previous moment.

[0110] For example, based on the determination of the duty cycle compensation amount, compensation direction, target compensation tube, and integral parameter for eliminating static error, the specific process of performing voltage equalization control on the target compensation tube is as follows:

[0111] like The result of is 0, or , then:

[0112] when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle + DutyComp , G3 duty cycle- DutyCom - ;

[0113] when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle - DutyComp , G3 duty cycle + DutyCom + ;

[0114] when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle - DutyComp , G3 duty cycle + DutyCom + ;

[0115] when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle + DutyComp , G3 duty cycle- DutyCom - .

[0116] like The result of is 1, then there is :

[0117] when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle + DutyComp , G3 duty cycle- DutyCom ;

[0118] when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle - DutyComp , G3 duty cycle + DutyCom ;

[0119] when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle - DutyComp , G3 duty cycle + DutyCom ;

[0120] when When the target compensation tubes G2 and G3 are compensated: G2 duty cycle + DutyComp , G3 duty cycle- DutyCom .

[0121] Among them, the G1 and G4 tubes complement the G2 and G3 tubes in outputting complementary functions, controlling the output duty cycle compensation value to perform voltage correction on the corresponding switching tubes.

[0122] In one embodiment, in order to make the technical solution of the present invention clearer, in a three-level circuit converter, a 3-sink 1-way bidirectional DC converter with a rated power of 50kW is taken as an example to specifically illustrate the specific implementation process of the technical solution of the present invention.

[0123] Figure 2 For the single-channel topology diagram, the relevant parameters are as follows: the inductor L1 has an inductance of 424μH, the half-bus capacitors C2 and C3 have a capacitance of 1μF, the maximum current on the low-voltage side is 100A, the control cycle is 18kHz, and TBPRD=2083.

[0124] First, calculate the amplitude of the voltage-sharing control loop limiter module according to the circuit parameters. When the running direction is forward, the voltage-sharing loop selects the output limiter value. If the current on the low-voltage side is , select 10V / control cycle as the maximum voltage regulation capability, and reversely calculate the output limit value of the voltage equalizing ring :

[0125]

[0126] Therefore, the output limit of the voltage-sharing loop is set to ±187 V. The output limit of the integral circuit is set to ±187 V. Therefore, the maximum voltage regulation capability of the integral circuit per cycle is set to 2 V. The maximum limit of the integral circuit is calculated to be 187 × 2 / 10 = 37 V. Therefore, the maximum limit of the integral circuit is ±37 V.

[0127] During operation, the equipment is adaptively controlled according to the current load and power change rate parameters. For example, when the limit is switched, when the positive and negative 50kW are switched, the low voltage side voltage is 500V, the high voltage side voltage is 800V, and the power response time is 80ms, then the current change rate at this time is calculated to be 200A / 80ms×55μs=0.137A. At this time, the power changes faster, so take k is 0.00001, after adaptive calculation of integral parameter K i =0.00001 / 0.137=0.00007299.

[0128] The current single-cycle bias voltage is measured to be 16V (this value cannot be predicted and is related to environmental factors such as the IGBT switch temperature, switch gate resistance, collector current, and drive power supply voltage, and needs to be based on the actual measured value). Assuming that the current inductor current reaches 2A during the power change process, the duty cycle compensation is calculated as:

[0129]

[0130] Since the duty cycle compensation value 299V exceeds the duty cycle compensation limit value 187V, the output after limiting is 187V. Finally, according to the above process, the current moment is used. 、 , last moment 、 Calculate the corresponding compensation tube and whether the integral is cleared, and finally control the output duty cycle compensation value to the corresponding switching tube for voltage correction.

[0131] It can be seen that the voltage balancing control method for a three-level circuit converter proposed in the present invention determines the integral parameter for eliminating static error based on the average value of the half-bus bias voltage and the inductor current in the current and previous switching cycles. This dynamic adjustment based on real-time data can avoid response lag and control instability caused by an overly strong integral link, while also reducing the problem of reduced dynamic response speed caused by a too weak integral link, thereby avoiding the lack of reliance on personnel experience during the debugging process and reducing the risk of bias and equipment failure caused by improper debugging. In addition, based on the data of the current and previous switching cycles, the compensation direction, target compensation tube, and duty cycle compensation amount are determined, and the voltage balancing control of the compensation tube is performed, which can ensure the accuracy and timeliness of compensation, thereby effectively performing voltage correction, effectively solving the problems caused by an overly strong or weak integral link, reducing the workload of equipment maintenance and technical support, reducing output voltage and current ripple, improving output control accuracy, and improving the overall performance and stability of the system, providing a strong guarantee for the normal operation of the equipment.

[0132] See also Figure 7 One embodiment provides a controller, which is used to execute the voltage balancing control method of the three-level circuit converter in the above embodiment.

[0133] The present application also provides a controller, see Figure 7 The controller 200 may include: at least one processor 210 and a memory 220, wherein the memory 220 stores a computer program that can be run on at least one processor 210, and when the processor 210 executes the computer program, the steps in any of the above method embodiments are implemented.

[0134] For example, the computer program may be divided into one or more modules / units, one or more modules / units being stored in the memory 220 and executed by the processor 210 to complete the present application. One or more modules / units may be a series of computer program segments capable of completing specific functions, and the program segments are used to describe the execution process of the computer program in the controller 200.

[0135] Those skilled in the art will understand that Figure 7This is only an example of a controller and does not constitute a limitation of the controller. The controller may include more or fewer components than shown in the figure, or a combination of certain components, or different components, such as input and output devices, network access devices, buses, etc.

[0136] The processor 210 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0137] Memory 220 can be an internal storage unit of the controller or an external storage device, such as a plug-in hard drive, a Smart Media Card (SMC), a Secure Digital (SD) card, or a flash memory card. Memory 220 is used to store computer programs and other programs and data required by the controller. Memory 220 can also be used to temporarily store data that has been output or is about to be output.

[0138] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0139] The voltage balancing control method for a three-level circuit converter provided in the embodiments of the present application can be applied to controllers such as computers, tablet computers, laptop computers, netbooks, and personal digital assistants (PDAs). The embodiments of the present application do not impose any restrictions on the specific type of controller.

[0140] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0141] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A voltage balancing control method for a three-level circuit converter, characterized in that: include: Obtaining a half bus bias voltage of a current switching cycle of a three-level circuit converter, an average value of an inductor current of the current switching cycle, a half bus bias voltage of a previous switching cycle, and an average value of an inductor current of a previous switching cycle; the half bus bias voltage refers to a difference between a half bus voltage at an input end and a half bus voltage at an output end; Determining a duty cycle compensation amount based on a half bus bias voltage of the current switching cycle; determining a duty cycle compensation amount based on a half bus bias voltage of the current switching cycle, comprising: Determine the conversion relationship between the duty cycle compensation amount and time based on the carrier cycle value and the switching frequency of the time reference module of the three-level circuit converter; Determining the duty cycle compensation amount based on a conversion relationship between the half bus bias voltage of the current switching cycle and the duty cycle compensation amount and time; Based on the half bus bias of the current switching cycle, the average value of the inductor current of the current switching cycle, the half bus bias of the previous switching cycle and the average value of the inductor current of the previous switching cycle, the corresponding compensation direction, the target compensation tube and the integral parameter for eliminating the static error are judged; based on the half bus bias of the current switching cycle, the average value of the inductor current of the current switching cycle, the half bus bias of the previous switching cycle and the average value of the inductor current of the previous switching cycle, the corresponding compensation direction, the target compensation tube and the integral parameter for eliminating the static error are judged, including: Determining a change trend of the half bus bias based on the half bus bias of the current switching cycle and the half bus bias of the previous switching cycle; Determining a change trend of the inductor current based on an average value of the inductor current in the current switching cycle and an average value of the inductor current in the previous switching cycle; Determining a compensation direction based on a change trend of the half-bus bias voltage and a change trend of the inductor current; determining the target compensation tube in the compensation direction; For the target compensation tube, determining a corresponding integral parameter for eliminating static error; Based on the duty cycle compensation amount, the compensation direction, the target compensation tube and the integral parameter for eliminating static error, the target compensation tube is subjected to voltage equalization control to perform voltage correction.

2. The voltage balancing control method of a three-level circuit converter according to claim 1, characterized in that: The duty cycle compensation amount It is expressed as: in, is the absolute value of the half bus bias voltage of the current switching cycle; is half bus capacitance value; is the switching frequency; is the carrier period value of the time reference module of the three-level circuit converter; is the average value of the inductor current in the current switching cycle.

3. The voltage balancing control method of a three-level circuit converter according to claim 1, characterized in that: After determining the duty cycle compensation amount based on the half bus bias of the current switching cycle, the voltage sharing control method of the three-level circuit converter further includes: A preset value of a maximum adjustment bias voltage of a single switching cycle is set, and a limit value of a duty cycle compensation amount is determined based on the preset value of the maximum adjustment bias voltage of a single switching cycle; the limit value of the duty cycle compensation amount is used to limit the duty cycle compensation amount; wherein, when the average value of the inductor current of the current switching cycle is less than 2A, the limit value of the duty cycle compensation amount is 0; The duty cycle compensation amount is updated based on the limit value of the duty cycle compensation amount to obtain an updated duty cycle compensation amount.

4. The voltage balancing control method of a three-level circuit converter according to claim 1, characterized in that: The step of determining the corresponding integral parameter for eliminating static error comprises: Determining a rate of change of the inductor current based on an average value of the inductor current of the current switching cycle and an average value of the inductor current of the previous switching cycle; An integral parameter for eliminating static error is determined based on the rate of change of the inductor current and the half bus bias of the current switching cycle.

5. The voltage balancing control method of a three-level circuit converter according to claim 4, characterized in that: The rate of change of the inductor current It is expressed as: in, is the average value of the inductor current in the current switching cycle; is the average value of the inductor current in the previous switching cycle; is the switching frequency; The integral parameter for eliminating static error It is expressed as: in, is the initial integration parameter, ; k is the current switching cycle; is the half bus bias voltage of the current switching cycle; t For time.

6. The voltage balancing control method of a three-level circuit converter according to claim 1, characterized in that: The voltage balancing control method of the three-level circuit converter further includes: In the commutation process of voltage-equalizing control of the target compensation tube, a commutation digital logic is set; the commutation digital logic includes clearing the integral parameter for eliminating static error when the positive or negative polarity of a single quantity of the half-bus bias or the average value of the inductor current changes between the current moment and the previous moment.

7. The voltage balancing control method of a three-level circuit converter according to any one of claims 1 to 6, characterized in that: Obtaining the half bus bias voltage of the current switching cycle of the three-level circuit converter and the average value of the inductor current of the current switching cycle, including: Obtaining a capacitance value of a half busbar of a three-level circuit converter in a current switching cycle and an inductor current in a current switching cycle; Determining an average value of the inductor current in the current switching cycle based on the inductor current in the current switching cycle; A half bus bias voltage of the current switching cycle is determined based on the capacitance value of the current switching cycle and the inductor current of the current switching cycle.

8. A controller, characterized in that: The controller is used to execute the voltage balancing control method of a three-level circuit converter according to any one of claims 1 to 7.

Images