Voltage drop control circuit of operational amplifier and operational amplifier circuit

Abstract

The invention relates to a voltage drop control circuit of an operational amplifier and an operational amplifier circuit, and the voltage drop control circuit comprises a detection module and a voltage division module. The voltage dividing module comprises a bypass switch and a voltage dividing device; the detection module is used for generating a voltage division control signal according to the power supply voltage of the operational amplifier and outputting the signal to the bypass switch; the bypass switch is switched off in response to a first voltage division control signal generated when the power supply voltage is greater than a detection threshold value, so that the connection between the voltage division device and the gain stage of the operational amplifier is conducted; the bypass switch is switched on in response to a second voltage division control signal generated when the power supply voltage is smaller than or equal to the detection threshold value so as to disconnect the voltage division device and the gain stage; the voltage drop control circuit can ensure that the gain of the operational amplifier is not obviously reduced when the power supply voltage is high, so that the operational amplifier can keep stable gain in a wider power supply voltage range, the circuit structure is simple, and the cost and the implementation difficulty are reduced.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a voltage drop control circuit of an operational amplifier and an operational amplifier circuit. Background Art

[0002] An operational amplifier is a basic analog circuit module used to provide analog signal amplification function. It is generally composed of an input stage, a gain stage, and an output stage. The premise for an operational amplifier to achieve high gain is that the output voltage of its gain stage cannot exceed its output swing limit. In practical applications, the power supply voltage of an operational amplifier is usually allowed to be adjusted within a relatively wide range. When the power supply voltage is high, the voltage at the output node of the operational amplifier gain stage is high. At this time, the MOS tube in the gain stage will have a leakage effect, which will cause the gain of the operational amplifier to decrease at high power supply voltage. Summary of the invention

[0003] In view of this, the present application proposes a voltage drop control circuit and an operational amplifier circuit of an operational amplifier, which can ensure that the gain of the operational amplifier does not drop significantly at a high power supply voltage, so that the operational amplifier can maintain a stable gain within a wider power supply voltage range.

[0004] According to one aspect of the present application, a voltage drop control circuit of an operational amplifier is provided, comprising: a detection module and a voltage divider module; the voltage divider module comprises a bypass switch and a voltage divider device; the detection module is used to generate a voltage divider control signal according to the power supply voltage of the operational amplifier and output it to the bypass switch; the bypass switch is used to be turned on or off in response to the voltage divider control signal; wherein the voltage divider control signal comprises: a first voltage divider control signal generated when the power supply voltage is greater than a detection threshold and a second voltage divider control signal generated when the power supply voltage is less than or equal to the detection threshold; the first voltage divider control signal is used to control the bypass switch to be turned off so that the connection between the voltage divider device and the gain stage of the operational amplifier is turned on to achieve voltage reduction for the device in the gain stage; the second voltage divider control signal is used to control the bypass switch to be turned on so as to disconnect the connection between the voltage divider device and the gain stage.

[0005] In a possible implementation, the bypass switch includes a first switch and a second switch; the voltage divider device includes a first device and a second device; the gain stage includes a first NMOS tube, a second NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a first gain-enhanced operational amplifier and a second gain-enhanced operational amplifier; the source of the fourth PMOS tube and the source of the fifth PMOS tube are connected to the power supply voltage; the drain of the fourth PMOS tube, the source of the sixth PMOS tube and the positive input end of the second gain-enhanced operational amplifier are connected; the drain of the fifth PMOS tube, the source of the seventh PMOS tube and the negative input end of the second gain-enhanced operational amplifier are connected; the gate of the sixth PMOS tube is connected to a first bias voltage; the gate of the seventh PMOS tube is connected to the output end of the second gain-enhanced operational amplifier; the gate of the fourth PMOS tube, the gate of the fifth PMOS tube, The drain of the sixth PMOS tube, the first end of the first device and the first end of the first switch are connected; the drain of the seventh PMOS tube, the first end of the second device and the first end of the second switch are connected; the second end of the first device, the second end of the first switch and the drain of the fourth NMOS tube are connected; the second end of the second device, the second end of the second switch and the drain of the fifth NMOS tube are connected; the source of the fourth NMOS tube, the drain of the first NMOS tube and the negative input end of the first gain-enhanced operational amplifier are connected; the source of the fifth NMOS tube, the drain of the second NMOS tube and the positive input end of the first gain-enhanced operational amplifier are connected; the gate of the fourth NMOS tube is connected to the output end of the first gain-enhanced operational amplifier; the gate of the first NMOS tube, the gate of the second NMOS tube and the gate of the fifth NMOS tube are connected to a second bias voltage; the source of the first NMOS tube and the source of the second NMOS tube are grounded.

[0006] In a possible implementation, the first switch includes a sixth NMOS tube and a ninth PMOS tube; the second switch includes a seventh NMOS tube and a tenth PMOS tube; the drain of the sixth NMOS tube is connected to the source of the ninth PMOS tube, forming a first end of the first switch; the source of the sixth NMOS tube is connected to the drain of the ninth PMOS tube, forming a second end of the first switch; the drain of the seventh NMOS tube is connected to the source of the tenth PMOS tube, forming a first end of the second switch; the source of the seventh NMOS tube is connected to the drain of the tenth PMOS tube, forming a second end of the second switch; the gate of the sixth NMOS tube and the gate of the seventh NMOS tube are used to receive the voltage division control signal; the gate of the ninth PMOS tube and the gate of the tenth PMOS tube are used to receive a voltage division control inverse signal; the voltage division control inverse signal is opposite in phase to the voltage division control signal.

[0007] In a possible implementation, the first device includes an eleventh PMOS tube; the second device includes a twelfth PMOS tube; the source of the eleventh PMOS tube is the first end of the first device; the gate and the drain of the eleventh PMOS tube are connected to form the second end of the first device; the source of the twelfth PMOS tube is the first end of the second device; the gate and the drain of the twelfth PMOS tube are connected to form the second end of the second device.

[0008] In a possible implementation, the detection module includes a thirteenth PMOS tube, an eighth NMOS tube, a first inverter and a second inverter; the source of the thirteenth PMOS tube, the first power supply terminal of the first inverter and the first power supply terminal of the second inverter are connected to the power supply voltage; the drain of the thirteenth PMOS tube, the drain of the eighth NMOS tube, the gate of the eighth NMOS tube and the input terminal of the first inverter are connected; the gate of the thirteenth PMOS tube is connected to a third bias voltage; the source of the eighth NMOS tube, the second power supply terminal of the first inverter and the second power supply terminal of the second inverter are grounded; the output terminal of the first inverter is connected to the input terminal of the second inverter; and the output terminal of the second inverter outputs the voltage division control signal.

[0009] In a possible implementation, at least one of the third bias voltage, the width-to-length ratio of the thirteenth PMOS tube, the width-to-length ratio of the eighth NMOS tube, or the relative strength of the pull-up capability and the pull-down capability of the first inverter is set and adjusted according to the detection threshold; the pull-up capability of the first inverter represents the ability of the first inverter to charge the output level to a high level; and the pull-down capability of the first inverter represents the ability of the first inverter to discharge the output level to a low level.

[0010] In a possible implementation, the first switch and the second switch are turned off simultaneously in response to the first voltage division control signal; and the first switch and the second switch are turned on simultaneously in response to the second voltage division control signal.

[0011] According to another aspect of the present application, an operational amplifier circuit is provided, comprising an operational amplifier and a voltage drop control circuit; the voltage drop control circuit comprises a detection module and a voltage divider module; the voltage divider module comprises a bypass switch and a voltage divider device; the detection module is used to generate a voltage divider control signal according to the power supply voltage of the operational amplifier and output it to the bypass switch; the bypass switch is used to be turned on or off in response to the voltage divider control signal; wherein the voltage divider control signal comprises: a first voltage divider control signal generated when the power supply voltage is greater than a detection threshold and a second voltage divider control signal generated when the power supply voltage is less than or equal to the detection threshold; the first voltage divider control signal is used to control the bypass switch to be turned off so that the connection between the voltage divider device and the gain stage of the operational amplifier is turned on to achieve voltage reduction for the device in the gain stage; the second voltage divider control signal is used to control the bypass switch to be turned on so as to disconnect the connection between the voltage divider device and the gain stage.

[0012] The voltage drop control circuit of the operational amplifier of the present application can connect the voltage divider device to the gain stage of the operational amplifier when the power supply voltage is high, and reduce the leakage effect of the MOS tube in the gain stage through the redundant device voltage division, so as to ensure that the gain of the operational amplifier does not drop significantly when the power supply voltage is high; at the same time, when the power supply voltage is low, the connection between the voltage divider device and the gain stage is disconnected (for example, it can be achieved by short-circuiting the voltage divider device) so that it does not occupy the additional gain stage output voltage margin, thereby enabling the operational amplifier to maintain a stable gain in the entire power supply voltage range.

[0013] Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present application and, together with the description, serve to explain the principles of the present application.

[0015] Figure 1 A schematic diagram showing the use of an operational amplifier in a feedback loop.

[0016] Figure 2 A schematic diagram of the circuit structure of a conventional operational amplifier is shown.

[0017] Figure 3Schematic diagram showing the output swing of an operational amplifier's gain stage.

[0018] Figure 4 A schematic diagram showing simulation results of an operational amplifier.

[0019] Figure 5 A schematic structural diagram of a voltage drop control circuit of an operational amplifier according to an embodiment of the present application is shown.

[0020] Figure 6 A circuit structure schematic diagram of an operational amplifier and a voltage drop control circuit according to an embodiment of the present application is shown.

[0021] Figure 7 A schematic diagram of the circuit structure of a detection module and a voltage divider module according to an embodiment of the present application is shown.

[0022] Figure 8 A schematic structural diagram of an operational amplifier circuit according to an embodiment of the present application is shown.

[0023] Fig. 9 A schematic diagram showing simulation results of an operational amplifier circuit according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0024] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0025] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0026] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0027] The operational amplifier is an important basic analog circuit module. The operational amplifier is generally composed of an input stage, a gain stage, and an output stage, and can provide analog signal amplification function; among them, the input stage is used to receive the input signal, the gain stage is used to amplify the input signal, and the output stage is used to output the amplified signal. In order to achieve high linearity between the output signal and the input signal, a high-gain operational amplifier is usually used in a feedback loop as an error amplifier. Figure 1 A schematic diagram showing the use of an operational amplifier in a feedback loop is shown below. Figure 1 As shown, the operational amplifier includes an input stage, a gain stage, and an output stage, which are used to amplify the input signal and output the amplified signal. The feedback network is usually implemented by a passive voltage divider network. By using the feedback network to feed back the output of the operational amplifier to the input end, the output signal can be adjusted to maintain the linear relationship between the output signal VOUT and the input signal VIN, thereby achieving a high linearity signal amplification function.

[0028] Figure 2 FIG. 1 shows a circuit structure diagram of a conventional operational amplifier, in which MNx (x is a number) represents an NMOS tube and MPx represents a PMOS tube. Figure 2 As shown, the differential input pair of tubes MP1 and MP2 constitute the differential input stage of the operational amplifier. The input voltage vin is converted into a differential input current iout after being input by the differential input stage, iout = gm*vin, where gm is the input transconductance. MP4, MP5, MP6, and MP7 can form a PMOS cascode current mirror, and MN1, MN2, MN4, and MN5 can form an NMOS cascode current mirror. The differential input current iout flows through the gain stage formed by the cascode current mirror load and generates an amplified output voltage vout at the gain stage output node, vout = iout*rout, where rout is the equivalent output impedance of the gain stage output node. Usually, in order to increase the equivalent output impedance of the gain stage output node, it is necessary to introduce a gain-enhancing operational amplifier (i.e., Figure 2 A1 and A2 in the circuit form a local negative feedback loop. The output voltage of the gain stage can be further amplified by using a common source amplifier with Miller compensation as the output stage. The gain stage usually provides a large output voltage swing and has a certain gain, so that the output swing of the gain stage does not need to be too large.

[0029] Only when the operational amplifier has high gain can the entire closed-loop system have high linearity and low gain error. The premise for achieving high gain is that the output voltage of the gain stage cannot exceed its output swing limit. Once the output voltage exceeds the output swing limit, the common source and common gate current mirror load will enter the linear region, causing the output impedance to decrease, which in turn causes the gain to decrease. Figure 3 A schematic diagram showing the output swing of a gain stage of an operational amplifier, which can be Figure 2 The operational amplifier shown, such as Figure 3 As shown, if VSS is ground potential, the maximum output swing allowed by the operational amplifier gain stage (i.e. Figure 3The gain stage output voltage margin in the circuit is determined by the drain-source voltage VDSP of the PMOS cascode current mirror, the drain-source voltage VDSN of the NMOS cascode current mirror, and the power supply voltage VDD. The maximum output swing is equal to VDD minus VDSP minus VDSN.

[0030] In many applications, in order to improve system-level application flexibility, the power supply voltage of the operational amplifier is usually allowed to be adjusted within a relatively wide range, for example, it can be adjusted between 2.3 V and 5.5 V. However, the drain-source voltage required by the common-source common-gate current mirror load does not change with the power supply voltage, which means that when the power supply voltage is high, the output voltage swing is larger, and when the power supply voltage is low, the output voltage swing is smaller.

[0031] When the absolute value of the drain-to-bulk voltage (ie, VDB voltage) of a low-voltage CMOS device is high, leakage current from the drain terminal (Drain) to the bulk terminal (Bulk) exists. Figure 2 When the power supply voltage of the operational amplifier shown is high, the voltage of the gain stage output node is high. At this time, the VDB voltage of the NMOS common-gate transistor MN5 in the NMOS common-source common-gate current mirror is large, which will cause leakage of the drain-bulk junction (DB junction). Since the body end of the NMOS tube is usually grounded, the leakage effect is equivalent to a resistor connected in series from the drain end of MN5 (i.e., the gain stage output end) to the ground. The resistor is connected in parallel with the equivalent output resistance of the gain stage output node, reducing the total equivalent output impedance, thereby reducing the gain of the operational amplifier at a high power supply voltage.

[0032] Figure 4 A schematic diagram showing simulation results of an operational amplifier, which may be Figure 2 In the operational amplifier shown, the body terminals of all NMOS tubes in the operational amplifier are connected to the ground potential, and the body terminals of the PMOS tubes are connected to the power supply voltage. The operational amplifier can be connected in a unit gain negative feedback form. Figure 4 The red curve shows how the loop gain of the operational amplifier changes with the power supply voltage, the yellow curve shows how the VDB voltage of MP7 changes with the power supply voltage, the green curve shows how the VDB voltage of MN5 changes with the power supply voltage, the light blue curve shows how the leakage current of the MP7 body changes with the power supply voltage, and the dark blue curve shows how the leakage current of the MN5 body changes with the power supply voltage. Figure 4As shown in the figure, when the power supply voltage exceeds 4.5V, the loop gain of the operational amplifier is significantly reduced, and the loop gain begins to decrease significantly with the increase of the power supply voltage. At the same time, it can be seen that the VDB voltage of MN5 increases with the increase of the power supply voltage, and the leakage current of its body increases with the increase of the power supply voltage. This means that when implementing a high-gain operational amplifier, if the allowable power supply voltage range is very wide, the gain of the operational amplifier will be significantly reduced under the high power supply voltage configuration compared to the low power supply voltage configuration, resulting in the deterioration of the linearity and static gain error of the overall operational amplifier closed-loop system under high power supply voltage. In addition to the performance of gain and linearity, for a single-ended operational amplifier, the voltage of the non-output node of the gain stage (i.e., the drain of MN4) is different from the voltage of the output node of the gain stage, and the leakage is also different. The leakage of the drain of MN4 will affect the output current of the output node of the gain stage, which will cause an offset error.

[0033] To solve the problems of leakage, offset and reduced gain of operational amplifier caused by high VDB voltage, a MOS device with too large drain-source voltage (i.e. VDS voltage) is often used (e.g. Figure 2 The above problem can be solved by connecting the NMOS common-gate transistors MN4 and MN5 in the circuit to a self-well (i.e., short-circuiting the source and body of the MOS transistor) to make the resistance generated by the leakage effect change from being in parallel with the equivalent output resistance of the gain stage output node to being in series. However, this method requires special processing of the MOS device on the layout, placing the MOS device away from the main circuit, and using a guard ring with an independent potential, which will significantly increase the layout area, increase the difficulty of layout implementation and the chip cost.

[0034] In view of this, an embodiment of the present application provides a voltage drop control circuit for an operational amplifier, which can ensure that the gain of the operational amplifier does not drop significantly at a high power supply voltage, so that the operational amplifier can maintain a stable gain within a wider power supply voltage range, and the circuit structure is simple, reducing the difficulty of layout implementation and chip cost.

[0035] Figure 5 FIG. 4 is a schematic diagram showing a structure of a voltage drop control circuit of an operational amplifier according to an embodiment of the present application. Figure 5 As shown, the circuit may include a detection module 501 and a voltage dividing module 502 ; the voltage dividing module 502 includes a bypass switch 5021 and a voltage dividing device 5022 .

[0036] The detection module 501 is used to generate a voltage-dividing control signal according to the power supply voltage of the operational amplifier and output it to the bypass switch 5021; the bypass switch 5021 is used to be turned on or off in response to the voltage-dividing control signal; wherein the voltage-dividing control signal includes: a first voltage-dividing control signal generated when the power supply voltage is greater than a detection threshold and a second voltage-dividing control signal generated when the power supply voltage is less than or equal to the detection threshold; the first voltage-dividing control signal is used to control the bypass switch 5021 to be turned off so that the connection between the voltage-dividing device 5022 and the gain stage of the operational amplifier is turned on, so as to achieve voltage reduction for the device in the gain stage; the second voltage-dividing control signal is used to control the bypass switch 5021 to be turned on so as to disconnect the connection between the voltage-dividing device 5022 and the gain stage.

[0037] Exemplarily, disconnecting the voltage divider device from the gain stage of the operational amplifier may be achieved by short-circuiting the voltage divider device.

[0038] The voltage drop control circuit of the embodiment of the present application can connect the voltage divider device to the gain stage of the operational amplifier when the power supply voltage is high, and reduce the leakage effect of the MOS tube in the gain stage through the redundant device voltage division, so as to ensure that the gain of the operational amplifier does not drop significantly when the power supply voltage is high; at the same time, when the power supply voltage is low, the connection between the voltage divider device and the gain stage is disconnected (for example, it can be achieved by short-circuiting the voltage divider device) so that it does not occupy additional output voltage margin, and ensure that the common source and common gate current mirror load of the gain stage does not enter the linear region when the power supply voltage is low, so that a high gain state can be maintained within the entire power supply voltage range, so that when a closed-loop system is formed using an operational amplifier, the entire closed-loop system can achieve high linearity and low gain error.

[0039] The voltage drop control circuit of the embodiment of the present application can be applied to Figure 2 The operational amplifier shown.

[0040] Figure 6 A schematic diagram of the circuit structure of an operational amplifier and a voltage drop control circuit according to an embodiment of the present application is shown. The operational amplifier is Figure 2 The operational amplifier shown. Figure 6 As shown, the gain stage of the operational amplifier may include a first NMOS tube MN1, a second NMOS tube MN2, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, a first gain-enhanced operational amplifier A1 and a second gain-enhanced operational amplifier A2; in the voltage-dividing module of the voltage-drop control circuit, the bypass switch may include a first switch S1 and a second switch S2; and the voltage-dividing device may include a first device and a second device.

[0041] The source of MP4 and the source of MP5 are connected to the power supply voltage (i.e., VDD); the drain of MP4, the source of MP6 and the positive input terminal of A2 are connected; the drain of MP5, the source of MP7 and the negative input terminal of A2 are connected; the gate of MP6 is connected to the first bias voltage (i.e., vbp_mirror); the gate of MP7 is connected to the output terminal of A2; the gate of MP4, the gate of MP5, the drain of MP6, the first terminal of the first device and the first terminal of S1 are connected; the drain of MP7, the first terminal of the second device and the first terminal of S2 are connected The second end of the first device, the second end of S1 and the drain of MN4 are connected; the second end of the second device, the second end of S2 and the drain of MN5 are connected; the source of MN4, the drain of MN1 and the negative input of A1 are connected; the source of MN5, the drain of MN2 and the positive input of A1 are connected; the gate of MN4 and the output of A1 are connected; the gate of MN1, the gate of MN2 and the gate of MN5 are connected to the second bias voltage (i.e. vbn_mirror); the source of MN1 and the source of MN2 are grounded (i.e. VSS). vbp_mirror and vbn_mirror can be set by those skilled in the art according to actual needs.

[0042] The operational amplifier may further include an input stage and an output stage. The input stage may include a first PMOS tube MP1, a second PMOS tube MP2 and a third PMOS tube MP3, wherein the gate of MP1 is the positive input terminal of the operational amplifier, and the gate of MP2 is the negative input terminal of the operational amplifier; the output stage may include an eighth PMOS tube MP8, a first capacitor C1, a first resistor R1 and a third NMOS tube MN3, wherein the drain of MP8 is the output terminal of the operational amplifier.

[0043] The detection module of the voltage drop control circuit can generate a corresponding voltage division control signal D according to the magnitude relationship between the power supply voltage and the detection threshold, and the voltage division control signal can control S1 and S2 to be turned on or off at the same time. When the power supply voltage is greater than the detection threshold, the first voltage division control signal generated by the detection module can control S1 and S2 to be turned off at the same time, so that the first device is connected between the drain of MP6 and the drain of MN4, and the second device is connected between the drain of MP7 and the drain of MN5; when the power supply voltage is less than or equal to the detection threshold, the second voltage division control signal generated by the detection module can control S1 and S2 to be turned on at the same time, so that the first device and the second device are short-circuited.

[0044] In this way, the voltage drop control circuit of the embodiment of the present application inserts a voltage divider device and a bypass switch at the high impedance node of the gain stage. When the power supply voltage exceeds the detection threshold, the bypass switch is controlled to be disconnected to connect the voltage divider device to the circuit, and a part of the power supply voltage is shared across the voltage divider device. This can reduce the VDB voltage of the common-gate tube (i.e., MN4 and MN5) at the high impedance node of the gain stage and reduce the leakage effect of the common-gate tube. When the power supply voltage does not exceed the detection threshold, the bypass switch is controlled to be turned on, the voltage divider device is short-circuited, and the voltage margin of the output node of the gain stage is not occupied, thereby avoiding the common-source and common-gate current mirror load from entering the linear region and causing the output impedance to decrease, thereby maintaining a higher output impedance throughout the entire power supply voltage range, so that the operational amplifier can maintain a stable gain over a wider power supply voltage range.

[0045] Exemplarily, the bypass switch may be implemented by a transmission gate, an NMOS switch, a PMOS switch, or a gate voltage bootstrap switch.

[0046] Exemplarily, the voltage divider device can be implemented by a passive device such as a resistor, a diode, or an active device such as a MOS tube.

[0047] It should be noted that those skilled in the art can select the implementation method of the bypass switch and the voltage divider device according to actual needs, and this application does not limit this, as long as the needs are met.

[0048] In the following, the first switch and the second switch are implemented by a transmission gate, and the first device and the second device are implemented by a MOS tube. Figure 6 The detection module and voltage divider module shown are introduced.

[0049] Figure 7 FIG. 1 shows a schematic diagram of the circuit structure of a detection module and a voltage divider module according to an embodiment of the present application. Figure 7 As shown, the detection module may include a thirteenth PMOS transistor MP13, an eighth NMOS transistor MN8, a first inverter P1 and a second inverter P2. The source of MP13, the first power supply terminal of P1 and the first power supply terminal of P2 are connected to the power supply voltage (i.e., VDD); the drain of MP13, the drain of MN8, the gate of MN8 and the input terminal of P1 are connected; the gate of MP13 is connected to the third bias voltage (i.e., vbp_3); the source of MN8, the second power supply terminal of P1 and the second power supply terminal of P2 are grounded (i.e., VSS); the output terminal of P1 is connected to the input terminal of P2; the output terminal of P1 outputs a voltage division control inverse signal DN; the output terminal of P2 outputs a voltage division control signal D; the phases of D and DN are opposite.

[0050] MN8 can be regarded as a gate-drain short-circuit device biased by current. When a constant voltage vbp_3 is applied to the gate of MP13, the drain of MP13 can generate a constant bias current, which can make MN8 generate a constant gate voltage input to P1. The output level of the inverter is related to its input voltage, power supply voltage, and the relative strength of the pull-up and pull-down capabilities of the inverter (i.e., the relative pull-up / pull-down capabilities). The pull-up capability of the inverter indicates the ability of the inverter to charge the output level to a high level; the pull-down capability of the inverter indicates the ability of the inverter to discharge the output level to a low level.

[0051] In one possible implementation, at least one of the value of vbp_3, the aspect ratio of MP13, the aspect ratio of MN8, or the relative pull-up / pull-down capability of P1 is set and adjusted according to a detection threshold, and the detection threshold can be set by a person skilled in the art according to actual needs.

[0052] Exemplarily, the detection threshold is recorded as VDDTH. The bias current generated by MP13 can be adjusted by adjusting the value of vbp_3 and / or the width-to-length ratio of MP13, thereby adjusting the gate voltage generated by MN8 (i.e., the input voltage of P1) and thus adjusting VDDTH; the gate voltage generated by MN8 can be adjusted by adjusting the width-to-length ratio of MN8 to adjust VDDTH; VDDTH can also be adjusted by adjusting the relative pull-up / pull-down capability of P1, and the method for adjusting the relative pull-up / pull-down capability can refer to the relevant technology; so that when VDD>VDDTH, P1 outputs a high level and P2 outputs a low level, i.e., DN=1, D=0; when VDD≤VDDTH, P1 outputs a low level and P2 outputs a high level, i.e., DN=0, D=1.

[0053] Exemplarily, the charging and discharging currents of P1 and P2 may be limited, thereby reducing the rate of change of the voltage division control signal and making the circuit switching region smoother and more continuous.

[0054] The first switch in the voltage divider module may include a sixth NMOS transistor MN6 and a ninth PMOS transistor MP9; the second switch may include a seventh NMOS transistor MN7 and a tenth PMOS transistor MP10; the first device may include an eleventh PMOS transistor MP11; the second device may include a twelfth PMOS transistor MP12. The source of MP11 is the first end of the first device; the gate and drain of MP11 are connected to form the second end of the first device; the source of MP12 is the first end of the second device; the gate and drain of MP12 are connected to form the second end of the second device; the drain of MN6 is connected to the source of MP9 to form the first end of the first switch; the source of MN6 is connected to the drain of MP9 to form the second end of the first switch; the drain of MN7 is connected to the source of MP10 to form the first end of the second switch; the source of MN7 is connected to the drain of MP10 to form the second end of the second switch; the gate of MN6 and the gate of MN7 are used to receive the voltage divider control signal D; the gate of MP9 and the gate of MP10 are used to receive the voltage divider control inverse signal DN.

[0055] The voltage divider is implemented by PMOS tubes MP11 and MP12 with shorted gates and drains, the first switch is implemented by a transmission gate composed of MN6 and MP9, and the second switch is implemented by a transmission gate composed of MN7 and MP10. When VDD>VDDTH, DN=1, D=0, at which time MN6, MP9, MN7 and MP10 are all disconnected (equivalent to the first switch and the second switch being disconnected at the same time), MP11 is connected between the drain of MP6 and the drain of MN4, MP12 is connected between the drain of MP7 and the drain of MN5, a voltage drop VDS1 can be generated across the drain-source of MP11, and a voltage drop VDS2 can be generated across the drain-source of MP12, thereby reducing the VDB voltage of the common-gate tubes MN4 and MN5. When VDD≤VDDTH, DN=0, D=1, at this time MN6, MP9, MN7 and MP10 are all turned on (equivalent to the first switch and the second switch being turned on at the same time), MP11 and MP12 are short-circuited, VDS1 and VDS2 are approximately 0, so that no additional output voltage margin is occupied.

[0056] In this way, the detection module of the voltage drop control circuit of the embodiment of the present application can detect the power supply voltage of the operational amplifier in real time, determine whether the power supply voltage exceeds the detection threshold, and generate a corresponding voltage division control signal according to the magnitude relationship between the power supply voltage and the detection threshold; the voltage division module can respond to the voltage division control signal, and when the power supply voltage exceeds the detection threshold, control the bypass switch to be disconnected so that the voltage division device is connected to the gain stage, reduce the VDB voltage of the common-gate tube in the gain stage, thereby reducing its leakage effect, and ensure that the gain of the operational amplifier will not drop significantly at high power supply voltage; when the power supply voltage does not exceed the detection threshold, the voltage division module can control the bypass switch to be turned on to short-circuit the voltage division device, so that the voltage division device does not occupy additional output voltage margin, thereby achieving stable gain in the entire power supply voltage range. In addition, the circuit structure of the voltage drop control circuit of the embodiment of the present application is simple, and the area is greatly reduced compared with the traditional common-gate device self-well method, thereby reducing the chip cost and layout implementation difficulty.

[0057] The embodiment of the present application also provides an operational amplifier circuit.

[0058] Figure 8 FIG. 1 is a schematic diagram showing a structure of an operational amplifier circuit according to an embodiment of the present application. Figure 8 As shown, the circuit may include an operational amplifier 801 and a voltage drop control circuit 802; the voltage drop control circuit 802 includes a detection module 8021 and a voltage divider module 8022; the voltage divider module 8022 includes a bypass switch and a voltage divider device. The detection module 8021 is used to generate a voltage divider control signal according to the power supply voltage of the operational amplifier 801 and output it to the bypass switch; the bypass switch is used to turn on or off in response to the voltage divider control signal; wherein the voltage divider control signal includes: a first voltage divider control signal generated when the power supply voltage is greater than a detection threshold and a second voltage divider control signal generated when the power supply voltage is less than or equal to the detection threshold; the first voltage divider control signal is used to control the bypass switch to be turned off so that the connection between the voltage divider device and the gain stage of the operational amplifier is turned on to achieve voltage reduction for the device in the gain stage; the second voltage divider control signal is used to control the bypass switch to be turned on so as to disconnect the connection between the voltage divider device and the gain stage.

[0059] For example, the operational amplifier 801 may be as described above. Figure 2 The operational amplifier shown in the figure can be used with the detection module 8021 described above. Figure 7 The detection module shown in FIG. 8 is the same as that shown in FIG. 8 , and the voltage divider module 8022 can be used as the above Figure 6 or Figure 7 The connection method of the operational amplifier 801 and the voltage drop control circuit 802 can refer to the above Figure 6 or Figure 7 .

[0060] The operational amplifier circuit of the embodiment of the present application realizes the power supply voltage detection function of the operational amplifier through the detection module in the voltage drop control circuit, and generates a corresponding voltage divider control signal according to the relationship between the power supply voltage and the detection threshold; the voltage divider module in the voltage drop control circuit can respond to the voltage divider control signal, and control the voltage divider device to connect to the gain stage of the operational amplifier when the power supply voltage is high, and reduce the leakage effect through the redundant device voltage divider to ensure that the gain of the operational amplifier does not decrease significantly at high power supply voltage; when the power supply voltage is low, the voltage divider module can control the connection between the voltage divider device and the gain stage to be disconnected (for example, it can be achieved by short-circuiting the voltage divider device) so that it does not occupy additional output voltage margin, thereby enabling the operational amplifier to maintain a stable gain within the entire power supply voltage range, so that when the operational amplifier is used to form a closed-loop system, the linearity, gain error and other performance of the entire closed-loop system will not deteriorate with changes in the power supply voltage.

[0061] Fig. 9 A schematic diagram showing simulation results of an operational amplifier circuit according to an embodiment of the present application is shown. The operational amplifier circuit may be as described above. Figure 6 or Figure 7 In the circuit shown, the operational amplifier in the operational amplifier circuit can be connected in a unit gain negative feedback form. Fig. 9 The red curve shows how the loop gain of the operational amplifier changes with the power supply voltage, the yellow curve shows how the VDB voltage of MP7 changes with the power supply voltage, the green curve shows how the VDB voltage of MN5 changes with the power supply voltage, the light blue curve shows how the leakage current of the MP7 body changes with the power supply voltage, and the dark blue curve shows how the leakage current of the MN5 body changes with the power supply voltage. Fig. 9 As shown in the figure, after adding the voltage drop control circuit to the operational amplifier, the loop gain of the operational amplifier can be kept stable in the entire power supply voltage range. The detection threshold VDDTH is set at around 3.7V. The VDB voltage of MN5 first increases with the increase of the power supply voltage. When the power supply voltage exceeds VDDTH, the voltage divider module of the voltage drop control circuit controls the voltage divider device to access the circuit. The VDB voltage of MN5 is shared by the voltage divider device and then decreases. Then it increases with the increase of the power supply voltage. Compared with Figure 4The simulation results of the operational amplifier without using the voltage drop control circuit are shown. It can be seen that within the entire power supply voltage range, the VDB voltage of MN5 is limited to a smaller range, and the leakage current of the MN5 body terminal is also limited to a smaller range. When the voltage drop control circuit is not used, the leakage current of the MN5 body terminal can reach -10nA. After using the voltage drop control circuit, the leakage current of the MN5 body terminal is limited to -3.4pA. The embodiment of the present application can alleviate the problems of leakage, offset and operational amplifier gain reduction caused by high VDB voltage by applying a voltage drop control circuit that can be dynamically adjusted with the power supply voltage to the operational amplifier, so that the operational amplifier can maintain a stable gain within a wider power supply voltage range, so that the linearity, gain error and other performance of the closed-loop system composed of the operational amplifier do not deteriorate with the change of the power supply voltage, and the output offset does not change with the change of the power supply voltage.

[0062] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A voltage drop control circuit for an operational amplifier, characterized in that: include: A detection module and a voltage dividing module; the voltage dividing module includes a bypass switch and a voltage dividing device; The detection module is used to generate a voltage division control signal according to the power supply voltage of the operational amplifier and output the signal to the bypass switch; The bypass switch is used to be turned on or off in response to the voltage division control signal; Wherein, the voltage division control signal includes: a first voltage division control signal generated when the power supply voltage is greater than a detection threshold and a second voltage division control signal generated when the power supply voltage is less than or equal to the detection threshold; The first voltage-dividing control signal is used to control the bypass switch to be disconnected so as to connect the voltage-dividing device to the gain stage of the operational amplifier, so as to achieve voltage reduction for the device in the gain stage; The second voltage-dividing control signal is used to control the bypass switch to be turned on so as to disconnect the voltage-dividing device from the gain stage.

2. The circuit according to claim 1, characterized in that The bypass switch includes a first switch and a second switch; the voltage divider device includes a first device and a second device; the gain stage includes a first NMOS transistor, a second NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a first gain-enhanced operational amplifier and a second gain-enhanced operational amplifier; The source of the fourth PMOS tube and the source of the fifth PMOS tube are connected to the power supply voltage; the drain of the fourth PMOS tube, the source of the sixth PMOS tube and the positive input terminal of the second gain-enhanced operational amplifier are connected; the drain of the fifth PMOS tube, the source of the seventh PMOS tube and the negative input terminal of the second gain-enhanced operational amplifier are connected; the gate of the sixth PMOS tube is connected to the first bias voltage; the gate of the seventh PMOS tube is connected to the output terminal of the second gain-enhanced operational amplifier; the gate of the fourth PMOS tube, the gate of the fifth PMOS tube, the drain of the sixth PMOS tube, the first end of the first device and the first end of the first switch are connected; the drain of the seventh PMOS tube, the first end of the second device and the first end of the second switch are connected. The first device and the second switch are connected to the drain of the fourth NMOS tube; the second device and the second switch are connected to the drain of the fifth NMOS tube; the source of the fourth NMOS tube, the drain of the first NMOS tube and the negative input of the first gain-enhanced operational amplifier are connected; the source of the fifth NMOS tube, the drain of the second NMOS tube and the positive input of the first gain-enhanced operational amplifier are connected; the gate of the fourth NMOS tube is connected to the output of the first gain-enhanced operational amplifier; the gate of the first NMOS tube, the gate of the second NMOS tube and the gate of the fifth NMOS tube are connected to a second bias voltage; the source of the first NMOS tube and the source of the second NMOS tube are grounded.

3. The circuit according to claim 2, characterized in that The first switch includes a sixth NMOS tube and a ninth PMOS tube; the second switch includes a seventh NMOS tube and a tenth PMOS tube; The drain of the sixth NMOS tube is connected to the source of the ninth PMOS tube, forming a first end of the first switch; the source of the sixth NMOS tube is connected to the drain of the ninth PMOS tube, forming a second end of the first switch; the drain of the seventh NMOS tube is connected to the source of the tenth PMOS tube, forming a first end of the second switch; the source of the seventh NMOS tube is connected to the drain of the tenth PMOS tube, forming a second end of the second switch; the gate of the sixth NMOS tube and the gate of the seventh NMOS tube are used to receive the voltage division control signal; the gate of the ninth PMOS tube and the gate of the tenth PMOS tube are used to receive a voltage division control inverse signal; the voltage division control inverse signal is opposite in phase to the voltage division control signal.

4. The circuit according to claim 2 or 3, characterized in that The first device includes an eleventh PMOS tube; the second device includes a twelfth PMOS tube; the source of the eleventh PMOS tube is the first end of the first device; the gate and the drain of the eleventh PMOS tube are connected to form the second end of the first device; the source of the twelfth PMOS tube is the first end of the second device; the gate and the drain of the twelfth PMOS tube are connected to form the second end of the second device.

5. The circuit according to claim 1, characterized in that The detection module includes a thirteenth PMOS tube, an eighth NMOS tube, a first inverter and a second inverter; The source of the thirteenth PMOS tube, the first power supply terminal of the first inverter and the first power supply terminal of the second inverter are connected to the power supply voltage; the drain of the thirteenth PMOS tube, the drain of the eighth NMOS tube, the gate of the eighth NMOS tube and the input terminal of the first inverter are connected; the gate of the thirteenth PMOS tube is connected to a third bias voltage; the source of the eighth NMOS tube, the second power supply terminal of the first inverter and the second power supply terminal of the second inverter are grounded; the output terminal of the first inverter is connected to the input terminal of the second inverter; and the output terminal of the second inverter outputs the voltage division control signal.

6. The circuit according to claim 5, characterized in that At least one of the third bias voltage, the width-to-length ratio of the thirteenth PMOS tube, the width-to-length ratio of the eighth NMOS tube, or the relative strength of the pull-up capability and the pull-down capability of the first inverter is set and adjusted according to the detection threshold; the pull-up capability of the first inverter represents the ability of the first inverter to charge the output level to a high level; and the pull-down capability of the first inverter represents the ability of the first inverter to discharge the output level to a low level.

7. The circuit according to claim 2, characterized in that The first switch and the second switch are turned off simultaneously in response to the first voltage division control signal; the first switch and the second switch are turned on simultaneously in response to the second voltage division control signal.

8. An operational amplifier circuit, characterized in that: It includes an operational amplifier and a voltage drop control circuit; the voltage drop control circuit includes a detection module and a voltage divider module; the voltage divider module includes a bypass switch and a voltage divider device; The detection module is used to generate a voltage division control signal according to the power supply voltage of the operational amplifier and output the signal to the bypass switch; The bypass switch is used to be turned on or off in response to the voltage division control signal; Wherein, the voltage division control signal includes: a first voltage division control signal generated when the power supply voltage is greater than a detection threshold and a second voltage division control signal generated when the power supply voltage is less than or equal to the detection threshold; The first voltage-dividing control signal is used to control the bypass switch to be disconnected so as to connect the voltage-dividing device to the gain stage of the operational amplifier, so as to achieve voltage reduction for the device in the gain stage; The second voltage-dividing control signal is used to control the bypass switch to be turned on so as to disconnect the voltage-dividing device from the gain stage.

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