Asynchronous pulse signal generation circuit

Abstract

The invention provides an asynchronous pulse signal generation circuit. The asynchronous pulse signal generation circuit comprises a first latch input control module, a pulse delay module, a second latch input control module and a latch module, the first latch input control module outputs a first control signal of a level hopping signal and a level non-hopping signal when detecting that the edge of an input signal occurs, and the pulse delay module generates an output signal and a delay control signal according to the first control signal. The second latch input control module generates a second control signal according to the output signal and the delay control signal, and the latch module outputs a feedback signal according to the first control signal and the second control signal to indicate the first latch input control module to jump the level state of the level jump signal back to the original level state. Therefore, the pulse delay module outputs the pulse signal with the preset pulse width, and a good solution is provided for operation control of the storage unit.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to an asynchronous pulse signal generating circuit. Background Art

[0002] Integrated circuits can be classified into synchronous circuits and asynchronous circuits according to their working modes. The data transmission and processing of asynchronous circuits do not rely on clock signals, but are based on signal changes. Each time a signal jumps, it indicates that an operation needs to be performed, such as writing data to a memory. Therefore, a pulse signal can be generated when the signal jumps to identify the moment when the operation needs to be performed. However, due to the lack of unified control of the clock signal, asynchronous signals may jump at different times, and the width of the generated pulse signal needs to be long enough to ensure that the data can be operated (for example, completely written to the memory). Therefore, how to stably generate a pulse signal that meets the pulse width requirements has always been a difficulty in the design of asynchronous circuits. Summary of the invention

[0003] The main purpose of the present application is to provide an asynchronous pulse signal generating circuit to ensure that a pulse signal that meets the pulse width requirement can be stably generated.

[0004] To achieve the above-mentioned purpose, the present application provides an asynchronous pulse signal generating circuit, comprising: a first latch input control module, which is electrically connected to an external data signal generator and a read-write control signal generator, respectively, and is used to output a first control signal when an edge event of an asynchronous input signal is detected; wherein the first control signal includes a signal with a level jump and a signal with a level that does not jump; a pulse delay module, which is electrically connected to the first latch input control module and an external storage unit, respectively, and is used to generate a corresponding output signal and a delay control signal according to the level states of the two signals in the first control signal; wherein the output signal The level state of the output signal is consistent with the level state of the first control signal; a second latch input control module is electrically connected to the pulse delay module, and is used to generate a corresponding second control signal according to the level state of the output signal and the delayed control signal; a latch module is electrically connected to the first latch input control module and the second latch input control module, respectively, and is used to output a corresponding feedback signal according to the level states of the two signals in the first control signal and the second control signal; wherein the feedback signal is used to instruct the first latch input control module to restore the level state of the level jump signal to the original level state.

[0005] From the above description, it can be seen that the present application detects the edge of the asynchronous input signal through the first latch input control module. When the edge of the asynchronous input signal is detected, the first control signal is output. The first control signal includes a signal whose level jumps, such as a signal that jumps from a high level to a low level, and a signal whose level does not jump, such as a signal that remains at a high level. Both first control signals are transmitted to the pulse delay module and the latch module. The second latch input control module generates a second control signal according to the output signal and the delay control signal generated by the pulse delay module. Then the latch module generates a feedback signal according to the first control signal and the second control signal to make the low level signal in the first control signal jump to a high level, thereby generating a low pulse signal at the output end of the pulse delay module. Since the moment when the low pulse signal jumps from a low level signal to a high level can be controlled by the delay control circuit, the second latch input control module and the latch module, the pulse width of the low pulse signal can be ensured to be stable at a fixed value, thereby ensuring the stability of the operation of the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0007] Figure 1 is a structural schematic diagram of a first asynchronous pulse signal generating circuit according to an embodiment of the present application; Figure 2 is a circuit schematic diagram of a first latch input control module of an embodiment of the present application; Figure 3 It is a structural diagram of a three-input NAND gate according to an embodiment of the present application; Figure 4 is a schematic structural diagram of an inverter according to an embodiment of the present application; Figure 5 is a circuit schematic diagram of a pulse delay module according to an embodiment of the present application; Figure 6 is a schematic structural diagram of a buffer according to an embodiment of the present application; Figure 7 is a circuit schematic diagram of a second latch input control module of an embodiment of the present application; Figure 8 is a circuit schematic diagram of a latch module according to an embodiment of the present application; Fig. 9 This is a schematic diagram of the structure of a two-input NAND gate according to an embodiment of the present application; Fig.10 It is a structural schematic diagram of a two-input NOR gate according to an embodiment of the present application; Fig.11 is a structural schematic diagram of a second asynchronous pulse signal generating circuit according to an embodiment of the present application; Fig.12 is a circuit schematic diagram of an asynchronous pulse signal generating circuit according to an embodiment of the present application; Fig.13 is a waveform diagram of relevant signals in the first asynchronous pulse signal generating circuit of an embodiment of the present application; Fig.14 It is a waveform diagram of relevant signals in the second asynchronous pulse signal generating circuit of the embodiment of the present application. DETAILED DESCRIPTION

[0008] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0009] In the design of asynchronous circuits such as asynchronous SRAM, it is difficult to generate stable pulse signals to control data operations because the asynchronous signals have no unified clock signal control. For this reason, an embodiment of the present application provides an asynchronous pulse signal generating circuit.

[0010] like Figure 1The figure is a schematic diagram of the structure of the first asynchronous pulse signal generating circuit provided by an embodiment of the present application, and the asynchronous pulse signal generating circuit comprises: a first latch input control module 100, which is electrically connected to an external data signal generator 200 and a read / write control signal generator 300, respectively, and is used to output a first control signal when an edge event of the asynchronous input signal is detected; wherein the first control signal comprises a signal with a level jump and a signal with a level not jump; a pulse delay module 400, which is electrically connected to the first latch input control module 100 and an external storage unit 500, respectively, and is used to generate two corresponding output signals and two delayed control signals according to the level states of the two signals in the first control signal; wherein the two output signals are The level state of the output signal is the same as the level state of the two first control signals, and the level state of the two delayed control signals is opposite to the level state of the corresponding first control signal; the second latch input control module 600 is electrically connected to the pulse delay module 400, and is used to generate a corresponding second control signal according to the level state of the output signal and the delayed control signal; the latch module 700 is electrically connected to the first latch input control module 100 and the second latch input control module 600, respectively, and is used to output a corresponding feedback signal according to the level state of the two signals in the first control signal and the second control signal; wherein the feedback signal is used to instruct the first latch input control module 100 to restore the level state of the signal with a level jump to the original level state.

[0011] Specifically, in the present embodiment, the first latch input control module 100 is used to detect the edge (i.e., rising edge, falling edge) of the asynchronous input signal (i.e., data signal and read / write operation control signal). When the edge of the asynchronous input signal is detected, the first control signal is output. The first control signal includes a signal whose level jumps, such as a signal that jumps from a high level to a low level, and a signal whose level does not jump, such as a signal that remains at a high level. Both first control signals are transmitted to the pulse delay module 400 and the latch module 700. The second latch input control module 600 generates a second control signal according to the output signal generated by the pulse delay module 400 and the delay control signal. signal, and then the latch module 700 generates a feedback signal according to the first control signal and the second control signal to make the low-level signal in the first control signal jump to a high level. Since the output signal of the pulse delay module 400 is consistent with the first control signal, a low pulse signal can be generated at the output end of the pulse delay module 400. Since the moment when the low pulse signal jumps from a low-level signal to a high level can be controlled by the delay control circuit, the second latch input control module 600 and the latch module 700, it can ensure that the pulse width of the low pulse signal is stable at a fixed value. Transmitting the low pulse signal to the storage unit 500 can effectively ensure the stability of the operation of the storage unit 500.

[0012] like Figure 2 FIG. 1 is a circuit diagram of a first latch input control module provided in this embodiment, see Figure 1 to Figure 2 The first latch input control module 100 includes a first inverter I1, a second inverter I2, a first NAND gate I3 and a second NAND gate I4; the input end of the first inverter I1 is used to be electrically connected to the data signal generator 200, and the output end of the first inverter I1 is electrically connected to the input end of the second inverter I2 and the first input end of the second NAND gate I4 respectively; the first input end of the first NAND gate I3 is electrically connected to the output end of the second inverter I2, and the second input end of the first NAND gate I3 is electrically connected to the output end of the second inverter I2. The first NAND gate I3 is electrically connected to the latch module 700, the third input terminal of the first NAND gate I3 is electrically connected to the second input terminal of the second NAND gate I4 and is used to be electrically connected to the read-write control signal generator 300, and the output terminal of the first NAND gate I3 is electrically connected to the latch module 700 and the pulse delay module 400 respectively; the third input terminal of the second NAND gate I4 is electrically connected to the latch module 700, and the output terminal of the second NAND gate I4 is electrically connected to the latch module 700 and the pulse delay module 400 respectively.

[0013] Specifically, the first NAND gate I3 and the second NAND gate I4 are both three-input NAND gates, and their circuit structures are as follows: Figure 3 As shown, the three-input NAND gate circuit includes three PMOS tubes PM30, PM31, PM32 and three NMOS tubes NM31, NM30, NM32, the inputs of the three-input NAND gate are A, B, C, and the output of the NAND gate is Y. In the three-input NAND gate circuit, the PMOS tube PM30, the PMOS tube PM31, and the PMOS tube PM32 are connected in parallel, and the NMOS tube NM30, the NMOS tube NM31, and the NMOS tube NM32 are connected in series. The gates of the PMOS tube PM30 and the NMOS tube NM30 are connected to A, the gates of the PMOS tube PM31 and the NMOS tube NM31 are connected to B, the gates of the PMOS tube PM32 and the NMOS tube NM32 are connected to C, the source of the NMOS tube NM32 is grounded, the drain of the NMOS tube NM32 and the source of the NMOS tube NM31 are connected to net1, the drain of the NMOS tube NM31 and the source of the NMOS tube NM30 are connected to net0, the drain of the NMOS tube NM30, the drain of the PMOS tube PM30, the drain of the PMOS tube PM31 and the drain of the PMOS tube PM32 are connected through the signal line Y, the substrates of the PMOS tubes PM32, PM31 and PM30 are connected to VDD, and the substrates of the NMOS tubes NM30, NM31 and NM32 are connected to VSS.

[0014] The circuit structures of the inverters in this embodiment are the same. Figure 4As shown, the inverter includes a PMOS tube PM40 and an NMOS tube NM40, the input of the inverter is A, the output of the inverter is Y, the gates of the PMOS tube PM40 and the NMOS tube NM40 are connected to A, the source of the PMOS tube PM40 is connected to the power supply VDD, the drain of the PMOS tube PM40 and the drain of the NMOS tube NM40 are connected through the signal line Y, the substrate of the PMOS tube PM40 is connected to VDD, and the source and substrate of the NMOS tube NM40 are connected to VSS.

[0015] In this embodiment, the data signal is transmitted to the input end of the first inverter I1 through the signal line DATA, the read-write control signal is transmitted to the input ends of the first NAND gate I3 and the second NAND gate I4 through the signal line C, the output port of the first inverter I1 is connected to the input end of the second inverter I2 and the input end of the second NAND gate I4 through the signal line N12, and at the same time, the output end of the second inverter I2 is connected to the input end of the first NAND gate I3 through the signal line N11, and N12 and N11 are two mutually inverted signal lines. One of the input ends of the two NAND gates is also connected to the latch module 700 through signal lines N1 and N2, and is used to receive the feedback signal transmitted by the latch module 700. The output ends of the two three-input NAND gates are connected to the input ends of the latch module 700 and the pulse delay module 400 through signal lines N3 and N4 to transmit control signals, namely signals N3 and N4, to the latch module 700 and the pulse delay module 400. The control signals N3 and N4 can be used to control the data latching state of the latch module 700. At the same time, the control signals N3 and N4 will jump as the feedback signals N1 and N2 generated by the latch module 700 change, thereby generating a low pulse signal.

[0016] like Figure 5 The circuit diagram of a pulse delay module provided in this embodiment is shown in FIG. Figure 5The pulse delay module includes a first delay circuit and a second delay circuit, and the first delay circuit and the second delay circuit both include a third inverter I19 / I22, a fourth inverter 120 / I23, a fifth inverter I21 / I24, a first buffer I25 / I26, a first PMOS transistor PM8 / PM4 and a second PMOS transistor PM9 / PM5; taking the first delay circuit as an example, the input end of the third inverter I19 is electrically connected to the output end of the first latch input control module 100, and the output end of the third inverter I19 is electrically connected to the input end of the fourth inverter I20; the input end of the fifth inverter I21 is electrically connected to the output end of the first latch input control module 100; The output end of the fourth inverter I20 is electrically connected, and the output end of the fifth inverter I21 is electrically connected to the input end of the second latch input control module 600; the input end of the first buffer I25 is electrically connected to the output end of the first latch input control module 100, and the output end of the first buffer I25 is electrically connected to the input end of the second latch input control module 600; the gates of the first PMOS tube PM8 and the second PMOS tube PM9 are both electrically connected to the output end of the third inverter I19, and the source, drain, and substrate of the first PMOS tube PM8 and the second PMOS tube PM9 are all electrically connected to the power supply VDD.

[0017] For further information, see Figure 5 , the first delay circuit and the second delay circuit both further include a third PMOS tube PM10 / PM6, a fourth PMOS tube PM11 / PM7 and a first NMOS tube NM9 / NM8; taking the first delay circuit as an example, the gate, source, drain and substrate of the third PMOS tube PM10 are all electrically connected to the power supply VDD, the gate of the fourth PMOS tube PM11 is electrically connected to the output end of the fourth inverter I20, the source, drain and substrate of the fourth PMOS tube PM11 are all electrically connected to the power supply VDD, the gate of the first NMOS tube NM9 is electrically connected to the output end of the first latch input control module 100, the drain of the first NMOS tube NM9 is electrically connected to the output end of the fifth inverter I21, and the source and substrate of the first NMOS tube NM9 are both grounded.

[0018] Specifically, the structures of the buffers in this embodiment are the same, and their circuit structures are as follows: Figure 6 As shown, the buffer includes 2 PMOS tubes and 2 NMOS tubes, the input of the buffer is A, and the output of the inverter is Y. The gates of the PMOS tube PM60 and the NMOS tube NM60 are connected to A, the drain of the PMOS tube PM60 and the drain of the NMOS tube NM60 are connected to the gate of the PMOS tube PM1, the NMOS tube NM61 is connected through the signal line net0, the drain of the PMOS tube PM61 and the drain of the NMOS tube NM61 are connected through the signal line Y, and the source substrate of the PMOS tubes PM60 and PM61 is connected to VDD. The source and substrate of the NMOS tubes NM60 and NM61 are connected to VSS.

[0019] In this embodiment, the pulse delay module 400 includes two delay paths, namely, an upper delay path corresponding to the first delay circuit and a lower delay path corresponding to the second delay circuit. The structures and devices of the two delay paths are the same. Taking the first delay circuit as an example, the PMOS tubes PM8 and PM9 in the first delay circuit are used to provide MOS capacitors for the output signal line N15 of the third inverter I19 to increase the delay time of signal transmission. The PMOS tube PM10 is used as an optional MOS capacitor to adjust the delay time. That is, when the PMOS tube PM10 is connected to the circuit, the total capacitance of the circuit will be changed, thereby realizing the adjustment of the delay time. Section; in addition, a PMOS tube PM11 can be added to the output signal line N17 of the fourth inverter I20 to provide a MOS capacitor for the signal line N17 and increase the delay time of signal transmission; the NMOS tube NM9 is respectively connected to the output end of the NAND gate I3 of the first latch input control module 100 and the output end of the inverter I21. When the output signal N4 of the NAND gate I3 is at a high level, the NMOS tube NM9 is turned on and the output signal N6 of the inverter I21 is quickly pulled down to a low level, wherein the output signal N6 of the inverter I21 is used to provide a gate control signal for the second latch input control module 600. The pulse delay module 400 in this embodiment is used to provide four control signals with different delay times for the second latch input control module 600, which are divided into an output signal DWY with a smaller delay and an output signal N5 with a larger delay obtained after processing the signal N3, and an output signal DWYN with a smaller delay and an output signal N6 with a larger delay obtained after processing the signal N4, wherein the signals N5 and N6 provide gate control signals for the second latch input control module 600, the signals DWYN and DWY provide input control signals for the second latch input control module 600, and are output signals of an asynchronous pulse signal generating circuit, which are used to control an asynchronous circuit such as a storage unit 500 of an asynchronous SRAM, and when the pulse signal is a write pulse signal, it is used to control the write operation of the storage unit 500.

[0020] like Figure 7 FIG. 1 is a circuit diagram of a second latch input control module provided in this embodiment. Figure 7The second latch input control module 600 includes a second NMOS tube NM0, a third NMOS tube NM1, a first NMOS tube module, a second NMOS tube module, a fifth PMOS tube PM0 and a sixth PMOS tube PM1; the gate and source of the second NMOS tube NM0 and the third NMOS tube NM1 are electrically connected to the output end of the pulse delay module 400, the drain of the second NMOS tube NM0 is electrically connected to the drain of the fifth PMOS tube PM0 and the latch module 700, the drain of the third NMOS tube NM1 is electrically connected to the drain of the sixth PMOS tube PM1, and the substrates of the second NMOS tube NM0 and the third NMOS tube NM1 are grounded; the fifth PMOS tube PM0 and the sixth PMOS tube PM1 are electrically connected to the output end of the pulse delay module 400, and the drain of the second NMOS tube NM0 is electrically connected to the drain of the fifth PMOS tube PM0 and the latch module 700, respectively. The gates of the PMOS tube PM1 are used to be electrically connected to an external low-level signal generator, and the sources and substrates of the fifth PMOS tube PM0 and the sixth PMOS tube PM1 are electrically connected to the power supply VDD; the first end of the first NMOS tube module is electrically connected to the drain of the second NMOS tube NM0, the second end of the first NMOS tube module is electrically connected to the first end of the second NMOS tube module, the second end of the second NMOS tube module is electrically connected to the drain of the third NMOS tube NM1, the third ends of the first NMOS tube module and the second NMOS tube module are electrically connected to the output end of the pulse delay circuit and the input end of the latch module 700, respectively, and the fourth ends of the first NMOS tube module and the second NMOS tube module are grounded.

[0021] For further information, see Figure 7The first NMOS tube module includes a fourth NMOS tube NM4 and a fifth NMOS tube NM5, and the second NMOS tube module includes a sixth NMOS tube NM6 and a seventh NMOS tube NM7; the source of the fourth NMOS tube NM4 is electrically connected to the drain of the second NMOS tube NM0, the gate of the fourth NMOS tube NM4 is electrically connected to the output end of the pulse delay circuit, the drain of the fourth NMOS tube NM4 is electrically connected to the source of the fifth NMOS tube NM5 and the input end of the latch module 700, respectively, and the substrate of the fourth NMOS tube NM4 is grounded; the gate of the fifth NMOS tube NM5 is electrically connected to the input end of the latch module 700 The drain of the fifth NMOS tube NM5 is electrically connected to the source of the sixth NMOS tube NM6, and the substrate of the fifth NMOS tube NM5 is grounded; the gate of the sixth NMOS tube NM6 is electrically connected to the input end of the latch module 700, the drain of the sixth NMOS tube NM6 is electrically connected to the source of the seventh NMOS tube NM7 and the input end of the latch module 700, and the substrate of the sixth NMOS tube NM6 is grounded; the gate of the seventh NMOS tube NM7 is electrically connected to the output end of the pulse delay circuit, the drain of the seventh NMOS tube NM7 is electrically connected to the drain of the third NMOS tube NM1, and the substrate of the seventh NMOS tube NM7 is grounded. Among them, the first NMOS tube module and the second NMOS tube module are used to output the second control signal to the latch module 700.

[0022] Specifically, the second latch input control module 600 in this embodiment includes a completely symmetrical signal processing circuit, in which each device is a 1.8V device. Since the signal TIELOM is always a low-level signal, the PMOS tubes PM0 and PM1 remain turned on, and the signals N11 and N12 are both high-level when the NMOS tubes NM0 and NM1 are not turned on. When one of the NMOS tubes, such as NM0, is turned on, since the pull-down capability of NM0 is stronger than the pull-up capability of PM0, the signal N11 is pulled low, so that the NMOS tube NM4 is turned on, and the signal N10 is pulled low, thereby inputting a low-level control signal N10 to the latch module 700. The control signals N9 and N10 are used to control the data latching state of the latch module 700. NMOS tubes NM5 and NM6 are used to receive feedback signals N7 and N8 transmitted by the latch module 700. When either of the two NMOS tubes is turned on, it can be used to prevent backflow to isolate the NMOS tubes NM4 and NM7, and can also adjust the control signals N9 and N10.

[0023] like Figure 8 FIG. 1 is a circuit diagram of a latch module provided in this embodiment, see Figure 8The latch module 700 includes a first latch circuit, a second latch circuit, a NOR gate I17 and a sixth inverter I18; the first ends of the first latch circuit and the second latch circuit are electrically connected to the output end of the first latch input control module 100, the second ends of the first latch circuit and the second latch circuit are electrically connected to the output end of the sixth inverter I18 and the second latch input control module 600 respectively, the third ends of the first latch circuit and the second latch circuit are electrically connected to the input end of the NOR gate I17, and the output end of the NOR gate I17 is electrically connected to the input end of the sixth inverter I18.

[0024] For further information, see Figure 8 , the first latch circuit and the second latch circuit both include a third NAND gate I5 / I11, a fourth NAND gate I10 / I16, a seventh inverter I6 / I12, an eighth inverter I9 / I15 and a latch; taking the first latch circuit as an example, the first input end of the third NAND gate I5 is electrically connected to the output end of the first latch input control module 100, the second input end of the third NAND gate I5 is electrically connected to the output end of the sixth inverter I18, and the output end of the third NAND gate I5 is electrically connected to the input end of the seventh inverter I6, the output end of the second latch input control module 10 ... output end of the seventh inverter I6, the output end of the second latch input control module 100, and the output end of the third NAND gate I5 is electrically connected to the output end of the seventh inverter I6, the output end of the second latch input control module 100, and the output end of the third NAND gate I5 is electrically The control module 600 is electrically connected; the first end of the latch is electrically connected to the output end of the seventh inverter I6, and the second end of the latch is electrically connected to the input end of the eighth inverter I9 and the second latch input control module 600 respectively; the first input end of the fourth NAND gate I10 is electrically connected to the output end of the eighth inverter I9, the second input end of the fourth NAND gate I10 is electrically connected to the output end of the first latch input control module 100, and the output end of the fourth NAND gate I10 is electrically connected to the input end of the NOR gate I17 and the first latch input control module 100 respectively.

[0025] Further, see Figure 8 The latch includes a ninth inverter I7 / I13 and a tenth inverter I8 / I14. Taking the latch corresponding to I7 and I8 as an example, the input end of the ninth inverter I7 is electrically connected to the output end of the seventh inverter I6 and the output end of the tenth inverter I8, respectively, and the output end of the ninth inverter I7 is electrically connected to the input end of the eighth inverter I9, the input end of the tenth inverter I8, and the second latch input control module 600, respectively.

[0026] For further information, see Figure 8, the first latch circuit and the second latch circuit both further include a seventh PMOS transistor PM2 / PM3 and an eighth NMOS transistor NM2 / NM3; taking the first latch circuit as an example, the gate of the seventh PMOS transistor PM2 is electrically connected to the first latch input control module 100, the drain of the seventh PMOS transistor PM2 is electrically connected to the second end of the latch, and the source and substrate of the seventh PMOS transistor PM2 are electrically connected to the power supply VDD; the gate of the eighth NMOS transistor NM2 is electrically connected to the output end of the third NAND gate I5, the drain of the eighth NMOS transistor NM2 is electrically connected to the output end of the eighth inverter I9, and the source and substrate of the eighth NMOS transistor NM2 are grounded.

[0027] Specifically, the third NAND gate and the fourth NAND gate in this embodiment are both two-input NAND gates, and their circuit structures are as follows: Fig. 9 As shown, the two-input NAND gate circuit includes two PMOS tubes PM90 and PM91 and two NMOS tubes NM91 and NM90, and the inputs of the two-input NAND gate are A and B, and the output of the two-input NAND gate is Y. In the two-input NAND gate circuit, the PMOS tube PM90 and the PMOS tube PM91 are connected in parallel, and the NMOS tube NM90 and the NMOS tube NM91 are connected in series. The gates of the PMOS tube PM90 and the NMOS tube NM90 are connected to A, the gates of the PMOS tube PM91 and the NMOS tube NM91 are connected to B, the source of the NMOS tube NM91 is grounded, and the drain of the NMOS tube NM91 and the source of the NMOS tube NM90 are connected to net0. The drain of the NMOS tube NM90, the drain of the PMOS tube PM90, and the drain of the PMOS tube PM91 are connected through the signal line Y. The substrates of the PMOS tubes PM91 and PM90 are connected to VDD, and the substrates of the NMOS tubes NM90 and NM91 are connected to VSS.

[0028] The circuit structure of the NOR gate in this embodiment is as follows: Fig.10As shown, the two-input NOR gate circuit includes two PMOS tubes PM100 and PM101 and two NMOS tubes NM101 and NM100. The inputs of the two-input NOR gate are A and B, and the output of the two-input NAND gate is Y. In the two-input NOR gate circuit, the PMOS tube PM100 and the PMOS tube PM101 are connected in series, and the NMOS tube NM100 and the NMOS tube NM101 are connected in parallel. The gates of the PMOS tube PM100 and the NMOS tube NM100 are connected to A, the gates of the PMOS tube PM101 and the NMOS tube NM101 are connected to B, the source of the PMOS tube PM101 is connected to the power supply VDD, and the drain of the PMOS tube PM101 and the source of the PMOS tube PM100 are connected to net0. The drain of the PMOS tube PM100, the drain of the NMOS tube NM100, and the drain of the NMOS tube NM101 are connected through the signal line Y. The substrates of the PMOS tubes PM101 and PM100 are connected to VDD, and the sources and substrates of the NMOS tubes NM100 and NM101 are connected to VSS.

[0029] In this embodiment, the input signals of the latch module 700 come from the output signals N3 and N4 of the first latch input control module 100, and the output signals N9 and N10 of the second latch input control module 600. After being processed by the latch module 700, these input signals will generate four output signals, namely, the feedback signals N1 and N2 output to the first latch input control module 100, and the gate control signals N7 and N8 output to the second latch input control module 600. In addition, in this embodiment, the first latch circuit and the second latch circuit of the latch module 700 both include latches, and each latch includes two cross-coupled inverters. Taking the first latch as an example, the common connection end of the output end of the inverter I8 of the first latch and the input end of the inverter I7 serves as the input left end of the first latch (i.e., the port corresponding to the signal N13), and the common connection end of the input end of the inverter I8 of the first latch and the output end of the inverter I7 serves as the input right end of the first latch (i.e., the port corresponding to the signal N9). ); PMOS tube PM2 is used as a pull-up PMOS tube. When the output signal N3 of the first latch input control module 100 is at a low level, the PMOS tube PM2 will be turned on, thereby quickly pulling up the potential of the right end of the first latch; NMOS tube NM2 is used as a pull-down NMOS tube. When the output signal N7 of the NAND gate I5 is at a high level, the NMOS tube NM2 will be turned on, thereby quickly pulling down the level of the output signal N20 of the inverter I9 to a low level; the output end of the NAND gate I10 is the output end of the feedback signal N2. The latch module 700 latches two mutually inverted data. The latched data will flip with the changes of the control signals N3, N4 and the signals N9, N10, and output the corresponding feedback signal to control the input signals from the two input control modules.

[0030] For further information, see Figures 1 to 14 ,in, Fig.11 It is the structural diagram of the second asynchronous pulse signal generating circuit. Fig.12 This is a circuit schematic diagram of an asynchronous pulse signal generating circuit. Fig.13 This is the waveform diagram of the relevant signals in the first asynchronous pulse signal generation circuit. Fig.14 : is a waveform diagram of related signals in the second asynchronous pulse signal generating circuit. In the asynchronous pulse signal generating circuit of this embodiment, the first latch input control module 100 receives the DATA signal and the C signal, and outputs control signals N3 and N4 to the latch module 700 to control the data latching state in the latch. At the same time, the control signals N3 and N4 will jump with the change of the feedback signals N1 and N2 generated by the latch module 700, thereby generating a low pulse signal. The first latch input control module 100 outputs the control signals N3 and N4, and also serves as the input of the pulse delay module 400. The pulse delay module 400 receives the control signals N3 and N4 output by the first latch input control module 100 and generates four signals N5, N6, DWY, and DWYN with different delay times. These signals serve as input control signals of the second latch input control module 600, and the signals DWY and DWYN are the output signals of the entire asynchronous pulse signal generating circuit, which are transmitted to the storage unit such as SRAM to control the operation of the storage unit (such as write operation). The second latch input control module 600 receives control signals N5, N6, DWY, DWYN, and outputs control signals N9, N10 to the latch module 700 to control the data latching state in the latch, and the control signals N9, N10 will change with the feedback signals N7, N8 generated by the latch module. The latch module 700 latches two mutually inverted data, and the latched data will flip with the input signals received from the first latch input control module 100 and the second latch input control module 600, and output the corresponding feedback signal to control the control signals transmitted by the two input modules.

[0031] Specifically, when the first latch input control module 100 does not detect a data signal (ie, DATA signal) jump or a read / write control signal such as a chip select enable signal (ie, C signal) jump, the feedback signal N1 output by the latch module 700 is high level, and N2 is low level. At this time, the output signals N3 and N4 of the first latch input control module 100 are both high level. Afterwards, when the DATA signal is low level, the signal reaches the input end of the NAND gate I3 after passing through the inverters I1 and I2. At this time, the first input signal of the NAND gate I3 is low level. Since the second input signal C of the inverter I3 is high level, the third input signal, i.e., the feedback signal N1, is also high level, so the output signal N4 of the inverter I3 remains high level and does not flip. Therefore, when the first latch input control module 100 does not detect a data signal jump, the signal N4 does not generate a pulse signal (e.g. Fig.11 When the DATA signal reaches the input end of the NAND gate I4 after passing through the inverter I1, the first input signal of the NAND gate I4 is at a high level. Since the second input signal C of the NAND gate I4 is at a high level, the third input signal, i.e., the feedback signal N2, is at a low level, the output signal N3 of the NAND gate I4 remains at a high level and does not flip. Therefore, when the first latch input control module 100 does not detect a data signal jump, the signal N3 will not generate a pulse signal (for example, Fig.11 signal N3 in the output).

[0032] When the DATA signal of the first latch input control module 100 jumps to a rising edge, the C signal is at a high level at this time. The DATA signal passes through the inverters I1 and I2 and reaches the input end of the NAND gate I3. At this time, the signal at the input end is at a high level, the second input signal C of the NAND gate I3 is also at a high level, and the third input signal, i.e., the feedback signal N1, is also at a high level. Therefore, the output signal N4 of the NAND gate I3 becomes a low level, and a flip occurs (for example, Fig.11 The DATA signal passes through the inverter I1 and reaches the input of the NAND gate I4. At this time, the input signal is low, the second input signal C of the NAND gate I4 is high, and the third input signal, i.e., the feedback signal N2, is low. Therefore, the output signal N3 of the NAND gate I4 remains high and does not flip (for example, Fig.11 signal N3 in the output).

[0033] In the second latch input control module 600, when the output signals N3 and N4 of the first latch input control module 100 are both high level, after passing through the buffers I26 and I25 of the pulse delay module 400, the generated signals DWY and DWYN will also become high level. In this case, the gate voltages of the NMOS tubes NM1 and NM0 in the second latch input control module 600 are DWY and DWYN respectively, and the source voltages are DWYN and DWY respectively, and both voltages are high voltages. At the same time, the signals N5 and N6, as the signals N3 and N4 processed by the three-stage inverter in the pulse delay module 400, will become low level, which makes the NMOS tubes NM4 and NM7 turned off. The TIELOM signal is always low level, and the PMOS tubes PM1 and PM0 are always kept on, so that the signals N11 and N12 are kept high level. In such a configuration, the right input of the latch module 700 (ie, the second latch input control module 600 ) is closed.

[0034] When the output signal N4 of the first latch input control module 100 jumps to a low level, and the signal N3 remains at a high level, after the signals N4 and N3 pass through the buffers I25 and I26 of the pulse delay module 400, the potentials of the output signals DWYN and DWY follow the input signal, so that the source potential of the NMOS tube NM1 changes from a high level to a low level, while the source potential of the NMOS tube NM0 continues to remain at a high level, so that the NMOS tube NM1 is turned on, while the NMOS tube NM0 continues to remain in the off state. Since PM1 is a small-sized PMOS tube and NM1 is a large-sized NMOS tube, the pull-down capability of NM1 is much stronger than the pull-up capability of PM1, which causes the potential of the signal N12 to change from high to low. After being processed by the three-stage inverter of the pulse delay module 400, the signal N4 becomes a high level (that is, the signal N6 is a high level), and reaches the gate of the NMOS tube NM7, turning on the NMOS tube NM7, and pulling down the source of the NMOS tube NM7 to a low potential. This low potential will be output to the latch module 700 through the signal N9, pulling down the input of the corresponding latch, and when NM7 is turned on, NM4 will be turned off, so that the input of the latch corresponding to the signal N10 is closed.

[0035] When the output signal N4 of the first latch input control module 100 changes to a low level, and the signal N3 remains at a high level, the two input signals N4 and N11 of the NAND gate I11 in the second latch circuit are low and high levels respectively, which makes the output signal N8 of the NAND gate I11 high. After the signal N8 passes through the inverter I12, the output signal N14 is low. At this time, the level of the left end signal N14 of the latch of the second latch circuit changes from high to low, and the flip is achieved. At the same time, since the gate N8 of the pull-down NMOS tube NM3 is high and the gate N4 of the pull-up PMOS tube PM3 is low, the NMOS tube NM3 and the PMOS tube PM3 are both turned on. This makes the potential of the drain terminal N10 of the PMOS tube PM3 become high, and the drain terminal N21 of the NMOS tube NM3 becomes low, thereby ensuring that the latch in the second latch circuit is flipped.

[0036] When the output signal N4 of the first latch input control module 100 changes to a low level and the signal N3 remains at a high level, the left end signal N13 of the first latch changes from a low level to a high level, and the right end signal N9 of the latch in the first latch circuit changes from a high level to a low level. At the same time, the feedback signal N1 changes from a high level to a low level, and the feedback signal N2 changes from a low level to a high level. Thus, the output signal N3 of the NAND gate I4 of the first latch input control module 100 still remains at a high level, and the output signal N4 of the NAND gate I3 changes from a low level to a high level, thereby generating a low pulse signal on the signal line N4. Therefore, when the input signal DATA jumps to a rising edge, a low pulse signal with a pulse width of 1ns is generated in the signal line N4, i.e., the output signal line DWYN.

[0037] When the DATA signal of the first latch input control module 100 undergoes a falling edge transition, the first input signal N12 of the NAND gate I4 is high, the second input signal C of the NAND gate I4 is high, and the third input signal of the NAND gate I4, namely the feedback signal N2, is also high, which causes the output signal N3 of the NAND gate I4 to become low, that is, the output signal N3 is flipped; and the first input signal N11 of the NAND gate I3 is low, the second input signal C of the NAND gate I3 is high, and the third input signal of the NAND gate I3, namely the feedback signal N1, is low, which causes the output signal N4 of the NAND gate I3 to remain high, that is, the output signal N4 does not flip.

[0038] When the output signal N3 of the first latch input control module 100 jumps to a low level and the signal N4 remains at a high level, the signals N4 and N3 pass through the buffers I25 and I26 of the pulse delay module 400, so that the potential of DWYN is high and the potential of DWY is low. Correspondingly, the NMOS tube NM0 of the second latch input control module 600 is turned on and the NMOS tube NM1 is turned off, and the source potential of the NMOS tube NM0 changes from a high level to a low level while the source potential of the NMOS tube NM1 continues to remain at a high level. Since the PMOS tube PM0 is a small-sized PMOS tube and the NMOS tube NM0 is a large-sized NMOS tube, the pull-down capability of the NMOS tube NM0 is much stronger than the pull-up capability of PM0, which causes the potential of the signal N11 to change from high to low. Subsequently, the signal N3 is processed by the three-stage inverter of the pulse delay module 400 and becomes a high level (i.e., the signal N5 is a low level), and reaches the gate of the NMOS tube NM4, thereby turning on the NMOS tube NM4 and pulling the source of the NMOS tube NM4 down to a low potential. Then, this low potential is output to the latch module 700 through the signal N10, and at this time, the potential of the signal N14 of the latch module 700 changes from low to high, achieving a flip. At the same time, the NMOS tube NM7 is turned off, so that the input of the latch corresponding to the signal N9 is closed.

[0039] When the output signal N3 of the first latch input control module 100 jumps to a low level and N4 remains at a high level, the two input signals N3 and N11 of the NAND gate I5 in the first latch circuit are low and high levels respectively. This makes the output signal N7 of the NAND gate I5 high. After the signal N7 passes through the inverter I6, the output signal N13 is low. At this time, the level of the left end signal N13 of the first latch changes from high to low, and flipping is achieved. At the same time, since the gate N7 of the pull-down NMOS tube NM2 is high, and the gate N3 of the pull-up PMOS tube PM2 is low, the NMOS tube NM2 and the PMOS tube PM2 are both turned on. This makes the potential of the drain terminal N9 of the PMOS tube PM2 become high, and the drain terminal N20 of the NMOS tube NM2 becomes low, thereby ensuring that the latch in the first latch circuit is flipped.

[0040] When the output signal N3 of the first latch input control module 100 changes to a low level and the signal N4 is a high level, the left end N13 of the first latch changes from a high level to a low level, the left end signal N14 of the latch in the second latch circuit changes from a low level to a high level, the feedback signal N1 changes from a low level to a high level, and the feedback signal N2 changes from a high level to a low level. Afterwards, the output signal N4 of the NAND gate I3 in the first latch input control module 100 remains at a high level, and the output N3 of the NAND gate I4 changes from a low level to a high level, thereby generating a low pulse signal on the N3 signal line. Thus, when the input signal DATA has a falling edge jump, a low pulse signal with a pulse width of 1ns will be generated in the signal line N3, i.e., the output signal line DWY, and when the input signal DATA has a rising edge jump, a low pulse signal with a pulse width of 1ns will be generated in the signal line N4, i.e., the output signal line DWYN, thereby realizing the conversion of the signal jump in the continuous DATA signal into a corresponding low pulse pair (for example Fig.11 The signals N3 and N4 in the figure) can be used to control the subsequent storage unit 500 through a low pulse pair, for example, a write operation can be performed.

[0041] When the read / write control signal (i.e., C signal) has a rising edge transition and the DATA signal is at a high level, the DATA signal will pass through inverters I1 and I2 and then reach the input end of the NAND gate I3, at which point the input signal is at a high level. At the same time, the second input signal C of the NAND gate I3 is also at a high level, and the third input signal, i.e., the feedback signal N1, is also at a high level. Therefore, the output signal N4 of the NAND gate I3 will become a low level, causing the output signal N4 of the first latch input control module 100 to flip (e.g., Fig.12 At this time, the output signal N3 of the NAND gate I4 remains at a high level and does not flip (for example Fig.12 Once the signal N4 flips, the states of the two latches in the latch module 700 will also flip, and the feedback signals N1 and N2 will also flip. Afterwards, since the input signal N1 of the NAND gate I3 becomes low level, its output signal N4 also changes from low level to high level, thereby generating a low pulse signal (for example Fig.12In this process, the output signal N3 always maintains a high level and does not generate a low pulse signal. After that, no matter how the C signal changes, since the signals N1, N2 and DATA signal do not jump, the signals N3 and N4 will remain in a high level state. Therefore, when the DATA signal is at a high level, the system will generate a low pulse signal on the signal line N4 after detecting the first rising edge of the C signal. The low pulse signal can also realize the operation control of the subsequent storage unit 500. The purpose of introducing the C signal in this embodiment is to introduce an additional control signal for the pulse signal generation circuit to meet the needs of controlling subsequent operations in multiple ways in practical applications.

[0042] It should be noted that the various embodiments in the present application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0043] It should also be noted that, in the content of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" can expressly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0044] The above description of the disclosed embodiments enables professionals and technicians in the field to implement or use the present application. Various modifications to these embodiments will be apparent to professionals and technicians in the field, and the general principles defined in the present application can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown in the present application, but will conform to the widest range consistent with the principles and novel features disclosed in the present application.

Claims

1. An asynchronous pulse signal generating circuit, characterized in that: include: A first latch input control module is electrically connected to an external data signal generator and a read / write control signal generator, respectively, and is used to output a first control signal when an edge event of an asynchronous input signal is detected; wherein the first control signal includes a signal with a level jump and a signal with no level jump; A pulse delay module, electrically connected to the first latch input control module and an external storage unit, respectively, for generating a corresponding output signal and a delay control signal according to the level states of the two signals in the first control signal; wherein the level state of the output signal is consistent with the level state of the first control signal; A second latch input control module, electrically connected to the pulse delay module, and configured to generate a corresponding second control signal according to the level state of the output signal and the delay control signal; The latch module is electrically connected to the first latch input control module and the second latch input control module respectively, and is used to output a corresponding feedback signal according to the level status of the two signals in the first control signal and the second control signal; wherein the feedback signal is used to instruct the first latch input control module to restore the level state of the level-jumped signal to the original level state.

2. The asynchronous pulse signal generating circuit according to claim 1, characterized in that: The first latch input control module includes a first inverter, a second inverter, a first NAND gate and a second NAND gate; The input end of the first inverter is used to be electrically connected to the data signal generator, and the output end of the first inverter is electrically connected to the input end of the second inverter and the first input end of the second NAND gate respectively; The first input end of the first NAND gate is electrically connected to the output end of the second inverter, the second input end of the first NAND gate is electrically connected to the latch module, the third input end of the first NAND gate is electrically connected to the second input end of the second NAND gate and is used to be electrically connected to the read-write control signal generator, and the output end of the first NAND gate is electrically connected to the latch module and the pulse delay module respectively; The third input end of the second NAND gate is electrically connected to the latch module, and the output end of the second NAND gate is electrically connected to the latch module and the pulse delay module respectively.

3. The asynchronous pulse signal generating circuit according to claim 1, characterized in that: The pulse delay module includes a first delay circuit and a second delay circuit, and the first delay circuit and the second delay circuit each include a third inverter, a fourth inverter, a fifth inverter, a first buffer, a first PMOS tube and a second PMOS tube; The input end of the third inverter is electrically connected to the output end of the first latch input control module, and the output end of the third inverter is electrically connected to the input end of the fourth inverter; The input end of the fifth inverter is electrically connected to the output end of the fourth inverter, and the output end of the fifth inverter is electrically connected to the input end of the second latch input control module; The input end of the first buffer is electrically connected to the output end of the first latch input control module, and the output end of the first buffer is electrically connected to the input end of the second latch input control module; The gates of the first PMOS tube and the second PMOS tube are electrically connected to the output end of the third inverter, and the source, drain and substrate of the first PMOS tube and the second PMOS tube are electrically connected to a power supply.

4. The asynchronous pulse signal generating circuit according to claim 3, characterized in that: The first delay circuit and the second delay circuit both further include a third PMOS transistor, a fourth PMOS transistor and a first NMOS transistor; The gate, source, drain and substrate of the third PMOS tube are all electrically connected to the power supply, the gate of the fourth PMOS tube is electrically connected to the output end of the fourth inverter, and the source, drain and substrate of the fourth PMOS tube are all electrically connected to the power supply; the gate of the first NMOS tube is electrically connected to the output end of the first latch input control module, the drain of the first NMOS tube is electrically connected to the output end of the fifth inverter, and the source and substrate of the first NMOS tube are both grounded.

5. The asynchronous pulse signal generating circuit according to claim 1, characterized in that: The second latch input control module includes a second NMOS tube, a third NMOS tube, a first NMOS tube module, a second NMOS tube module, a fifth PMOS tube and a sixth PMOS tube; The gate and source of the second NMOS tube and the third NMOS tube are electrically connected to the output end of the pulse delay module, the drain of the second NMOS tube is electrically connected to the drain of the fifth PMOS tube and the latch module respectively, the drain of the third NMOS tube is electrically connected to the drain of the sixth PMOS tube, and the substrates of the second NMOS tube and the third NMOS tube are grounded; The gates of the fifth PMOS tube and the sixth PMOS tube are both used to be electrically connected to an external low-level signal generator, and the source and substrate of the fifth PMOS tube and the sixth PMOS tube are both electrically connected to a power supply; The first end of the first NMOS tube module is electrically connected to the drain of the second NMOS tube, the second end of the first NMOS tube module is electrically connected to the first end of the second NMOS tube module, the second end of the second NMOS tube module is electrically connected to the drain of the third NMOS tube, the third ends of the first NMOS tube module and the second NMOS tube are electrically connected to the output end of the pulse delay circuit and the input end of the latch module respectively, and the fourth ends of the first NMOS tube module and the second NMOS tube module are grounded.

6. The asynchronous pulse signal generating circuit according to claim 5, characterized in that: The first NMOS tube module includes a fourth NMOS tube and a fifth NMOS tube, and the second NMOS tube module includes a sixth NMOS tube and a seventh NMOS tube; The source of the fourth NMOS tube is electrically connected to the drain of the second NMOS tube, the gate of the fourth NMOS tube is electrically connected to the output end of the pulse delay circuit, the drain of the fourth NMOS tube is electrically connected to the source of the fifth NMOS tube and the input end of the latch module respectively, and the substrate of the fourth NMOS tube is grounded; The gate of the fifth NMOS tube is electrically connected to the input end of the latch module, the drain of the fifth NMOS tube is electrically connected to the source of the sixth NMOS tube, and the substrate of the fifth NMOS tube is grounded; The gate of the sixth NMOS tube is electrically connected to the input end of the latch module, the drain of the sixth NMOS tube is electrically connected to the source of the seventh NMOS tube and the input end of the latch module respectively, and the substrate of the sixth NMOS tube is grounded; The gate of the seventh NMOS tube is electrically connected to the output end of the pulse delay circuit, the drain of the seventh NMOS tube is electrically connected to the drain of the third NMOS tube, and the substrate of the seventh NMOS tube is grounded.

7. The asynchronous pulse signal generating circuit according to claim 1, characterized in that: The latch module includes a first latch circuit, a second latch circuit, a NOR gate and a sixth inverter; The first ends of the first latch circuit and the second latch circuit are electrically connected to the output end of the first latch input control module, the second ends of the first latch circuit and the second latch circuit are electrically connected to the output end of the sixth inverter and the second latch input control module, respectively, the third ends of the first latch circuit and the second latch circuit are electrically connected to the input end of the NOR gate, and the output end of the NOR gate is electrically connected to the input end of the sixth inverter.

8. The asynchronous pulse signal generating circuit according to claim 7, characterized in that: The first latch circuit and the second latch circuit both include a third NAND gate, a fourth NAND gate, a seventh inverter, an eighth inverter and a latch; The first input end of the third NAND gate is electrically connected to the output end of the first latch input control module, the second input end of the third NAND gate is electrically connected to the output end of the sixth inverter, and the output end of the third NAND gate is electrically connected to the input end of the seventh inverter and the second latch input control module respectively; The first end of the latch is electrically connected to the output end of the seventh inverter, and the second end of the latch is electrically connected to the input end of the eighth inverter and the second latch input control module respectively; The first input end of the fourth NAND gate is electrically connected to the output end of the eighth inverter, the second input end of the fourth NAND gate is electrically connected to the output end of the first latch input control module, and the output end of the fourth NAND gate is electrically connected to the input end of the NOR gate and the first latch input control module respectively.

9. The asynchronous pulse signal generating circuit according to claim 8, characterized in that: The latch includes a ninth inverter and a tenth inverter, the input end of the ninth inverter is electrically connected to the output end of the seventh inverter and the output end of the tenth inverter respectively, and the output end of the ninth inverter is electrically connected to the input end of the eighth inverter, the input end of the tenth inverter, and the second latch input control module respectively.

10. The asynchronous pulse signal generating circuit according to claim 8, characterized in that: The first latch circuit and the second latch circuit both further include a seventh PMOS transistor and an eighth NMOS transistor; The gate of the seventh PMOS tube is electrically connected to the first latch input control module, the drain of the seventh PMOS tube is electrically connected to the second end of the latch, and the source and substrate of the seventh PMOS tube are electrically connected to the power supply; The gate of the eighth NMOS tube is electrically connected to the output end of the third NAND gate, the drain of the eighth NMOS tube is electrically connected to the output end of the eighth inverter, and the source and substrate of the eighth NMOS tube are grounded.

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