Delay phase-locked loop circuit and system device

Abstract

The present invention provides a delay phase-locked loop circuit and a system device. The delay phase-locked loop circuit is based on the original DLL circuit architecture (including the first phase detector), and the first to seconda+1 delay circuits and the second to seconda+1 phase detectors are added. The first delay circuit is arranged between a controllable delay chain and a clock buffer circuit. The second to seconda+1 delay circuits are cascaded and further delay the feedback clock signal output by the replica clock buffer circuit. Thus, the second to seconda+1 delay circuits and the replica clock buffer circuit generate 2a+1 feedback clock signals in total. The first to seconda+1 phase detectors detect the phase relationship between these feedback clock signals and an external clock signal, so that the control circuit can at least quickly determine the moment when the phase difference between the output clock signal and the external clock signal is less than 1C (the 1C is the unit length of the coarse adjustment of the controllable delay chain) or less than 2C and 1C respectively according to the detection results of these phase detectors, thereby reducing the locking steps, shortening the locking time, and accelerating the locking of the DLL circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of phase-locked loops, and in particular to a delay phase-locked loop circuit and a system device. Background Art

[0002] When the external clock signal applied from the external device is used in the corresponding system device, a delay or clock deviation caused by the internal circuit of the system device may be generated. At present, a delay-locked loop (DLL) circuit is usually used to compensate for this delay or clock deviation, so that the output frequency and phase of the system device are locked to an output clock signal with a fixed frequency and phase, and the phase of the output clock signal and the external clock signal are synchronized (they can be edge-aligned or differ by a fixed value). At this time, the DLL is locked to ensure the normal operation of the system device. The DLL circuit technology is currently widely used in various timing fields, such as providing one or more clocks with required frequencies in a chip system, or generating local oscillator signals in a receiver, or maintaining synchronization in a communication system.

[0003] Therefore, fast locking of the DLL circuit has always been one of the technical problems that those skilled in the art need to solve urgently. Summary of the invention

[0004] The object of the present invention is to provide a delay phase-locked loop circuit and a system device, which can achieve rapid locking.

[0005] To achieve the above object, the present invention provides a delay phase-locked loop circuit, comprising a controllable delay chain, a clock buffer circuit, a replica clock buffer circuit and a control circuit, characterized in that it also comprises first to seconda+1 delay circuits and first to seconda+1 phase detectors, a≥1 and is an integer, wherein:

[0006] The input end of the first delay circuit and the input end of the replica clock buffer circuit are both coupled to the output end of the controllable delay chain, the output end of the first delay circuit is coupled to the input end of the clock buffer circuit, the clock buffer circuit is used to output the clock signal output by the first delay circuit as a corresponding output clock signal, the second to 2a+1 delay circuits are cascaded in sequence, and the input end of the second delay circuit is coupled to the output end of the replica clock buffer circuit;

[0007] The first input ends of the 1st to 2a+1th phase detectors and the input end of the controllable delay chain are both coupled to the external clock signal, the second input end of the 1st phase detector is coupled to the output end of the replica clock buffer circuit, the second input ends of the 2nd to 2a+1th phase detectors are coupled to the output ends of the 2nd to 2a+1 delay circuits one by one, the output ends of the 1st to 2a+1 phase detectors are both coupled to the corresponding input ends of the control circuit, and the output end of the control circuit is coupled to the control end of the controllable delay chain to determine whether to switch from coarse adjustment to fine adjustment according to the detection results of the 1st to 2a+1 phase detectors.

[0008] Optionally, the first delay circuit is used to delay the clock signal output by the controllable delay chain for a specific time length and then output it to the clock buffer circuit;

[0009] The second to 2a+1 delay circuits are used to delay the feedback clock signal output by the replica clock buffer circuit by a time corresponding to the specific time length;

[0010] The first to second a+1 phase detectors are used to detect the phase relationship between the feedback clock signals output by the replica clock buffer circuit and the second to second a+1 delay circuits and the external clock signal respectively;

[0011] The control circuit is used to first perform coarse adjustment on the controllable delay chain according to the detection results of the 1st to 2a+1th phase detectors, and determine whether to switch from the coarse adjustment to the fine adjustment according to the detection results, and then perform the fine adjustment on the controllable delay chain after the coarse adjustment is completed, so as to synchronize the phases of the output clock signal and the external clock signal.

[0012] Optionally, the control circuit performs coarse adjustment on the controllable delay chain by using a coarse adjustment step size binary decreasing method, and performs fine adjustment on the controllable delay chain by using a fine adjustment step size binary decreasing method.

[0013] Optionally, the control circuit is used to determine the phase difference between the feedback clock signal output by the a+1th delay circuit and the external clock signal based on the detection results of at least the ath to a+2th phase detectors, and then decide whether to switch from the coarse adjustment to the fine adjustment, and / or switch the step size and / or direction of coarse or fine adjustment of the controllable delay chain.

[0014] Optionally, the delay durations provided by the 2nd to 2a+1th delay circuits are the same, and the specific duration is a times the delay duration.

[0015] Optionally, the delay duration is a unit length of the controllable delay chain for performing the coarse adjustment.

[0016] Optionally, the control circuit is further used to determine whether the phase difference between the feedback clock signal output by the a+1th delay circuit and the external clock signal is less than the unit length of the coarse adjustment according to the detection results of the ath to a+2th phase detectors during the coarse adjustment of the controllable delay chain, so as to determine whether to switch from the coarse adjustment to the fine adjustment;

[0017] Among them, when the a-th phase detector detects that the rising edge of the feedback clock signal it receives is ahead of the rising edge of the external clock signal, and the a+1-th phase detector detects that the rising edge of the feedback clock signal output by the a+1-th delay circuit is ahead of or lags behind the rising edge of the external clock signal, and the a+2-th phase detector detects that the rising edge of the feedback clock signal output by the a+2-th delay circuit lags behind the rising edge of the external clock signal, it is determined that the phase difference between the feedback clock signal output by the a+1-th delay circuit and the external clock signal is less than the unit length of the coarse adjustment.

[0018] Optionally, each of the phase detectors is used to detect the phase relationship between the rising edge of the feedback clock signal it receives and the rising edge of the external clock signal, and outputs 0 when it detects that the rising edge of the feedback clock signal it receives is ahead of the rising edge of the external clock signal, and outputs 1 when it detects that the rising edge of the feedback clock signal it receives is behind the rising edge of the external clock signal, wherein the detection results of the ath to a+2th phase detectors are recorded as PD<a:a+2> , the control circuit is further used to perform the following steps to switch the step size and / or direction of coarse or fine adjustment of the controllable delay chain:

[0019] Using a first coarse adjustment step size to adjust the delay of the controllable delay chain along a first direction until the rising edge of the feedback clock signal output by the a+1th delay circuit reaches the right side of the falling edge of the external clock signal or reaches the vicinity of the rising edge of the external clock signal;

[0020] The delay of the controllable delay chain is adjusted along a suitable direction of the first direction and the second direction by using a second coarse adjustment step length which is smaller than the first coarse adjustment step length until PD<a:a+2> becomes <001> , wherein the first direction is opposite to the second direction;

[0021] The delay of the controllable delay chain is adjusted along the first direction using a first fine adjustment step until PD<a:a+2> becomes <011> ;

[0022] The delay of the controllable delay chain is adjusted along the second direction using a second fine adjustment step length which is smaller than the first fine adjustment step length until PD<a:a+2> becomes <001> ;

[0023] The delay of the controllable delay chain is adjusted along the first direction using a third fine adjustment step length which is smaller than the second fine adjustment step length until PD<a:a+2> becomes <011> , thereby completing the locking of the delay phase-locked loop circuit.

[0024] Optionally, a≥2, the detection results of the a-1th to a+3th phase detectors are recorded as PD<a-1:a+3> The control circuit is further configured to adjust the delay of the controllable delay chain along a first direction using a first coarse adjustment step size equal to 2C until PD<a-1:a+3> becomes <00001> , so that the rising edge of the feedback clock signal output by the a+3th delay circuit reaches the right side of the rising edge of the external clock signal, and the rising edge of the feedback clock signal output by the a+1th delay circuit reaches the left side of the rising edge of the external clock signal, where 1C is the unit length of the coarse adjustment of the controllable delay chain.

[0025] Optionally, each of the phase detectors further has an enable terminal, and the control circuit is further used to enable the PD<a-1:a+3> becomes <00001> Afterwards, the outputs of the 1st to a-1th phase detectors and the a+3th to 2a+1th phase detectors are disabled by controlling the enable terminals of the 1st to a-1th phase detectors and the a+3th to 2a+1th phase detectors, and the outputs of the ath to a+2th phase detectors are maintained by controlling the enable terminals of the ath to a+2th phase detectors, so as to switch the step size and / or direction of coarse or fine adjustment of the controllable delay chain using the detection results of the ath to a+2th phase detectors, until the delay phase-locked loop circuit is locked;

[0026] Alternatively, the control circuit is further configured to:<a-1:a+3> becomes <00001> Afterwards, it is further used for:

[0027] The delay of the controllable delay chain is adjusted along the first direction using a second coarse adjustment step size equal to 1C until PD<a-1:a+3> becomes <00011> ;

[0028] The delay of the controllable delay chain is adjusted along the first direction using a first fine adjustment step until PD<a-1:a+3> becomes <00111> ;

[0029] The delay of the controllable delay chain is adjusted along the second direction using a second fine adjustment step length which is smaller than the first fine adjustment step length until PD<a-1:a+3> becomes <00011> ;

[0030] The delay of the controllable delay chain is adjusted along the first direction using a third fine adjustment step length which is smaller than the second fine adjustment step length until PD<a-1:a+3> becomes <00111> , thereby completing the locking of the delay phase-locked loop circuit.

[0031] Optionally, the unit length of the controllable delay chain fine adjustment is 1F, the first fine adjustment step is 4F, the second fine adjustment step is 2F, and the third fine adjustment step is 1F.

[0032] Optionally, the control circuit includes a state machine coupled to the controllable delay chain and each of the phase detectors, the state machine being used to enter different states according to a combination of output results of each of the phase detectors, and when the state machine is in different states, different adjustment steps or adjustment directions are used to adjust the delay of the controllable delay chain.

[0033] Based on the same inventive concept, the present invention further provides a system device, which includes the delay phase-locked loop circuit as described in the present invention.

[0034] Optionally, the system device is a memory chip, and the output clock signal output by the delay phase-locked loop circuit is a data selection pulse signal of the memory chip. The delay phase-locked loop circuit is used to adjust the phase difference between the external clock signal input to the memory chip and the data selection pulse signal until the external clock signal is phase-synchronized with the data selection pulse signal and locked.

[0035] Compared with the prior art, the technical solution of the present invention adds the first to second a+1 delay circuits and the second to second a+1 phase detectors to the original DLL circuit architecture (including the first phase detector), and the first delay circuit is arranged between the controllable delay chain and the clock buffer circuit, and the second to second a+1 delay circuits are cascaded and further delay the feedback clock signal output by the replica clock buffer circuit, so that the second to second a+1 delay circuits and the replica clock buffer circuit generate 2a+1 feedback clock signals in total, and the first to second a+1 phase detectors detect the phase relationship between these feedback clock signals and the external clock signal, and the control circuit can quickly determine whether to switch from coarse adjustment to fine adjustment according to the detection results of these phase detectors. In a further embodiment, the control circuit can at least quickly determine the moment when the phase difference between the output clock signal and the external clock signal is less than 1C (where 1C is the unit length of the coarse adjustment of the controllable delay chain) or less than 2C and 1C respectively according to the detection results of these phase detectors, thereby shortening the locking time and accelerating the locking of the DLL circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0037] Figure 1 It is a typical schematic diagram of the DLL circuit architecture.

[0038] Figure 2 yes Figure 1 Schematic diagram of the locking process of the DLL circuit shown.

[0039] Figure 3 It is a schematic diagram of the architecture of the DLL circuit of the present invention.

[0040] Figure 4 FIG. 4 is a schematic diagram of the structure of a DLL circuit according to the first embodiment of the present invention.

[0041] Figure 5A and Figure 5B yes Figure 4 Schematic diagram of two phase relationships between the feedback clock signal and VCLK in the DLL circuit shown.

[0042] Figure 6 yes Figure 4 The schematic diagram of the controllable delay chain and control circuit in the DLL circuit shown.

[0043] Figure 7 yes Figure 4 An exemplary structural diagram of a coarse adjustment delay circuit in a controllable delay chain of a DLL circuit is shown.

[0044] Figure 8 yes Figure 4 Schematic diagram of the locking process of the DLL circuit shown.

[0045] Fig. 9 FIG. 4 is a schematic diagram of the structure of a DLL circuit according to a second embodiment of the present invention.

[0046] Fig.10 yes Fig. 9 Schematic diagram of the locking process of the DLL circuit shown.

[0047] Fig.11 FIG. 4 is a schematic diagram of the structure of a DLL circuit according to a third embodiment of the present invention.

[0048] Fig.12 yes Fig.11 Schematic diagram of the locking process of the DLL circuit shown.

[0049] Fig.13 FIG. 4 is a schematic diagram of the architecture of a system device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0050] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0051] As described in the background technology, the application field of DLL circuit technology is relatively wide. For example, in DRAM (Dynamic Random Access Memory) chips, the DLL circuit is used to align the phase of the external clock signal VCLK input to the DRAM chip by the external bus and the output clock signal DQS generated by the DRAM chip. When the phases of VCLK and DQS are aligned, the DLL circuit is locked. For DRAM chips, the fast locking of the DLL circuit can ensure the correct implementation of operations such as reading and writing.

[0052] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a typical DLL circuit, which includes a controllable delay chain (i.e., Delay Line) 10, a clock buffer circuit 11, a control circuit 12, a replica clock buffer circuit 13, and a phase detector (PD) 14. The replica clock buffer circuit 13 is a replica circuit of the clock buffer circuit 11. The controllable delay chain 10 receives an external clock signal VCLK, delays the external clock signal VCLK, and outputs it as a delayed clock signal CLKout. The replica clock buffer circuit 13 provides a feedback clock signal DQS after delaying the delayed clock signal CLKout. fb , phase detector 14 pairs of VCLK and DQSfb The control circuit 12 controls the length of the controllable delay chain (Delay Line) 10 to increase or decrease according to the detection and comparison result of the phase detector 14, so as to increase or decrease the delay of CLKout relative to VCLK, and then adjust the phase difference between VCLK and DQS until the phase between VCLK and DQS is synchronized (or the phase difference between the two is 0), and the DLL circuit is locked. At this time, VCLK and DQS are aligned (i.e., synchronized).

[0053] Please combine Figure 1 and Figure 2 , the control circuit 12 controls the controllable delay chain 10 to increase or decrease the delay, which usually includes coarse delay adjustment and fine delay adjustment, and the unit length of coarse delay adjustment (i.e., the minimum coarse adjustment step length) is 1Coarse (denoted as 1C), which represents the minimum delay that the controllable delay chain 10 (delay line) can increase or decrease during the coarse delay adjustment process; the unit length of fine delay adjustment (i.e., the minimum fine adjustment step length) is 1Fine (denoted as F), which represents the minimum delay that the controllable delay chain 10 (delay line) can increase or decrease during the fine delay adjustment process, 1F = C / k, k is a positive integer greater than 1. As an example, k = 16.

[0054] During the locking process of the DLL circuit, the control circuit 12 first performs a coarse adjustment based on the detection and comparison results of the phase detector 14, and then performs a fine adjustment after the coarse adjustment is completed until the DLL circuit is locked. fb Initial position of rising edge Figure 2 ① in the Figure 2 The DLL circuit lock process is as follows:

[0055] (1) The control circuit 12 adjusts the delay of the controllable delay chain 10 to the right (i.e., roughly adjusts) with a coarse adjustment step of 2C, so that DQS fb Move right as a whole until DQS fb The rising edge reaches the right side of the falling edge of VCLK, such as Figure 2 As shown in ②;

[0056] (2) The control circuit 12 adjusts the delay of the controllable delay chain 10 to the right (i.e., coarsely adjusts) with a coarse adjustment step size of 1C so that DQS fb Continue to adjust the whole to the right until DQS fb The rising edge reaches the right side of the second rising edge of VCLK, such as Figure 2 As shown in ③;

[0057] (3) The control circuit 12 adjusts the delay of the controllable delay chain 10 to the left (i.e., roughly adjusts) with a coarse adjustment step size of 1C, so that DQS fb Continue to adjust the whole to the left until DQS fb The rising edge reaches the left side of the second rising edge of VCLK, such as Figure 2 As shown in ④;

[0058] (4) The control circuit 12 controls the delay of the controllable delay chain 10 to be adjusted (i.e., fine-tuned) with a fine-tuning step size of 4F, so that DQS fb Adjust the whole to the right again until DQS fb The rising edge reaches the right side of the second rising edge of VCLK, such as Figure 2 As shown in ⑤;

[0059] (5) The control circuit 12 adjusts (i.e., fine tunes) the delay of the controllable delay chain 10 with a fine adjustment step of 2F so that DQS fb Adjust the whole to the left again until DQS fb The rising edge reaches the left side of the second rising edge of VCLK, such as Figure 2 As shown in ⑥;

[0060] (6) The control circuit 12 adjusts (i.e., fine tunes) the delay of the controllable delay chain 10 with a fine adjustment step size of 1F so that DQS fb Adjust the whole to the right again until DQS fb The rising edge reaches the right side of the second rising edge of VCLK, such as Figure 2 As shown in Figure ⑦;

[0061] (7) At this point, DQS fb The rising edge crosses the second rising edge of VCLK twice at a fine adjustment step of 1F, and the control circuit 12 considers that DQS fb When the phase difference with VCLK reaches a preset range (that is, the phase difference between DQS and VCLK can be regarded as 0), the delay of the controllable delay chain 10 no longer changes, and the DLL circuit completes locking.

[0062] The above-mentioned DLL circuit locking process requires more adjustment steps, longer locking time, and slower locking, which affects the output of the required output clock signal DQS, and further affects the correct implementation of the read and write operations of the DRAM chip having the DLL circuit.

[0063] Based on this, please refer to Figure 3 and Fig.13The present invention provides a delay phase-locked loop (DLL) circuit and a system device having the delay phase-locked loop (DLL) circuit. The delay phase-locked loop circuit further adds the first to the second a+1 delay circuits and the second to the second a+1 phase detectors on the original DLL circuit architecture (including a controllable delay chain 10, a clock buffer circuit 11, a control circuit 12, a first phase detector and a replica clock buffer circuit 13), wherein a ≥ 1 and is an integer, and the input end of the first delay circuit and the input end of the replica clock buffer circuit 13 are both coupled to the controllable delay chain (Delay The output end of the first delay circuit is coupled to the input end of the clock buffer circuit 11, the second to the 2a+1 delay circuits are cascaded in sequence, and the input end of the second delay circuit is coupled to the output end of the replica clock buffer circuit 13, the first input ends of the first to the 2a+1 phase detectors and the input end of the controllable delay chain 10 are both coupled to the external clock signal VCLK, the second input end of the first phase detector is coupled to the output end of the replica clock buffer circuit 13, the second input ends of the second to the 2a+1 phase detectors are coupled to the output ends of the second to the 2a+1 delay circuits one by one, the output ends of the first to the 2a+1 phase detectors are all coupled to the corresponding input ends of the control circuit 12, and the output end of the control circuit 12 is coupled to the control end of the controllable delay chain 10.

[0064] The controllable delay chain 10 is used to controllably delay the external clock signal VCLK and output it as a delayed clock signal CLKout.

[0065] The first delay circuit is used to delay the clock signal CLKout output by the controllable delay chain 10 by a specific time length (eg, td or 2td) and then output the delayed signal to the clock buffer circuit 11 .

[0066] The clock buffer circuit 11 is used to output the clock signal output by the first delay circuit as a corresponding output clock signal DQS. The replica clock buffer circuit 13 is a replica circuit of the clock buffer circuit 11.

[0067] The second to the seconda+1 delay circuits are used to further delay the feedback clock signal output by the replica clock buffer circuit 13, so that the second to the seconda+1 delay circuits and the replica clock buffer circuit 13 generate 2a+1 feedback clock signals fb0 to fb2a. Furthermore, the delays provided by the second to the seconda+1 delay circuits are all delays corresponding to the specific time length of the first delay circuit, and their delay time lengths can be the same. For example, the delays provided by the second to the seconda+1 delay circuits are all td, and the delay provided by the first delay circuit is a*td (that is, the specific time length is a times the delay provided by the second to the seconda+1 delay circuits, a≥1 and is an integer), and when the feedback clock signal fba=DQS output by the a+1 delay circuit fb When fb0 = DQSfb -a*td,fb1=DQS fb -a*td+td, and so on, fb2a=DQS fb +a*td. The feedback clock signals fb0-fba-1 generated by the replica clock buffer circuit 13, the 2nd to ath delay circuits, and the feedback clock signals fba+1-fb2a generated by the a+2nd to 2a+1th delay circuits are symmetrically distributed about the feedback clock signal fba generated by the a+1th delay circuit. At this point, it can be said that the 1st to ath phase detectors and the a+2nd to 2a+1th phase detectors are symmetrically distributed on both sides of the a+1th phase detector.

[0068] The first to second a+1 phase detectors are used to detect the phase relationship between the feedback clock signals fb0 to fb2a outputted by the replica clock buffer circuit 13 and the second to second a+1 delay circuits and the external clock signal VCLK, thereby generating a detection result PD <1> ~PD<2a+1> (which can be recorded as PD<1:2a+1>). Further, each phase detector in the 1st to 2a+1th phase detectors detects the rising edge of the feedback clock signal it receives and the rising edge of the external clock signal VCLK (i.e. Figure 8 The detection result PD is outputted as 0 when it is detected that the rising edge of the feedback clock signal it receives is ahead of the rising edge of the external clock signal VCLK in phase, and the detection result PD is outputted as 1 when it is detected that the rising edge of the feedback clock signal it receives is behind the rising edge of the external clock signal VCLK in phase.

[0069] The control circuit 12 is used to first coarsely adjust the controllable delay chain 10 according to the detection results PD<1:2a+1> of the 1st to 2a+1th phase detectors, and then fine-tune the controllable delay chain 10 after the coarse adjustment is completed, so that the output clock signal DQS and the external clock signal VCLK are phase-synchronized (that is, DQS and VCLK are aligned or the phase difference is within a negligible allowable range).

[0070] Optionally, the control circuit 12 can use a binary decreasing method of a coarse adjustment step size (e.g., 2C, 1C in sequence) to coarsely adjust the controllable delay chain 10, and use a binary decreasing method of a fine adjustment step size (e.g., 4F, 2F, 1F in sequence) to finely adjust the controllable delay chain 10. Wherein, 1C is the unit length of the coarse adjustment of the controllable delay chain 10 (also the minimum coarse adjustment step size), and 1F is the unit length of the fine adjustment of the controllable delay chain 10 (also the minimum fine adjustment step size). Exemplarily, 1C=16F.

[0071] Optionally, the control circuit 10 is used to determine the feedback clock signal DQS output by the a+1 delay circuit according to the detection results of at least the ath to a+2th phase detectors. fb The phase difference between the controllable delay chain 10 and the external clock signal VCLK is determined, thereby switching the step size and / or direction of coarse or fine adjustment of the controllable delay chain 10. For example, when the delay time td provided by the second to 2a+1 delay circuits is the unit length 1C of the coarse adjustment of the controllable delay chain, the control circuit 10 can, in the stage of coarse adjustment of the controllable delay chain 10, according to the detection results PD of the ath to a+2th phase detectors<a:a+2> Is it <001> or <011> To determine the feedback clock signal DQS output by the a+1 delay circuit fb Whether the phase difference with the external clock signal VCLK is less than 1C (i.e., whether to switch from the coarse adjustment to the fine adjustment), if so, the coarse adjustment is terminated and the fine adjustment is switched.<a:a+2> for <001> The following are also shown: (1) The a-th phase detector detects that the feedback clock signal fba-1=DQS fb -td's rising edge precedes VCLK's rising edge (e.g. Figure 8 As shown in the second rising edge of VCLK in the fb -td phase leads VCLK); (2) the a+1th phase detector detects the feedback clock signal fba=DQS output by the a+1th delay circuit fb The rising edge of DQS is ahead of the rising edge of VCLK (at this time, DQS fb Phase is ahead of VCLK); (3) the a+2th phase detector detects the feedback clock signal fba+1=DQS output by the a+2th delay circuit fb +td’s rising edge lags behind VCLK’s rising edge (at this time, VCLK phase relative to DQS fb +td ahead). PD<a:a+2> for <011> The following are also shown: (1) The a-th phase detector detects that the feedback clock signal fba-1=DQS fb -td's rising edge precedes VCLK's rising edge (at this time, VCLK phase relative to DQS fb -td lag); (2) the a+1th phase detector detects the feedback clock signal fba=DQS output by the a+1th delay circuit fb The rising edge of DQS lags behind the rising edge of VCLK (that is, the phase of VCLK relative to DQS fb (3) The a+2 phase detector detects the feedback clock signal fba+1=DQS output by the a+2 delay circuit. fb +td’s rising edge lags behind VCLK’s rising edge (i.e., VCLK phase relative to DQS fb +td ahead).

[0072] Further optionally, the control circuit 12 is further configured to:

[0073] (1) The delay of the controllable delay chain 10 is adjusted along a first direction (for example, to the right) using a first coarse adjustment step size (for example, 2C) until the feedback clock signal fba output by the a+1th delay circuit is equal to DQS fb The rising edge of VCLK reaches the right side of the falling edge of VCLK (i.e., the falling edge before the target rising edge), or until the feedback clock signal fba=DQS output by the a+1 delay circuit fb The rising edge of PD reaches the rising edge of VCLK (i.e., the target rising edge).<a:a+2> becomes <100> or PD<a-1:a+3> becomes <00001> ;

[0074] (2) Using a second coarse adjustment step size (e.g., 1C) smaller than the first coarse adjustment step size, the delay of the controllable delay chain 10 is adjusted in a suitable direction (e.g., rightward) in the first direction and the second direction until PD<a:a+2> becomes <001> , wherein the first direction and the second direction are opposite;

[0075] (3) Using a first fine adjustment step (e.g., 4F, 1C=16F), adjust the delay of the controllable delay chain 10 along a first direction (e.g., to the right) until PD<a:a+2> becomes <011> ;

[0076] (4) Using a second fine adjustment step (e.g., 2F) smaller than the first fine adjustment step, the delay of the controllable delay chain 10 is adjusted in a second direction (e.g., to the left) until PD<a:a+2> becomes <001> ;

[0077] (5) Using a third fine adjustment step (e.g., 1F) smaller than the second fine adjustment step, the delay of the controllable delay chain 10 is adjusted along a first direction (e.g., to the right) until PD<a:a+2> becomes <011> , thereby completing the locking of the delay phase-locked loop circuit.

[0078] Therefore, the delay phase-locked loop circuit of the present invention can generate 2a+1 feedback clock signals by using the replica clock buffer circuit and the second to 2a+1 delay circuits, and detect the phase relationship between these feedback clock signals and the external clock signal VCLK by using 2a+1 phase detectors, so that the control circuit can quickly determine the moment when the phase difference between the output clock signal DQS provided by the delay phase-locked loop circuit and VCLK is less than 1C according to the detection results of these phase detectors, thereby Figure 2Compared with the DLL circuit locking process of the present invention, at least the locking process from ② to ⑤ can be shortened, thereby reducing the locking steps, shortening the locking time, and accelerating the locking of the DLL circuit. It is worth noting that the "rising edge of VCLK" and "rising edge of VCLK" in each embodiment of the present invention refer to the rising edge of VCLK referenced when the coarse adjustment switches to the fine adjustment, such as Figure 8 or Fig.10 or Fig.12 The second rising edge of VCLK in FIG.

[0079] Further, when a≥2 and the delay time length td provided by the 2nd to 2a+1th delay circuits is the unit length 1C of the coarse adjustment of the controllable delay chain, the control circuit 10 can adjust the controllable delay chain 10 according to the detection results PD of at least the a-1th to a+3th phase detectors at the stage of coarse adjustment of the controllable delay chain 10 with 2C as the first coarse adjustment step.<a-1:a+3> Is it <00001> or <01111> To determine the feedback clock signal DQS output by the a+1 delay circuit fb Whether it reaches the rising edge of the external clock signal VCLK (DQS fb Is the phase difference with VCLK less than 2C), if so, switch from the first coarse adjustment step size 2C to the second coarse adjustment step size 1C, and use the second coarse adjustment step size 1C to coarsely adjust the controllable delay chain.

[0080] Among them, PD<a-1:a+3> for <00001> The following are also explained: (1) The a-1 phase detector detects that the feedback clock signal fba-2=DQS fb -2td's rising edge precedes VCLK's rising edge (that is, VCLK phase relative to DQS fb -2td lag); (2) the ath phase detector detects the feedback clock signal fba-1=DQS output by the ath delay circuit fb -td's rising edge precedes VCLK's rising edge (that is, VCLK phase relative to DQS fb -td lag); (3) the a+1th phase detector detects the feedback clock signal fba=DQS output by the a+1th delay circuit fb The rising edge of DQS is ahead of the rising edge of VCLK (that is, the phase of VCLK relative to DQS fb (4) the a+2 phase detector detects the feedback clock signal fba+1=DQS output by the a+2 delay circuit fb +td’s rising edge precedes VCLK’s rising edge (i.e., VCLK phase relative to DQS fb +td lag); (5) the a+3th phase detector detects the feedback clock signal fba+2=DQS output by the a+2th delay circuit fbThe rising edge of +2td lags behind the rising edge of VCLK (that is, the phase of VCLK relative to DQS fb +2td ahead).

[0081] PD<a-1:a+3> for <01111> The following are also explained: (1) The a-1 phase detector detects that the feedback clock signal fba-2=DQS fb -2td's rising edge precedes VCLK's rising edge (that is, VCLK phase relative to DQS fb -2td lag); (2) the ath phase detector detects the feedback clock signal fba-1=DQS output by the ath delay circuit fb -td’s rising edge lags behind VCLK’s rising edge (i.e., VCLK phase relative to DQS fb -td ahead); (3) the a+1th phase detector detects the feedback clock signal fba=DQS output by the a+1th delay circuit fb The rising edge of DQS lags behind the rising edge of VCLK (that is, the phase of VCLK relative to DQS fb (4) The a+2 phase detector detects the feedback clock signal fba+1=DQS output by the a+2 delay circuit. fb +td’s rising edge lags behind VCLK’s rising edge (i.e., VCLK phase relative to DQS fb +td ahead); (5) the a+3th phase detector detects the feedback clock signal fba+2=DQS output by the a+2th delay circuit fb The rising edge of +2td lags behind the rising edge of VCLK (that is, the phase of VCLK relative to DQS fb +2td ahead).

[0082] Therefore, the delay phase-locked loop circuit of the present invention can also quickly determine the moment when the phase difference between the output clock signal DQS provided by the delay phase-locked loop circuit and VCLK is less than 2C or 1C, thereby Figure 2 Compared with the DLL circuit locking process, the time from ② to ③ can be further shortened, thereby further speeding up the locking of the DLL circuit.

[0083] Optionally, each phase detector also has an enable terminal, and the control circuit 12 is also used to disable the outputs of the 1st to a-1th phase detectors and the a+3th to 2a+1th phase detectors by controlling the enable terminals of the 1st to a-1th phase detectors and the a+3th to 2a+1th phase detectors after switching to the second coarse adjustment step equal to 1C, and to maintain the outputs of the ath to a+2th phase detectors by controlling the enable terminals of the ath to a+2th phase detectors, so as to use the detection results of the ath to a+2th phase detectors to determine the moment when the phase difference between the feedback clock signal output by the a+1th delay circuit and the external clock signal is within 1C.

[0084] Optionally, each phase detector further has an enable terminal, and the control circuit controls the enable terminal of each phase detector to at least maintain the output of the a-1th to a+3th phase detectors, and uses a first coarse adjustment step equal to 2C to adjust the delay of the controllable delay chain to the right until PD<a-1:a+3> becomes <00001> At this time, the feedback clock signal DQS output by the a+3 delay circuit fb +2td reaches the right side of the rising edge of the external clock signal VCLK, and the feedback clock signal DQS output by the a+1 delay circuit fb The rising edge of the external clock signal VCLK reaches the left side of the rising edge (that is, DQS fb The rising edge of the external clock signal VCLK reaches the rising edge of the external clock signal VCLK), the control circuit in PD<a-1:a+3> becomes <00001> It is then further used to:

[0085] The delay of the controllable delay chain is adjusted along a first direction (eg, to the right) using a second coarse adjustment step size equal to 1C until PD<a-1:a+3> becomes <00011> ;

[0086] The delay of the controllable delay chain is adjusted along a first direction (eg, rightward) using a first fine adjustment step until PD<a-1:a+3> becomes <00111> ;

[0087] The delay of the controllable delay chain is adjusted along a second direction (eg, leftward) using a second fine adjustment step length that is smaller than the first fine adjustment step length until PD<a-1:a+3> becomes <00011> ;

[0088] The delay of the controllable delay chain is adjusted along a first direction (eg, rightward) using a third fine adjustment step length that is smaller than the second fine adjustment step length until PD<a-1:a+3> becomes <00111> , thereby completing the locking of the delay phase-locked loop circuit.

[0089] Optionally, the control circuit 12 includes a state machine (such as a state machine) coupled to the controllable delay chain 10 and each of the phase detectors. Figure 6 As shown in 12a), the state machine is used to enter different states according to the combination of the output results of each of the phase detectors, and the state machine is in different states, using different adjustment steps or adjustment directions to adjust the delay of the controllable delay chain 10.

[0090] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0091] First embodiment

[0092] Please refer to Figure 4 This embodiment provides a delay phase-locked loop circuit (where a=1), which includes a controllable delay chain (Delay Line) 10, a clock buffer circuit 11, a control circuit 12, a replica clock buffer circuit 13, a first phase detector 141, a second phase detector 142, a third phase detector 143, a first delay circuit 151, a second delay circuit 152, and a third delay circuit 153.

[0093] The input end of the first delay circuit 151 and the input end of the replica clock buffer circuit 13 are both coupled to the output end of the controllable delay chain 10, the output end of the first delay circuit 151 is coupled to the input end of the clock buffer circuit 11, the replica clock buffer circuit 13, the second delay circuit 152 and the third delay circuit 153 are cascaded, the first input end of the first phase detector 141, the first input end of the second phase detector 142, the first input end of the third phase detector 143 and the input end of the controllable delay chain 10 are all coupled to the external clock signal VCLK, the second input end of the first phase detector 141 is coupled to the output end of the replica clock buffer circuit 13, the second input end of the second phase detector 142 is coupled to the output end of the second delay circuit 152, and the second input end of the third phase detector 143 is coupled to the output end of the third delay circuit 153. The control circuit 12 is coupled to the output ends of the first phase detector 141, the second phase detector 142, and the third phase detector 143, and adjusts the phase difference between the external clock signal VCLK and the output clock signal DQS output by the clock buffer circuit 11 by increasing or decreasing the length of the controllable delay chain 10 (i.e., the delay size). When the phase difference between VCLK and DQS is 0 or the phase difference is within a negligible allowable range, it is considered that VCLK and DQS are phase synchronized, and the DLL circuit is locked.

[0094] Among them, the controllable delay chain 10, the clock buffer circuit 11, the control circuit 12, the replica clock buffer circuit 13, the first phase detector 141, the second phase detector 142, the third phase detector 143, the first delay circuit 151, the second delay circuit 152, and the third delay circuit 153 can be implemented by any suitable circuit design, and their functions can be referred to as described above and will not be repeated here.

[0095] In this embodiment, the first delay circuit 151 delays the clock signal CLKout output by the controllable delay chain 10 by td and then outputs it to the clock buffer circuit 11. The second delay circuit 152 and the third delay circuit 153 are replica circuits of the first delay circuit 151, and both generate a delay time of td. Therefore, the feedback clock signal fb0 output by the replica buffer circuit 13 is equal to DQS fb-td, the feedback clock signal fb1 output by the second delay circuit 152 = DQS fb , the feedback clock signal fb2 output by the third delay circuit 153 = DQS fb +td.

[0096] The first phase detector 141 detects the rising edge of fb0 and the rising edge of VCLK (i.e. Figure 8 If the VCLK phase lags, the detection result PD output by the first phase detector 141 will be <1> If VCLK phase leads, the detection result PD output by the first phase detector 141 is 0. <1> is 1, that is, the first phase detector 141 samples VCLK at the rising edge of fb0 and samples a low level output PD <1> is 0, sampled to high level output PD <1> is 1. Similarly, the second phase detector 142 detects the phase relationship between the rising edge of fb1 and the rising edge of VCLK. If the phase of VCLK lags behind, the detection result PD output by the second phase detector 142 is <2> If VCLK is ahead in phase, the detection result PD output by the second phase detector 142 is <2> The third phase detector 143 detects the phase relationship between the rising edge of fb2 and the rising edge of VCLK. If the VCLK phase lags, the detection result PD output by the third phase detector 143 is <3> If VCLK phase leads, the detection result PD output by the third phase detector 143 is 0. <3> The combination of the detection results output by the first phase detector 141, the second phase detector 142, and the third phase detector 143 is recorded as PD<1:3>. Figure 5A and Figure 5B , Figure 5A PD<1:3> is shown as <001> situation, Figure 5B PD<1:3> is shown as <011> Both cases represent DQS fb The phase difference between the rising edge and the VCLK rising edge is less than td.

[0097] Optionally, refer to Figure 6 In this embodiment, the control circuit 12 has a state machine 12a, and the controllable delay chain 10 has a coarse adjustment delay circuit 10a and a fine adjustment delay circuit 10b.

[0098] The state machine 12a can enter different states according to the flip (or change) of PD<1:3>, and these states include: Figure 8In the states corresponding to ① to ⑥, when the state machine 12a is in different states, the controllable delay chain 10 can be controlled to adjust the delay generated by it with different adjustment steps or adjustment directions. Therefore, during the locking process of the DLL circuit, the control circuit 12 can first coarsely adjust the controllable delay chain 10 through the different states of the state machine 12a, and then fine-tune the controllable delay chain 10 after the coarse adjustment is completed until the DLL circuit is locked, and in the coarse adjustment process and fine adjustment process, different adjustment steps and / or adjustment directions are switched according to the state changes of the state machine 12a.

[0099] The coarse adjustment delay circuit 10a is used to perform coarse adjustment of the delay with a larger adjustment step (i.e., coarse adjustment step, such as 2C, 1C) under the control of the control circuit 12, that is, to perform coarse phase adjustment on the rising edge of DQS with a larger adjustment step to adjust the rising edge of DQS until the phase difference between the rising edge of DQS and the rising edge of VCLK is within 1C.

[0100] The fine-tuning delay circuit 10b is used to perform delay fine-tuning with a smaller adjustment step (i.e., fine-tuning step, such as 4F, 2F, 1F) under the control of the control circuit 12, that is, to perform phase fine-tuning on the rising edge of DQS with a smaller adjustment step, so that the rising edge of DQS crosses the rising edge of VCLK to the left and right until the phase difference between VCLK and DQS is 0 or reaches an allowable range that can be ignored. At this time, it is considered that VCLK and DQS are phase-synchronized or aligned, and the DLL circuit is locked.

[0101] The state machine 12a, the coarse delay circuit 10a and the fine delay circuit 10b may be implemented by any suitable design.

[0102] As an example, see Figure 7The coarse adjustment delay circuit 10a in the controllable delay chain 10 includes a plurality of cascaded delay branches (delay branches 1, 2, ...), each of which is coupled to the state machine 12a of the control circuit 12, and is connected to the state machine 12a one by one to provide corresponding control signals D0, D1, ..., and the circuit structure of each delay branch can be the same, for example, each of which includes at least three NAND gates and an inverter. Specifically, the delay branch 1 includes at least three NAND gates NAND0_1~NAND0_3 and an inverter INV0, and the delay branch 2 includes at least three NAND gates NAND1_1~NAND1_3 and an inverter INV1. One input end of the NAND gate NAND0_1 is coupled to an input end of the NAND gate NAND0_2 and connected to VCLK, the other input end of the NAND gate NAND0_1 is coupled to the input end of the inverter INV0 and connected to the control signal D0, the output end of the NAND gate NAND0_1 is coupled to an input end of the NAND gate NAND1_1 and an input end of the NAND gate NAND1_2 of the delay branch 2, the other input end of the NAND gate NAND0_2 is coupled to the output end of the inverter INV0, the output end of the NAND gate NAND0_2 is coupled to an input end of the NAND gate NAND0_3, the other input end of the NAND gate NAND0_3 is coupled to the output end of the NAND gate NAND1_3 in the delay branch 2, and the output end of the NAND gate NAND0_3 outputs the clock signal CLKout delayed by the coarse adjustment delay unit 10a. The other input end of the NAND gate NAND1_1 is coupled to the input end of the inverter INV1 and connected to the control signal D1, the other input end of the NAND gate NAND1_2 is coupled to the output end of the inverter INV1, and the output end of the NAND gate NAND1_2 is coupled to an input end of the NAND gate NAND1_3. By analogy, the cascade of these delay branches in the coarse adjustment delay circuit 10a can be completed, thereby forming a delay line in the coarse adjustment delay circuit 10a. The control circuit 12 changes the control signals D0, D1, ... output by the state machine 12a according to PD<1:3>, and can gradually increase or decrease the number of delay branches connected to the coarse adjustment delay circuit 10a, that is, gradually increase or decrease the number of NAND gates connected to the delay line of the coarse adjustment delay circuit 10a, thereby gradually adjusting the delay of CLKout relative to VCLK, and finally completing the coarse adjustment. Among them, when the adjustment direction is to the right, each additional delay branch can increase the delay of CLKout relative to VCLK by 1C (that is, the unit length of coarse adjustment, which is also the minimum coarse adjustment step). When the adjustment direction is to the left, each reduction of a delay branch can reduce the delay of CLKout relative to VCLK by 1C. Therefore, 1C represents that the length of the delay line increases or decreases the delay of 2 NAND gates.For example, initially, the control signal D0 is 0, D1... are all 1, then the delay branch 1 is connected, and VCLK is output as CKout after only being delayed by two NAND gates, NAND0_2 and NAND0_3. CKout is only delayed by 1C relative to VCLK. If the rising edge of CLKout does not reach the specified position, the control signal D0 is further adjusted to 1, D1 is 0, and D2... are maintained to be 1, and the delay branch 2 is connected. VCLK is output as CLKout after being delayed by four NAND gates, NAND0_1, NAND1_2, NAND1_3 and NAND0_3. At this time, CLKout is delayed by 2C relative to VCLK..., and so on. Obviously, by gradually changing the control signal D0... output by the state machine 12a of the control circuit 12, the coarse adjustment step generated by the coarse adjustment delay circuit 10a can be changed, and the number of adjustment beats (or "the number of adjustment steps under the coarse adjustment step") can be controlled based on the coarse adjustment step until the rising edge of CLKout reaches the specified position of VCLK.

[0103] In other examples, the coarse adjustment delay circuit 10a can also be implemented by hanging load capacitors, that is, each delay branch is hung on a first-level load capacitor (providing a 1C delay) to participate in the delay, and the increased delay time of the entire coarse adjustment delay circuit 10a is the coarse adjustment step.

[0104] In this embodiment, the delay introduced by the first delay circuit to the third delay circuit is td=1C, which can ensure that fb0=DQSfb-td, fb1=DQSfb, and fb2=DQSfb+td have the same polarity and are in-phase clocks, which facilitates the first phase detector to the third phase detector to perform phase comparison. fb If the phase difference with VCLK is greater than 1C, the delay of the coarse adjustment delay circuit 10a is adjusted with a large coarse adjustment step size (e.g., 2C, 1C) to perform DQS fb Phase adjustment, if DQS fb If the phase difference with VCLK is less than 1C, it switches to a small fine-tuning step (such as 4F, 2F, 1F) to adjust the delay of the fine-tuning delay circuit 10b to perform DQS fb Phase adjustment, where 1C=16F.

[0105] Please combine Figure 4 and Figure 8 , assuming that the initial position of the DQS rising edge is Figure 8 At ① (i.e., the rising edge of DQS is located on the right side of the first rising edge of VCLK), the locking process of the delay locked loop (DLL) circuit of this embodiment includes the following steps:

[0106] (1) The control circuit 12 adjusts the delay of the controllable delay chain 10 to the right with a first coarse adjustment step of 2C until fb1 = DQS fb The rising edge reaches the right side of the falling edge of VCLK, such as Figure 8 As shown in ②, PD<1:3> is <100> , and it can be considered that DQS fb The rising edge initially reaches the vicinity of the second rising edge of VCLK, but DQS fb The phase difference between the rising edge and the second rising edge of VCLK is not necessarily less than 1C;

[0107] (2) The control circuit 12 changes to adjust the delay of the controllable delay chain 10 to the right with a second coarse adjustment step of 1C until PD<1:3> becomes <001> , at this time DQS fb The rising edge is still near the second rising edge of VCLK, and DQS fb The phase difference between the rising edge and the second rising edge of VCLK is adjusted to less than 1C, such as Figure 8 As shown in ③, the coarse adjustment is finished at this time;

[0108] (3) The control circuit 12 starts to adjust the delay of the controllable delay chain 10 to the right with the first fine adjustment step of 4F (i.e., starts fine adjustment) until PD<1:3> becomes <011> ,like Figure 8 As shown in ④;

[0109] (4) The control circuit 12 is changed to adjust the delay of the controllable delay chain 10 to the left with a second fine adjustment step of 2F until PD<1:3> becomes <001> ,like Figure 8 As shown in ⑤;

[0110] (5) The control circuit 12 is changed to adjust the delay of the controllable delay chain 10 to the right with the third fine adjustment step of 1F until PD<1:3> becomes <011> ,like Figure 8 As shown in ⑥, at this time, it is considered that the DQS finally output by the DLL circuit is synchronized with the VCLK phase, and the DLL circuit is now locked.

[0111] It should be understood that in other examples of this embodiment, in step (2), the step length may be adjusted with 1C as the step length until PD<1:3> becomes <011> , to make DQS fb The rising edge reaches the second rising edge of VCLK, at which time DQS is determined fbThe moment when the phase difference between the rising edge and the second rising edge of VCLK is less than 1C is later than the above example. However, in this example, the subsequent step (3) adjusts the delay of the controllable delay chain 10 to the left until PD<1:3> becomes <001> , step (4) adjusts the delay of the controllable delay chain 10 to the right until PD<1:3> becomes <011> , step (5) adjusts the delay of the controllable delay chain 10 to the left until PD<1:3> becomes <001> , and similar technical effects can be achieved.

[0112] Obviously, the DLL circuit locking process of this embodiment can use PD<1:3> to become <001> or <011> At the moment, quickly and in advance determine the DQS fb The rising edge and VCLK rising edge (i.e. Figure 8 The moment when the phase difference between the second rising edge of VCLK in the DLL circuit is less than 1C (this moment is also regarded as the moment when the phase difference between DQS and VCLK provided by the DLL circuit is less than 1C), the coarse adjustment can be terminated directly and fine adjustment can be performed with a step size of 4F. Figure 2 The DLL circuit locking process shown omits the step of "adjusting to the left by 1C" (this step is used to determine that the phase difference between the rising edge of DQSfb and the rising edge of VCLK is less than 1C), thereby shortening the locking time of the DLL circuit and accelerating the locking of the DLL circuit.

[0113] Second embodiment

[0114] Please combine Figure 1 and Figure 2 In the existing DLL circuit design, when the DLL circuit starts to lock, regardless of DQS fb The phase difference between the rising edge and VCLK is generally adjusted by the state machine (not shown) in the control circuit 12 to adjust the delay of the controllable delay chain 10 to ensure that DQS fb The rising edge is basically aligned with the next rising edge of VCLK, and the delay of the controllable delay chain 10 is continued to make DQS fb When the rising edge is aligned with the rising edge of VCLK, the delay that needs to be added will be less than 1 Tck (i.e., one cycle of VCLK).

[0115] Based on this, please refer to Fig. 9The present embodiment provides a delay phase-locked loop circuit (where a=2), which includes a controllable delay chain (Delay Line) 10, a clock buffer circuit 11, a control circuit 12, a replica clock buffer circuit 13, a first phase detector 141, a second phase detector 142, a third phase detector 143, a fourth phase detector 144, a fifth phase detector 145, a first delay circuit 151, a second delay circuit 152, a third delay circuit 153, a fourth delay circuit 154, and a fifth delay circuit 155.

[0116] Among them, the connection relationship among the controllable delay chain 10, the clock buffer circuit 11, the control circuit 12, the replica clock buffer circuit 13, the first phase detector 141, the second phase detector 142, the third phase detector 143, the first delay circuit 151, the second delay circuit 152, and the third delay circuit 153 is the same as that in the first embodiment and will not be repeated here.

[0117] The difference between this embodiment and the first embodiment is that the delay provided by the first delay circuit 151 is 2*td (which can be recorded as 2td), the fourth delay circuit 154, the fifth delay circuit 155 and the fourth phase detector 144, the fifth phase detector 145 are added, and the fourth delay circuit 154 and the fifth delay circuit 155 are cascaded on the rear stage of the third delay circuit 153, the first input end of the fourth phase detector 144 and the first input end of the fifth phase detector 145 are both connected to VCLK, the second input end of the fourth phase detector 144 is coupled to the output end of the fourth delay circuit 154, and the second input end of the fifth phase detector 145 is coupled to the output end of the fifth delay circuit 155. The feedback clock signal fb0 output by the replica clock buffer circuit 13 is equal to DQS fb -2td, the feedback clock signal fb1 output by the second delay circuit 152 = DQS fb -td, the feedback clock signal fb2 output by the third delay circuit 153 = DQS fb , the feedback clock signal fb3 output by the fourth delay circuit 154 = DQS fb +td, the feedback clock signal fb4 output by the fifth delay circuit 155 = DQS fb +2td.

[0118] The first phase detector 141 detects the rising edge of fb0 and the rising edge of VCLK (i.e. Fig.10If the VCLK phase lags, the detection result PD output by the first phase detector 141 will be <1> If VCLK phase leads, the detection result PD output by the first phase detector 141 is 0. <1> is 1, that is, the first phase detector 141 samples VCLK at the rising edge of fb0 and samples a low level output PD <1> is 0, sampled to high level output PD <1> is 1. Similarly, the second phase detector 142 detects the phase relationship between the rising edge of fb1 and the rising edge of VCLK. If the phase of VCLK lags behind, the detection result PD output by the second phase detector 142 is <2> If VCLK is ahead in phase, the detection result PD output by the second phase detector 142 is <2> The third phase detector 143 detects the phase relationship between the rising edge of fb2 and the rising edge of VCLK. If the VCLK phase lags, the detection result PD output by the third phase detector 143 is <3> If VCLK phase leads, the detection result PD output by the third phase detector 143 is 0. <3> The fourth phase detector 144 detects the phase relationship between the rising edge of fb3 and the rising edge of VCLK. If the VCLK phase lags, the detection result PD output by the fourth phase detector 144 is <4> If VCLK phase leads, the detection result PD output by the fourth phase detector 144 is 0. <4> The fifth phase detector 145 detects the phase relationship between the rising edge of fb4 and the rising edge of VCLK. If the VCLK phase lags, the detection result PD output by the fifth phase detector 145 is <5> If VCLK phase leads, the detection result PD output by the fifth phase detector 145 is 0. <5> is 1. The combination of detection results output by the first phase detector 141 , the second phase detector 142 , the third phase detector 143 , the fourth phase detector 144 , and the fifth phase detector 145 is recorded as PD<1:5>.

[0119] Please combine Fig. 9 and Fig.10 , assuming that the clock period of VCLK is Tck, the minimum coarse adjustment step of the controllable delay chain 10 is 1C, assuming that 0.5Tck>4C, and the initial position of the DQS rising edge is Fig.10 At ① in FIG. 1 (i.e., the right side of the first rising edge of VCLK), the locking process of the delay locked loop (DLL) circuit of this embodiment includes the following steps:

[0120] (1) The control circuit 12 adjusts the delay of the controllable delay chain 10 to the right with a first coarse adjustment step of 2C until PD<1:5> becomes <00001> , at this time DQS fb The rising edge reaches near the second rising edge of VCLK, and represents fb2 = DQS fbThe phase difference between the rising edge and the second rising edge of VCLK (i.e., the target rising edge) is less than 2C (this moment is also regarded as the moment when the phase difference between DQS and VCLK provided by the DLL circuit is less than 2C). Fig.10 As shown in ③, specifically, the rising edge of fb4 reaches the right side of the second rising edge of VCLK (i.e., the target rising edge), and the rising edges of fb0 to fb3 are still on the left side of the second rising edge of VCLK. This process will experience fb2 = DQS fb The rising edge reaches the state to the right of the falling edge of VCLK, such as Fig.10 As shown in ②, compared with Figure 2 Unlike the first embodiment in which the process from ② to ③ is completed with 1C, in this embodiment, the process from ② to ③ is completed with 2C, so the process from ② to ③ is optimized and can be adjusted to the target rising edge (i.e., the second rising edge of VCLK) relatively faster;

[0121] (2) The control circuit 12 changes to adjust the delay of the controllable delay chain 10 to the right with a second coarse adjustment step of 1C until PD<1:5> becomes <00011> , which means fb2 = DQS fb The phase difference between the rising edge and the second rising edge of VCLK is less than 1C. Fig.10 As shown in ③', the coarse adjustment is ended at this time;

[0122] (3) The control circuit 12 starts to adjust the delay of the controllable delay chain 10 to the right with a first fine adjustment step of 4F (i.e., starts fine adjustment) until PD<1:5> becomes <00111> ,like Fig.10 As shown in ④;

[0123] (4) The control circuit 12 changes to adjust the delay of the controllable delay chain 10 to the left with a second fine adjustment step of 2F until PD<1:5> becomes <00011> ,like Fig.10 As shown in ⑤;

[0124] (5) The control circuit 12 changes to adjust the delay of the controllable delay chain 10 to the right with the third fine adjustment step of 1F until PD<1:5> becomes <00111> ,like Fig.10 As shown in ⑥ in the figure, the DLL circuit is now locked.

[0125] It should be understood that in other examples of this embodiment, in step (1), the step size may be adjusted with 2C as the step size until PD<1:5> becomes <01111> , to make DQS fb The rising edge reaches the second rising edge of VCLK, which determines DQS fbWhen the phase difference between the rising edge of fb2 and the second rising edge of VCLK is less than 2C, the PD<1:5> can be adjusted in steps of 1C in step (3) until PD<1:5> becomes <00111> , to determine DQS fb The phase difference between the rising edge and the second rising edge of VCLK is less than 1C. In this example, DQS is determined fb Relative to the moment when the phase difference with VCLK is less than 2C and 1C Fig.10 The example shown is from later times.

[0126] The DLL circuit locking process of this embodiment can use PD<1:5> to become <00001> or <01111> At the moment, quickly and in advance determine the DQS fb The rising edge and VCLK rising edge (i.e. Fig.10 The time from ② to ③ can be shortened, and PD<1:5> can be further used to change to <00011> or <00111> At the moment, quickly and in advance determine the DQS fb The rising edge and VCLK rising edge (i.e. Fig.10 When the phase difference of the second rising edge of VCLK in the control circuit is less than 1C, the coarse adjustment is ended and the fine adjustment is switched. Compared with the first embodiment, the present embodiment can further shorten the locking time of the DLL circuit and accelerate the locking of the DLL circuit.

[0127] Third embodiment

[0128] Please refer to Fig.12 This embodiment provides a delay phase-locked loop circuit (where a=2), which includes a controllable delay chain (Delay Line) 10, a clock buffer circuit 11, a control circuit 12, a replica clock buffer circuit 13, a first phase detector 141, a second phase detector 142, a third phase detector 143, a fourth phase detector 144, a fifth phase detector 145, a first delay circuit 151, a second delay circuit 152, a third delay circuit 153, a fourth delay circuit 154, and a fifth delay circuit 155. Their connection relationship is the same as that of the second embodiment, and will not be repeated here.

[0129] The difference between this embodiment and the second embodiment is that the first phase detector 141, the second phase detector 142, the third phase detector 143, the fourth phase detector 144, and the fifth phase detector 145 all have enable terminals, and the control circuit 12 can control the enable terminals of each phase detector as needed to enable or disable these phase detectors to save power consumption.

[0130] As an example, combine Fig.11 and Fig.12, assuming that the initial position of the DQS rising edge is Fig.12 At ① in FIG. 1 (i.e., the right side of the first rising edge of VCLK), the locking process of the delay locked loop (DLL) circuit of this embodiment includes the following steps:

[0131] (1) The control circuit 12 adjusts the delay of the controllable delay chain 10 to the right with a second coarse adjustment step of 2C until PD<1:5> becomes <00001> , at this time DQS fb The rising edge reaches near the second rising edge of VCLK, and represents fb2 = DQS fb The phase difference between the rising edge and the second rising edge of VCLK is less than 2C. Fig.12 As shown in ③, specifically, the rising edge of fb4 reaches the right side of the second rising edge of VCLK (i.e., the target rising edge), and the rising edges of fb0 to fb3 are still on the left side of the second rising edge of VCLK. This process will experience fb2 = DQS fb The rising edge reaches the state to the right of the falling edge of VCLK, such as Fig.12 As shown in ②, compared with Figure 2 Unlike the first embodiment in which the process from ② to ③ is completed with 1C, in this embodiment, the process from ② to ③ is completed with 2C, so the process from ② to ③ is optimized and can be adjusted to the target rising edge (i.e., the second rising edge of VCLK) relatively faster;

[0132] (2) The control circuit 12 changes to adjust the delay of the controllable delay chain 10 to the right with a second coarse adjustment step of 1C until PD<2:4> becomes <001> , representing DQS fb The phase difference between the rising edge and the second rising edge of VCLK is less than 1C. Fig.12 As shown in ③', the coarse adjustment is ended at this time;

[0133] (3) The control circuit 12 starts to adjust the delay of the controllable delay chain 10 to the right with a first fine adjustment step of 4F (i.e., starts fine adjustment) until PD<2:4> becomes <011> ,like Fig.12 As shown in ④;

[0134] (4) The control circuit 12 changes to adjust the delay of the controllable delay chain 10 to the left with a second fine adjustment step of 2F until PD<2:4> becomes <001> ,like Fig.12 As shown in ⑤;

[0135] (5) The control circuit 12 changes to adjust the delay of the controllable delay chain 10 to the right with the third fine adjustment step of 1F until PD<2:4> becomes <011> ,like Fig.12 As shown in ⑥ in the figure, the DLL circuit is now locked.

[0136] It should be understood that in other examples of this embodiment, in step (1), the step size may be adjusted with 2C as the step size until PD<1:5> becomes <01111> , to determine that the phase difference between the rising edge of DQSfb and the second rising edge of VCLK is less than 2C, in step (3), the step size of 1C can be adjusted until PD<2:4> becomes <011> , to determine that the phase difference between the rising edge of DQSfb and the second rising edge of VCLK is less than 1C, the adjustment direction of the subsequent steps (4) to (6) and the reference datum PD<2:4> are adaptively changed.

[0137] The DLL circuit locking process of this embodiment can use PD<1:5> to become <00001> or <01111> At the moment, quickly and in advance determine the DQSfb rising edge and VCLK rising edge (i.e. Fig.10 The moment when the phase difference of the second rising edge of VCLK in the input is less than 2C, and after this moment, the first phase detector and the fifth phase detector are disabled, and PD<2:4> is further used to become <001> or <011> At the moment, quickly and in advance determine the DQSfb rising edge and VCLK rising edge (i.e. Fig.12 When the phase difference of the second rising edge of VCLK in the embodiment is less than 1C, the coarse adjustment is ended and the fine adjustment is switched. Compared with the second embodiment, this embodiment can save power consumption.

[0138] Fourth embodiment

[0139] Based on the same invention concept, please refer to Fig.13 An embodiment of the present invention further provides a system device, comprising a delay phase-locked loop (DLL) circuit as described in any embodiment of the present invention, wherein the delay phase-locked loop circuit receives an external clock signal VCLK from outside the system device and outputs a corresponding output clock signal DQS.

[0140] As an example, the system device is a memory chip such as DRAM, and the output clock signal DQS is a data selection pulse signal of the memory chip. The delay phase-locked loop circuit is locked after adjusting DQS to be in phase synchronization with the external clock signal VCLK.

[0141] The memory chip further has an internal circuit (not labeled) having a storage array for storing data. The memory chip uses DQS to collect corresponding data DQ in the storage array to implement a data read operation.

[0142] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A delay phase-locked loop circuit, comprising a controllable delay chain, a clock buffer circuit, a replica clock buffer circuit and a control circuit, characterized in that: It also includes the first to the second a+1 delay circuits and the first to the second a+1 phase detectors, a≥1 and is an integer, wherein: The input end of the first delay circuit and the input end of the replica clock buffer circuit are both coupled to the output end of the controllable delay chain, the output end of the first delay circuit is coupled to the input end of the clock buffer circuit, the clock buffer circuit is used to output the clock signal output by the first delay circuit as a corresponding output clock signal, the second to 2a+1 delay circuits are cascaded in sequence, and the input end of the second delay circuit is coupled to the output end of the replica clock buffer circuit; The first input terminals of the 1st to 2a+1st phase detectors and the input terminal of the controllable delay chain are coupled to the external clock signal, the second input terminal of the 1st phase detector is coupled to the output terminal of the replica clock buffer circuit, the second input terminals of the 2nd to 2a+1st phase detectors are coupled to the output terminals of the 2nd to 2a+1st delay circuits one by one, the output terminals of the 1st to 2a+1st phase detectors are coupled to the corresponding input terminals of the control circuit, and the output terminal of the control circuit is coupled to the control terminal of the controllable delay chain; The first delay circuit is used to delay the clock signal output by the controllable delay chain for a specific time and then output it to the clock buffer circuit; The second to 2a+1 delay circuits are used to delay the feedback clock signal output by the replica clock buffer circuit by a time corresponding to the specific time length, so as to output a corresponding feedback clock signal; The first to second a+1 phase detectors are used to detect the phase relationship between the feedback clock signals output by the replica clock buffer circuit and the second to second a+1 delay circuits and the external clock signal respectively; The control circuit is used to first perform coarse adjustment on the controllable delay chain according to the detection results of the 1st to 2a+1th phase detectors, and determine whether to switch from the coarse adjustment to the fine adjustment according to the detection results, and then perform the fine adjustment on the controllable delay chain after the coarse adjustment is completed, so as to synchronize the phases of the output clock signal and the external clock signal.

2. The delay phase-locked loop circuit according to claim 1, characterized in that: The control circuit performs coarse adjustment on the controllable delay chain by using a coarse adjustment step size binary decreasing method, and performs fine adjustment on the controllable delay chain by using a fine adjustment step size binary decreasing method.

3. The delay phase-locked loop circuit according to claim 1, characterized in that: The control circuit is used to determine the phase difference between the feedback clock signal output by the a+1th delay circuit and the external clock signal based on the detection results of at least the ath to a+2th phase detectors, and then decide whether to switch from the coarse adjustment to the fine adjustment, and / or switch the step size and / or direction of the coarse or fine adjustment of the controllable delay chain.

4. The delay phase-locked loop circuit as claimed in claim 3, characterized in that: The delay time lengths provided by the 2nd to 2a+1th delay circuits are the same, and the specific time length is a times of the delay time length.

5. The delay phase-locked loop circuit as claimed in claim 4, characterized in that: The delay duration is the unit length of the controllable delay chain for the coarse adjustment.

6. The delay phase-locked loop circuit as claimed in claim 5, characterized in that: The control circuit is further used to determine whether the phase difference between the feedback clock signal output by the a+1th delay circuit and the external clock signal is less than the unit length of the coarse adjustment according to the detection results of the ath to a+2th phase detectors during the coarse adjustment of the controllable delay chain, so as to determine whether to switch from the coarse adjustment to the fine adjustment; Among them, when the a-th phase detector detects that the rising edge of the feedback clock signal it receives is ahead of the rising edge of the external clock signal, and the a+1-th phase detector detects that the rising edge of the feedback clock signal output by the a+1-th delay circuit is ahead of or lags behind the rising edge of the external clock signal, and the a+2-th phase detector detects that the rising edge of the feedback clock signal output by the a+2-th delay circuit lags behind the rising edge of the external clock signal, it is determined that the phase difference between the feedback clock signal output by the a+1-th delay circuit and the external clock signal is less than the unit length of the coarse adjustment.

7. The delay phase-locked loop circuit according to claim 5, characterized in that: Each of the phase detectors is used to detect the phase relationship between the rising edge of the feedback clock signal it receives and the rising edge of the external clock signal, and outputs 0 when it detects that the rising edge of the feedback clock signal it receives is ahead of the rising edge of the external clock signal, and outputs 1 when it detects that the rising edge of the feedback clock signal it receives is behind the rising edge of the external clock signal, wherein the detection results of the ath to a+2th phase detectors are recorded as PD<a:a+2> , the control circuit is further used to perform the following steps to switch the step size and / or direction of coarse or fine adjustment of the controllable delay chain: Using a first coarse adjustment step size to adjust the delay of the controllable delay chain along a first direction until the rising edge of the feedback clock signal output by the a+1th delay circuit reaches the right side of the falling edge of the external clock signal or reaches the vicinity of the rising edge of the external clock signal; The delay of the controllable delay chain is adjusted along a suitable direction of the first direction and the second direction using a second coarse adjustment step length which is smaller than the first coarse adjustment step length until PD<a:a+2> becomes <001> , wherein the first direction is opposite to the second direction; The delay of the controllable delay chain is adjusted along the first direction using a first fine adjustment step until PD<a:a+2> becomes <011> ; The delay of the controllable delay chain is adjusted along the second direction using a second fine adjustment step length which is smaller than the first fine adjustment step length until PD<a:a+2> becomes <001> ; The delay of the controllable delay chain is adjusted along the first direction using a third fine adjustment step length which is smaller than the second fine adjustment step length until PD<a:a+2> becomes <011> , thereby completing the locking of the delay phase-locked loop circuit.

8. The delay phase-locked loop circuit according to claim 7, characterized in that: a≥2, the detection results of the a-1th to a+3th phase detectors are recorded as PD<a-1:a+3> The control circuit is further configured to adjust the delay of the controllable delay chain along the first direction using a first coarse adjustment step size equal to 2C until PD<a-1:a+3> becomes <00001> , so that the rising edge of the feedback clock signal output by the a+3th delay circuit reaches the right side of the rising edge of the external clock signal, and the rising edge of the feedback clock signal output by the a+1th delay circuit reaches the left side of the rising edge of the external clock signal, where 1C is the unit length of the coarse adjustment of the controllable delay chain.

9. The delay phase-locked loop circuit according to claim 8, characterized in that: Each of the phase detectors also has an enable terminal, and the control circuit is also used to<a-1:a+3> becomes <00001> Afterwards, the outputs of the 1st to a-1th phase detectors and the a+3th to 2a+1th phase detectors are disabled by controlling the enable terminals of the 1st to a-1th phase detectors and the a+3th to 2a+1th phase detectors, and the outputs of the ath to a+2th phase detectors are maintained by controlling the enable terminals of the ath to a+2th phase detectors, so as to switch the step size and / or direction of coarse or fine adjustment of the controllable delay chain using the detection results of the ath to a+2th phase detectors, until the delay phase-locked loop circuit is locked; Alternatively, the control circuit is further configured to:<a-1:a+3> becomes <00001> Afterwards, it is further used for: The delay of the controllable delay chain is adjusted along the first direction using a second coarse adjustment step size equal to 1C until PD<a-1:a+3> becomes <00011> ; The delay of the controllable delay chain is adjusted along the first direction using a first fine adjustment step until PD<a-1:a+3> becomes <00111> ; The delay of the controllable delay chain is adjusted along the second direction using a second fine adjustment step length which is smaller than the first fine adjustment step length until PD<a-1:a+3> becomes <00011> ; The delay of the controllable delay chain is adjusted along the first direction using a third fine adjustment step length which is smaller than the second fine adjustment step length until PD<a-1:a+3> becomes <00111> , thereby completing the locking of the delay phase-locked loop circuit.

10. The delay phase-locked loop circuit according to claim 8, characterized in that: The unit length of the controllable delay chain fine adjustment is 1F, the first fine adjustment step is 4F, the second fine adjustment step is 2F, and the third fine adjustment step is 1F.

11. The delay phase-locked loop circuit according to any one of claims 7 to 10, characterized in that: The control circuit includes a state machine coupled to the controllable delay chain and each of the phase detectors, wherein the state machine is used to enter different states according to a combination of output results of each of the phase detectors, and when the state machine is in different states, different adjustment steps or adjustment directions are used to adjust the delay of the controllable delay chain.

12. A memory chip, characterized in that: It comprises a delay phase-locked loop circuit as claimed in any one of claims 1 to 11.

13. The memory chip according to claim 12, wherein: The output clock signal output by the delay phase-locked loop circuit is the data selection pulse signal of the memory chip. The delay phase-locked loop circuit is used to adjust the phase difference between the external clock signal input to the memory chip and the data selection pulse signal until the external clock signal and the data selection pulse signal are phase-synchronized and locked.

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