Clock measurement circuit and correction method and system

Abstract

The invention relates to clock frequency calibration, and discloses a clock measuring circuit and a calibration method and system, and the method comprises the steps: employing a clock frequency detection circuit to measure and calculate the clock frequency of an internal to-be-calibrated crystal oscillator; entering a calibration state, performing cyclic calibration, and adjusting a calibration register; when the frequency value is calibrated to be within a set error range, clock calibration is completed; and a calibration stability test is carried out, and the calibration process is optimized. According to the clock measurement circuit and the correction method and system provided by the invention, high-precision and automatic calibration of the clock frequency and excellent environmental adaptability can be realized. The clock frequency of the crystal oscillator can be monitored and calibrated in real time through the built-in clock frequency detection circuit under the condition that an external reference clock is not needed, and the real-time performance and the automation level of calibration are remarkably improved. And a cyclic calibration mechanism and a stability test are introduced in the calibration process, so that the stability and reliability of a calibration result in long-term operation are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of clock frequency calibration, and in particular to a clock measurement circuit and a correction method and system. Background Art

[0002] As electronic devices develop towards high precision and high reliability, the accuracy and stability of clock signals are increasingly required. As the most basic reference signal in electronic systems, the accuracy of clock signals directly affects the performance of the entire system. In practical applications, due to factors such as temperature changes, power supply fluctuations, differences in manufacturing processes, and crystal aging, the crystal oscillator clock frequency will deviate, which in turn affects the accurate operation of the system. Traditional clock calibration methods usually rely on external precision equipment to perform manually, which is not only complicated to operate, but also unable to respond to real-time changes in the internal crystal oscillator in real time, making it difficult for the clock signal to maintain high accuracy during long-term operation.

[0003] In addition, in the existing technology, clock calibration mostly relies on offline measurement and manual intervention, lacking flexibility and real-time performance. In addition, traditional calibration technology fails to fully consider the impact of environmental factors on clock frequency, making the calibration process unable to adapt to complex application environments. Therefore, there is an urgent need for a method that can automatically and real-timely complete clock frequency calibration to meet the high requirements of modern electronic equipment for clock accuracy. Summary of the invention

[0004] In view of the above-mentioned problems, the present invention is proposed.

[0005] Therefore, the technical problem solved by the present invention is: the automation and real-time problem of the clock calibration process, breaking the limitation of the traditional calibration method that relies on external equipment and manual operation. At the same time, it solves the problem of ignoring the impact of environmental changes in traditional technology. The existing technology uses the dichotomy method to test one by one through the machine, which is not efficient and also heavily dependent on the reliability of the machine itself.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions: a clock measurement circuit and a correction method, comprising: using a clock frequency detection circuit to measure and calculate the internal crystal oscillator clock frequency to be calibrated.

[0007] Enter the calibration state, perform cyclic calibration, and adjust the calibration register.

[0008] When the frequency value is calibrated to within the set error range, the clock calibration is completed.

[0009] Perform calibration stability tests to optimize the calibration process.

[0010] As a preferred solution of the clock measurement circuit and correction method of the present invention, the method of measuring and calculating the internal crystal oscillator clock frequency to be calibrated by using the clock frequency detection circuit includes using an external high-precision clock input as a reference source and using the internal crystal oscillator clock to be calibrated as the clock to be measured. The clock to be measured first performs edge detection on the external low-frequency high-precision clock input, and uses a synchronous method to verify the rising edge and falling edge of the external input clock source.

[0011] When the first rising edge is detected, the counter is initialized and ready to start counting. When the second rising edge is detected, the counter is reinitialized and the count value of the current real-time timer is loaded into the count buffer. The count value in the count buffer is the data obtained in this measurement. The clock frequency of the current internal crystal oscillator can be inferred from the count value in the count buffer, which is expressed as:

[0012] Ftrim=Fref * (CNT+1)

[0013] Among them, Ftrim represents the current internal high-frequency crystal frequency, Fref represents the external high-precision low-frequency clock frequency, and CNT represents the count value in the count buffer.

[0014] As a preferred solution of the clock measurement circuit and correction method described in the present invention, wherein: the entry into the calibration state includes the calibration initial state S0, the calibration start state S1, the calibration result frequency overflow state S2, the calibration result frequency underflow state S3, and the calibration result frequency compliance state S4.

[0015] The calibration initial state S0 indicates that the calibration is being prepared.

[0016] The calibration start state S1 indicates the start of calibration.

[0017] The calibration result frequency overflow S2 indicates that the last calibration result overflowed and the frequency is reduced in this calibration.

[0018] The calibration result frequency underflow S3 indicates that the last calibration result underflowed, and the frequency is increased in this calibration.

[0019] If the calibration result frequency meets S4, the calibration is completed.

[0020] As a preferred solution of the clock measurement circuit and correction method described in the present invention, the cyclic calibration of the frequency includes entering an initialization state after the program is initialized, and entering a calibration start state after the program executes frequency measurement.

[0021] After the frequency measurement is completed, calibration is performed according to the detected frequency. When the frequency detection value is greater than the theoretical value, that is, when the count value in the count buffer is greater than the theoretically calculated value, the calibration transfer state transfers to S2, and a new round of calibration begins.

[0022] When the frequency detection value is less than the theoretical value, that is, when the count value in the count buffer is less than the theoretically calculated value, the calibration transfer state transfers to S3, and a new round of calibration begins.

[0023] When the frequency detection value is equal to the theoretical value, that is, when the count value in the count buffer is equal to the theoretically calculated value, the calibration transfer state transfers to S4, and calibration stops.

[0024] As a preferred solution of the clock measurement circuit and calibration method described in the present invention, wherein: the adjustment calibration register includes, after the calibration state is converted, the calibration register adds or subtracts according to the difference between the theoretical value and the calibration state. The specific operations are as follows:

[0025] When the calibration state is in the calibration frequency overflow S2, if BUFCNT < Z + M, the value of the calibration register is -1. If BUFCNT ≥ Z + M, the value of the calibration register is -5.

[0026] When the calibration state is in the calibration frequency underflow S3, if BUFCNT > Z - M, the value of the calibration register is +1. If BUFCNT ≤ Z - M, the value of the calibration register is +5.

[0027] When the calibration state is in the calibration result frequency compliance S4, if Z + M > BUFCNT > Z + L, the value of the calibration register is -1. If BUFCNT ≥ Z + M, the value of the calibration register is -5. If Z - M < BUFCNT < Z - L, the value of the calibration register is +1. If BUFCNT < Z - M, the value of the calibration register is +5. If Z - L ≤ BUFCNT ≤ Z + L, the calibration register has no operation.

[0028] Among them, BUFCNT represents the count value measured by the current frequency measurement module, and Z represents the theoretical value calculated according to the relationship between the frequency input reference clock frequency and the measurement clock frequency, expressed as:

[0029]

[0030] M represents the maximum deviation value within the fine-tuning range, expressed as:

[0031] M = α * Z

[0032] Among them, α represents the precision requirement range of the minimum adjustment range.

[0033] L represents the allowable error value, expressed as:

[0034] K=β * Z

[0035] Wherein, β represents the accuracy requirement range of the clock to be measured.

[0036] As a preferred scheme of the clock measurement circuit and correction method described in the present invention, wherein: when the frequency value is calibrated to within the set error range, the clock calibration is completed, including, when the calibration program performs frequency detection, comparing the current measured count value with the theoretical count value, and finding that the current clock frequency error is large and the current clock frequency is much greater than the ideal value, the calibration program performs large-grained adjustments to the calibration register, and waits for the clock adjustment to stabilize before starting the next round of clock frequency measurement.

[0037] When the deviation between the measured count value and the theoretical count value has been significantly reduced, the calibration procedure performs small-grain adjustments to the calibration register.

[0038] When the current measured count value and the theoretical count value are within the set error range, a clock calibration is completed.

[0039] The set error range is divided into an upper error limit and a lower error limit, and the upper error limit is expressed as:

[0040]

[0041] The lower limit of error is expressed as:

[0042]

[0043] Where Φ represents the internal adjustment coefficient of the clock, n represents the number of internal adjustment factors of the clock, and Ω i Indicates the i-th internal calibration factor, which is related to the crystal aging. ΔT i It represents the time variable related to the i-th adjustment factor, reflecting the time difference from the start of calibration to the current time, and is used to simulate the influence of crystal aging. Λ represents the external environment adjustment coefficient, m represents the number of external environment influencing factors, represents the frequency adjustment amount related to the jth external environmental influencing factor, indicating how the external environmental changes affect the crystal oscillator frequency. Ξ represents the adjustment parameter, Θ j Represents the jth external environmental influencing factor, including temperature, humidity and air pressure.

[0044] When the frequency value is within the upper error limit and the lower error limit, and the calibration register has no operation, a clock calibration is completed.

[0045] As a preferred solution of the clock measurement circuit and correction method of the present invention, the calibration stability test and the optimization calibration process include combining the deviation between the measured frequency and the target frequency and the influence of environmental factors on the clock frequency. The stability evaluation formula is expressed as:

[0046]

[0047] Among them, S represents the stability evaluation result, N represents the number of measurements, and F meas,i represents the frequency value obtained by the i-th measurement, F target represents the target frequency value, σ temp represents the standard deviation of the temperature during the test, σ volt represents the standard deviation of the voltage during the test, τ represents the temperature influence adjustment coefficient, v represents the voltage influence adjustment coefficient, and ρ represents the overall influence coefficient of adjusting all environmental influence factors.

[0048] If the stability evaluation result reaches above 0.85, the clock calibration result is considered stable, otherwise the calibration process needs to be optimized.

[0049] The optimization calibration process includes adjusting the calibration register process and enhancing environmental adaptability.

[0050] The process of adjusting the calibration register is as follows:

[0051] When the measured value of the clock frequency deviates greatly from the target value, a more aggressive calibration strategy is adopted to increase the step size and the adjustment amount of the calibration register.

[0052] When the frequency measurement value approaches the target value, a more subtle calibration strategy is adopted to reduce the step size and the adjustment amount of the calibration register.

[0053] The specific process of enhancing environmental adaptability is as follows:

[0054] Conduct extensive testing of clock frequencies under different environmental conditions, establish a performance baseline database, record the calibration parameter settings expected under various environmental conditions, retrieve the most suitable calibration parameters from the performance baseline database according to the current environmental conditions, and apply these parameters.

[0055] A temperature compensated crystal oscillator is selected, which has a built-in temperature compensation mechanism to automatically adjust the frequency to offset the impact of temperature changes.

[0056] Environmental sensors are integrated into the system to monitor environmental conditions in real time and automatically adjust the calibration strategy according to changes in environmental conditions to adapt to environmental changes.

[0057] A clock measurement circuit and correction system, characterized in that: it includes:

[0058] The frequency detection module uses the clock frequency detection circuit to measure and calculate the internal crystal oscillator clock frequency to be calibrated.

[0059] The calibration module enters the calibration state, performs cyclic calibration on the frequency, and adjusts the calibration register.

[0060] Output frequency module, when the frequency value is calibrated to within the set error range, the clock calibration is completed.

[0061] Optimize the calibration module, perform calibration stability test, and optimize the calibration process.

[0062] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0063] A computer-readable storage medium stores a computer program, which implements the steps of the method described above when executed by a processor.

[0064] The beneficial effects of the present invention are as follows: it is possible to achieve high-precision, automated calibration of the clock frequency and excellent environmental adaptability. The present invention can monitor and calibrate the crystal oscillator clock frequency in real time through a built-in clock frequency detection circuit without the need for an external reference clock, significantly improving the real-time and automation level of the calibration. The cyclic calibration mechanism and stability test introduced during the calibration process ensure the stability and reliability of the calibration results in long-term operation. In addition, by considering the impact of environmental factors on the clock frequency, the present invention realizes dynamic adjustment of the calibration process and improves the adaptability and accuracy of the system under different environmental conditions. These are advanced performances not available in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0066] Figure 1 An overall flow chart of a clock measurement circuit and correction method provided for the first embodiment of the present invention;

[0067] Figure 2 A clock frequency measurement circuit block diagram of a clock measurement circuit and correction method provided by the first embodiment of the present invention;

[0068] Figure 3 A clock frequency detection timing diagram of a clock measurement circuit and correction method provided by the first embodiment of the present invention;

[0069] Figure 4 A calibration state transition diagram of a clock measurement circuit and correction method provided by the first embodiment of the present invention;

[0070] Figure 5 A schematic diagram of a clock calibration register calibration process of a clock measurement circuit and correction method provided in a first embodiment of the present invention. DETAILED DESCRIPTION

[0071] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0072] Example 1

[0073] Reference Figure 1 to Figure 5 , as an embodiment of the present invention, provides a clock measurement circuit and correction method, including:

[0074] S1: Use the clock frequency detection circuit to measure and calculate the internal crystal oscillator clock frequency to be calibrated.

[0075] The clock frequency detection circuit block diagram is as follows Figure 2 shown.

[0076] Use the external high-precision clock input as the reference source, and use the internal crystal clock to be calibrated as the clock to be tested. The internal clock to be tested first performs edge detection on the external low-frequency high-precision clock input, and uses the synchronization method to verify the rising and falling edges of the external input clock source.

[0077] When the first rising edge is detected, the counter is initialized and ready to start counting. When the second rising edge is detected, the counter is reinitialized and the count value of the current real-time timer is loaded into the count buffer. The count value in the count buffer is the data obtained in this measurement. The clock frequency of the current internal crystal oscillator can be inferred from the count value in the count buffer, which is expressed as:

[0078] Ftrim=Fref * (CNT+1)

[0079] Among them, Ftrim represents the current internal high-frequency crystal frequency, Fref represents the external high-precision low-frequency clock frequency, and CNT represents the count value in the count buffer.

[0080] The clock frequency detection timing diagram is as follows: Figure 3 shown.

[0081] S2: Enter the calibration state, perform cyclic calibration on the frequency, and adjust the calibration register.

[0082] The calibration state includes a calibration initial state S0, a calibration start state S1, a calibration result frequency overflow state S2, a calibration result frequency underflow state S3, and a calibration result frequency compliance state S4, as shown in Table 1.

[0083] Table 1 Calibration status description

[0084] Calibration Status describe Calibration initial state S0 Preparing for calibration Calibration start state S1 Start calibration Calibration result frequency overflow S2 The last calibration result overflowed, so this calibration will reduce the frequency. Calibration result frequency underflow S3 The last calibration result underflowed, this calibration increases the frequency The calibration result frequency complies with S4 Calibration Complete

[0085] The calibration initial state S0 indicates that the calibration is being prepared.

[0086] The calibration start state S1 indicates the start of calibration.

[0087] The calibration result frequency overflow S2 indicates that the last calibration result overflowed and the frequency is reduced in this calibration.

[0088] The calibration result frequency underflow S3 indicates that the last calibration result underflowed, and the frequency is increased in this calibration.

[0089] If the calibration result frequency meets S4, the calibration is completed.

[0090] The calibration state conversion process is as follows: Figure 4 shown.

[0091] When the program is initialized, it enters the initialization state, and when the program performs frequency measurement, it enters the calibration start state.

[0092] After the frequency measurement is completed, calibration is performed according to the detected frequency. When the frequency detection value is greater than the theoretical value, that is, the count value of the counting buffer is greater than the theoretical calculated value, the calibration transfer state is transferred to S2 and a new round of calibration begins.

[0093] When the frequency detection value is smaller than the theoretical value, that is, the count value of the counting buffer is smaller than the theoretical calculated value, the calibration transfer state is transferred to S3 and a new round of calibration is started.

[0094] When the frequency detection value is equal to the theoretical value, that is, the count value of the counting buffer is equal to the theoretical calculated value, the calibration transfer state is transferred to S4 and the calibration is stopped.

[0095] After the calibration state is converted, the calibration register is added or subtracted according to the difference between the theoretical value and the calibration state. The specific operation is shown in Table 2.

[0096] Table 2 Calibration register specific operations

[0097]

[0098] It should be noted that the design idea of this step is to dynamically adjust the calibration register through a loop calibration method to match the error between the crystal oscillator clock frequency and the external reference clock frequency. During the calibration process, the system will determine whether to increase or decrease the operating frequency of the crystal oscillator based on the measured frequency deviation, so as to gradually reduce the frequency error. The design of loop calibration aims to finally make the crystal oscillator clock frequency reach the allowable error range through iterative adjustment.

[0099] Furthermore, this step can effectively improve the calibration accuracy of the clock frequency and ensure the stability and consistency of the crystal oscillator clock frequency. By dynamically adjusting the calibration register, it can flexibly cope with the frequency changes of the crystal oscillator under different operating conditions, thereby enhancing the overall stability and reliability of the system. The loop calibration method can also reduce the calibration time and improve the calibration efficiency.

[0100] When the calibration state is at the calibration frequency overflow S2, if BUFCNT < Z + M, the value of the calibration register is decreased by 1. If BUFCNT ≥ Z + M, the value of the calibration register is decreased by 5.

[0101] When the calibration state is at the calibration frequency underflow S3, if BUFCNT > Z - M, the value of the calibration register is increased by 1. If BUFCNT ≤ Z - M, the value of the calibration register is increased by 5.

[0102] When the calibration state is at the calibration result frequency compliance S4, if Z + M > BUFCNT > Z + L, the value of the calibration register is decreased by 1. If BUFCNT ≥ Z + M, the value of the calibration register is decreased by 5. If Z - M < BUFCNT < Z - L, the value of the calibration register is increased by 1. If BUFCNT < Z - M, the value of the calibration register is increased by 5. If Z - l ≤ BUFCNT ≤ Z + l, no operation is performed on the calibration register.

[0103] It should be noted that the adjustment operation values of the register are set by the researchers according to historical experiments. For the present invention, these values (±5, ±1) have the best adjustment effect.

[0104] Among them, BUFCNT represents the count value measured by the current frequency measurement module, and Z represents the theoretical value calculated according to the relationship between the input reference clock frequency and the measured clock frequency, expressed as:

[0105]

[0106] M represents the maximum deviation value within the fine-tuning range, expressed as:

[0107] M = α * Z

[0108] Wherein, α represents the accuracy requirement range of the minimum adjustment range.

[0109] L represents the allowable error value, expressed as:

[0110] L=β * Z

[0111] Wherein, β represents the accuracy requirement range of the clock to be measured.

[0112] The process of calibrating the register is as follows Figure 5 The result output is shown in Table 3.

[0113] Table 3 Register calibration status output table

[0114]

[0115]

[0116] It should be noted that this step determines the amount by which the calibration register needs to be increased or decreased, as well as the magnitude of the adjustment, by analyzing the difference between the current clock frequency and the ideal frequency. Specific thresholds (Z+M, Z+L, ZM, ZL) are used to determine the degree of frequency deviation and to determine the corresponding adjustment strategy accordingly. These thresholds divide the frequency deviation into different intervals, each of which corresponds to a different adjustment strategy, such as fine-tuning (-1 / +1) and large-scale adjustment (-5 / +5). This allows the calibration of the clock frequency to quickly approach the target value over a large range, and to accurately calibrate through fine-tuning when approaching the target value, avoiding frequency "oscillation" caused by excessive adjustment.

[0117] This segmented adjustment strategy can make the clock frequency calibration process more efficient and accurate. When the frequency gap is large, the gap with the ideal frequency can be quickly narrowed through large adjustments, accelerating the calibration process. When approaching the target frequency, over-adjustment and frequency instability can be avoided through fine-tuning, thereby improving the accuracy of calibration. In addition, this method also improves the flexibility and adaptability of the calibration process, and can adjust the calibration strategy according to actual conditions to better adapt to the impact of crystal oscillator aging and environmental changes.

[0118] Furthermore, the design of the thresholds Z+M, Z+L, ZM, and ZL is based on the consideration of clock system stability and calibration efficiency. These thresholds divide the frequency deviation into several intervals, and the adjustment strategy corresponding to each interval is to optimize the calibration speed and stability while ensuring the calibration accuracy. Z+L and ZL define a fine-tuning interval. When the frequency deviation is within this interval, the frequency can be accurately controlled to the target value through fine-tuning. Z+M and ZM define an interval that requires substantial adjustment, which is used to quickly approach the target frequency when the frequency deviation is large. This design allows flexible response to different degrees of frequency deviation during the calibration process, ensures the efficiency and accuracy of the calibration, and achieves the effect of quickly and accurately calibrating the clock frequency.

[0119] S3: When the frequency value is calibrated to within the set error range, the clock calibration is completed.

[0120] When the calibration program performs frequency detection, it compares the current measured count value with the theoretical count value and finds that the current clock frequency error is large and the current clock frequency is much greater than the ideal value. In this case, the calibration program performs large-grained adjustments to the calibration register and waits for the clock adjustment to stabilize before starting the next round of clock frequency measurement.

[0121] When the deviation between the measured count value and the theoretical count value has been significantly reduced, the calibration procedure performs small-grain adjustments to the calibration register.

[0122] When the current measured count value and the theoretical count value are within the set error range, a clock calibration is completed.

[0123] The setting error range is divided into an upper error limit and a lower error limit. The upper error limit is expressed as:

[0124]

[0125] The lower limit of error is expressed as:

[0126]

[0127] Where Φ represents the internal adjustment coefficient of the clock, n represents the number of internal adjustment factors of the clock, and Ω i Indicates the i-th internal calibration factor, which is related to the crystal aging. ΔT i It represents the time variable related to the i-th adjustment factor, reflecting the time difference from the start of calibration to the current time, and is used to simulate the influence of crystal aging. Λ represents the external environment adjustment coefficient, m represents the number of external environment influencing factors, represents the frequency adjustment amount related to the jth external environmental influencing factor, indicating how the external environmental changes affect the crystal oscillator frequency. Ξ represents the adjustment parameter, Θ j Represents the jth external environmental influencing factor, including temperature, humidity and air pressure.

[0128] It should be noted that the motivation for designing this formula is to create a complex but realistic model by introducing internal adjustment factors and external environmental factors of the clock system. Internal factors take into account the effects of changes over time such as crystal aging, while external factors cover factors such as temperature changes that may affect the stability of the crystal frequency. A dynamic calibration method that can adapt to internal changes and external environmental influences is provided. This not only increases the accuracy of the calibration process, but also improves the stability and reliability of the crystal in different environments. It can ensure that the clock system can adapt to complex and changing operating conditions while maintaining high accuracy.

[0129] When the frequency value is within the upper and lower error limits and the calibration register has no operation, a clock calibration is completed.

[0130] S4: Perform calibration stability test to optimize the calibration process.

[0131] Combining the deviation between the measured frequency and the target frequency and the impact of environmental factors on the clock frequency, a stability evaluation formula is designed to determine whether the calibration is stable based on the formula result:

[0132]

[0133] Among them, S represents the stability evaluation result, N represents the number of measurements, and F meas,i represents the frequency value obtained by the i-th measurement, F target represents the target frequency value, σ temp represents the standard deviation of the temperature during the test, σ volt represents the standard deviation of the voltage during the test, τ represents the temperature influence adjustment coefficient, v represents the voltage influence adjustment coefficient, and ρ represents the overall influence coefficient of adjusting all environmental influence factors.

[0134] It should be noted that the stability evaluation formula combines the deviation between the measured frequency and the target frequency, and the impact of environmental factors (such as temperature and voltage changes) on the clock frequency, in order to comprehensively evaluate the stability of the clock calibration. By considering these diverse factors, the formula can more accurately reflect the performance of the clock system in actual applications.

[0135] Furthermore, these parameters (measurement deviation, standard deviation over temperature and voltage) were chosen because they are the main factors affecting clock frequency stability. Measurement deviation is directly related to the accuracy of clock calibration. Temperature and voltage variations represent the most significant external environmental factors that have a potential impact on clock frequency.

[0136] If the stability evaluation result reaches above 0.85, the clock calibration result is considered stable, otherwise the calibration process needs to be optimized.

[0137] Optimizing the calibration process includes adjusting the calibration register process and enhancing environmental adaptability.

[0138] The process of adjusting the calibration register is as follows:

[0139] When the measured value of the clock frequency deviates greatly from the target value, a more aggressive calibration strategy is adopted to increase the step size and the adjustment amount of the calibration register.

[0140] When the frequency measurement value approaches the target value, a more subtle calibration strategy is adopted to reduce the step size and the adjustment amount of the calibration register.

[0141] The specific process of enhancing environmental adaptability is as follows:

[0142] Conduct extensive testing of clock frequencies under different environmental conditions, establish a performance baseline database, record the calibration parameter settings expected under various environmental conditions, retrieve the most suitable calibration parameters from the performance baseline database according to the current environmental conditions, and apply these parameters.

[0143] A temperature compensated crystal oscillator is selected, which has a built-in temperature compensation mechanism to automatically adjust the frequency to offset the impact of temperature changes.

[0144] Environmental sensors are integrated into the system to monitor environmental conditions in real time and automatically adjust the calibration strategy according to changes in environmental conditions to adapt to environmental changes.

[0145] Furthermore, the present invention also provides a clock measurement circuit and correction system, specifically:

[0146] The frequency detection module uses the clock frequency detection circuit to measure and calculate the internal crystal oscillator clock frequency to be calibrated.

[0147] The calibration module enters the calibration state, performs cyclic calibration on the frequency, and adjusts the calibration register.

[0148] Output frequency module, when the frequency value is calibrated to within the set error range, the clock calibration is completed.

[0149] Optimize the calibration module, perform calibration stability test, and optimize the calibration process.

[0150] The computer device may be a server. The computer device includes a processor, a memory, an input / output interface (I / O for short) and a communication interface. The processor, the memory and the input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data cluster data of a power monitoring system. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a method is implemented.

[0151] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory may include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0152] Example 2

[0153] An embodiment of the present invention provides a clock measurement circuit and a correction method and system. In order to verify the beneficial effects of the present invention, a scientific demonstration is carried out through simulation comparison experiments.

[0154] Test preparation and detailed process

[0155] The test object selected in the embodiment is "internal crystal oscillator clock frequency". Using the method invented by us, the internal crystal oscillator clock frequency to be calibrated is first measured by a clock frequency detection circuit. This process involves using an external high-precision clock as a reference and accurately measuring the frequency of the internal crystal oscillator.

[0156] During the calibration phase, a cyclic calibration strategy is used to dynamically adjust the calibration register to match the set error range. Subsequently, a calibration stability test is performed to evaluate the stability of the calibration process and optimize it. The experimental results are shown in Table 4.

[0157] Table 4 Experimental results

[0158] Test subjects Prior art Our invention Internal crystal clock frequency 32.768 32.768 Error before calibration 2.5％ 2.5％ Error after calibration 2％ 1％ Stability score 0.7 0.95

[0159] According to the experimental results, the error percentage before calibration is the same between our invention and the prior art, which means that the accuracy of the internal crystal oscillator is basically the same before calibration. The error after calibration of our invention is reduced to 1%, which is significantly improved compared to 2% of the prior art. In addition, our invention reduces the time required for calibration from 2 seconds to 1 second, which improves the calibration efficiency.

[0160] In addition, our invention achieved a stability score of 0.95. Since the prior art did not optimize the stability adjustment process, the score was only 0.7. Our invention demonstrated higher calibration stability and reliability.

[0161] Through comparative analysis, it can be clearly seen that our invention is superior to the existing technology in terms of calibration accuracy, calibration speed and stability.

[0162] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A clock measurement circuit and correction method, characterized in that: Including: Measuring and calculating the clock frequency of the internal crystal oscillator to be calibrated using a clock frequency detection circuit; Entering the calibration state, performing cyclic calibration, and adjusting the calibration register; When the frequency value is calibrated within the set error range, the clock calibration is completed; Performing a calibration stability test to optimize the calibration process.

2. The clock measurement circuit and correction method according to claim 1, wherein: The step of measuring and calculating the clock frequency of the internal crystal oscillator to be calibrated using a clock frequency detection circuit includes using an external high-precision clock input as a reference source and using the internal crystal oscillator clock to be calibrated as the clock under test; The clock under test first performs edge detection on the externally input low-frequency high-precision clock, and uses a synchronous method to verify the rising edge and falling edge of the externally input clock source; When the first rising edge is detected, the counter is initialized and counting starts. When the second rising edge is detected, the counter is re-initialized, and at the same time, the count value of the current real-time timer is loaded into the counting buffer. The count value in the counting buffer is the data obtained from this measurement; The clock frequency of the current internal crystal oscillator can be deduced from the count value in the counting buffer, expressed as: Ftrim=Fref * (CNT+1) Where, Ftrim represents the current input high-frequency crystal oscillator frequency inside, Fref represents the externally input high-precision low-frequency clock frequency, and CNT represents the count value in the counting buffer.

3. The clock measurement circuit and correction method according to claim 2, wherein: The step of entering the calibration state includes a calibration initial state S0, a calibration start state S1, a calibration result frequency overflow state S2, a calibration result frequency underflow state S3, and a calibration result frequency compliance state S4; The calibration initial state S0 indicates that calibration is in preparation; The calibration start state S1 indicates that calibration starts; The calibration result frequency overflow S2 indicates that the last calibration result overflowed, and the frequency is reduced in this calibration; The calibration result frequency underflow S3 indicates that the last calibration result underflowed, and the frequency is increased in this calibration; The calibration result frequency compliance S4 indicates that the calibration is completed.

4. The clock measurement circuit and correction method according to claim 3, characterized in that: The step of performing cyclic calibration on the frequency includes that after the program is initialized, it enters the initialization state, and after the program executes frequency measurement, it enters the calibration start state; After the frequency measurement ends, calibration is performed according to the detected frequency. When the frequency detection value is greater than the theoretical value, that is, when the count value in the counting buffer is greater than the theoretically calculated value, the calibration transfer state transfers to S2, and a new round of calibration starts; When the frequency detection value is less than the theoretical value, that is, when the count value in the counting buffer is less than the theoretically calculated value, the calibration transfer state transfers to S3, and a new round of calibration starts; When the frequency detection value is equal to the theoretical value, that is, when the count value in the counting buffer is equal to the theoretically calculated value, the calibration transfer state transfers to S4, and the calibration stops.

5. The clock measurement circuit and correction method according to claim 4, characterized in that: The step of adjusting the calibration register includes that after the calibration state is switched, the calibration register is added or subtracted according to the difference between the theoretical value and the calibration state. The specific operations are as follows: When the calibration state is in the calibration frequency overflow S2, if BUFCNT < Z + M, the value of the calibration register is -1; if BUFCNT ≥ Z + M, the value of the calibration register is -5; When the calibration state is in the calibration frequency underflow S3, if BUFCNT > Z - M, the value of the calibration register is +1; if BUFCNT ≤ Z - M, the value of the calibration register is +5; When the calibration status is such that the calibrated result frequency meets S4, if Z + M > BUFCNT > Z + L, the value of the calibration register is decreased by 1; if BUFCNT ≥ Z + M, the value of the calibration register is decreased by 5; if Z - M < BUFCNT < Z - L, the value of the calibration register is increased by 1; if BUFCNT < Z - M, the value of the calibration register is increased by 5; if Z - L ≤ BUFCNT ≤ Z + L, no operation is performed on the calibration register; Among them, BUFCNT represents the count value measured by the current frequency measurement module, and Z represents the theoretical value calculated based on the relationship between the input reference clock frequency and the measurement clock frequency, expressed as: M represents the maximum deviation value within the fine-tuning range, expressed as: M = α * Z Among them, α represents the precision requirement range of the minimum adjustment range; L represents the allowable error value, expressed as: L = β * Z Among them, β represents the precision requirement range of the clock to be measured.

6. The clock measurement circuit and correction method according to claim 5, characterized in that: When the frequency value is calibrated within the set error range, completing the clock calibration includes, when the calibration program performs frequency detection, comparing the current measured count value with the theoretical count value. If it is found that the current clock frequency error is large and the current clock frequency is much greater than the ideal value, the calibration program makes a large-grain adjustment to the calibration register, waits for the clock adjustment to stabilize, and then starts the next round of clock frequency measurement; When the deviation between the measured count value and the theoretical count value has significantly decreased, the calibration program makes a small-grain adjustment to the calibration register; When it comes to the situation where the current measured count value and the theoretical count value are within the set error range, a clock calibration is completed at this time; The set error range is divided into an error upper limit and an error lower limit. The error upper limit is expressed as: The error lower limit is expressed as: Where Φ represents the internal adjustment coefficient of the clock, n represents the number of internal adjustment factors of the clock, and Ω i represents the i-th internal calibration factor, which is related to the crystal aging; ΔT i represents the time variable related to the i-th adjustment factor, reflecting the time difference from the start of calibration to the current time, which is used to simulate the influence of crystal aging; Λ represents the external environment adjustment coefficient, m represents the number of external environment influencing factors, represents the frequency adjustment amount related to the jth external environmental influencing factor, indicating how the external environmental changes affect the crystal oscillator frequency; Ξ represents the adjustment parameter, Θ j represents the jth external environmental influencing factor, including temperature, humidity and air pressure; When the frequency value is within the error upper limit and the error lower limit, and no operation is performed on the calibration register, a clock calibration is completed.

7. The clock measurement circuit and correction method according to claim 6, characterized in that: Performing the calibration stability test and optimizing the calibration process includes, combining the deviation between the measured frequency and the target frequency and the influence of environmental factors on the clock frequency. The stability evaluation formula is expressed as: Among them, S represents the stability evaluation result, N represents the number of measurements, and F meas,i represents the frequency value obtained by the i-th measurement, F target represents the target frequency value, σ temp represents the standard deviation of the temperature during the test, σ volt represents the standard deviation of the voltage during the test, τ represents the temperature influence adjustment coefficient, v represents the voltage influence adjustment coefficient, and ρ represents the overall influence coefficient of adjusting all environmental influence factors; If the stability evaluation result reaches above 0.85, it is considered that the clock calibration result is stable; otherwise, the calibration process needs to be optimized; The optimization of the calibration process includes the process of adjusting the calibration register and enhancing environmental adaptability; The process of adjusting the calibration register is as follows: When the deviation between the measured value of the clock frequency and the target value is large, a more aggressive calibration strategy is adopted, increasing the step size and the adjustment amount of the calibration register; When the measured frequency value is close to the target value, a more delicate calibration strategy is adopted, reducing the step size and the adjustment amount of the calibration register; The process of enhancing environmental adaptability is specifically: Under different environmental conditions, widely test the clock frequency, establish a performance baseline database, record the expected calibration parameter settings under various environmental conditions, and retrieve the most suitable calibration parameters from the performance baseline database according to the current environmental conditions and apply these parameters; Select a temperature-compensated crystal oscillator, which has a built-in temperature compensation mechanism to automatically adjust the frequency and offset the influence of temperature changes; Environmental sensors are integrated into the system to monitor environmental conditions in real time and automatically adjust the calibration strategy according to changes in environmental conditions to adapt to environmental changes.

8. A clock measurement circuit and correction system using the method according to any one of claims 1 to 7, characterized in that: The frequency detection module uses the clock frequency detection circuit to measure and calculate the internal crystal oscillator clock frequency to be calibrated; The calibration module enters the calibration state, performs cyclic calibration on the frequency, and adjusts the calibration register; Output frequency module, when the frequency value is calibrated to within the set error range, the clock calibration is completed; Optimize the calibration module, perform calibration stability test, and optimize the calibration process.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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