SiP-based four-channel peak signal acquisition circuit and packaging structure thereof

Abstract

The invention relates to a SiP-based four-channel peak signal acquisition circuit and a packaging structure thereof, the circuit comprises a four-channel peak holding module and a data acquisition module, the input of the four-channel peak holding module is an analog pulse signal, and after peak holding processing, a held analog signal is output; and inputting the maintained analog signal into a data acquisition module, and outputting a corresponding serial digital signal after analog-to-digital conversion. The circuit can carry out peak holding operation on pulse signals of four channels, and the holding time is adjustable. The circuit packaging structure is applied to packaging of the SiP-based four-channel peak signal acquisition circuit, the circuit packaging structure comprises a base, a plastic packaging cavity and a packaging piece, and the four-channel peak holding module and the data acquisition module are fixedly arranged on the base. The packaging size of the circuit packaging structure is only 6.8 mm * 6.8 mm and is reduced by more than 95% compared with the traditional design size, the integration level is greatly improved, and application and debugging are facilitated.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal acquisition, and in particular relates to a SiP-based four-channel peak signal acquisition circuit and a packaging structure thereof. Background Art

[0002] Peak hold and acquisition circuits are widely used in multi-quadrant detector signal acquisition systems. Depending on the number of channels for acquiring signals, there are single-channel, dual-channel, and four-channel acquisition systems. In applications, the system needs to perform peak hold operations on the signal, and then perform analog-to-digital conversion and digital processing on the held signal. The components used generally include operational amplifiers, diodes, A / D converters, and digital processing devices, such as single-chip microcomputers, field-programmable gate arrays (FPGAs) or digital signal processors (DSPs). The system generally uses low-voltage power supply, such as 3.3V, 5V, etc., and has certain requirements on the bandwidth of the operational amplifier, the speed of the A / D converter, and the digital processor.

[0003] In the prior art, the implementation of this system is generally as follows: according to the number of channels, separate operational amplifiers and diodes, microcontroller units or single-chip microcomputers (MCU) and other devices are used to build circuits to provide a fixed output signal holding time. The devices used in the system may also require different power supply voltages, and multiple external power supplies are required for power supply. This solution has many shortcomings: the number of channels is designed according to actual needs, which is not universal, and a set of solutions is only for one application; the peak holding of the front end and the analog-to-digital conversion and digital processing of the back end use multiple devices in cascade, which makes debugging difficult and the process cumbersome; different devices use multiple power supply modules, which take up a lot of space in the system, cause large noise, and reduce the acquisition accuracy. Therefore, how to make the system universal, simplify the design in application, and improve the accuracy is a major issue facing the existing design. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a four-channel peak signal acquisition circuit with a new structure, which is used to solve the problems in the prior art of difficult debugging, limited number of channels and large space occupied by multiple independent devices.

[0005] The first aspect of the present invention provides a four-channel peak signal acquisition circuit based on SiP, including: a four-channel peak holding module and a data acquisition module, the input of the four-channel peak holding module is an analog pulse signal, and the held analog signal is output after peak holding processing; the held analog signal is input into the data acquisition module, and the corresponding serial digital signal is output after analog-to-digital conversion.

[0006] Furthermore, the four-channel peak holding module includes four channels with the same circuit structure, and the channel includes: a dual-way operational amplifier chip, a diode chip, a first resistor, a second resistor and a capacitor, the dual-way operational amplifier chip includes two operational amplifiers connected in a cascade manner, whose positive power supply pin is connected to the positive power supply and the negative power supply pin is grounded; the first positive input pin of the dual-way operational amplifier chip receives the analog pulse signal of the first channel, and the first positive input pin is grounded through the first resistor; the second negative input pin of the dual-way operational amplifier chip is connected to the first output pin of the dual-way operational amplifier chip and used as the output pin of the channel; the first output pin of the dual-way operational amplifier chip is connected to the anode of the diode, the cathode of the diode is connected to the second positive input pin of the dual-way operational amplifier chip, and is connected to a common end of the capacitor and the second resistor, and the other common end of the capacitor and the second resistor is grounded.

[0007] Furthermore, the second aspect of the present invention provides a circuit packaging structure, which is applied to the SiP-based four-channel peak signal acquisition circuit packaging. The circuit packaging structure includes a base, a plastic packaging cavity and a packaging component, and the four-channel peak holding module and the data acquisition module are fixedly arranged on the base.

[0008] The beneficial effects of the present invention are as follows: the four-channel peak holding module of the present invention can receive four-channel peak signals at the same time, perform peak voltage holding operations on them, output four-channel holding voltages, and can adjust the holding time of the output voltage through the control port; the signal acquisition module can perform analog-to-digital conversion on the holding voltage through digital signal control, can output four digital signals at the same time, and can perform calculation operations on the digital signals according to requirements, which can greatly simplify the upper computer calculation. The four-channel peak holding module and the signal acquisition module are encapsulated in the same plastic packaging cavity, based on the integrated packaging of bare chips and peripheral components, which effectively reduces the size and volume of the device, has the characteristics of miniaturization and high density, greatly simplifies the application design, and expands the scope of application. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematic diagram of the principle of a four-channel peak signal acquisition circuit based on SiP according to an embodiment of the present invention;

[0010] Figure 2for Figure 1 Circuit diagram of the four-channel peak hold module;

[0011] Figure 3 for Figure 1 Circuit diagram of the signal acquisition module;

[0012] Figure 4 This is a schematic diagram of the packaging structure of a four-channel peak signal acquisition circuit based on SiP according to an embodiment of the present invention;

[0013] Figure 5 This is a pinout diagram of the packaging structure of a four-channel peak signal acquisition circuit based on SiP according to an embodiment of the present invention;

[0014] Description of reference numerals:

[0015] VCC: internal op amp power supply; GND: ground;

[0016] MCU (Microcontroller Unit): microcontroller unit or single-chip microcomputer;

[0017] URAT interface (Universal Asynchronous Receiver / Transmitter interface): universal asynchronous receiver and transmitter interface;

[0018] I2C interface: two-wire serial bus interface, used to connect MCU and other peripherals;

[0019] IN1: first channel analog input; IN2: second channel analog input;

[0020] IN3: the third channel analog input; IN4: the fourth channel analog input;

[0021] SET1: The first channel keeps the settings; SET2: The second channel keeps the settings;

[0022] SET3: The third channel keeps the setting; SET4: The fourth channel keeps the setting;

[0023] OUT1: The first channel keeps output; OUT2: The second channel keeps output;

[0024] OUT3: The third channel keeps output; OUT4: The fourth channel keeps output;

[0025] OP1-A: One amplifier in the first dual operational amplifier chip;

[0026] OP1-B: Another amplifier in the first dual operational amplifier chip;

[0027] R1: first resistor; D1: first diode; C1: first capacitor; R2: second resistor;

[0028] OP2-A: One amplifier in the second dual operational amplifier chip;

[0029] OP2-B: Another amplifier in the second dual operational amplifier chip;

[0030] R3: third resistor; D2: second diode; C2: second capacitor; R4: fourth resistor;

[0031] OP3-A: One amplifier in the third dual operational amplifier chip;

[0032] OP3-B: Another amplifier in the third dual operational amplifier chip;

[0033] R5: fifth resistor; D3: third diode; C3: third capacitor; R6: sixth resistor;

[0034] OP4-A: One amplifier in the second dual operational amplifier chip;

[0035] OP4-B: Another amplifier in the second dual op amp chip;

[0036] R7: seventh resistor; D4: fourth diode; C4: fourth capacitor; R8: eighth resistor;

[0037] IC1: the first dual-channel operational amplifier chip; IC2: the second dual-channel operational amplifier chip;

[0038] IC3: the third dual operational amplifier chip; IC4: the fourth dual operational amplifier chip;

[0039] IC5: microcontroller chip. DETAILED DESCRIPTION

[0040] The terms "first", "second", "third", "fourth", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances. This is just a way of distinguishing objects with the same attributes when describing the embodiments of this application.

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] It should be noted that the diagrams provided in the present embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, so the diagrams only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation can be changed at will, and the component layout type may also be more complicated. The structure, proportion, size, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions that the present invention can be implemented, so they have no technical substantive significance. Any modification of the structure, change of the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effect and purpose that can be achieved by the present invention.

[0043] Terminology explanation:

[0044] SiP: System in a Package, system-level packaging.

[0045] BT organic substrate, that is, BT resin substrate material, is a high-performance substrate made of BT resin as the base material and is widely used in the PCB (printed circuit board) field.

[0046] UART: Universal Asynchronous Receiver / Transmitter, universal asynchronous receiver and transmitter, is a commonly used serial communication interface.

[0047] I2C: (Inter-Integrated Circuit, IIC), integrated circuit bus, I2C is a serial communication bus.

[0048] As mentioned in the background technology above: the number of channels is designed according to actual needs, which is not universal, and one solution is only for one application; the peak holding at the front end and the analog-to-digital conversion and digital processing at the back end use multiple devices in cascade, which makes debugging difficult and the process cumbersome; different devices use multiple power supply modules, which takes up a lot of space in the system, causes large noise, and reduces the acquisition accuracy. Based on this, the present invention proposes a newly designed four-channel peak signal acquisition circuit and its packaging structure.

[0049] Figure 1The figure is a schematic diagram of the principle of a four-channel peak signal acquisition circuit based on SiP according to an embodiment of the present invention. Figure 1 In the figure, IN1~IN4 respectively represent the analog pulse signals received by the four-channel peak holding module; the external configuration signals SET1~SET4 respectively represent the optional signals of the four-channel peak holding module, which are used to control the holding time of the output signal; OUT1~OUT4 respectively represent the analog signals after holding output by the four-channel peak holding module, VCC is a 5V power supply, and GND is ground.

[0050] The embodiment of the present invention provides a four-channel peak signal acquisition circuit based on SiP, referring to Figure 1 As shown, the circuit includes: a four-channel peak holding module and a data acquisition module, the input of the four-channel peak holding module is an analog pulse signal, and the held analog signal is output after peak holding processing; the held analog signal is input into the data acquisition module, and the corresponding serial digital signal is output after analog-to-digital conversion.

[0051] As a preferred embodiment, refer to Figure 1 As shown, the four-channel peak holding module includes four channels with the same circuit structure, which are:

[0052] The first channel includes a first dual-channel operational amplifier chip OP1, a first diode chip D1, a first resistor R1, a second resistor R2 and a first capacitor C1. The first dual-channel operational amplifier chip includes two operational amplifiers connected in cascade, specifically, amplifier OP1-A and amplifier OP1-B are connected in cascade; the positive power supply pin of the first dual-channel operational amplifier chip is connected to the positive power supply VCC, and the negative power supply pin is grounded; the first positive input pin of the first dual-channel operational amplifier chip (i.e., the positive input pin of the amplifier OP1-A) receives the analog pulse signal IN1 of the first channel, and the first positive input pin is grounded through the first resistor R1; the first negative input pin of the first dual-channel operational amplifier chip (i.e., the negative input pin of the amplifier OP1-A) is connected to the second output pin of the first dual-channel operational amplifier chip. The first output pin of the first dual-way operational amplifier chip (i.e., the output pin of the amplifier OP1-A) is connected to the anode of the first diode D1, the cathode of the first diode D1 is connected to the second positive input pin of the first dual-way operational amplifier chip (i.e., the positive input pin of the amplifier OP1-B), and is connected to a common end of the first capacitor C1 and the second resistor R2, and the other common end of the first capacitor C1 and the second resistor R2 is grounded.

[0053] The second channel includes a second dual-way operational amplifier chip OP2, a second diode chip D2, a third resistor R3, a fourth resistor R4 and a second capacitor C2. The second dual-way operational amplifier chip includes two operational amplifiers connected in cascade, specifically, amplifier OP2-A and amplifier OP2-B are connected in cascade; the positive power supply pin of the second dual-way operational amplifier chip is connected to the positive power supply VCC, and the negative power supply pin is grounded; the first positive input pin of the second dual-way operational amplifier chip (i.e., the positive input pin of the amplifier OP2-A) receives the analog pulse signal IN2 of the second channel, and the first positive input pin is grounded through the first resistor R3; the first negative input pin of the second dual-way operational amplifier chip (i.e., the negative input pin of the amplifier OP2-A) is connected to the second output of the second dual-way operational amplifier chip The first negative input pin (i.e., the negative input pin of the amplifier OP2-A), the second negative input pin (i.e., the negative input pin of the amplifier OP2-B) and the second output pin (i.e., the output pin of the amplifier OP2-B) of the second dual-way operational amplifier chip are connected as the output pin of the second channel; the first output pin (i.e., the output pin of the amplifier OP2-A) of the second dual-way operational amplifier chip is connected to the anode of the second diode D2, the cathode of the second diode D2 is connected to the second positive input pin (i.e., the positive input pin of the amplifier OP2-B), and is connected to a common end of the second capacitor C2 and the fourth resistor R4, and the other common end of the second capacitor C2 and the fourth resistor R4 is grounded.

[0054] The third channel comprises a third dual-way operational amplifier chip OP3, a third diode chip D3, a fifth resistor R5, a sixth resistor R6 and a third capacitor C3. The third dual-way operational amplifier chip comprises two operational amplifiers connected in cascade, specifically, amplifier OP3-A and amplifier OP3-B are connected in cascade; the positive power supply pin of the third dual-way operational amplifier chip is connected to the positive power supply VCC, and the negative power supply pin is grounded; the first positive input pin of the third dual-way operational amplifier chip (i.e., the positive input pin of the amplifier OP3-A) receives the analog pulse signal IN3 of the third channel, and the first positive input pin is grounded through the fifth resistor R5; the first negative input pin of the third dual-way operational amplifier chip (i.e., the negative input pin of the amplifier OP3-A) is connected to the second output pin of the third dual-way operational amplifier chip. The first negative input pin (i.e., the negative input pin of the amplifier OP3-A), the second negative input pin (i.e., the negative input pin of the amplifier OP3-B) and the second output pin (i.e., the output pin of the amplifier OP3-B) of the third dual-way operational amplifier chip are connected to serve as the output pin of the third channel; the first output pin (i.e., the output pin of the amplifier OP3-A) of the third dual-way operational amplifier chip is connected to the anode of the third diode D3, the cathode of the third diode D3 is connected to the second positive input pin (i.e., the positive input pin of the amplifier OP3-B) of the third dual-way operational amplifier chip, and is connected to a common end of the third capacitor C3 and the sixth resistor R6, and the other common end of the third capacitor C3 and the sixth resistor R6 is grounded.

[0055] The fourth channel includes a fourth dual-way operational amplifier chip OP4, a fourth diode chip D4, a seventh resistor R7, an eighth resistor R8 and a fourth capacitor C4. The fourth dual-way operational amplifier chip includes two operational amplifiers connected in cascade, specifically, amplifier OP4-A and amplifier OP4-B are connected in cascade; the positive power supply pin of the fourth dual-way operational amplifier chip is connected to the positive power supply VCC, and the negative power supply pin is grounded; the first positive input pin of the fourth dual-way operational amplifier chip (that is, the positive input pin of the amplifier OP4-A) receives the analog pulse signal IN4 of the fourth channel, and the first positive input pin is grounded through the seventh resistor R7; the first negative input pin of the fourth dual-way operational amplifier chip (that is, the negative input pin of the amplifier OP4-A) is connected to the second output pin of the fourth dual-way operational amplifier chip. The first negative input pin (i.e., the negative input pin of the amplifier OP4-A), the second negative input pin (i.e., the negative input pin of the amplifier OP4-B) and the second output pin (i.e., the output pin of the amplifier OP4-B) of the fourth dual-way operational amplifier chip are connected to serve as the output pin of the fourth channel; the first output pin (i.e., the output pin of the amplifier OP4-A) of the fourth dual-way operational amplifier chip is connected to the anode of the fourth diode D4, the cathode of the fourth diode D4 is connected to the second positive input pin (i.e., the positive input pin of the amplifier OP4-B) of the fourth dual-way operational amplifier chip, and is connected to a common end of the fourth capacitor C4 and the eighth resistor R8, and the other common end of the fourth capacitor C4 and the eighth resistor R8 is grounded.

[0056] In the above four channels, diodes D1 to D4 are all SC070H100A5F produced by International Rectifier (IR). Resistors R1 to R8 are of the same model and their resistance values ​​are all 10kΩ. Capacitors C1 to C4 are of the same model and their capacitance values ​​are all 0.01μF. The power supply voltage is 5V, and the pulse width of signals IN1 to IN4 is ≥200ns, with an amplitude of 0 to 4V.

[0057] Figure 2 for Figure 1 Circuit diagram of the four-channel peak hold module.

[0058] As a preferred embodiment, refer to Figure 2 As shown, in the four-channel peak holding module, the two-way operational amplifiers all use a two-way operational amplifier chip with model number AD8042. Furthermore, the four-channel peak holding module is specifically composed of four units with the same structure, and the four units are specifically:

[0059] The first unit includes a first dual-channel operational amplifier chip IC1, a first diode chip D1, a first resistor R1, a second resistor R2, and a first capacitor C1. Pin 8 of the dual-channel operational amplifier chip IC1 is connected to a positive 5V power supply VCC, and pin 4 is grounded; pin 3 of the dual-channel operational amplifier chip IC1 receives a pulse signal IN1 of the first channel, and is grounded through the first resistor R1; pin 2 of the dual-channel operational amplifier chip IC1 is connected to its pin 6, and pin 6 of the dual-channel operational amplifier chip IC1 is connected to its pin 7, and it is used as the first channel output terminal OUT1; pin 1 of the dual-channel operational amplifier chip IC1 is connected to the cathode of the first diode D1, pin 5 of the dual-channel operational amplifier chip IC1 is connected to the anode of the first diode D1, a common end of the first capacitor C1 and the second resistor R2 is connected to pin 5 of the dual-channel operational amplifier chip IC1, and the other common end of the first capacitor C1 and the second resistor R2 is grounded.

[0060] The second unit includes a second dual-channel operational amplifier chip IC2, a second diode chip D2, a third resistor R3, a fourth resistor R4, and a second capacitor C2. Pin 8 of the second dual-channel operational amplifier chip IC2 is connected to a positive 5V power supply VCC, and pin 4 is grounded; pin 3 of the second dual-channel operational amplifier chip IC2 receives a pulse signal IN2 of the second channel, and is grounded through the third resistor R3; pin 2 of the second dual-channel operational amplifier chip IC2 is connected to its pin 6, and pin 6 of the second dual-channel operational amplifier chip IC2 is connected to its pin 7, and it is used as the second channel output terminal OUT2; pin 1 of the second dual-channel operational amplifier chip IC2 is connected to the cathode of the second diode D2, pin 5 of the second dual-channel operational amplifier chip IC2 is connected to the anode of the second diode D2, a common end of the second capacitor C2 and the fourth resistor R4 is connected to pin 5 of the second dual-channel operational amplifier chip IC2, and another common end of the second capacitor C2 and the fourth resistor R4 is grounded.

[0061] The third unit includes a third dual-channel operational amplifier chip IC3, a third diode chip D3, a fifth resistor R5, a sixth resistor R6, and a third capacitor C3. Pin 8 of the third dual-channel operational amplifier chip IC3 is connected to a positive 5V power supply VCC, and pin 4 is grounded; pin 3 of the third dual-channel operational amplifier chip IC3 receives a pulse signal IN3 of the third channel, and is grounded through the fifth resistor R5; pin 2 of the third dual-channel operational amplifier chip IC3 is connected to its pin 6, and pin 6 of the third dual-channel operational amplifier chip IC3 is connected to its pin 7, and it is used as the third channel output terminal OUT3; pin 1 of the third dual-channel operational amplifier chip IC3 is connected to the cathode of the third diode D3, pin 5 of the third dual-channel operational amplifier chip IC3 is connected to the anode of the third diode D3, a common end of the third capacitor C3 and the sixth resistor R6 is connected to pin 5 of the third dual-channel operational amplifier chip IC3, and another common end of the third capacitor C3 and the sixth resistor R6 is grounded.

[0062] The fourth unit includes a fourth dual-channel operational amplifier chip IC4, a fourth diode chip D4, a seventh resistor R7, an eighth resistor R8, and a fourth capacitor C4. Pin 8 of the fourth dual-channel operational amplifier chip IC4 is connected to a positive 5V power supply VCC, and pin 4 is grounded; pin 3 of the fourth dual-channel operational amplifier chip IC4 receives a pulse signal IN4 of the fourth channel, and is grounded through the seventh resistor R7; pin 2 of the fourth dual-channel operational amplifier chip IC4 is connected to its pin 6, and pin 6 of the fourth dual-channel operational amplifier chip IC4 is connected to its pin 7, and it is used as the fourth channel output terminal OUT4; pin 1 of the fourth dual-channel operational amplifier chip IC4 is connected to the cathode of the fourth diode D4, pin 5 of the fourth dual-channel operational amplifier chip IC4 is connected to the anode of the fourth diode D4, a common end of the fourth capacitor C2 and the eighth resistor R4 is connected to pin 5 of the fourth dual-channel operational amplifier chip IC4, and another common end of the fourth capacitor C2 and the eighth resistor R4 is grounded.

[0063] The AD8042 dual operational amplifier chip (IC1 to IC4) is produced by ADI.

[0064] Figure 3 for Figure 1 Circuit diagram of the signal acquisition module. Figure 3In the embodiment, the signal acquisition module includes a single-chip microcomputer chip, and pins 18, 19, 20, and 26 of the single-chip microcomputer chip are respectively connected to the output pins OUT1 to OUT4 of the front-end four-channel peak holding module for receiving analog input signals. Pins 59 and 60 are led out of the circuit as the input / output pins of the I2C digital control signal. Pins 63 and 67 are led out of the circuit as the download interface of the internal program of the single-chip microcomputer. Pins 80 and 82 are led out of the circuit as the input / output pins of the UART digital control signal.

[0065] As a preferred embodiment, refer to Figure 3 As shown, the signal acquisition module adopts a single-chip microcomputer chip, and the single-chip microcomputer chip includes four signal input ports, whose input signals are respectively four output signals of the four-channel peak holding module, and whose output signals are serial digital signals.

[0066] As a preferred embodiment, the model of the single-chip microcomputer chip is STM32F031. The I2C digital control signal complies with the I2C bus protocol standard, and the UART digital control signal complies with the UART communication protocol standard.

[0067] The embodiment of the present invention uses a substrate-type plastic packaging process to package the SiP-based four-channel peak signal acquisition circuit to form a circuit packaging structure.

[0068] An embodiment of the present case provides a circuit packaging structure, which is applied to the SiP-based four-channel peak signal acquisition circuit packaging. The circuit packaging structure includes a base, a plastic packaging cavity and a packaging component, and the four-channel peak holding module and the data acquisition module are fixedly arranged on the base.

[0069] As a preferred embodiment, the base of the plastic packaging cavity adopts a BT organic substrate.

[0070] Specifically, on the BT organic substrate (i.e., the base), the four-channel peak holding module is fixed on the BT organic substrate using conductive glue, and the data acquisition module is fixed on the BT organic substrate using solder paste. The electrical connection between each chip (such as a dual-channel operational amplifier chip, MCU) used in the four-channel peak holding module and the data acquisition module and the BT organic substrate is achieved using a gold wire ball welding process, and each chip (such as a dual-channel operational amplifier chip, MCU) is fixed on the BT organic substrate in a stacked manner in pairs, and the BT organic substrate uses multi-layer wiring to achieve the electrical connection of each module or chip. Each vital component (such as a dual-channel operational amplifier chip, MCU) is integrated using bare chips, and extremely small packaged passive components (such as resistors, capacitors, etc.) are used, and a substrate-type plastic sealing process is used in the process. In this way, the size of the circuit packaging structure can be significantly reduced, the integration level is greatly improved, and it is easy to apply and debug.

[0071] Figure 4 The figure is a schematic diagram of the packaging structure of a four-channel peak signal acquisition circuit based on SiP according to an embodiment of the present invention.

[0072] Table 1 Figure 4 The dimension table of the package structure.

[0073] Table 1 Figure 4 Dimensions of the package structure

[0074]

[0075] Figure 5 This is a pinout diagram of the packaging structure of a four-channel peak signal acquisition circuit based on SiP according to an embodiment of the present invention.

[0076] Table 2 Figure 5 Pin assignment table for the package structure.

[0077] Table 2 Figure 5 Pin assignment table for package structure

[0078]

[0079] As a preferred embodiment, refer to Figure 5and Table 2, the bottom of the circuit packaging structure is connected with 24 leadless pins, including: the first pin is the serial port sending end, the second pin is the serial port receiving end, the third pin is the analog input end of the second channel in the four-channel peak holding module, the fourth pin is the holding output end of the second channel in the four-channel peak holding module, the fifth pin is the holding setting end of the second channel in the four-channel peak holding module, the sixth pin provides power for the data acquisition module, the seventh pin is the reset end of the data acquisition module, the eighth pin is the clock signal end of the data acquisition module, the ninth pin is the analog input end of the fourth channel in the four-channel peak holding module, the tenth pin is the holding output end of the fourth channel in the four-channel peak holding module, and the eleventh pin is the holding setting end of the fourth channel in the four-channel peak holding module. , the 12th pin is the internal op amp power supply terminal, the 13th pin is the ground terminal, the 14th pin is the I2C interface clock signal terminal, the 15th pin is the analog input terminal of the third channel in the four-channel peak hold module, the 16th pin is the hold output terminal of the third channel in the four-channel peak hold module, the 17th pin is the hold setting terminal of the third channel in the four-channel peak hold module, the 18th pin is the I2C interface data terminal, the 19th pin is the program download interface data terminal, the 20th pin is the program download interface clock terminal, the 21st pin is the analog input terminal of the first channel in the four-channel peak hold module, the 22nd pin is the hold output terminal of the first channel in the four-channel peak hold module, the 23rd pin is the hold setting terminal of the first channel in the four-channel peak hold module, and the 23rd pin is the ground terminal.

[0080] The embodiments of the present invention can achieve the goals of versatility, high density, and miniaturization, while simplifying the complexity of applications.

[0081] As a preferred embodiment, a metal heat sink is welded on the bottom of the circuit packaging structure. The metal heat sink has a size of 3.8 mm×3.8 mm. When in use, the metal heat sink is welded to the PCB board to play a role in heat dissipation.

[0082] As a preferred embodiment, the packaging dimensions of the circuit packaging structure are as follows: its length is 6.8 mm, its width is 6.8 mm, and its height is 1.2 mm.

[0083] Reference Figure 4 As shown in Table 1, the package size of the circuit package structure is 6.8 mm×6.8 mm×1.2 mm, and the bottom thereof includes 24 leadless pins for input and output of circuit signals.

[0084] The present invention is designed based on multiple bare chips and peripheral components, and can simultaneously hold the peak values ​​of four narrow pulse signals and collect the held signals to output digital signals. The peak holding module designed based on the operational amplifier can process four signals at the same time, and the default holding time (100% to 90%) is greater than 10us, and can be adjusted by external resistors; the data acquisition module integrates a microprocessor chip with a maximum operating frequency of 72MHz, a collection resolution of 12bit, a maximum conversion rate of 1MSPS, and provides UART and I2C interfaces; the devices are all integrated using bare chips, and passive devices with extremely small packages are used. The substrate-type plastic sealing process is used in the process, and the design size is only 6.8mm×6.8mm×1.2mm, which is more than 95% smaller than the traditional design size, greatly improving the integration and facilitating application and debugging.

[0085] In summary, the present invention provides a four-channel peak signal acquisition circuit based on SiP and its packaging structure. Based on the circuit structure design of multiple bare chips and peripheral components, the peak holding operation can be performed on the pulse signals of four channels at the same time, and the holding time is adjustable; at the same time, the output signal after holding is converted into analog to digital, and certain calculations and processing can be performed on the digital signal. The circuit is based on miniaturization, high density, and modular design, and has high flexibility and simplicity in application. Compared with the existing system, it greatly increases the scope of application and reduces the difficulty of use.

[0086] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A four-channel peak signal acquisition circuit based on SiP, characterized in that: include: A four-channel peak hold module and a data acquisition module, wherein the input of the four-channel peak hold module is an analog pulse signal, and after peak hold processing, the analog signal after hold is output; the analog signal after hold is input into the data acquisition module, and after analog-to-digital conversion, the corresponding serial digital signal is output.

2. The four-channel peak signal acquisition circuit based on SiP according to claim 1, characterized in that: The four-channel peak holding module includes four channels with the same circuit structure, and the channel includes: a dual-way operational amplifier chip, a diode chip, a first resistor, a second resistor and a capacitor. The dual-way operational amplifier chip includes two operational amplifiers connected in a cascade manner, and its positive power supply pin is connected to the positive power supply, and the negative power supply pin is grounded; the first positive input pin of the dual-way operational amplifier chip receives the analog pulse signal of the first channel, and the first positive input pin is grounded through the first resistor; the second negative input pin of the dual-way operational amplifier chip is connected to the first output pin of the dual-way operational amplifier chip and used as the output pin of the channel; the first output pin of the dual-way operational amplifier chip is connected to the anode of the diode, and the cathode of the diode is connected to the second positive input pin of the dual-way operational amplifier chip, and is connected to a common end of the capacitor and the second resistor, and the other common end of the capacitor and the second resistor is grounded.

3. The SiP-based four-channel peak signal acquisition circuit according to claim 2, characterized in that: In the four-channel peak hold module, the dual-channel operational amplifier chip adopts a dual-channel operational amplifier chip of model AD8042, whose pin (8) is connected to a positive power supply, whose pin (4) is grounded, whose pin (3) receives a pulse signal, whose pin (3) is grounded through a first resistor, whose pin (5) is connected to the anode of a diode, whose pin (1) is connected to the cathode of a diode, and whose pin (5) is connected to a common end of the capacitor and a second resistor, whose other common end is grounded, whose pin (2), pin (6) and pin (7) are connected and used as the output end of the module.

4. The four-channel peak signal acquisition circuit based on SiP according to claim 1, characterized in that: The signal acquisition module adopts a single-chip microcomputer chip, which includes four signal input ports, whose input signals are respectively four output signals of the four-channel peak holding module, and whose output signals are serial digital signals.

5. The four-channel peak signal acquisition circuit based on SiP according to claim 4, characterized in that: The model of the single-chip microcomputer chip is STM32F031.

6. A circuit packaging structure, characterized in that: The circuit packaging structure is applied to the SiP-based four-channel peak signal acquisition circuit package as claimed in claim 1, and the circuit packaging structure includes a base, a plastic packaging cavity and a packaging component, and the four-channel peak holding module and the data acquisition module are fixedly arranged on the base.

7. The circuit packaging structure according to claim 6, characterized in that: The bottom of the circuit packaging structure is connected with 24 leadless pins, including: pin 1 is the serial port sending end, pin 2 is the serial port receiving end, pin 3 is the analog input end of the second channel in the four-channel peak holding module, pin 4 is the holding output end of the second channel in the four-channel peak holding module, pin 5 is the holding setting end of the second channel in the four-channel peak holding module, pin 6 provides power for the data acquisition module, pin 7 is the reset end of the data acquisition module, pin 8 is the clock signal end of the data acquisition module, pin 9 is the analog input end of the fourth channel in the four-channel peak holding module, pin 10 is the holding output end of the fourth channel in the four-channel peak holding module, pin 11 is the holding setting end of the fourth channel in the four-channel peak holding module, pin 12 is the analog input end of the fourth channel in the four-channel peak holding module, pin 13 is the analog input end of the fourth channel in the four-channel peak holding module, pin 14 is the analog input end of the fourth channel in the four-channel peak holding module, pin 15 is the analog input end of the fourth channel in the four-channel peak holding module, pin 16 is the analog input end of the fourth channel in the four-channel peak holding module, pin 17 is the analog input end of the fourth channel in the four-channel peak holding module, pin 18 is the analog input end of the fourth channel in the four-channel peak holding module, pin 19 is the analog input end of the fourth channel in the four-channel peak holding module, pin 20 is the analog input end of the fourth channel in the four-channel peak holding module, pin 21 is the analog input end of the fourth channel in the four-channel peak holding module, pin 22 is the analog input end of the fourth channel in the four-channel peak holding module, pin 23 is the analog input end of the fourth channel in the four-channel peak holding module, pin 24 is the analog input end of the fourth channel in the four-channel peak holding module Pin 2 is the internal op amp power supply terminal, pin 13 is the ground terminal, pin 14 is the I2C interface clock signal terminal, pin 15 is the analog input terminal of the third channel in the four-channel peak hold module, pin 16 is the hold output terminal of the third channel in the four-channel peak hold module, pin 17 is the hold setting terminal of the third channel in the four-channel peak hold module, pin 18 is the I2C interface data terminal, pin 19 is the program download interface data terminal, pin 20 is the program download interface clock terminal, pin 21 is the analog input terminal of the first channel in the four-channel peak hold module, pin 22 is the hold output terminal of the first channel in the four-channel peak hold module, pin 23 is the hold setting terminal of the first channel in the four-channel peak hold module, and pin 23 is the ground terminal.

8. The circuit packaging structure according to claim 6, characterized in that: A metal heat sink is welded on the bottom of the circuit packaging structure.

9. The circuit packaging structure according to claim 6, characterized in that: The package dimensions of the circuit package structure are specifically: 6.8 mm in length, 6.8 mm in width, and 1.2 mm in height.

10. The circuit packaging structure according to claim 6, characterized in that: The base adopts a BT organic substrate.

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