Multi-device high-precision synchronization system and method
By using high-frequency reference clocks and clock generators in a multi-device system to generate integer multiples of FPGA clocks and sampling clocks, combined with the synchronization control of the state machine and data interaction module, the problem of poor synchronization accuracy between different devices is solved, and high Accurate device synchronization.
Patent Information
- Application Number
- CN202411526604.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-01-03
AI Technical Summary
The existing synchronization triggering technology cannot achieve high-precision synchronization, especially between devices with different FPGA clocks and sampling clocks. The clock phase relationship and transmission delay uncertainty lead to poor synchronization accuracy, making it difficult to reconcile between multiple device systems. Use measurement results.
Adopt a multi-device high-precision synchronization system to generate integer multiple FPGA clocks and sampling clocks through high-frequency reference clocks, clock generators and converters, and realize synchronization control between devices through the state machine and data interaction module to ensure that all devices are external. Synchronous operation under trigger signal.
Accurate synchronization of FPGA clock and sampling clock is achieved, avoiding the uncertainty of cable transmission delay and clock skew, ensuring high-precision pulse triggering, and meeting the needs of high-precision synchronization.
Smart Images
Figure CN119254372A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of device synchronization triggering, and in particular to a multi-device high-precision synchronization system and method. Background Art
[0002] Most of the existing synchronous trigger technologies are aimed at the synchronization of multiple channels of a single device (single FPGA). They use the same clock but with an unknown phase relationship as the sampling clock of all channels, and ensure that the trigger is delivered to each channel at the same time, so that signal transmission or signal acquisition operations can be completed synchronously between multiple channels.
[0003] However, most existing digital processing devices have sampling rates (such as DAC or ADC) that are much higher than the clock frequency that the FPGA can keep up with. In this case, the FPGA must have an interactive part (such as JESD204 Block) with the input (from ADC) or output (to DAC) data, which requires two important clocks - the sampling clock that drives the DAC or ADC, and the FPGA clock that drives the part of the FPGA that interacts with the DAC or ADC. If synchronization between devices is required, it can only be guaranteed to use carefully matched cables so that each trigger reaches different devices at the same time as much as possible, but the FPGA clocks between different devices are likely to be different, and the sampling clocks may also be different.
[0004] Therefore, the above-mentioned traditional method has the following disadvantages:
[0005] 1. The synchronization between devices using different FPGA clocks and sampling clocks can only be accurate to tens or even hundreds of nanoseconds, which is completely unable to meet the needs of current applications that require high-precision synchronization (such as MIMO).
[0006] 2. Even if the same frequency clock is used, the uncertainty of the clock phase relationship between different devices will lead to poor synchronization accuracy.
[0007] 3. The uncertainty of transmission delay and clock skew of different channels will also lead to poor synchronization accuracy. If the delay is adjusted inside the FPGA to offset this effect, the difficulty lies in measuring the transmission delay and clock skew, and the measured transmission delay cannot be reused between different multi-device systems. Summary of the invention
[0008] To solve the above problems, the present invention provides a multi-device high-precision synchronization system and method, which solves the problem of high-precision synchronization between devices with different frequency clocks.
[0009] The present invention provides a multi-device high-precision synchronization system, and the specific technical solution is as follows:
[0010] The system includes several synchronization devices, a high-frequency reference clock, a clock generator and a converter. The synchronization devices are connected through a synchronization control line group. The high-frequency reference clock is input into the clock generator. The clock generator outputs two clock signals, namely a sampling clock and an FPGA clock. The sampling clock is input into the converter, and the FPGA clock is input into the synchronization device.
[0011] The synchronization device includes a clock management module, a digital processing module, a data interaction module, a state machine and a corresponding state control module; the clock generator is connected to the clock management module through the processing module, and the state machine is controlled and connected with the data interaction module and the data processing module; the state machine is connected to the state machines of other synchronization devices through a synchronization control line group.
[0012] Furthermore, the high-frequency reference clock is 10 MHz, and the FPGA clock and sampling clock are integer multiples of the high-frequency reference clock.
[0013] Furthermore, the clock management module also includes an input and output interface of an external reference clock.
[0014] Furthermore, the external reference clock is 10 MHz.
[0015] Furthermore, the converter is an ADC module or a DAC module.
[0016] The present invention also provides a multi-device high-precision synchronization method based on the above system, and the specific scheme is as follows:
[0017] S1: Set one of the synchronous devices as the master device and the other synchronous devices as slave devices. The master and slave devices are initialized, the synchronization alignment of each clock is completed, and then enter the idle state.
[0018] S2: External trigger input, the master device enters the ready state and pulls down the synchronization signal line, and the slave device also enters the ready state after the falling edge on the synchronization signal line;
[0019] S3: When all devices are ready, both the master and slave devices enter the trigger state;
[0020] S4: After entering the trigger state, the master device receives the external trigger signal and pulls down the synchronization signal line at the rising edge of the next 10MHz clock to initiate synchronization and enter the sampling process.
[0021] Furthermore, in step S3, when all devices are ready, the ready signal line becomes high, and the slave device feeds back a ready completion signal to the master device. After the master device recognizes that all slave devices are ready, it releases the synchronization signal line, and all devices enter the trigger state together.
[0022] Furthermore, the synchronization device is in an operating state during sampling, and the operating state is a state in which the synchronization device performs its main functions.
[0023] Furthermore, when the synchronous device is in the running state, if the synchronous device executes a task of limited duration, the ready signal line is continuously pulled low until the task is completed, and after completion, the synchronous device enters the idle or triggered state together with other synchronous devices.
[0024] Furthermore, when the synchronization device is in the running state, if the synchronization device executes a task of infinite duration, the ready signal line is released in the running state, allowing other synchronization devices to continue to use the ready signal line in subsequent synchronization operations.
[0025] The beneficial effects of the present invention are as follows:
[0026] The trigger pulse is generated by synchronizing the FPGA clock, sampling clock and trigger pulse to avoid timing degradation. At the same time, a cycle longer than the transmission delay is created as the trigger clock cycle. All FPGA clock cycles and sampling clock cycles are integer multiples of the trigger clock cycle, avoiding the uncertainty caused by the transmission delay of the cable and the clock skew, and achieving precise triggering of precise pulses. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 It is a schematic diagram of the system framework.
[0028] Figure 2 It is a schematic diagram of the interconnection structure between multiple devices.
[0029] Figure 3 It is a state diagram of the state machine. DETAILED DESCRIPTION
[0030] The following description clearly and completely describes the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0031] In the description of the embodiments of the present invention, it should be noted that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the invention product is usually placed when in use, or the orientation or positional relationship commonly understood by those skilled in the art, or the orientation or positional relationship in which the invention product is usually placed when in use, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0032] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0033] Example 1
[0034] Embodiment 1 of the present invention discloses a multi-device high-precision synchronization system, such as Figure 1 As shown, the system includes several synchronization devices, a high-frequency reference clock, a clock generator, and a converter;
[0035] One of the synchronization devices is recorded as the master device, and the other synchronization devices are recorded as slave devices;
[0036] The synchronization devices are connected via a synchronization control line group, the high-frequency reference clock is input into a clock generator, and the clock generator outputs two clock signals, namely a sampling clock and an FPGA clock;
[0037] In this embodiment, the high-frequency reference clock is 10 MHz, and the FPGA clock and the sampling clock are integer multiples of the high-frequency reference clock.
[0038] Specifically, the FPGA clock and sampling clock can be generated by directly multiplying the 10MHz, or can be generated by another high-frequency reference clock that is the same source as the 10MHz, and calibrated with the 10MHz during the initialization phase to synchronize the three.
[0039] The sampling clock is input into the converter, and the FPGA clock is input into the synchronization device;
[0040] Specifically, the converter is an ADC module or a DAC module.
[0041] The synchronization device includes a clock management module, a digital processing module, a data interaction module, a state machine and a corresponding state control module;
[0042] The clock generator is connected to the clock management module through the processing module, and one of the clock signals output by the clock generator is processed once to obtain the FPGA clock, and is input into the clock management module after secondary processing. The state machine is controlled and connected with the data interaction module and the data processing module; the state machine is connected with the state machines of other synchronization devices through a synchronization control line group.
[0043] In this embodiment, the clock management module also includes an input and output interface of an external reference clock.
[0044] Specifically, the external reference clock is 10 MHz.
[0045] When there is an independent external 10MHz reference, both the master and slave devices can use this reference. When there is no independent external 10MHz reference, the master device uses its internal 10MHz output as the external 10MHz reference of the slave device to ensure 10MHz synchronization between the master and slave devices.
[0046] Example 2
[0047] Embodiment 2 of the present invention discloses a multi-device high-precision synchronization method based on the above embodiment 1, such as Figure 2 and Figure 3 As shown, the details are as follows:
[0048] S1: Set one of the synchronous devices as the master device and the other synchronous devices as slave devices. The master and slave devices are initialized, the synchronization alignment of each clock is completed, and then enter the idle state.
[0049] Specifically, the idle state represents a benign non-operational state, and the control module of the state machine can force the device to maintain the idle state; usually, the host loads the initial configuration parameters into the device at this time.
[0050] S2: External trigger input, the master device enters the ready state and pulls down the synchronization signal line, and the slave device also enters the ready state after the falling edge on the synchronization signal line;
[0051] The synchronization signal line is a signal line of the synchronization control line group, which is initiated by the master device and received by all slave devices;
[0052] S3: When all devices are ready, both the master and slave devices enter the trigger state;
[0053] Specifically, when all devices are ready, the ready signal line becomes high, and the slave device feeds back a ready completion signal to the master device. After the master device recognizes that all slave devices are ready, it releases the synchronization signal line, and all devices enter the trigger state together.
[0054] The ready signal line is a signal line of the control line group and is a signal line shared by all slave devices. The signal line will be high level only when all slave devices are released, otherwise it will be low level;
[0055] S4: After entering the trigger state, the master device receives the external trigger signal and pulls down the synchronization signal line at the rising edge of the next 10MHz clock to initiate synchronization and enter the sampling process.
[0056] In this embodiment, the synchronization device is in a running state during sampling, and the running state is a state in which the synchronization device performs its main function;
[0057] When the synchronous device is in the running state, if the synchronous device executes a task of limited duration, the ready signal line is continuously pulled low until the task is completed, and after completion, the synchronous device enters the idle or triggered state together with other synchronous devices.
[0058] When the synchronization device is in the running state, if the synchronization device executes a task of infinite duration, the ready signal line is released in the running state, allowing other synchronization devices to continue to use the ready signal line in subsequent synchronization operations.
[0059] Releasing the ready signal line means giving up the device's control over the signal line. When all slave devices are released, the ready signal line will return to a high level.
[0060] The present invention is not limited to the above-mentioned specific embodiments, but extends to any new features or any new combination disclosed in this specification, as well as any new method or process steps or any new combination disclosed.
Claims
1. A multi-device high-precision synchronization system, characterized in that: The system includes several synchronization devices, a high-frequency reference clock, a clock generator and a converter. The synchronization devices are connected through a synchronization control line group. The high-frequency reference clock is input into the clock generator. The clock generator outputs two clock signals, namely a sampling clock and an FPGA clock. The sampling clock is input into the converter, and the FPGA clock is input into the synchronization device. The synchronization device includes a clock management module, a digital processing module, a data interaction module, a state machine and a corresponding state control module; the clock generator is connected to the clock management module through the processing module, and the state machine is controlled and connected with the data interaction module and the data processing module; the state machine is connected to the state machines of other synchronization devices through a synchronization control line group.
2. The multi-device high-precision synchronization system according to claim 1, characterized in that: The high-frequency reference clock is 10 MHz, and the FPGA clock and sampling clock are integer multiples of the high-frequency reference clock.
3. The multi-device high-precision synchronization system according to claim 1, characterized in that: The clock management module also includes an input and output interface for an external reference clock.
4. The multi-device high-precision synchronization system according to claim 3, characterized in that: The external reference clock is 10 MHz.
5. The multi-device high-precision synchronization system according to claim 1, characterized in that: The converter is an ADC module or a DAC module.
6. A multi-device high-precision synchronization method, characterized in that: Based on the multi-device high-precision synchronization system according to any one of claims 1 to 5, the method comprises: S1: Set one of the synchronous devices as the master device and the other synchronous devices as slave devices. The master and slave devices are initialized, the synchronization alignment of each clock is completed, and then enter the idle state. S2: External trigger input, the master device enters the ready state and pulls down the synchronization signal line, and the slave device also enters the ready state after the falling edge on the synchronization signal line; S3: When all devices are ready, both the master and slave devices enter the trigger state; S4: After entering the trigger state, the master device receives the external trigger signal and pulls down the synchronization signal line at the rising edge of the next 10MHz clock to initiate synchronization and enter the sampling process.
7. The multi-device high-precision synchronization method according to claim 6, characterized in that: In step S3, when all devices are ready, the ready signal line becomes high, and the slave device feeds back a ready completion signal to the master device. After the master device recognizes that all slave devices are ready, it releases the synchronization signal line, and all devices enter the trigger state together.
8. The multi-device high-precision synchronization method according to claim 6, characterized in that: During sampling, the synchronization device is in a running state, and the running state is a state in which the synchronization device performs its main functions.
9. The multi-device high-precision synchronization method according to claim 8, characterized in that: When the synchronous device is in the running state, if the synchronous device executes a task of limited duration, the ready signal line is continuously pulled low until the task is completed, and after completion, the synchronous device enters the idle or triggered state together with other synchronous devices.
10. The multi-device high-precision synchronization method according to claim 8, characterized in that: When the synchronization device is in the running state, if the synchronization device executes a task of infinite duration, the ready signal line is released in the running state, allowing other synchronization devices to continue to use the ready signal line in subsequent synchronization operations.