Clock synchronization system and method based on FPGA and vehicle electronic equipment

Abstract

The invention provides a clock synchronization system based on an FPGA (Field Programmable Gate Array). The clock synchronization system comprises an ADC (Analog to Digital Converter) and a phase discriminator, the phase discriminator is used for determining a first phase difference signal between the first local clock and a second local clock of the slave node; the ADC is used for converting the first phase difference signal into a second phase difference signal; the slave node is used for determining a time deviation according to the second phase difference signal, a first timestamp of the synchronization message sent from the master node, a second timestamp of the synchronization message arriving at the slave node, a third timestamp of the delay request message sent by the slave node and a fourth timestamp of the delay request message arriving at the master node; therefore, the phase difference between the master node and the slave node is determined by using the phase discriminator and the ADC, and the phase difference is considered when the time deviation is determined, so that the determination precision of the time deviation can be improved, and the synchronization precision between the master node and the slave node is further improved; and specific network and software configuration is not needed, so that the cost and the complexity are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of clock synchronization network, and in particular to a clock synchronization system and method based on FPGA and vehicle electronic equipment. Background Art

[0002] The 1588v2 protocol, also known as the IEEE 1588-2008 standard, provides sub-microsecond time synchronization accuracy. This high-precision time synchronization plays an important role in fields such as telecommunications, financial transactions, power systems, and industrial automation.

[0003] At present, the IEEE 1588 protocol can be combined with the BeiDou satellite navigation system to form the IEEE 1588 BeiDou satellite time server. The IEEE 1588 protocol can also make important contributions to the clock synchronization of the industrial Internet of Things. It can not only be used in traditional wired networks, but also extended to wireless network clock synchronization. The protocol plays an important role in industrial applications such as WLAN, optical data centers, and smart grids.

[0004] However, the existing time synchronization solutions have the following typical problems: 1. Complexity and cost: Implementing high-precision Precision Time Protocol (PTP) may require specific network hardware and software configuration, increasing system complexity and cost.

[0005] 2. The synchronization accuracy of existing solutions is mostly in the sub-microsecond and sub-nanosecond levels, and the synchronization accuracy is relatively low.

[0006] Based on this, there is an urgent need for a clock synchronization method and system to reduce the complexity and cost of the time synchronization system and improve the synchronization accuracy. Summary of the invention

[0007] In view of the problems existing in the prior art, the embodiments of the present invention provide a clock synchronization system, method and vehicle electronic equipment based on FPGA to solve or partially solve the technical problems of low synchronization accuracy and high cost of the clock synchronization system in the prior art.

[0008] In a first aspect of the present invention, a clock synchronization system based on a field programmable gate array (FPGA) is provided, the system comprising: a master node and a slave node; the master node comprises: an analog-to-digital converter ADC and a phase discriminator; wherein, The phase discriminator is used to determine a first phase difference signal between a first local clock of the master node and a second local clock of the slave node; the first phase difference signal is a voltage analog signal; The analog-to-digital converter ADC is used to convert the first phase difference signal into a second phase difference signal; the second phase difference signal is a voltage digital signal; The slave node is used to receive the synchronization message sent by the master node and send a delay request message to the master node; determine the time deviation between the first local clock and the second local clock according to the second phase difference signal, the first timestamp when the synchronization message is sent from the master node, the second timestamp when the synchronization message arrives at the slave node, the third timestamp when the delay request message is sent from the slave node, and the fourth timestamp when the delay request message arrives at the master node; adjust the timestamp of the second local clock according to the time deviation, so that the slave node keeps synchronized with the master node.

[0009] In the above solution, the slave node is specifically used for: determining a true phase difference between the first local clock and the second local clock according to the second phase difference signal, a maximum value that can be output by the ADC, and a maximum phase difference that can be measured by the phase discriminator; Determine the real time when the delay request message arrives at the master node according to the real phase difference, the fourth timestamp and the clock period of the second local clock; The time deviation is determined based on a first timestamp when the synchronization message is sent from the master node, a second timestamp when the synchronization message arrives at the slave node, a third timestamp when the delay request message is sent from the slave node, and the actual time when the delay request message arrives at the master node.

[0010] In the above solution, the slave node is specifically used for: According to the formula Determine the true phase difference between the first local clock and the second local clock phase ;in, Said is the second phase difference signal, is the maximum value that the ADC can output, is the maximum phase difference that can be measured by the phase discriminator.

[0011] In the above solution, the slave node is specifically used for: According to the formula Determine the actual time when the delay request message arrives at the master node ; wherein said is the fourth timestamp, the phase is the real phase difference, T is the clock period of the second local clock.

[0012] In the above solution, the phase difference calculation module is specifically used for: According to the formula Determine the time offset ;in, Said is the first timestamp, the is the second timestamp, the is the third timestamp, the It is the actual time when the delay request message arrives at the master node.

[0013] In the above solution, the slave node is specifically used for: Obtaining a timestamp of the first local clock; A sum of the timestamp of the first local clock and the time offset is determined as the timestamp of the second local clock.

[0014] A second aspect of the present invention provides a clock synchronization method based on FPGA, which is applied to the clock synchronization system based on FPGA described in any one of the first aspects, and the method comprises: Determine a first phase difference signal between a first local clock of the master node and a second local clock of the slave node by using a phase discriminator; the first phase difference signal is a voltage analog signal; The first phase difference signal is converted into a second phase difference signal by using an analog-to-digital converter ADC; the second phase difference signal is a voltage digital signal; The slave node is used to determine the time deviation between the first local clock and the second local clock according to the second phase difference signal, the first timestamp of the synchronization message sent from the master node, the second timestamp of the synchronization message arriving at the slave node, the third timestamp of the delay request message sent from the node, and the fourth timestamp of the delay request message arriving at the master node; the timestamp of the second local clock is adjusted according to the time deviation so that the slave node remains synchronized with the master node.

[0015] In the above scheme, the method of using the slave node to determine the time deviation between the first local clock and the second local clock according to the second phase difference signal, the first timestamp of the synchronization message sent from the master node, the second timestamp of the synchronization message arriving at the slave node, the third timestamp of the delay request message sent from the slave node, and the fourth timestamp of the delay request message arriving at the master node includes: determining a true phase difference between the first local clock and the second local clock according to the second phase difference signal, a maximum value that can be output by the ADC, and a maximum phase difference that can be measured by the phase discriminator; Determine the real time when the delay request message arrives at the master node according to the real phase difference, the fourth timestamp and the clock period of the second local clock; The time deviation is determined based on a first timestamp when the synchronization message is sent from the master node, a second timestamp when the synchronization message arrives at the slave node, a third timestamp when the slave node sends a response message, and the actual time when the delay request message arrives at the master node.

[0016] In the above solution, the determining of the true phase difference between the first local clock and the second local clock according to the second phase difference signal, the maximum value that can be output by the ADC, and the maximum phase difference that can be measured by the phase discriminator includes: According to the formula Determine the true phase difference between the first local clock and the second local clock phase ;in, Said is the second phase difference signal, is the maximum value that the ADC can output, is the maximum phase difference that can be measured by the phase discriminator.

[0017] A third aspect of the present invention provides a vehicle electronic device, comprising the FPGA-based clock synchronization system described in any one of the first aspects.

[0018] The present invention provides a clock synchronization system, method and vehicle electronic equipment based on FPGA, the system comprises: a master node and a slave node; the master node comprises: an analog-to-digital converter ADC and a phase discriminator; wherein the phase discriminator is used to determine a first phase difference signal between a first local clock of the master node and a second local clock of the slave node; the first phase difference signal is a voltage analog signal; the analog-to-digital converter ADC is used to convert the first phase difference signal into a second phase difference signal; the second phase difference signal is a voltage digital signal; the slave node is used to receive a synchronization message sent by the master node and send a delay request message to the master node; according to the second phase difference signal, a first timestamp of the synchronization message sent from the master node, a second timestamp of the synchronization message arriving at the slave node, the The time deviation between the first local clock and the second local clock is determined by the third timestamp of the delay request message sent from the slave node and the fourth timestamp of the delay request message arriving at the master node; the timestamp of the second local clock is adjusted according to the time deviation, so that the slave node is synchronized with the master node; in this way, the phase difference between the master node and the slave node is first determined by using the phase discriminator and ADC, and the phase difference is taken into account when determining the time deviation, so the accuracy of determining the time deviation can be improved, and this hardware synchronization method can further improve the synchronization accuracy, the accuracy can reach nanosecond level, thereby improving the synchronization accuracy between the master and slave nodes; and the present invention only needs to add a phase discriminator and ADC in the master node in hardware implementation, and does not require a specific network and related software configuration, thereby reducing cost and complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings: Figure 1 A schematic diagram of a message exchange process between a master and a slave node in the IEEE 1588 protocol according to an embodiment of the present invention is shown; Figure 2 A schematic diagram of the structure of a clock synchronization system based on FPGA according to an embodiment of the present invention is shown; Figure 3 A schematic diagram of the structure of a master node according to an embodiment of the present invention is shown; Figure 4 A schematic diagram of the structure of a slave node according to an embodiment of the present invention is shown; Figure 5 A schematic diagram of clock transmission between a master node and a slave node according to an embodiment of the present invention is shown; Figure 6 A schematic diagram showing a clock relationship between a master node and a slave node according to an embodiment of the present invention is shown; Figure 7 A schematic flow chart of a clock synchronization method based on FPGA according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0020] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0021] In order to better understand the technical solution of the present invention, the IEEE 1588 protocol standard is first introduced here. The 1588 protocol standard stipulates that there are master nodes 1 and slave nodes 2, and the master nodes 1 and slave nodes 2 are synchronized based on the IEEE 1588 protocol standard. The full name of the 1588 protocol is the precision clock synchronization protocol standard for network measurement and control systems. The basic function is that all clocks in a distributed network are synchronized with the most accurate clock. It defines a precise time protocol PTP (precision Time Protocol). The IEEE 1588 protocol defines five types of PTP messages: synchronization message (Sync), follow message (Follow_up), delay request message (Delay_req), delay response message (Delay_resp) and management message (Management).

[0022] Among them, the first four messages are mainly used for timestamp exchange. The specific timestamp exchange process diagram is as follows: Figure 1 As shown in the figure, the message sending and receiving process is as follows: 1. Master node 1 (MASTER) periodically sends out Sync messages and records the first timestamp when the Sync message leaves master node 1 ; 2. Master node 1 will first timestamp Encapsulate it into a Follow_up message and send it to slave node 2 (SLAVE); 3. Slave node 2 records the second timestamp when the Sync message arrives at slave node 2 ; 4. Send a delay request message Delay_req from node 2 and record the corresponding third timestamp ; 5. Master node 1 records the fourth timestamp when the Delay_req message arrives at master node 1 ; 6. Master node 1 sends a message with the fourth timestamp The delay request response message Delay_resp is sent to slave node 2.

[0023] However, during the message exchange process, due to the existence of a propagation path, when the master node 1 and the slave node 2 are not synchronized, the timestamp of the second local clock of the slave node 2 has a time deviation relative to the timestamp of the first local clock of the master node 1. offset The purpose of synchronization is to calculate the time deviation, and then adjust the timestamp of the second local clock of slave node 2 according to the time deviation, so as to achieve the purpose of master-slave node synchronization. The purpose of timestamp synchronization is to make the timestamp of the second local clock of slave node 2 relatively synchronized with the timestamp of the first local clock of master node 1.

[0024] Based on this, the present invention provides a clock synchronization system based on FPGA, such as Figure 2 As shown, the system includes: a master node 1 and a slave node 2; the master node 1 includes: an analog-to-digital converter ADC, a phase discriminator 11 and a first FPGA chip; the slave node 2 includes: a second FPGA chip; wherein, A phase discriminator 11, used to determine a first phase difference signal between a first local clock of the master node 1 and a second local clock of the slave node; the first phase difference signal is a voltage analog signal; The analog-to-digital converter ADC is used to convert the first phase difference signal into a second phase difference signal; the second phase difference signal is a voltage digital signal; Slave node 2 is used to receive the synchronization message sent by the master node and send a delay request message to the master node; determine the time deviation between the first local clock and the second local clock according to the second phase difference signal, the first timestamp when the synchronization message is sent from the master node, the second timestamp when the synchronization message arrives at the slave node, the third timestamp when the delay request message is sent from the slave node, and the fourth timestamp when the delay request message arrives at the master node; adjust the timestamp of the second local clock according to the time deviation so that the slave node keeps synchronized with the master node.

[0025] Specifically, refer to Figure 2, the master node 1 and the slave node 2 can use the same PCB circuit board, each PCB circuit board is equipped with an FPGA chip, and the master node 1 and the slave node 2 are both phase-locked loop (PLL) circuits. When designing the circuit, a jumper can be set on the hardware circuit board to determine the master-slave relationship of the two hardware circuit boards, thereby determining the master node 1 and the slave node 2. To ensure the symmetry between the links of the master node 1 and the slave node 2, the length of the PCB circuit board clock transceiver path and the PTP message transceiver path should be ensured to be consistent with the serpentine line.

[0026] The master node 1 and the slave node 2 both include a debugging interface Quick USB, and the host computer can debug and solidify the program of the first FPGA chip and the second FPGA chip respectively through the Quick USB interface.

[0027] In addition, in order to eliminate the influence of the frequency drift and frequency deviation of the crystal oscillator, slave node 2 does not use the local crystal oscillator, but directly uses the clock signal transmitted by master node 1 as the timestamp clock. In other words, master node 1 and slave node 2 use the same source clock.

[0028] Among them, the first FPGA chip can refer to Figure 3 The first FPGA chip includes: a master node clock synchronization protocol module 31, a first sending buffer module 32, a first receiving buffer module 33, a first local clock module 34, an A / D control module 35 and a phase measurement control module 36; wherein, The master node clock synchronization protocol module 31 is used to control the sending and receiving of messages; The first sending buffer module 32 is used to send the communication message in the master node clock synchronization protocol module 31 in Manchester encoding mode; The first receiving buffer module 33 is used to decode the corresponding communication message from the receiving path; The first local clock module 34 is used to maintain the first local clock of the master node 1; The A / D control module 35 is used to send a signal conversion control instruction to the analog-to-digital converter ADC; The phase measurement control module 36 is used to send a phase measurement instruction to the phase discriminator 11 .

[0029] Specifically, two groups of independent input ports are provided in the phase discriminator 11, one group of input ports is used to receive the clock signal of the first local clock of the master node 1, and the other group of input ports is used to receive the clock signal of the second local clock of the slave node 2. When the first local clock of the master node 1 is triggered, the phase measurement control module 36 will send a phase measurement instruction to the phase discriminator 11, and the phase discriminator 11 will detect the rising edge or falling edge of the clock signal of the first local clock and the clock signal of the second local clock. When the edge of the first local clock arrives, if the edge of the second local clock follows the first local clock, it is considered that the phase deviation is small; if the edge of the second local clock is ahead of or behind the edge of the first local clock, it is considered that the phase deviation is large, and the first phase difference signal is output at this time, and the first phase difference signal is a voltage analog signal at this time.

[0030] Then the A / D control module 35 sends a signal conversion control instruction to the analog-to-digital converter ADC, and the ADC converts the first phase difference signal into a second phase difference signal based on the signal conversion control instruction, and the second phase difference signal is a voltage digital signal. That is, the ADC is used to convert an analog signal into a voltage digital signal.

[0031] The structure of the second FPGA chip can be referenced Figure 4 The second FPGA chip includes: a slave node clock synchronization protocol module 41, a second sending buffer module 42, a second receiving buffer module 43, and a second local clock module 44; wherein, The slave node clock synchronization protocol module 41 is used to control the sending and receiving of messages; The second sending buffer module 42 is used to send the communication message in the slave node clock synchronization protocol module 41 in Manchester encoding mode; The second receiving buffer module 43 is used to decode the corresponding communication message from the receiving path; The second local clock module 44 is used to maintain the second local clock of the slave node 2 .

[0032] The second FPGA chip also includes: a phase difference calculation module 45 and a time deviation calculation module 46; wherein, a phase difference calculation module 45, configured to determine a true phase difference between the first local clock and the second local clock according to the second phase difference signal, a maximum value that can be output by the ADC, and a maximum phase difference that can be measured by the phase discriminator 11; The time deviation calculation module 46 is used to determine the real time when the delay request message arrives at the master node 1 according to the real phase difference, the fourth timestamp and the clock cycle of the second local clock; The time deviation is determined based on the first timestamp when the synchronization message is sent from the master node 1, the second timestamp when the synchronization message arrives at the slave node 2, the third timestamp when the delay request message is sent from the slave node 2, and the actual time when the delay request message arrives at the master node 1.

[0033] Furthermore, the clock transmission between the master node 1 and the slave node 2 can refer to Figure 5 ,exist Figure 5 In the figure, Clk1 is the crystal oscillator clock of the master node. Therefore, when the message is sent from the transmitter Tx1 of the master node 1 and reaches the receiver Rx2 of the slave node 2, the clock of the slave node 2 should be the Clk2 clock. Since there is a propagation path of a certain distance between the master node 1 and the slave node 2, there will be a phase difference between Clk2 and Clk1.

[0034] After slave node 2 feeds back the message to the receiving end Rx1 of master node 1 through the transmitting end Tx2 under the Clk2 clock, a Clk3 clock will be generated at this time. There will be a phase difference between Clk3 and Clk2. The waveform diagram of Clk1, Clk2 and Clk3 can be referred to Figure 6 . Combined Figure 2 , Figure 2 The Master_Clk in contains Clk1 and Clk3, and the Slave_Clk contains Clk2.

[0035] exist Figure 6 It can be seen that there is a phase difference Phase between Clk1 and Clk3.

[0036] Map to Figure 1 For the first timestamp For example, It refers to the time when the synchronization message is sent from the master node 1. The trigger clock is Clk1, and the timestamp clock is the first local clock Clk1 of the master node 1. Therefore is accurate. For the second timestamp For example, is the time when the synchronization message arrives at slave node 2. The trigger clock is Clk2, and the timestamp clock is the second local clock Clk2 of slave node 2. Therefore is accurate. For the third timestamp For example, is the time when the delay request message is sent from node 2. The trigger clock is Clk2, and the timestamp clock is the second local clock Clk2 of slave node 2. Therefore is precise. For the fourth timestamp For example, is the time when the delay request message arrives at the master node 1. The trigger clock is Clk3, and the timestamp clock is the first local clock Clk1 of the master node 1. Therefore There are errors.

[0037] from Figure 6 As can be seen, the real moment Should be Therefore, in order to ensure that the master node 1 and the slave node 2 are accurately synchronized, it is necessary to eliminate the influence of the phase difference between the first local clock and the second local clock on the synchronization accuracy. Then in one embodiment, the phase difference calculation module 45 is specifically used for: According to the formula Determine the true phase difference between the first local clock and the second local clock phase ;in, is the second phase difference signal, is the maximum value that the ADC can output, is the maximum phase difference that can be measured by the phase discriminator.

[0038] The maximum value that the ADC can output needs to be determined according to the resolution of the ADC. For example, if the resolution of the ADC is 12 bits, the maximum value that the ADC can output is 4096. The maximum phase difference that the phase discriminator 11 can measure is generally Radians or 360 degrees.

[0039] True phase difference phase After the determination, the phase difference calculation module 45 is further used to: According to the formula Determine the actual time when the delay request message arrives at master node 1 ;in, is the fourth timestamp, phase is the real phase difference, T is the clock period of the second local clock.

[0040] The actual time when the delay request message arrives at master node 1 After the determination, the phase difference calculation module 45 is further used to: According to the formula Determining time deviation ;in, is the first timestamp, is the second timestamp, is the third timestamp, It is the actual time when the delay request message arrives at master node 1.

[0041] After the time deviation is determined, slave node 2 may update the timestamp of the second local clock according to the time deviation, including: Get the timestamp of the first local clock; The sum of the time stamp of the first local clock and the time offset is determined as the time stamp of the second local clock.

[0042] The present invention first uses a phase discriminator and an ADC to determine the phase difference between a master node and a slave node, and takes the phase difference into consideration when determining a time deviation, thereby improving the accuracy of determining the time deviation, with an accuracy of nanoseconds, thereby improving the synchronization accuracy between the master and slave nodes; and the present invention only needs to add a phase discriminator and an ADC to the master node in hardware implementation, and does not require a specific network and related software configuration, thereby reducing costs and complexity.

[0043] Based on the same inventive concept as the above-mentioned embodiment, the present invention also provides a clock synchronization method based on FPGA, which is applied in the above-mentioned clock synchronization system based on FPGA. Figure 7 As shown, the method comprises the following steps: S710, using a phase identifier to determine a first phase difference signal between a first local clock of a master node and a second local clock of a slave node; the first phase difference signal is a voltage analog signal.

[0044] The phase discriminator is provided with two independent input ports, one of which is used to receive the clock signal of the first local clock of the master node, and the other is used to receive the clock signal of the second local clock of the slave node. When the first local clock of the master node is triggered, the phase measurement control module will send a phase measurement instruction to the phase discriminator, and the phase discriminator will detect the rising edge or falling edge of the clock signal of the first local clock and the clock signal of the second local clock. When the edge of the first local clock arrives, if the edge of the second local clock follows the first local clock, it is considered that the phase deviation is small; if the edge of the second local clock is ahead of or behind the edge of the first local clock, it is considered that the phase deviation is large, and the first phase difference signal is output at this time, and the first phase difference signal is a voltage analog signal.

[0045] S711, using ADC to convert the first phase difference signal into a second phase difference signal; the second phase difference signal is a voltage digital signal.

[0046] Then the A / D control module sends a signal conversion control instruction to the analog-to-digital converter ADC, and the ADC converts the first phase difference signal into a second phase difference signal based on the signal conversion control instruction, and the second phase difference signal is a voltage digital signal. That is, the ADC is used to convert an analog signal into a voltage digital signal.

[0047] S712, using the slave node to determine the time deviation between the first local clock and the second local clock according to the second phase difference signal, the first timestamp of the synchronization message sent from the master node, the second timestamp of the synchronization message arriving at the slave node, the third timestamp of the delay request message sent from the slave node, and the fourth timestamp of the delay request message arriving at the master node; adjust the timestamp of the second local clock according to the time deviation so that the slave node remains synchronized with the master node.

[0048] After the master node obtains the second phase difference signal fed back by the ADC, it sends the second phase difference signal to the slave node. The slave node can determine the time deviation between the first local clock and the second local clock based on the second phase difference signal, the first timestamp of the synchronization message sent from the master node, the second timestamp of the synchronization message arriving at the slave node, the third timestamp of the delay request message sent by the slave node, and the fourth timestamp of the delay request message arriving at the master node.

[0049] In one embodiment, the slave node determines the time deviation between the first local clock and the second local clock according to the second phase difference signal, the first timestamp of the synchronization message sent from the master node, the second timestamp of the synchronization message arriving at the slave node, the third timestamp of the response message sent by the slave node, and the fourth timestamp of the delay request message arriving at the master node, including: determining a true phase difference between the first local clock and the second local clock according to the second phase difference signal, a maximum value that can be output by the ADC, and a maximum phase difference that can be measured by the phase discriminator; Determine the real time when the delay request message arrives at the master node according to the real phase difference, the fourth timestamp and the clock cycle of the second local clock; The time deviation is determined based on the first timestamp when the synchronization message is sent from the master node, the second timestamp when the synchronization message arrives at the slave node, the third timestamp when the slave node sends the response message, and the actual time when the delay request message arrives at the master node.

[0050] In one embodiment, determining the true phase difference between the first local clock and the second local clock according to the second phase difference signal, the maximum value that can be output by the ADC, and the maximum phase difference that can be measured by the phase discriminator includes: According to the formula Determine the true phase difference between the first local clock and the second local clock phase ;in, is the second phase difference signal, is the maximum value that the ADC can output, is the maximum phase difference that can be measured by the phase discriminator.

[0051] In one implementation, determining the real time when the delay request message arrives at the master node according to the real phase difference, the fourth timestamp, and the clock period of the second local clock includes: According to the formula Determine the actual time when the delay request message arrives at the master node ;in, is the fourth timestamp, phase is the real phase difference, T is the clock period of the second local clock.

[0052] In one embodiment, the time deviation is determined according to a first timestamp when the synchronization message is sent from the master node, a second timestamp when the synchronization message arrives at the slave node, a third timestamp when the slave node sends a response message, and the actual time when the delay request message arrives at the master node, including: According to the formula Determining time deviation ;in, is the first timestamp, is the second timestamp, is the third timestamp, It is the actual time when the delay request message arrives at the master node.

[0053] In one embodiment, after the time deviation is determined, the method further includes: Get the timestamp of the first local clock; The sum of the time stamp of the first local clock and the time offset is determined as the time stamp of the second local clock.

[0054] The present invention further provides a vehicle electronic device, including the above-mentioned FPGA-based clock synchronization system. The specific structure and implementation principle of the system can be referred to the corresponding description above, so it will not be repeated here.

[0055] Through one or more embodiments of the present invention, the present invention has the following beneficial effects or advantages: The present invention provides a clock synchronization system, method and vehicle electronic equipment based on FPGA. The system comprises: a master node and a slave node; the master node comprises: an analog-to-digital converter ADC and a phase discriminator; wherein the phase discriminator is used to determine a first phase difference signal between a first local clock of the master node and a second local clock of the slave node; the first phase difference signal is a voltage analog signal; the analog-to-digital converter ADC is used to convert the first phase difference signal into a second phase difference signal; the second phase difference signal is a voltage digital signal; the slave node is used to receive a synchronization message sent by the master node and send a delay request message to the master node; determine the time deviation between the first local clock and the second local clock according to the second phase difference signal, a first timestamp when the synchronization message is sent from the master node, a second timestamp when the synchronization message arrives at the slave node, a third timestamp when the delay request message is sent from the slave node and a fourth timestamp when the delay request message arrives at the master node; adjust the timestamp of the second local clock according to the time deviation so that the slave node keeps synchronization with the master node. In this way, the phase difference between the master node and the slave node is first determined by using the phase discriminator and ADC, and the phase difference is taken into account when determining the time deviation, so the accuracy of determining the time deviation can be improved, and the accuracy can reach nanosecond level, thereby improving the synchronization accuracy between the master and slave nodes; and the present invention only needs to add a phase discriminator and ADC in the master node in hardware implementation, and does not require a specific network and related software configuration, thereby reducing cost and complexity.

[0056] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A clock synchronization system based on FPGA, characterized in that: The system comprises: a master node and a slave node; the master node comprises: an analog-to-digital converter ADC and a phase discriminator; wherein, The phase discriminator is used to determine a first phase difference signal between a first local clock of the master node and a second local clock of the slave node; the first phase difference signal is a voltage analog signal; The analog-to-digital converter ADC is used to convert the first phase difference signal into a second phase difference signal; the second phase difference signal is a voltage digital signal; The slave node is used to receive the synchronization message sent by the master node and send a delay request message to the master node; determine the time deviation between the first local clock and the second local clock according to the second phase difference signal, the first timestamp when the synchronization message is sent from the master node, the second timestamp when the synchronization message arrives at the slave node, the third timestamp when the delay request message is sent from the slave node, and the fourth timestamp when the delay request message arrives at the master node; adjust the timestamp of the second local clock according to the time deviation, so that the slave node keeps synchronized with the master node.

2. The system according to claim 1, characterized in that The slave node is specifically used for: determining a true phase difference between the first local clock and the second local clock according to the second phase difference signal, a maximum value that can be output by the ADC, and a maximum phase difference that can be measured by the phase discriminator; Determine the real time when the delay request message arrives at the master node according to the real phase difference, the fourth timestamp and the clock period of the second local clock; The time deviation is determined based on a first timestamp when the synchronization message is sent from the master node, a second timestamp when the synchronization message arrives at the slave node, a third timestamp when the delay request message is sent from the slave node, and the actual time when the delay request message arrives at the master node.

3. The system according to claim 2, characterized in that The slave node is specifically used for: According to the formula Determine the true phase difference between the first local clock and the second local clock phase ;in, Said is the second phase difference signal, is the maximum value that the ADC can output, is the maximum phase difference that can be measured by the phase discriminator.

4. The system according to claim 2, characterized in that The slave node is specifically used for: According to the formula Determine the actual time when the delay request message arrives at the master node ; wherein said is the fourth timestamp, the phase is the real phase difference, T is the clock period of the second local clock.

5. The system according to claim 2, characterized in that The phase difference calculation module is specifically used for: According to the formula Determine the time offset ;in, Said is the first timestamp, the is the second timestamp, the is the third timestamp, the It is the actual time when the delay request message arrives at the master node.

6. The system according to claim 1, wherein: The slave node is specifically used for: Obtaining a timestamp of the first local clock; A sum of the timestamp of the first local clock and the time offset is determined as the timestamp of the second local clock.

7. A clock synchronization method based on FPGA, characterized in that: Applied in the FPGA-based clock synchronization system according to any one of claims 1 to 6, the method comprises: Determine a first phase difference signal between a first local clock of a master node and a second local clock of a slave node by using a phase discriminator; the first phase difference signal is a voltage analog signal; The first phase difference signal is converted into a second phase difference signal by using an analog-to-digital converter ADC; the second phase difference signal is a voltage digital signal; The slave node is used to determine the time deviation between the first local clock and the second local clock according to the second phase difference signal, the first timestamp of the synchronization message sent from the master node, the second timestamp of the synchronization message arriving at the slave node, the third timestamp of the delay request message sent from the slave node, and the fourth timestamp of the delay request message arriving at the master node; the timestamp of the second local clock is adjusted according to the time deviation so that the slave node remains synchronized with the master node.

8. The method according to claim 7, characterized in that The determining, by the slave node, the time deviation between the first local clock and the second local clock according to the second phase difference signal, a first timestamp when a synchronization message is sent from the master node, a second timestamp when the synchronization message arrives at the slave node, a third timestamp when a delay request message is sent from the slave node, and a fourth timestamp when the delay request message arrives at the master node, includes: determining a true phase difference between the first local clock and the second local clock according to the second phase difference signal, a maximum value that can be output by the ADC, and a maximum phase difference that can be measured by the phase discriminator; Determine the real time when the delay request message arrives at the master node according to the real phase difference, the fourth timestamp and the clock period of the second local clock; The time deviation is determined based on a first timestamp when the synchronization message is sent from the master node, a second timestamp when the synchronization message arrives at the slave node, a third timestamp when the slave node sends a response message, and the actual time when the delay request message arrives at the master node.

9. The method according to claim 8, characterized in that The determining the real phase difference between the first local clock and the second local clock according to the second phase difference signal, the maximum value that can be output by the ADC, and the maximum phase difference that can be measured by the phase discriminator comprises: According to the formula Determine the true phase difference between the first local clock and the second local clock phase ;in, Said is the second phase difference signal, is the maximum value that the ADC can output, is the maximum phase difference that can be measured by the phase discriminator.

10. A vehicle electronic device, characterized in that: A clock synchronization system based on FPGA comprising any one of claims 1-6.

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