Embedded implementation method for network pressure test capable of customizing data content

Abstract

The invention discloses an embedded implementation method for a network pressure test capable of customizing data content, and relates to the technical field of bus pressure tests.The method comprises the following steps that S1, simulation data are prepared, and a 1GB continuous space is distributed in a DDR memory segment of embedded equipment to be used for storing the simulation data; according to the method, the bandwidth during bus limit transmission can be measured, and the transmitted message content can be customized; on the basis of customizable data content read and written by common DDR of software and logic, simulation data and a message list are pre-filled in the software, and after transmission parameters are set, DDR packet sending is read by the logic, so that the problem that only fixed message content can be transmitted during pressure testing is solved; according to the method, the transmission delay between two messages is shortened by adopting a logic mode of completing packaging and sending according to preset parameters and utilizing the characteristics of logic parallel task processing and waiting time minimization in the processing process.

Description

Technical Field

[0001] The invention relates to the technical field of bus stress testing, in particular to an embedded implementation method of a network stress test capable of customizing data content. Background Art

[0002] Bus stress testing measures the maximum transmission speed of the bus. The bandwidth calculation is completed by sending data packets at the fastest speed. It is usually completed using embedded nodes. When embedded devices transmit messages, a common method is to assemble the messages in the cache and send them as a whole to the logic, which then transmits them externally according to the transmission protocol.

[0003] The above method can customize the message content, but there will be a certain delay in the software packaging and transmission, and it is impossible to reach the limit of bus transmission. When using embedded devices for bus stress testing, the common method is to use logic to fix the transmission of a pre-configured message to form transmission pressure. The disadvantage of this method is that it has a narrow application range and is inflexible. It can be used as a temporary testing method, but it is not compatible with multiple application scenarios. For example, when testing the shortest time to send an image file, the fixed message content cannot meet the needs. Summary of the invention

[0004] The purpose of the present invention is to provide an embedded implementation method of network stress testing with customizable data content to solve the problems raised in the above background technology.

[0005] In order to solve the above technical problems, the present invention provides the following technical solution: an embedded implementation method of a network stress test with customizable data content, the method comprising the following steps: S1. Prepare simulation data. Allocate 1GB of continuous space in the embedded device DDR memory segment to store simulation data. Users can fill the data they want to transmit into any location within the allocated total range of the memory segment through DDR write operation. The data type can be arithmetic progression, random number and file. S2, maintain the message list, and provide various parameters of the message list to the embedded logic by writing registers, including the source address, destination address, load length, DDR offset address and data acquisition strategy of each message. After receiving these parameters, the logic will loop and execute the current message list before configuring the message list next time; S3, during data transmission, the user sends a command to the logic to start transmission. The command contains parameters such as execution time, message interval time, and execution times. The logic receives the command and starts transmission. Each time the message list is cycled, the state product is recorded to determine the starting position of the simulation data, the number of transmission messages, the number of transmission bytes, and whether to continue transmission in the next round of message transmission; S4. After the transmission is completed, the processor performs various reset operations.

[0006] Furthermore, in step S3, when transmitting data, the payload data content of the transmission message comes from the DDR memory area rather than the processor stack. The DDR has a large enough space to store the customized content required by the user for transmission, such as image and video data.

[0007] Furthermore, after the transmission starts, there is no need for upper-level software intervention. The logic completes the message list cyclic sending and state product calculation by itself. When the message sending interval is adjusted to 0, the message can be sent at the fastest speed to implement bus stress testing.

[0008] Compared with the prior art, the beneficial effect achieved by the present invention is that the method can not only measure the bandwidth of the bus during limit transmission, but also customize the content of the transmitted message.

[0009] This method includes two key points: First, the customizable data content based on DDR reading and writing by software and logic. The software pre-fills the simulation data and message list. After setting the transmission parameters, the logic reads the DDR package and sends it, which solves the problem that only fixed message content can be transmitted during stress testing.

[0010] The second is to use logic to complete the packaging and sending according to pre-set parameters; use the characteristics of logic parallel processing tasks and minimize the waiting time during the processing to shorten the transmission delay between two messages; the logic starts to execute the transmission after receiving the enable signal, and the logic is executed in sequence according to the order of messages in the message list. After each message is executed, the state product needs to be recorded, and a comprehensive judgment is made based on the number of executions and the execution time whether to continue execution until the end; at the same time, during the execution process, the logic fills the total number of transmitted messages and the total number of transmitted bytes into the register for the software to calculate the transmission bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings: Figure 1 is a flow chart of the present invention; Figure 2 It is a simulation data content customization process of the present invention and a result presentation diagram after customization is completed; Figure 3 This is the message transmission process of the present invention. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] See also Figure 1-3 The present invention provides a technical solution: an embedded implementation method for network stress testing with customizable data content, the method comprising the following steps (this application should be run on an embedded device, usually a ZYNQ chip. When implemented, the DDR memory segment needs to be initialized first. Since the DDR address segment of the ZYNQ chip is mapped one-to-one with the physical address segment, no initialization work is required. If it is other types of chips, DDR needs to be initialized first): S1. Prepare simulation data. Allocate 1GB of continuous space in the embedded device DDR memory segment to store simulation data. Users can fill the desired transmission data to any location in the memory segment that does not exceed the total allocation range through DDR write operations. The data type can be an arithmetic sequence, a random number, and a file. Configure one or several fixed data packets to the logic in advance and enable cyclic transmission to achieve bus stress testing. However, this method has a single function and is best used for a certain function of the product rather than all functions. When other transmission functions need to be completed, they will affect each other and have repeated functions. The present invention opens up a 1GB space in the embedded DDR memory segment, which can be larger depending on the situation. As a logical data acquisition area, users can fill the area with arbitrary data, and in this way, the customized message content transmission function is achieved; S2. Maintain the message list and provide various parameters of the message list to the embedded logic by writing registers, including the source address, destination address, load length, DDR offset address and the starting offset address StartAddr of the data acquisition strategy, the ending offset address EndAddr of the load data from DDR, and the single data acquisition length of each message. The source address, destination address, destination port and single data acquisition length usually remain unchanged during the transmission process. What needs to be calculated and saved is the location of the load part in the StartAddr to EndAddr area when each packet is assembled. After receiving these parameters, the logic will loop the current message list before configuring the message list next time; S3, during data transmission, the user sends a command to the logic to start transmission. The command contains parameters such as execution time, message interval time, and execution times. The logic receives the command and starts transmission. Each time the message list is cycled, the state product is recorded to determine the starting position of the simulation data, the number of transmission messages, the number of transmission bytes, and whether to continue transmission in the next round of message transmission; S4. After the transmission is completed, the processor performs various reset operations.

[0014] In step S3, when transmitting data, the payload data content of the transmission message comes from the DDR memory area rather than the processor stack. DDR has a large enough space to store the customized content required for user transmission, such as image and video data. The software and logic jointly access the DDR area to realize data interaction between the software and logic. The process of packet data interaction between the software and logic when each message is transmitted in the traditional way is concentrated in the transmission start segment. After the software completes the configuration of the DDR data segment, the data packet payload data in the logic transmission process is no longer obtained from the software, but is obtained from the DDR area by itself, and the statistical information is provided to the software to calculate the transmission bandwidth.

[0015] After the transmission starts, there is no need for upper-level software intervention. The logic completes the message list cyclic sending and state product calculation by itself. When the message sending interval is adjusted to 0, the message can be sent at the fastest speed to realize the bus stress test.

[0016] Working process: After initialization is completed, the DDR memory segment needs to be filled, for example, a 1K-byte arithmetic progression is filled at the offset address 0, a 1K-byte random number is filled at the offset address 1K-byte, and a file type data is filled at the offset address 2K-byte. This can be done directly using the memory assignment method. Any data can be filled into the DDR as needed. When in use, the logical data access address can be pointed to the offset address in the DDR where the corresponding type of data is located according to the message load requirements. In the actual use of the present invention, the upper computer interface software is used to fill in key parameters to generate data or read file data, and the simulation data is sent to the embedded software via Ethernet. The embedded software writes to the DDR memory after receiving the simulation data.

[0017] The software then configures the message list to be sent to the logic. The logic provides a register group to save the message list. The parameters of each message usually include the source address, destination address, destination port, the starting offset address StartAddr of the payload data from the DDR, the ending offset address EndAddr of the payload data from the DDR, the single acquisition length and the acquisition strategy. StartAddr and EndAddr are the range of data access for the payload data of the current message. When the message is transmitted, the payload data is obtained from the range of the data area. The single access length determines the length of each packet of data, and also determines the offset address from the DDR access range when the message is executed next time. For example, if the single access length is 100 bytes, the offset is 0 when the first round of data is sent, and the offset is 100 when the second round is sent, and the offset is shifted backwards in sequence. The access strategy also determines the offset address from the DDR access range when the message is executed next time. The access strategy is usually divided into stop after access and cyclic access. Stop after access means that when the next round of access exceeds EndAddr, access is taken from the position where the last successful access is taken. Cyclic access means that when the next round of access exceeds EndAddr, access starts again from the StartAddr position. After configuring the message list, the logic can determine how each message is transmitted.

[0018] After configuring the message list, the software needs to set the transmission parameters, including the transmission message interval, execution times, and execution time. The transmission message interval determines the transmission speed. When the transmission message interval is 0, the message is transmitted at the fastest speed. It can also be set to other values ​​for regular rate transmission. The execution times and execution time determine when the logic stops transmitting. Therefore, the logic needs to count and judge the execution times and execution time after transmitting a message list. After completing the transmission parameter setting, the software needs to send an enable signal to the logic.

[0019] After receiving the enable signal, the logic starts to execute the transmission. The logic executes in sequence according to the order of the messages in the message list. After each message is executed, the state product needs to be recorded, including the data acquisition address for the next transmission, the execution time of the next message calculated according to the message interval, the number of executions of the current message, the total number of transmitted messages, the total number of transmitted bytes, and the total transmission time. After executing a round of message lists, it is comprehensively determined whether to continue execution based on the number of executions and the execution time until the end. At the same time, during the execution process, the logic fills the total number of transmitted messages and the total number of transmitted bytes into the register for the software to read. After reading these statistical data, the software calculates the transmission bandwidth and displays it to the customer.

[0020] The above is a detailed introduction to the stress testing method for customizable data content of the present invention. It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0021] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0022] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0023] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The present invention is a block or a plurality of blocks. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An embedded implementation method for network stress testing with customizable data content, characterized in that: The method comprises the following steps: S1. Prepare simulation data. Allocate 1GB of continuous space in the embedded device DDR memory segment to store simulation data. Users can fill the data they want to transmit into any location within the allocated total range of the memory segment through DDR write operation. The data type can be arithmetic progression, random number and file. S2, maintain the message list, and provide various parameters of the message list to the embedded logic by writing registers, including the source address, destination address, load length, DDR offset address and data acquisition strategy of each message. After receiving these parameters, the logic will loop and execute the current message list before configuring the message list next time; S3, during data transmission, the user sends a command to the logic to start transmission. The command contains parameters such as execution time, message interval time, and execution times. The logic receives the command and starts transmission. Each time the message list is cycled, the state product is recorded to determine the starting position of the simulation data, the number of transmission messages, the number of transmission bytes, and whether to continue transmission in the next round of message transmission; S4. After the transmission is completed, the processor performs various reset operations.

2. The embedded implementation method of network stress testing with customizable data content according to claim 1 is characterized in that: In step S3, when transmitting data, the payload data content of the transmission message comes from the DDR memory area rather than the processor stack. DDR has a large enough space to store the customized content required by the user for transmission, such as image and video data.

3. The embedded implementation method of network stress testing with customizable data content according to claim 2 is characterized in that: After the transmission starts, there is no need for upper-level software intervention. The logic completes the message list cyclic sending and state product calculation by itself. When the message sending interval is adjusted to 0, the message can be sent at the fastest speed to realize the bus stress test.

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