A method, apparatus, device, and storage medium for protocol conversion of transactions.

Abstract

This invention relates to the field of multi-core processor technology and discloses a transaction protocol conversion method, apparatus, device, and storage medium. One end of a transaction protocol conversion component is connected to a processor using a first bus protocol, and the other end is connected to a master node using a second bus protocol. The transaction protocol conversion component receives transactions transmitted by the processor; according to the message format of the second bus protocol, it converts the transactions into transaction messages conforming to the second bus protocol. It then transmits a transaction message carrying a retransmission flag to the master node. The master node sends a retransmission response back to the processor through the transaction protocol conversion component. After receiving the retransmission response, the transaction protocol conversion component enters a waiting phase; upon receiving a retransmission notification from the master node, it retransmits the transaction message back to the master node. The transaction protocol conversion component implements the request channel conversion function for two different bus protocols and sets up a retransmission function to ensure the orderly processing of various transactions by the master node.

Description

Technical Field

[0001] This invention relates to the field of multi-core processor technology, and in particular to a transaction protocol conversion method, apparatus, device, and storage medium. Background Technology

[0002] With ever-increasing demands for computing power, the performance of single-core processors can no longer meet computational needs. The parallel computing capabilities of multi-core processor systems offer significantly higher processing power, making it a current trend in processor development. The Advanced eXtensible Interface (AXI) bus protocol is a crucial component of the Advanced Microcontroller Bus Architecture (AMBA) 3.0 protocol, representing a high-performance, high-bandwidth, and low-latency on-chip bus. AXI Coherency Extensions (ACE) and Coherent Hub Interface (CHI) protocols are cache coherency protocols used to maintain cache coherency in multi-core processor systems.

[0003] The CHI protocol, an evolution of the ACE protocol, is currently a popular protocol for cache coherency in multi-core processors and has a wider range of applications. Currently, there are only implementations of cache coherency based on the CHI protocol, which do not involve the processing of ACE-to-CHI conversion. This results in transactions generated by ACE processor cores being unable to be integrated into multi-core CPU systems with the CHI architecture.

[0004] It is evident that how to achieve the conversion of transactions under different protocols is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a transaction protocol conversion method, apparatus, device, and storage medium that can solve the problem that transactions generated by the ACE processor core cannot be accessed by the CHI architecture multi-core CPU system.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a transaction protocol conversion method, applicable to a transaction protocol conversion component. One end of the transaction protocol conversion component is connected to a processor of a first bus protocol, and the other end is connected to a master node of a second bus protocol. The method includes:

[0007] Receive transactions transmitted by the processor;

[0008] According to the message format of the second bus protocol, the transaction is converted into a transaction message conforming to the second bus protocol;

[0009] The transaction message is transmitted to the master node; wherein the transaction message carries a retransmission flag.

[0010] After receiving the retransmission response from the master node, it enters the waiting phase;

[0011] Upon receiving the retransmission notification from the master node, the transaction message is retransmitted to the master node.

[0012] On the one hand, after receiving the retransmission notification from the master node, retransmitting the transaction message to the master node includes:

[0013] Upon receiving the retransmission notification from the master node, it is determined whether the transaction identifier information carried in the retransmission notification is the same as the transaction identifier information carried in the retransmission response; wherein, the transaction identifier information includes the transaction number and the credit number;

[0014] If the transaction identifier information carried in the retransmission notification is the same as the transaction identifier information carried in the retransmission response, a transaction message carrying the transaction identifier information is transmitted to the master node so that the master node can process the transaction message after receiving it, provided that the transaction identifier information carried in the transaction message is consistent with the transaction identifier information carried in the retransmission notification it sends back.

[0015] On the one hand, after converting the transaction into a transaction message conforming to the second bus protocol, the process also includes:

[0016] Save transaction messages conforming to the second bus protocol to the register;

[0017] Upon receiving the retransmission notification from the master node, retransmitting the transaction message to the master node includes:

[0018] Upon receiving the retransmission notification from the master node, the transaction message is read from the register and transmitted to the master node.

[0019] On the one hand, it also includes:

[0020] After receiving the response information from the master node, the transaction message is deleted from the register.

[0021] On the one hand, the transactions include read channel transactions;

[0022] According to the message format of the second bus protocol, converting the transaction into a transaction message conforming to the second bus protocol includes:

[0023] The read address, read channel transaction number, and read channel transaction type carried in the read channel transaction are sent to the transaction management component as transaction management signals, so that the transaction management component can store the read address, read channel transaction number, and read channel transaction type corresponding to the read channel transaction;

[0024] Based on the data bit width and number of bits carried in the read channel transaction, a read channel transaction that satisfies the total data transmission volume of the second bus protocol is determined;

[0025] The field information corresponding to the read channel transaction that satisfies the total data transmission volume of the second bus protocol is converted into a transaction message that conforms to the second bus protocol; wherein, the field information includes the total data transmission volume of the second bus protocol, the read address, the read channel transaction number, the read channel transaction type, and the shared field.

[0026] On the one hand, the transactions include write channel transactions;

[0027] The transactions received from the processor include:

[0028] Receive write request signals conforming to the first bus protocol transmitted through the write request channel;

[0029] According to the message format of the second bus protocol, converting the transaction into a transaction message conforming to the second bus protocol includes:

[0030] The write address, write channel transaction number, and write channel transaction type carried in the write request signal are sent to the transaction management component as a transaction management signal, so that the transaction management component can store the write address, write channel transaction number, and write channel transaction type corresponding to the write request signal;

[0031] Based on the data bit width and number of bits carried in the write request signal, the total amount of data in the write request signal that satisfies the total amount of data transmission of the second bus protocol is determined;

[0032] Receive the total amount of write data that satisfies the write request signal transmitted through the write data channel;

[0033] The write data is cached in static random access memory;

[0034] When the write data transmission signal corresponding to the write data channel goes high, the number of write data splits is determined based on the single data transmission amount of the write data bus and the total amount of data in the write request signal.

[0035] The write data is read from the static random access memory and split into multiple sub-data according to the number of splits;

[0036] According to the message format of the second bus protocol, each sub-data is converted into a sub-data message conforming to the second bus protocol;

[0037] Transmitting the transaction message to the master node includes:

[0038] Each sub-data packet is transmitted to the master node.

[0039] On the one hand, the number of splits for the write data is determined based on the amount of data transmitted in a single write data bus and the total amount of data in the write request signal, including:

[0040] The total amount of data in the write request signal is divided by the amount of data transmitted in a single pass of the write data bus, and the quotient is used as the number of splits for the write data.

[0041] This invention also provides a transaction protocol conversion device, applicable to a transaction protocol conversion component. One end of the transaction protocol conversion component is connected to a processor of a first bus protocol, and the other end is connected to a master node of a second bus protocol. The device includes a receiving unit, a conversion unit, a transmission unit, a waiting unit, and a retransmission unit.

[0042] The receiving unit is used to receive transactions transmitted by the processor;

[0043] The conversion unit is used to convert the transaction into a transaction message conforming to the second bus protocol according to the message format of the second bus protocol.

[0044] The transmission unit is used to transmit the transaction message to the master node; wherein the transaction message carries a retransmission identifier.

[0045] The waiting unit is used to enter a waiting phase after receiving a retransmission response from the master node;

[0046] The retransmission unit is used to retransmit the transaction message to the master node after receiving the retransmission notification from the master node.

[0047] On the one hand, the retransmission unit is used to determine whether the transaction identification information carried in the retransmission notification and the transaction identification information carried in the retransmission response are the same after receiving the retransmission notification from the master node; wherein, the transaction identification information includes a transaction number and a credit number;

[0048] If the transaction identifier information carried in the retransmission notification is the same as the transaction identifier information carried in the retransmission response, a transaction message carrying the transaction identifier information is transmitted to the master node so that the master node can process the transaction message after receiving it, provided that the transaction identifier information carried in the transaction message is consistent with the transaction identifier information carried in the retransmission notification it sends back.

[0049] On the one hand, it also includes storage units;

[0050] The storage unit is used to save transaction messages conforming to the second bus protocol into a register;

[0051] The retransmission unit is used to read the transaction message from the register and transmit the transaction message to the master node after receiving the retransmission notification from the master node.

[0052] On the one hand, it also includes deletion units;

[0053] The deletion unit is used to delete the transaction message from the register after receiving the response information from the master node.

[0054] On the one hand, the transactions include read channel transactions;

[0055] The conversion unit includes a first sending subunit, a first determining subunit, and an information conversion subunit;

[0056] The first sending subunit is used to send the read address, read channel transaction number and read channel transaction type carried in the read channel transaction as a transaction management signal to the transaction management component, so that the transaction management component can store the read address, read channel transaction number and read channel transaction type corresponding to the read channel transaction;

[0057] The first determining subunit is used to determine a read channel transaction that satisfies the total data transmission volume of the second bus protocol based on the data bit width and the number of bits carried in the read channel transaction;

[0058] The information conversion subunit is used to convert the field information corresponding to the read channel transaction that satisfies the total data transmission volume of the second bus protocol into a transaction message that conforms to the second bus protocol; wherein, the field information includes the total data transmission volume of the second bus protocol, the read address, the read channel transaction number, the read channel transaction type, and the shared field.

[0059] On the one hand, the transactions include write channel transactions;

[0060] The receiving unit is used to receive write request signals conforming to the first bus protocol transmitted by the write request channel;

[0061] The conversion unit includes a second transmitting subunit, a second determining subunit, a receiving subunit, a buffering subunit, a third determining subunit, a reading subunit, a splitting subunit, and a sub-data conversion subunit;

[0062] The second sending subunit is used to send the write address, write channel transaction number and write channel transaction type carried in the write request signal as a transaction management signal to the transaction management component, so that the transaction management component can store the write address, write channel transaction number and write channel transaction type corresponding to the write request signal;

[0063] The second determining subunit is used to determine the total amount of data in the write request signal that satisfies the total amount of data transmission of the second bus protocol based on the data bit width and the number of bits carried in the write request signal.

[0064] The receiving subunit is used to receive the total amount of write data that satisfies the write request signal transmitted by the write data channel.

[0065] The cache subunit is used to cache the write data to static random access memory;

[0066] The third determining subunit is used to determine the number of splits of the write data based on the single data transmission amount of the write data bus and the total amount of data of the write request signal when the write data transmission signal corresponding to the write data channel is pulled high.

[0067] The read subunit is used to read the write data from the static random access memory;

[0068] The splitting subunit is used to split the write data into multiple sub-data according to the number of splits;

[0069] The sub-data conversion subunit is used to convert each sub-data into a sub-data message conforming to the second bus protocol according to the message format of the second bus protocol;

[0070] The transmission unit is used to transmit each sub-data packet to the master node.

[0071] On the one hand, the third determining subunit is used to divide the total amount of data in the write request signal by the amount of data transmitted in a single pass of the write data bus, and the quotient obtained is used as the number of splits of the write data.

[0072] This invention also provides a transaction protocol conversion device, comprising:

[0073] Memory, used to store computer programs;

[0074] A processor for executing the computer program to implement the protocol conversion method for transactions as described above.

[0075] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the transaction protocol conversion method described above.

[0076] This invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the above-described protocol conversion method for transactions.

[0077] As can be seen from the above technical solution, one end of the transaction protocol conversion component is connected to the processor of the first bus protocol, and the other end is connected to the master node of the second bus protocol. The transaction protocol conversion component receives transactions transmitted by the processor; according to the message format of the second bus protocol, it converts the transactions into transaction messages conforming to the second bus protocol. The transaction messages are then transmitted to the master node; the transaction messages carry a retransmission flag, indicating that the current transaction message supports retransmission. After receiving a transaction message, if the master node cannot process the transaction message immediately, it can send a retransmission response to the processor through the transaction protocol conversion component. After receiving the retransmission response from the master node, the transaction protocol conversion component enters a waiting phase. After receiving the retransmission notification from the master node, it indicates that the master node can process the transaction message in a timely manner, at which point the transaction protocol conversion component can retransmit the transaction message to the master node. The beneficial effect of this invention is that the transaction protocol conversion component implements the request channel conversion function for two different bus protocols, enabling various transactions conforming to the first bus protocol issued by the processor core to be accurately and timely converted into transactions conforming to the second bus protocol and sent to the master node for processing. To ensure the master node's processing performance, a retransmission function is implemented to guarantee the orderly processing of various transactions and prevent message loss due to untimely processing of transaction messages. Attached Figure Description

[0078] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0079] Figure 1 A flowchart illustrating a transaction protocol conversion method provided in an embodiment of the present invention;

[0080] Figure 2 A schematic diagram of the architecture of a transaction protocol conversion component provided in an embodiment of the present invention;

[0081] Figure 3A flowchart illustrating a method for processing read channel transactions according to an embodiment of the present invention;

[0082] Figure 4 A flowchart illustrating a write channel transaction processing method provided in an embodiment of the present invention;

[0083] Figure 5 A schematic diagram of the structure of a transaction protocol conversion device provided in an embodiment of the present invention;

[0084] Figure 6 This is a structural diagram of a transaction protocol conversion device provided in an embodiment of the present invention. Detailed Implementation

[0085] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0086] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0087] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0088] As an evolution of the ACE protocol, the CHI protocol has a wider range of applications. Depending on the system's drive performance, power consumption, and area requirements, the CHI architecture allows for flexible topology selection for component connections. Crossbar structures can be used for small systems, ring structures for medium-sized systems, and mesh structures for large systems.

[0089] Since some processor cores are still based on the ACE protocol, in order for them to connect to the CHI architecture system as Request Nodes (RNs), an interface that converts between the ACE and CHI protocols and also has RN functionality needs to be built. Furthermore, master nodes using the CHI protocol often handle a large number of transactions, and may not be able to process transactions transmitted by processors using the ACE protocol immediately, leading to a high risk of transaction packet loss.

[0090] Therefore, embodiments of the present invention provide a transaction protocol conversion method, apparatus, device, and storage medium. Through a transaction protocol conversion component, it implements a request channel conversion function between two different bus protocols, enabling various transactions issued by the processor core conforming to the first bus protocol to be accurately and promptly converted into transactions conforming to the second bus protocol and sent to the master node for processing. Considering the processing performance of the master node, a retransmission function is set up to ensure the orderly processing of various transactions by the master node and avoid the loss of transaction messages due to untimely processing.

[0091] Next, we will describe in detail a transaction protocol conversion method provided by an embodiment of the present invention. Figure 1 A flowchart of a transaction protocol conversion method provided in this embodiment of the invention is applicable to a transaction protocol conversion component. One end of the transaction protocol conversion component is connected to a processor of a first bus protocol, and the other end is connected to a master node of a second bus protocol. The method includes:

[0092] S101: Receives transactions transmitted by the processor.

[0093] In this embodiment of the invention, for ease of distinction, the device using the first bus protocol can be referred to as a processor (core), and the device using the second bus protocol can be referred to as a home node (HN). In order to enable the processor of the first bus protocol to access the system where the home node is located, the processor of the first bus protocol can be regarded as a request node (RN).

[0094] Processor-transmitted transactions can include write channel transactions and read channel transactions. Write channel transactions can include write data transactions and write channel no-data transactions; read channel transactions can include read data transactions and read channel no-data transactions. Write channel no-data transactions include cache line eviction transactions (Evicts), while read channel no-data transactions refer to no-data transactions other than Evicts.

[0095] S102: Convert the transaction into a transaction message conforming to the second bus protocol according to the message format of the second bus protocol.

[0096] The processor uses the first bus protocol, so the transactions transmitted by the processor also conform to the first bus protocol. In order to transmit the transactions transmitted by the processor to the master node so that the master node can process the transactions, the transaction format needs to be converted, transforming the transactions conforming to the first bus protocol into transaction messages conforming to the second bus protocol.

[0097] The transaction protocol conversion component can record the message format of the first bus protocol and the message format of the second bus protocol, thereby realizing the conversion between the first bus protocol and the second bus protocol.

[0098] S103: Transmit transaction messages to the master node.

[0099] In this embodiment of the invention, each processor can communicate with the master node through a transaction protocol conversion component. A master node can communicate with multiple processors, thus the number of transactions processed by the master node is often large. This can lead to the master node being unable to immediately process transaction messages transmitted by one or more processors. To address this, supporting a retransmission function can effectively prevent the master node from accumulating too many transaction messages, causing excessive load or even loss of transaction messages. Therefore, a retransmission function can be configured in the transaction protocol conversion component.

[0100] The transaction message can carry a retransmission flag. By carrying the retransmission flag, it indicates that the transaction message supports the retransmission function.

[0101] S104: After receiving the retransmission response from the master node, enter the waiting phase.

[0102] The processing method for each transaction message is similar. For ease of explanation, we will use the processing flow of one transaction message as an example.

[0103] After transmitting a transaction message to the master node, if the master node cannot process the transaction message immediately, it can send a retransmission response to the transaction protocol conversion component if the transaction message carries a retransmission flag. Upon receiving the retransmission response, the transaction protocol conversion component knows that the master node cannot process the transaction message at this time, and therefore can control the transaction message to enter a waiting phase.

[0104] S105: After receiving the retransmission notification from the master node, retransmit the transaction message to the master node.

[0105] When the master node is currently able to process a transaction message that has entered the waiting phase, it can send a retransmission notification to the transaction protocol conversion component. After receiving the retransmission notification from the master node, the transaction protocol conversion component can retransmit the transaction message to the master node.

[0106] The above description uses the processing flow of a single transaction message as an example. Considering that the number of transaction messages processed by the master node in actual applications is often large, in order to clearly distinguish different transaction messages, the master node can carry unique transaction identification information to distinguish transaction messages when sending retransmission responses and retransmission notifications. The transaction identification information may include the transaction number (TxnID) and the credit number (PCrdType).

[0107] After receiving the retransmission notification from the master node, the transaction protocol conversion component can determine whether the transaction identifier information carried in the retransmission notification is the same as the transaction identifier information carried in the retransmission response.

[0108] If the transaction identifier information carried in the retransmission notification is the same as that carried in the retransmission response, it indicates that the same transaction message is being addressed. In this case, the transaction protocol conversion component can determine the corresponding transaction message based on the transaction identifier information and then transmit the transaction message carrying the transaction identifier information to the master node. This allows the master node to process the transaction message after receiving it, provided that the transaction identifier information carried in the transaction message matches the transaction identifier information carried in the retransmission notification it sends back.

[0109] Figure 2 This is a schematic diagram of the architecture of a transaction protocol conversion component provided in an embodiment of the present invention. For the processing of write channel transactions and read channel transactions, the transaction protocol conversion component may include a write request conversion module (w_req), a read request conversion module (r_req), and a request generation module (req_gen).

[0110] The write request translation module receives write request signals (AWsignals) and write data (W) compliant with the ACE protocol transmitted by the processor. The write request translation module includes a data volume calculation module and static random access memory (SRAM). Write data can be cached in SRAM. The write request translation module can also transfer write data to the data generation module (dat_gen).

[0111] The read request conversion module receives read request signals (AR) compliant with the ACE protocol transmitted by the processor. This module can then send the read address, read channel transaction number, and read channel transaction type carried in the read request signal as transaction management signals (TM signals) to the transaction management unit. The transaction management unit can record relevant information for each transaction, with each transaction corresponding to one record. This record can include information corresponding to different fields such as address (Addr), transaction number (ID / TxnID), transaction type (AxSNP), identifier (DBID), status information (T_Stat), and conflict signal (sp).

[0112] The read / write response conversion module (rsp_br) can transmit Retry & PCrd signals to the request generation module.

[0113] The request generation module includes a Spec table and a Txn Reg module. The request generation module is used to convert the field information corresponding to the read channel transaction into transaction messages conforming to the second bus protocol; and to convert the sub-data corresponding to the write channel transaction into sub-data messages conforming to the second bus protocol. Figure 2 Taking the CHI protocol as an example of the second bus protocol, the request generation module can determine whether the transaction message transmitted to the master node carries retry signals, and identify the transaction identification information carried in the retry response and retry notification.

[0114] As can be seen from the above technical solution, one end of the transaction protocol conversion component is connected to the processor of the first bus protocol, and the other end is connected to the master node of the second bus protocol. The transaction protocol conversion component receives transactions transmitted by the processor; according to the message format of the second bus protocol, it converts the transactions into transaction messages conforming to the second bus protocol. The transaction messages are then transmitted to the master node; the transaction messages carry a retransmission flag, indicating that the current transaction message supports retransmission. After receiving a transaction message, if the master node cannot process the transaction message immediately, it can send a retransmission response to the processor through the transaction protocol conversion component. After receiving the retransmission response from the master node, the transaction protocol conversion component enters a waiting phase. After receiving the retransmission notification from the master node, it indicates that the master node can process the transaction message in a timely manner, at which point the transaction protocol conversion component can retransmit the transaction message to the master node. The beneficial effect of this invention is that the transaction protocol conversion component implements the request channel conversion function for two different bus protocols, enabling various transactions conforming to the first bus protocol issued by the processor core to be accurately and timely converted into transactions conforming to the second bus protocol and sent to the master node for processing. To ensure the master node's processing performance, a retransmission function is implemented to guarantee the orderly processing of various transactions and prevent message loss due to untimely processing of transaction messages.

[0115] In this embodiment of the invention, after converting a transaction into a transaction message conforming to the second bus protocol, the transaction message conforming to the second bus protocol can be saved in a register; after receiving a retransmission notification from the master node, the transaction message can be directly read from the register and transmitted to the master node.

[0116] After receiving the response from the master node, it indicates that the master node has completed processing the transaction message, and the transaction message can be deleted from the register at this time.

[0117] By saving transaction messages to registers, the loss of transaction messages can be avoided. After receiving the response information from the master node, the transaction message can be deleted from the register, preventing useless transaction messages from occupying register storage space for a long time and improving register utilization.

[0118] Transactions can include read channel transactions and write channel transactions. Different types of transactions have different processing procedures. Taking read channel transactions as an example... Figure 3 A flowchart of a method for processing read channel transactions provided in an embodiment of the present invention, the method comprising:

[0119] S301: The read address, read channel transaction number, and read channel transaction type carried in the read channel transaction are sent to the transaction management component as transaction management signals so that the transaction management component can store the read address, read channel transaction number, and read channel transaction type corresponding to the read channel transaction.

[0120] The read request conversion module of the transaction protocol conversion unit can receive read request signals and no data request signals transmitted by the processor through the read request channel. The processing methods for read request signals and no data request signals are similar; the following will take the read request signal as an example for further explanation.

[0121] The read request conversion module can send the read address (ARADDR), read channel transaction number (ARID), and read channel transaction type (ARSNOOP) carried in the read request signal as transaction management signals (TM signals) to the transaction manager (TM).

[0122] S302: Based on the data bit width and number of bits carried in the read channel transaction, determine the read channel transaction that satisfies the total data transmission volume of the second bus protocol.

[0123] The read request conversion module can calculate the total amount of data transferred in a read request.

[0124] In practical applications, the total data transfer volume can be calculated using the following formula: ARVolume = ARSIZE * ARLEN. Here, ARVolume represents the total data transfer volume of the read request, ARSIZE represents the data width of the read request, and ARLEN represents the number of data bits in the read request.

[0125] The data bit width and number of bits in the read request can be carried in the read request signal. Substituting the values ​​of these two parameters into the formula above, the total data transmission volume can be determined. The total data transmission volume can be 64 bytes.

[0126] S303: Convert the field information corresponding to the read channel transaction that satisfies the total data transmission volume of the second bus protocol into a transaction message that conforms to the second bus protocol.

[0127] The information in each field may include the total amount of data transmitted via the second bus protocol (Volume), the read address, the read channel transaction number, the read channel transaction type, and the shared domain (ARDOMAIN) corresponding to the read request signal.

[0128] It should be noted that, apart from the above-mentioned field information, the other fields of the second bus protocol can be filled in or deleted according to the protocol or functional requirements. Therefore, the bit width of the second bus protocol message depends on the requirements and is not limited here.

[0129] In practical applications, the read request conversion module can transmit the information of each field to the request generation module. The request generation module can then convert this field information into a transaction message conforming to the second bus protocol, based on the message format of the second bus protocol.

[0130] In this embodiment of the invention, by cooperating with the read request conversion module and the request generation module, the read request signal that conforms to the first bus protocol transmitted by the processor can be converted into a transaction message that conforms to the second bus protocol, thereby transmitting the transaction message to the master node that adopts the second bus protocol for processing, realizing the access of the read channel transaction generated by the processor core of the first bus protocol to the multi-core CPU system of the second bus protocol architecture.

[0131] Taking write channel transactions as an example, Figure 4 A flowchart of a write channel transaction processing method provided in an embodiment of the present invention, the method comprising:

[0132] S401: Receives a write request signal conforming to the first bus protocol transmitted via the write request channel.

[0133] The write request conversion module of the transaction protocol conversion unit can receive write request signals transmitted by the processor through the write request channel.

[0134] S402: The write address, write channel transaction number, and write channel transaction type carried in the write request signal are sent to the transaction management component as a transaction management signal so that the transaction management component can store the write address, write channel transaction number, and write channel transaction type corresponding to the write request signal.

[0135] The write request conversion module can send the write address (AWADDR), write channel transaction number (AWID), and write channel transaction type (AWSNOOP) carried in the write request signal to the transaction management component as a transaction management signal.

[0136] S403: Determine the total amount of data in the write request signal that satisfies the total data transmission volume of the second bus protocol based on the data bit width and the number of bits carried in the write request signal.

[0137] The write request transformation module can calculate the total amount of data in the write request.

[0138] In practical applications, the total data transfer volume of a write request can be calculated using the following formula: AWVolume = AWSIZE * AWLEN. Here, AWVolume represents the total data volume of the write request signal, AWSIZE represents the data bit width of the write request, and AWLEN represents the number of bits in the write request.

[0139] The data width and number of bits in the write request can be carried in the write request signal. Substituting the values ​​of these two parameters into the formula above, the total amount of data in the write request can be determined. The total amount of data can be 64 bytes.

[0140] S404: Receive the total amount of write data that satisfies the write request signal transmitted through the write data channel.

[0141] The processor can transmit write data to the write request conversion module through the write data channel.

[0142] S405: Cache write data to static random access memory.

[0143] The write request conversion module can have built-in static random access memory (SRAM) to cache write data.

[0144] S406: When the write data transmission signal corresponding to the write data channel is pulled high, the number of write data splits is determined based on the single data transmission amount of the write data bus and the total amount of data in the write request signal.

[0145] Each write data channel has its corresponding write data transmission signal (WLAST). When the write data transmission signal goes high, it indicates that the data transmission is complete. At this time, the write request conversion module can transmit the total data volume (AWVolume), write address, write channel transaction number, write channel transaction type, and the shared domain (AWDOMAIN) corresponding to the write request signal to the request generation module. Furthermore, the number of write data splits can be determined based on the single data transmission volume of the write data bus and the total data volume of the write request signal.

[0146] In practical applications, the total amount of data in the write request signal can be divided by the amount of data transferred in a single write data bus, and the quotient can be used as the number of write data splits.

[0147] For example, the data transfer volume of a single write bus is typically 16 bytes. When the total data volume of the write request signal is 64 bytes, the number of splits is 64 / 16 = 4.

[0148] S407: Read write data from static random access memory and split the write data into multiple sub-data according to the number of splits.

[0149] The write request conversion module can read write data from static random access memory, split the write data into multiple sub-data, and send the sub-data to the data generation module through the data bus (Wdata).

[0150] S408: Convert each sub-data into a sub-data message conforming to the second bus protocol according to the message format of the second bus protocol.

[0151] The data generation module can convert each sub-data into a sub-data message conforming to the second bus protocol, according to the message format of the second bus protocol.

[0152] S409: Transmit each sub-data packet to the master node.

[0153] The data generation module can transmit sub-data packets conforming to the second bus protocol to the master node through the request channel.

[0154] In this embodiment of the invention, by cooperating with the write request conversion module and the request generation module, the write request signal transmitted by the processor that conforms to the first bus protocol can be converted into a message that conforms to the second bus protocol, thereby transmitting the message to the master node that adopts the second bus protocol for processing, realizing the access of the write channel transaction generated by the processor core of the first bus protocol to the multi-core CPU system of the second bus protocol architecture.

[0155] The transaction protocol conversion component provided by this invention supports retransmission. Each retransmission consumes one credit. Specifically, when the master node cannot immediately process the initial request, it sends a retransmission response (RetryAck) to the transaction protocol conversion component. This retransmission response is sent to the request generation module via retransmission signals. The retransmission response can carry transaction identification information, including the transaction number and credit number. When the master node can process this information, it sends a retransmission notification (PCrdGrant) to the transaction protocol conversion component. This retransmission notification also contains the transaction identification information. Both the retransmission response and the retransmission notification are sent to the request generation module of the transaction protocol conversion component. The request generation module will only retransmit a transaction message with the same transaction number to the master node if it determines that the transaction identification information carried by the retransmission response and the retransmission notification are consistent.

[0156] In practical applications, the master node often supports up to 16 credits. In order to ensure the orderly processing of different transaction messages, 16 sets of registers can be used to store transaction messages.

[0157] After generating a transaction message, it can be stored in the corresponding register. If the transaction message is processed by the master node on the first transmission, the transaction protocol conversion unit, upon receiving the master node's response, will send a no-retry signal containing the transaction number to the request generation module. The request generation module will then clear the transaction message corresponding to that transaction number from its register. For transaction messages that were not processed by the master node on the first transmission, upon receiving a retransmission notification from the master node, the transaction message can be retrieved from the corresponding register based on the transaction number carried in the retransmission notification, and retransmitted to the master node. When the transaction protocol conversion unit receives the master node's response, it can clear the transaction message corresponding to that transaction number from its register.

[0158] For ease of description, AllowRetry can be used to indicate whether retransmission is supported. When AllowRetry=1, it indicates that retransmission is supported; when AllowRetry=0, it indicates that retransmission is not supported. In this embodiment of the invention, for the first transaction message sent, retransmission is supported by default, i.e., AllowRetry=1.

[0159] The credit number corresponding to different transaction messages can be represented by different numbers. Assuming that the master node supports a maximum of 16 credits, 0 to 15 can be used sequentially according to the processing order to represent 16 different credit numbers (PCrdType).

[0160] Taking the first transaction message as an example, its AllowRetry=1 and PCrdType=0. If a retransmission response is received from the master node, it needs to wait until a retransmission notification carrying the same transaction identifier information is received before the transaction message can be sent again. At this time, the AllowRetry corresponding to the transaction message is 0, and PCrdType is the credit number carried in the retransmission response and retransmission notification. The credit number will change during the waiting process. Assuming PCrdType=n, it means that the current master node has consumed n+1 credits.

[0161] Since the processor of the ACE protocol does not support retransmission, retransmission responses and retransmission notifications do not need to be sent to the processor. The retransmission function can be completed by the transaction protocol conversion component.

[0162] In this embodiment of the invention, the number of registers is set according to the processing performance of the master node, allowing different types of transaction messages to be stored in their corresponding registers, ensuring efficient querying and orderly processing of each transaction message. After the master node completes the processing of the transaction message, the transaction message in the corresponding register is deleted in a timely manner, preventing the retransmission function from being frequently occupied by the same transaction message.

[0163] Figure 5 This is a schematic diagram of a transaction protocol conversion device provided in an embodiment of the present invention. It is applicable to a transaction protocol conversion component. One end of the transaction protocol conversion component is connected to the processor of a first bus protocol, and the other end is connected to the master node of a second bus protocol. The device includes a receiving unit 51, a conversion unit 52, a transmission unit 53, a waiting unit 54, and a retransmission unit 55.

[0164] The receiving unit 51 is used to receive transactions transmitted by the processor;

[0165] The conversion unit 52 is used to convert transactions into transaction messages conforming to the second bus protocol according to the message format of the second bus protocol;

[0166] Transmission unit 53 is used to transmit transaction messages to the master node; wherein the transaction message carries a retransmission flag;

[0167] Waiting unit 54 is used to enter the waiting phase after receiving a retransmission response from the master node;

[0168] The retransmission unit 55 is used to retransmit the transaction message to the master node after receiving the retransmission notification from the master node.

[0169] In some embodiments, the retransmission unit is used to determine, after receiving a retransmission notification from the master node, whether the transaction identification information carried in the retransmission notification is the same as the transaction identification information carried in the retransmission response; wherein, the transaction identification information includes a transaction number and a credit number.

[0170] If the transaction identifier information carried in the retransmission notification is the same as that carried in the retransmission response, a transaction message carrying the transaction identifier information is transmitted to the master node. This allows the master node to process the transaction message after receiving it, provided that the transaction identifier information carried in the transaction message matches that carried in the retransmission notification it sent back.

[0171] In some embodiments, a storage unit is also included;

[0172] The storage unit is used to save transaction messages conforming to the second bus protocol into a register;

[0173] The retransmission unit is used to read the transaction message from the register and transmit the transaction message to the master node after receiving the retransmission notification from the master node.

[0174] In some embodiments, a deletion unit is also included;

[0175] The deletion unit is used to delete the transaction message from the register after receiving the response information from the master node.

[0176] In some embodiments, a transaction includes a read channel transaction;

[0177] The conversion unit includes a first transmitting subunit, a first determining subunit, and an information conversion subunit;

[0178] The first sending subunit is used to send the read address, read channel transaction number and read channel transaction type carried in the read channel transaction as a transaction management signal to the transaction management component, so that the transaction management component can store the read address, read channel transaction number and read channel transaction type corresponding to the read channel transaction;

[0179] The first determining subunit is used to determine the read channel transaction that satisfies the total data transmission volume of the second bus protocol based on the data bit width and the number of bits carried in the read channel transaction.

[0180] The information conversion subunit is used to convert the field information corresponding to the read channel transaction that satisfies the total data transmission volume of the second bus protocol into a transaction message that conforms to the second bus protocol; wherein, the field information includes the total data transmission volume of the second bus protocol, read address, read channel transaction number, read channel transaction type, and shared field.

[0181] In some embodiments, a transaction includes a write channel transaction;

[0182] The receiving unit is used to receive write request signals conforming to the first bus protocol transmitted by the write request channel;

[0183] The conversion unit includes a second transmitting subunit, a second determining subunit, a receiving subunit, a buffering subunit, a third determining subunit, a reading subunit, a splitting subunit, and a sub-data conversion subunit;

[0184] The second sending subunit is used to send the write address, write channel transaction number and write channel transaction type carried in the write request signal to the transaction management unit as a transaction management signal, so that the transaction management unit can store the write address, write channel transaction number and write channel transaction type corresponding to the write request signal;

[0185] The second determining subunit is used to determine the total amount of data in the write request signal that satisfies the total amount of data transmission of the second bus protocol, based on the data bit width and the number of bits carried in the write request signal.

[0186] The receiving subunit is used to receive the total amount of write data that satisfies the write request signal transmitted through the write data channel;

[0187] The cache subunit is used to cache write data to static random access memory;

[0188] The third determining subunit is used to determine the number of write data splits based on the single data transmission amount of the write data bus and the total amount of data of the write request signal when the write data transmission signal corresponding to the write data channel is pulled high.

[0189] The read subunit is used to read and write data from static random access memory;

[0190] Split sub-units are used to split write data into multiple sub-data according to the number of splits;

[0191] The sub-data conversion sub-unit is used to convert each sub-data into a sub-data message conforming to the second bus protocol according to the message format of the second bus protocol;

[0192] The transmission unit is used to transmit each sub-data packet to the master node.

[0193] In some embodiments, the third determining subunit is used to divide the total amount of data in the write request signal by the amount of data transmitted in a single pass of the write data bus, and the quotient is used as the number of write data splits.

[0194] Figure 5 For a description of the features in the corresponding embodiments, please refer to Figure 1 The relevant descriptions of the corresponding embodiments will not be repeated here.

[0195] As can be seen from the above technical solution, one end of the transaction protocol conversion component is connected to the processor of the first bus protocol, and the other end is connected to the master node of the second bus protocol. The transaction protocol conversion component receives transactions transmitted by the processor; according to the message format of the second bus protocol, it converts the transactions into transaction messages conforming to the second bus protocol. The transaction messages are then transmitted to the master node; the transaction messages carry a retransmission flag, indicating that the current transaction message supports retransmission. After receiving a transaction message, if the master node cannot process the transaction message immediately, it can send a retransmission response to the processor through the transaction protocol conversion component. After receiving the retransmission response from the master node, the transaction protocol conversion component enters a waiting phase. After receiving the retransmission notification from the master node, it indicates that the master node can process the transaction message in a timely manner, at which point the transaction protocol conversion component can retransmit the transaction message to the master node. The beneficial effect of this invention is that the transaction protocol conversion component implements the request channel conversion function for two different bus protocols, enabling various transactions conforming to the first bus protocol issued by the processor core to be accurately and timely converted into transactions conforming to the second bus protocol and sent to the master node for processing. To ensure the master node's processing performance, a retransmission function is implemented to guarantee the orderly processing of various transactions and prevent message loss due to untimely processing of transaction messages.

[0196] Figure 6A structural diagram of a transaction protocol conversion device provided in an embodiment of the present invention is shown below. Figure 6 As shown, the transaction protocol conversion device includes: a memory 60 for storing computer programs;

[0197] The processor 61 is used to implement the steps of the protocol conversion method as described in the above embodiments when executing a computer program.

[0198] The protocol conversion device for transactions provided in this embodiment may include, but is not limited to, smartphones, tablets, laptops, or desktop computers.

[0199] The processor 61 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 61 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 61 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 61 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0200] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 60 is used to store at least the following computer program 601, which, after being loaded and executed by the processor 61, is capable of implementing the relevant steps of the transaction protocol conversion method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, and the storage method may be temporary or permanent storage. The operating system 602 may include Windows, Unix, Linux, etc. The data 603 may include, but is not limited to, transaction messages, retransmitted responses, retransmitted notifications, etc.

[0201] In some embodiments, the transaction protocol conversion device may further include a display screen 62, an input / output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.

[0202] Those skilled in the art will understand that Figure 6 The structure shown does not constitute a limitation on the protocol conversion device for transactions and may include more or fewer components than illustrated.

[0203] It is understood that if the transaction protocol conversion method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk, or optical disk, and other media capable of storing program code.

[0204] Based on this, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described transaction protocol conversion method.

[0205] This invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the above-described protocol conversion method for transactions.

[0206] The foregoing has provided a detailed description of a transaction protocol conversion method, apparatus, device, and computer-readable storage medium provided by embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0207] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0208] The present invention has provided a detailed description of a transaction protocol conversion method, apparatus, device, and computer-readable storage medium. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of these embodiments are merely illustrative and are intended to aid in understanding the method and core concepts of the invention. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.

Claims

1. A transaction protocol conversion method, characterized in that, Applicable to a transaction protocol conversion component, wherein one end of the transaction protocol conversion component is connected to a processor of a first bus protocol and the other end is connected to a master node of a second bus protocol, the method includes: Receive transactions transmitted by the processor; According to the message format of the second bus protocol, the transaction is converted into a transaction message conforming to the second bus protocol; The transaction message is transmitted to the master node; wherein the transaction message carries a retransmission flag. After receiving the retransmission response from the master node, it enters the waiting phase; After receiving the retransmission notification from the master node, the transaction message is retransmitted to the master node. Upon receiving the retransmission notification from the master node, retransmitting the transaction message to the master node includes: Upon receiving the retransmission notification from the master node, it is determined whether the transaction identifier information carried in the retransmission notification is the same as the transaction identifier information carried in the retransmission response; wherein, the transaction identifier information includes the transaction number and the credit number; If the transaction identifier information carried in the retransmission notification is the same as the transaction identifier information carried in the retransmission response, a transaction message carrying the transaction identifier information is transmitted to the master node so that the master node can process the transaction message after receiving it, provided that the transaction identifier information carried in the transaction message is consistent with the transaction identifier information carried in the retransmission notification it sends back.

2. The transaction protocol conversion method according to claim 1, characterized in that, After converting the transaction into a transaction message conforming to the second bus protocol, the following is also included: Save transaction messages conforming to the second bus protocol to the register; Upon receiving the retransmission notification from the master node, retransmitting the transaction message to the master node includes: Upon receiving the retransmission notification from the master node, the transaction message is read from the register and transmitted to the master node.

3. The transaction protocol conversion method according to claim 2, characterized in that, Also includes: After receiving the response information from the master node, the transaction message is deleted from the register.

4. The transaction protocol conversion method according to claim 1, characterized in that, The transactions include read channel transactions; According to the message format of the second bus protocol, converting the transaction into a transaction message conforming to the second bus protocol includes: The read address, read channel transaction number, and read channel transaction type carried in the read channel transaction are sent to the transaction management component as transaction management signals, so that the transaction management component can store the read address, read channel transaction number, and read channel transaction type corresponding to the read channel transaction; Based on the data bit width and number of bits carried in the read channel transaction, a read channel transaction that satisfies the total data transmission volume of the second bus protocol is determined; The field information corresponding to the read channel transaction that satisfies the total data transmission volume of the second bus protocol is converted into a transaction message that conforms to the second bus protocol; wherein, the field information includes the total data transmission volume of the second bus protocol, the read address, the read channel transaction number, the read channel transaction type, and the shared field.

5. The transaction protocol conversion method according to claim 1, characterized in that, The transaction includes write channel transactions; The transactions received from the processor include: Receive write request signals conforming to the first bus protocol transmitted through the write request channel; According to the message format of the second bus protocol, converting the transaction into a transaction message conforming to the second bus protocol includes: The write address, write channel transaction number, and write channel transaction type carried in the write request signal are sent to the transaction management component as a transaction management signal, so that the transaction management component can store the write address, write channel transaction number, and write channel transaction type corresponding to the write request signal; Based on the data bit width and number of bits carried in the write request signal, the total amount of data in the write request signal that satisfies the total amount of data transmission of the second bus protocol is determined; Receive the total amount of write data that satisfies the write request signal transmitted through the write data channel; The write data is cached in static random access memory; When the write data transmission signal corresponding to the write data channel goes high, the number of write data splits is determined based on the single data transmission amount of the write data bus and the total amount of data in the write request signal. The write data is read from the static random access memory and split into multiple sub-data according to the number of splits; According to the message format of the second bus protocol, each sub-data is converted into a sub-data message conforming to the second bus protocol; Transmitting the transaction message to the master node includes: Each sub-data packet is transmitted to the master node.

6. The transaction protocol conversion method according to claim 5, characterized in that, The number of write data splits is determined based on the single data transfer volume of the write data bus and the total data volume of the write request signal, including: The total amount of data in the write request signal is divided by the amount of data transmitted in a single pass of the write data bus, and the quotient is used as the number of splits for the write data.

7. A transaction protocol conversion device, characterized in that, The device is applicable to a transaction protocol conversion component, one end of which is connected to a processor of a first bus protocol and the other end of which is connected to a master node of a second bus protocol. The device includes a receiving unit, a conversion unit, a transmission unit, a waiting unit, and a retransmission unit. The receiving unit is used to receive transactions transmitted by the processor; The conversion unit is used to convert the transaction into a transaction message conforming to the second bus protocol according to the message format of the second bus protocol. The transmission unit is used to transmit the transaction message to the master node; wherein the transaction message carries a retransmission identifier. The waiting unit is used to enter a waiting phase after receiving a retransmission response from the master node; The retransmission unit is configured to retransmit the transaction message to the master node after receiving a retransmission notification from the master node; after receiving the retransmission notification from the master node, it determines whether the transaction identifier information carried in the retransmission notification is the same as the transaction identifier information carried in the retransmission response; wherein the transaction identifier information includes a transaction number and a credit number; if the transaction identifier information carried in the retransmission notification is the same as the transaction identifier information carried in the retransmission response, it transmits a transaction message carrying the transaction identifier information to the master node, so that the master node can process the transaction message after receiving it if the transaction identifier information carried in the transaction message is consistent with the transaction identifier information carried in its retransmission notification.

8. A transaction protocol conversion device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the protocol conversion method for transactions as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the transaction protocol conversion method as described in any one of claims 1 to 6.

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