Method and device for realizing wireless communication algorithm, and computer readable medium

Abstract

The invention provides a method and a device for realizing a wireless communication algorithm, and a computer readable medium. The device for realizing the wireless communication algorithm comprises an algorithm realization module; wherein the algorithm implementation module comprises a central processing unit, a crossbar switch and an operator unit; wherein the operator unit realizes a corresponding data processing algorithm through hardware; wherein the central processing unit is configured to read microcode configuration information corresponding to a wireless communication algorithm; wherein the microcode configuration information comprises hardware connection configuration information and hardware unit configuration information; controlling a crossbar switch to connect the operator units into a combined operator unit according to the hardware connection configuration information; operator units in the combined operator unit are configured according to the hardware unit configuration information, so that the combined operator unit can realize a corresponding data processing algorithm; and the combined operator unit is configured to obtain to-be-processed data according to the configuration of the combined operator unit and perform corresponding data processing to obtain output data.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communication technology, and in particular, to a method and device for implementing a wireless communication algorithm, and a computer-readable medium. Background Art

[0002] Generally, in order to achieve high-quality wireless communication between base stations and terminals, several processes are required, including: cell search, cell measurement, cell residence and cell reconnection, as well as random access, channel estimation, channel feedback, multiple transmission and multiple reception, encoding and decoding, etc. The algorithms for implementing these processes have both similarities and differences. The current implementation method cannot take into account both algorithm flexibility and power consumption. Summary of the invention

[0003] The embodiments of the present application provide a method and device for implementing a wireless communication algorithm, and a computer-readable medium.

[0004] In a first aspect, an embodiment of the present application provides a device for implementing a wireless communication algorithm, comprising: at least one algorithm implementation module; wherein the algorithm implementation module comprises: at least one central processing unit, a cross switch and at least one operator unit; wherein the operator unit implements a corresponding data processing algorithm through hardware; wherein the central processing unit is configured to: read microcode configuration information corresponding to the wireless communication algorithm; wherein the microcode configuration information comprises: hardware connection configuration information and hardware unit configuration information; according to the hardware connection configuration information, control the cross switch to connect part or all of the operator units into a combination operator unit; according to the hardware unit configuration information, configure the operator units in the combination operator unit so that the combination operator unit can implement the corresponding data processing algorithm; the combination operator unit is configured to: obtain the data to be processed according to the configuration of the combination operator unit and perform corresponding data processing to obtain output data.

[0005] In a second aspect, an embodiment of the present application provides a method for implementing a wireless communication algorithm, comprising: reading microcode configuration information corresponding to the wireless communication algorithm; wherein the microcode configuration information comprises: hardware connection configuration information and hardware unit configuration information; according to the hardware connection configuration information, controlling part or all of the operator units to be connected into a combination operator unit through a cross switch; configuring the operator units in the combination operator unit according to the hardware unit configuration information so that the combination operator unit can implement the corresponding data processing algorithm; wherein the operator unit implements the corresponding data processing algorithm through hardware; the combination operator unit obtains the data to be processed according to the configuration of the combination operator unit and performs corresponding data processing to obtain output data.

[0006] In a third aspect, an embodiment of the present application provides a computer-readable medium having a computer program stored thereon, and when the computer program is executed by a processor, any one of the above-mentioned methods for implementing a wireless communication algorithm is implemented.

[0007] The device for implementing a wireless communication algorithm provided in the embodiment of the present application realizes the corresponding wireless communication algorithm by arbitrarily combining operator units. Since the operator units realize the corresponding data processing algorithm through hardware, the flexibility is improved, the data processing efficiency is improved, and the power consumption is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram of a device for implementing a wireless communication algorithm provided by an embodiment of the present application;

[0009] Figure 2 A flowchart of a method for implementing a wireless communication algorithm provided by another embodiment of the present application;

[0010] Figure 3 A block diagram of a device for a time-series wireless communication algorithm provided in Example 1 of an embodiment of the present application;

[0011] Figure 4 A block diagram of the composition of an apparatus for a timing wireless communication algorithm provided in Example 2 of an embodiment of the present application. DETAILED DESCRIPTION

[0012] In order to enable those skilled in the art to better understand the technical solution of the present application, the method and device for implementing the wireless communication algorithm and the computer-readable medium provided by the present application are described in detail below in conjunction with the accompanying drawings.

[0013] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make this application thorough and complete and to enable those skilled in the art to fully understand the scope of this application.

[0014] In the absence of conflict, the embodiments of the present application and the features therein may be combined with each other.

[0015] As used herein, the term "and / or" includes any and all combinations of at least one of the associated listed items.

[0016] The terms used herein are only used to describe specific embodiments and are not intended to limit the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of at least one other feature, whole, step, operation, element, component and / or its group is not excluded.

[0017] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined herein.

[0018] There are currently three ways to implement wireless communication algorithms: pure hardware implementation, pure software implementation, and a combination of hardware and software. Among them, the pure hardware implementation method uses hardware hardening to implement each calculation of the algorithm, and there may be resource reuse between hardware. This implementation method has poor flexibility and cannot adjust the algorithm implementation according to actual conditions; the pure software implementation method uses programmable hardware such as central processing units and data processing units to implement various algorithms, which consumes more power and is slower; the combination of hardware and software implements some algorithms using hardware and some algorithms using software. Although the advantages of both methods are combined, the flexibility of the part implemented by hardware is still poor, and the part implemented by software still consumes more power. Therefore, it is still impossible to take into account both flexibility and power consumption.

[0019] The apparatus for implementing the wireless communication algorithm in the embodiment of the present application may be included in a wireless communication device, and the wireless communication device may be, for example, a terminal.

[0020] Figure 1 A block diagram of a device for implementing a wireless communication algorithm provided in one embodiment of the present application.

[0021] First, refer to Figure 1 An embodiment of the present application provides a device for implementing a wireless communication algorithm, including: at least one algorithm implementation module.

[0022] The algorithm implementation module includes: at least one central processing unit 101, a cross switch 102 and at least one operator unit 103; wherein the operator unit 103 implements the corresponding data processing algorithm through hardware.

[0023] The central processing unit 101 is configured to: read microcode configuration information corresponding to the wireless communication algorithm; wherein the microcode configuration information includes: hardware connection configuration information and hardware unit configuration information; control the cross switch according to the hardware connection configuration information to connect part or all of the operator units into a combination operator unit; configure the operator units in the combination operator unit according to the hardware unit configuration information so that the combination operator unit can implement the corresponding data processing algorithm.

[0024] The combination operator unit is configured to: acquire the data to be processed according to the configuration of the combination operator unit and perform corresponding processing to obtain output data.

[0025] In some exemplary embodiments, when the apparatus for implementing a wireless communication algorithm includes two or more algorithm implementation modules, the two or more algorithm implementation modules are connected in sequence.

[0026] In some exemplary embodiments, the operator unit 103 may also be referred to as a general-purpose processor, a dedicated accelerator, a vector processor, etc.

[0027] In some exemplary embodiments, the central processing unit 101 may be a central processing unit, a digital signal processing (DSP, Digital Signal Processing), etc.

[0028] In some exemplary embodiments, the wireless communication algorithm may be any one of the following: a cell search algorithm, a cell measurement algorithm, a cell residence algorithm, a cell reconnection algorithm, a random access algorithm, a channel estimation algorithm, a channel feedback algorithm, a multiple-transmission and multiple-reception algorithm, a multiple-transmission and multiple-reception solution algorithm, a coding algorithm, a decoding algorithm, a modulation algorithm, a carrier aggregation algorithm, etc.

[0029] In some exemplary embodiments, the cell search algorithm includes the following data processing processes: blind detection of the primary synchronization signal, blind detection of the secondary synchronization signal, coarse or fine frequency offset estimation, blind detection of the demodulation reference signal, judging the signal reception strength of the cell, calculating the received power of the reference signal, calculating the strength indication, calculating the reception quality, calculating the signal-to-noise ratio, etc.

[0030] In some exemplary embodiments, the data processing algorithm that can be implemented by the operator unit includes any one of the following: a correlation algorithm, a Fourier transform algorithm, an inverse Fourier transform algorithm, a descrambling algorithm, a zero operation algorithm, an equalization algorithm, etc.

[0031] In some exemplary embodiments, the data processing algorithm implemented by the combined operator unit includes: the data processing algorithms implemented by all operator units included in the combined operator unit, and the data processing algorithm implemented by the operator unit includes the data processing algorithm implemented each time the operator unit is called. For example, a certain combined operator unit includes operator unit 1, operator unit 2, and operator unit 3, operator unit 1 is used to implement data processing algorithm 1, operator unit 2 is used to implement data processing algorithm 2, and operator unit 3 is used to implement data processing algorithm 3, then, the data processing algorithms implemented by the combined operator unit include: data processing algorithm 1, data processing algorithm 2, and data processing algorithm 3. If operator unit 2 is called twice, then, the data processing algorithms implemented by the combined operator unit include: data processing algorithm 1, two data processing algorithms 2, and data processing algorithm 3.

[0032] In some exemplary embodiments, the operator units included in the combined operator unit may be completely different, or may be partially the same and partially different. The same multiple operator units may implement the same data processing algorithm, or may implement different data processing algorithms.

[0033] In some exemplary embodiments, the execution order of the operator units included in the combined operator unit is determined by the connection relationship between the operator units. For example, if the data output interface of operator unit 1 is connected to the data input interface of operator unit 2, then operator unit 1 is executed first and operator unit 2 is executed later.

[0034] In some exemplary embodiments, the number of times that the combined operator unit calls the same operator unit when processing the data to be processed may be once, or may be twice or more.

[0035] When the same operator unit is called multiple times, the data processing algorithms implemented in different calls can be the same or different.

[0036] In some exemplary embodiments, the operator unit may include at least one data input interface and at least one data output interface.

[0037] For example, the data output interface 1 of operator unit 2 is connected to the data input interface of operator unit 1, the data output interface of operator unit 1 is connected to the data input interface of operator unit 2, and the data output interface 2 of operator unit 2 is connected to the data input interface of operator unit 3. Then the combined operator unit includes: operator unit 1, operator unit 2, and operator unit 3. The execution order of these three operator units is operator unit 2 - operator unit 1 - operator unit 2 - operator unit 3. In other words, operator unit 1 and operator unit 3 are called once, and operator unit 2 is called twice.

[0038] In some exemplary embodiments, the microcode configuration information corresponding to the wireless communication algorithm includes one or more microcode configuration information, each of which can implement at least one data processing process in the wireless communication algorithm. The data processing process implemented by a microcode configuration information can be set arbitrarily according to actual needs.

[0039] In some exemplary embodiments, each algorithm implementation module can read one microcode configuration information each time to perform corresponding configuration and data processing. Then, if the device that implements the wireless communication algorithm includes only one algorithm implementation module, and the wireless communication algorithm includes A microcode configuration information, A is greater than or equal to 2, then the algorithm implementation module needs to read A microcode configuration information in sequence to perform corresponding data processing, that is, it needs to be executed A times by the algorithm implementation module to fully implement the wireless communication algorithm. If the device that implements the wireless communication algorithm includes A algorithm implementation modules, and the wireless bucket algorithm includes A microcode configuration information, then each algorithm implementation module only needs to read one microcode configuration information to fully implement the wireless communication algorithm.

[0040] In some exemplary embodiments, a data memory 104 is also included, wherein the central processing unit 101 is further configured to: control the connection between the data memory and the operator unit in the combination operator unit according to the hardware connection configuration; and configure the data memory connected to the operator unit in the combination operator unit according to the hardware unit configuration information.

[0041] The combination operator unit is specifically configured as follows: according to the configuration of the combination operator unit and the configuration of the data storage unit, after reading the data to be processed from the data storage unit connected to the first operator unit in the combination operator unit and performing corresponding data processing to obtain output data, the output data is stored in the data storage unit connected to the last operator unit in the combination operator unit.

[0042] In some exemplary embodiments, the hardware connection configuration information includes: connection information between different data input interfaces and data output interfaces of different operator units.

[0043] In some exemplary embodiments, the hardware connection configuration information further includes: connection information between the operator unit and the data memory.

[0044] In some exemplary embodiments, the hardware unit configuration information includes: configuration information of an operator unit in a combination operator unit.

[0045] In some exemplary embodiments, the configuration information of the operator unit in the combined operator unit also includes: the number of times the operator unit is called, whether the data processing algorithm implemented when the operator unit is called different times is the same, the data processing algorithm implemented each time the operator unit is called, and the parameters in the data processing algorithm implemented each time the operator unit is called.

[0046] In some exemplary embodiments, the hardware unit configuration information includes: configuration information of a data memory connected to an operator unit in the combinational operator unit.

[0047] In some exemplary embodiments, configuration information of a data storage device connected to an operator unit in a combinational operator unit includes: the number of times data is read, the number of times data is stored, the address of each time data is read, the address of each time data is stored, the length of each time data is read, and the length of each time data is stored.

[0048] In some exemplary embodiments, the configuration information of the data memory connected to the operator unit in the combinational operator unit includes: the number of times data is read, the address of each data read, and the length of each data read.

[0049] In some exemplary embodiments, the configuration information of the data memory connected to the operator unit in the combination operator unit includes: the number of times data is stored, the address of each data storage, and the length of each data storage.

[0050] In some exemplary embodiments, when the control combination operator unit obtains the data to be processed and performs corresponding data processing to obtain the output data, the data to be processed is sequentially processed according to the connection relationship of the operator units in the combination operator unit. After the operator unit is configured according to the corresponding configuration information, the corresponding data processing algorithm can be implemented, and the corresponding data processing algorithm is used to perform corresponding data processing on the data output by the previous operator unit. If the same operator unit is called multiple times, it is necessary to configure the same operator unit multiple times to implement the corresponding data processing algorithm.

[0051] In some exemplary embodiments, the data storage connected to the operator unit in the combination operator unit can be configured according to the configuration information of the data storage connected to the operator unit in the combination operator unit, so that in the process of controlling the combination operator unit to obtain the data to be processed and perform corresponding data processing to obtain the output data, the data to be processed, the intermediate data obtained by processing the data to be processed, and at least one of the output data are stored in the corresponding data storage.

[0052] In some exemplary embodiments, the central processing unit is further configured to: determine whether there is any unprocessed microcode configuration information in the microcode configuration information corresponding to the wireless communication algorithm; if there is any unprocessed microcode configuration information, continue to execute the step of reading the next microcode configuration information until all the microcode configuration information in the microcode configuration information corresponding to the wireless communication algorithm is processed.

[0053] In some exemplary embodiments, different algorithm implementation modules share the same central processing unit; or, the central processing units in different algorithm implementation modules are different.

[0054] In some exemplary embodiments, different algorithm implementation modules share the same data memory; or, the data memories in different algorithm implementation modules are different.

[0055] In some exemplary embodiments, the output data of the i-th algorithm implementation module is the data to be processed by the i+1-th algorithm implementation module; wherein i is any integer between 1 and N, and N is the number of algorithm implementation modules.

[0056] In some exemplary embodiments, the central processing unit 101 is further configured to: generate microcode configuration information corresponding to the wireless communication algorithm; and store the microcode configuration information corresponding to the wireless communication algorithm in a microcode memory.

[0057] The device for implementing the wireless communication algorithm also includes a microcode memory, which is configured to store microcode configuration information corresponding to the wireless communication algorithm.

[0058] In some exemplary embodiments, the microcode memory and the data memory 104 may be the same memory or different memories.

[0059] The device for implementing a wireless communication algorithm provided in the embodiment of the present application realizes the corresponding wireless communication algorithm by arbitrarily combining operator units. Since the operator units realize the corresponding data processing algorithm through hardware, the flexibility is improved, the data processing efficiency is improved, and the power consumption is reduced.

[0060] Figure 2 A flowchart of a method for implementing a wireless communication algorithm is provided in accordance with another embodiment of the present application.

[0061] Second, refer to Figure 2 Another embodiment of the present application provides a method for implementing a wireless communication algorithm. The method may be executed by a wireless communication device. The wireless communication device may be, for example, a terminal. The method includes:

[0062] Step 200, read the microcode configuration information corresponding to the wireless communication algorithm; wherein the microcode configuration information includes: hardware connection configuration information and hardware unit configuration information.

[0063] In some exemplary embodiments, the wireless communication algorithm may be any one of the following: a cell search algorithm, a cell measurement algorithm, a cell residence algorithm, a cell reconnection algorithm, a random access algorithm, a channel estimation algorithm, a channel feedback algorithm, a multiple-transmission and multiple-reception algorithm, a multiple-transmission and multiple-reception solution algorithm, a coding algorithm, a decoding algorithm, a modulation algorithm, a carrier aggregation algorithm, etc.

[0064] In some exemplary embodiments, the cell search algorithm includes the following data processing processes: blind detection of the primary synchronization signal, blind detection of the secondary synchronization signal, coarse or fine frequency offset estimation, blind detection of the demodulation reference signal, judging the signal reception strength of the cell, calculating the received power of the reference signal, calculating the strength indication, calculating the reception quality, calculating the signal-to-noise ratio, etc.

[0065] In some exemplary embodiments, the data processing algorithm that can be implemented by the operator unit includes any one of the following: a correlation algorithm, a Fourier transform algorithm, an inverse Fourier transform algorithm, a descrambling algorithm, a zero operation algorithm, an equalization algorithm, etc.

[0066] Step 201 : Control the crossbar switch to connect part or all of the operator units into a combined operator unit according to the hardware connection configuration information.

[0067] In some exemplary embodiments, the operator unit 103 may also be referred to as a general-purpose processor, a dedicated accelerator, a vector processor, etc.

[0068] In some exemplary embodiments, the hardware connection configuration information includes: connection information between different data input interfaces and data output interfaces of different operator units.

[0069] In some exemplary embodiments, the hardware connection configuration information further includes: connection information between the operator unit and the memory.

[0070] In some exemplary embodiments, the hardware unit configuration information includes: configuration information of an operator unit in a combination operator unit.

[0071] In some exemplary embodiments, the configuration information of the operator unit in the combined operator unit also includes: the number of times the operator unit is called, whether the data processing algorithm implemented when the operator unit is called different times is the same, the data processing algorithm implemented each time the operator unit is called, and the parameters in the data processing algorithm implemented each time the operator unit is called.

[0072] In some exemplary embodiments, the hardware unit configuration information includes: configuration information of a data memory connected to an operator unit in the combinational operator unit.

[0073] In some exemplary embodiments, configuration information of a data storage device connected to an operator unit in a combinational operator unit includes: the number of times data is read, the number of times data is stored, the address of each time data is read, the address of each time data is stored, the length of each time data is read, and the length of each time data is stored.

[0074] In some exemplary embodiments, the configuration information of the data memory connected to the operator unit in the combinational operator unit includes: the number of times data is read, the address of each data read, and the length of each data read.

[0075] In some exemplary embodiments, the configuration information of the data memory connected to the operator unit in the combination operator unit includes: the number of times data is stored, the address of each data storage, and the length of each data storage.

[0076] In some exemplary embodiments, when the control combination operator unit obtains the data to be processed and performs corresponding data processing to obtain the output data, the data to be processed is sequentially processed according to the connection relationship of the operator units in the combination operator unit. After the operator unit is configured according to the corresponding configuration information, the corresponding data processing algorithm can be implemented, and the corresponding data processing algorithm is used to perform corresponding data processing on the data output by the previous operator unit. If the same operator unit is called multiple times, it is necessary to configure the same operator unit multiple times to implement the corresponding data processing algorithm.

[0077] In some exemplary embodiments, the data storage connected to the operator unit in the combination operator unit can be configured according to the configuration information of the data storage connected to the operator unit in the combination operator unit, so that in the process of inputting the data to be processed into the combination operator unit for corresponding data processing to obtain output data, the data to be processed, the intermediate data obtained by processing the data to be processed, and at least one of the output data are stored in the corresponding data storage.

[0078] Step 202, configure the operator unit in the combination operator unit according to the hardware unit configuration information, so that the combination operator unit can implement the corresponding data processing algorithm; wherein the operator unit implements the corresponding data processing algorithm through hardware.

[0079] In some exemplary embodiments, the data processing algorithm implemented by the combined operator unit includes: the data processing algorithms implemented by all operator units included in the combined operator unit, and the data processing algorithm implemented by the operator unit includes the data processing algorithm implemented each time the operator unit is called. For example, a certain combined operator unit includes operator unit 1, operator unit 2, and operator unit 3, operator unit 1 is used to implement data processing algorithm 1, operator unit 2 is used to implement data processing algorithm 2, and operator unit 3 is used to implement data processing algorithm 3, then, the data processing algorithms implemented by the combined operator unit include: data processing algorithm 1, data processing algorithm 2, and data processing algorithm 3. If operator unit 2 is called twice, then, the data processing algorithms implemented by the combined operator unit include: data processing algorithm 1, two data processing algorithms 2, and data processing algorithm 3.

[0080] In some exemplary embodiments, the operator units included in the combined operator unit may be completely different, or may be partially the same and partially different. The same multiple operator units may implement the same data processing algorithm, or may implement different data processing algorithms.

[0081] In some exemplary embodiments, the execution order of the operator units included in the combined operator unit is determined by the connection relationship between the operator units. For example, if the data output interface of operator unit 1 is connected to the data input interface of operator unit 2, then operator unit 1 is executed first and operator unit 2 is executed later.

[0082] In some exemplary embodiments, the number of times that the combined operator unit calls the same operator unit when processing the data to be processed may be once, or may be twice or more.

[0083] When the same operator unit is called multiple times, the data processing algorithms implemented in different calls can be the same or different.

[0084] In some exemplary embodiments, the operator unit may include at least one data input interface and at least one data output interface.

[0085] For example, the data output interface 1 of operator unit 2 is connected to the data input interface of operator unit 1, the data output interface of operator unit 1 is connected to the data input interface of operator unit 2, and the data output interface 2 of operator unit 2 is connected to the data input interface of operator unit 3. Then the combined operator unit includes: operator unit 1, operator unit 2, and operator unit 3. The execution order of these three operator units is operator unit 2 - operator unit 1 - operator unit 2 - operator unit 3. In other words, operator unit 1 and operator unit 3 are called once, and operator unit 2 is called twice.

[0086] In some exemplary embodiments, the microcode configuration information corresponding to the wireless communication algorithm includes one or more microcode configuration information, each of which can implement at least one data processing process in the wireless communication algorithm. The data processing process implemented by a microcode configuration information can be set arbitrarily according to actual needs.

[0087] In some exemplary embodiments, each algorithm implementation module can read one microcode configuration information each time to perform corresponding configuration and data processing. Then, if the device that implements the wireless communication algorithm includes only one algorithm implementation module, and the wireless communication algorithm includes A microcode configuration information, A is greater than or equal to 2, then the algorithm implementation module needs to read A microcode configuration information in sequence to perform corresponding data processing, that is, it needs to be executed A times by the algorithm implementation module to fully implement the wireless communication algorithm. If the device that implements the wireless communication algorithm includes A algorithm implementation modules, and the wireless bucket algorithm includes A microcode configuration information, then each algorithm implementation module only needs to read one microcode configuration information to fully implement the wireless communication algorithm.

[0088] Step 203: The combinatorial operator unit obtains the data to be processed according to the configuration of the combinatorial operator unit and performs corresponding data processing to obtain output data.

[0089] In some exemplary embodiments, before the combination operator unit obtains the data to be processed and performs corresponding data processing to obtain output data, the method also includes: controlling the connection between the data storage device and the operator unit in the combination operator unit according to the hardware connection configuration; and configuring the data storage device connected to some or all of the operator units in the combination operator unit according to the hardware unit configuration information.

[0090] After the combinatorial operator unit reads the data to be processed from the data storage connected to the first operator unit in the combinatorial operator unit according to the configuration of the combinatorial operator unit and the configuration of the data storage and performs corresponding processing to obtain output data, the method also includes: the combinatorial operator unit stores the output data in the data storage connected to the last operator unit in the combinatorial operator unit.

[0091] In some exemplary embodiments, the combinational operators in the combinational operator unit perform corresponding data processing according to the configuration of the operator unit.

[0092] In some exemplary embodiments, the combination operator in the combination operator unit obtains the data to be processed and performs corresponding data processing according to the configuration of the operator unit and the data storage connected to the operator unit.

[0093] In some exemplary embodiments, the combination operator in the combination operator unit obtains the data to be processed and performs corresponding data processing according to the configuration of the operator unit and the data storage connected to the operator unit, and stores the processed input in the data storage connected to the operator unit.

[0094] In some exemplary embodiments, the combination operator in the combination operator unit obtains the data to be processed and performs corresponding data processing according to the configuration of the operator unit and the data storage connected to the operator unit, and stores the processed input in the data storage connected to the operator unit.

[0095] In some exemplary embodiments, after the combination operator unit obtains the data to be processed and performs corresponding data processing to obtain output data, the method further includes: determining whether there is unprocessed microcode configuration information in the microcode configuration information corresponding to the wireless communication algorithm; if there is unprocessed microcode configuration information, continuing to execute the step of reading the next microcode configuration information until all microcode configuration information in the microcode configuration information corresponding to the wireless communication algorithm is processed.

[0096] In some exemplary embodiments, before reading the microcode configuration information corresponding to the wireless communication algorithm, the method further includes: generating the microcode configuration information corresponding to the wireless communication algorithm; and storing the microcode configuration information corresponding to the wireless communication algorithm in a microcode memory.

[0097] In order to more clearly present the device for implementing the wireless communication algorithm of the embodiment of the present application, two examples are listed below for illustration. The listed examples are not intended to limit the protection scope of the embodiment of the present application.

[0098] Example 1

[0099] This example describes a process of implementing an auxiliary synchronization signal blind detection algorithm by a device implementing a wireless communication algorithm.

[0100] like Figure 3 As shown, the device for implementing the wireless communication algorithm includes: a central processing unit 301, a cross switch 302, a data storage 303, a descrambling operator unit 304, a fast Fourier transform (FFT) operator unit 305, a zero operation operator unit 306, and an equalization operator unit 307.

[0101] The descrambling operator unit 304 is used to implement a descrambling algorithm.

[0102] The FFT operator unit 305 is used to implement an FFT algorithm or an Inverse Fast Fourier Transform (IFFT) algorithm.

[0103] The zero-wiping operator unit 306 is used to implement a zero-wiping algorithm, that is, to set the middle part of the input data to 0, and the starting position and the ending position of the middle part can be configured.

[0104] The equalization operator unit 307 is used to implement the equalization algorithm.

[0105] In this example, the auxiliary synchronization signal blind detection algorithm includes: a channel estimation process, a channel equalization process and a blind detection process.

[0106] Among them, the channel estimation process uses the known primary synchronization signal to estimate the channel condition, the channel equalization process uses the channel estimation result of the primary synchronization signal to equalize the received secondary synchronization signal, and the blind detection process uses 336 possible secondary synchronization signals to perform de-scrambling and comparison on the equalized secondary synchronization signal, and takes the closest ones to report to the software for decision-making.

[0107] There are three microcode configuration information corresponding to the auxiliary synchronization signal blind detection algorithm, namely, microcode configuration information 1 corresponding to the channel estimation process, microcode configuration information 2 corresponding to the channel equalization process, and microcode configuration information 3 corresponding to the blind detection process.

[0108] Microcode configuration information 1 includes hardware connection configuration information 1 and hardware unit configuration information 1.

[0109] The microcode configuration information 2 includes hardware connection configuration information 2 and hardware unit configuration information 2.

[0110] The microcode configuration information 3 includes hardware connection configuration information 3 and hardware unit configuration information 3 .

[0111] The central processing unit 301 reads the microcode configuration information 1, and controls the cross switch 302 to connect the data output interface of the data storage unit 303 to the data input interface 1 of the FFT operator unit 305 according to the hardware connection configuration information 1 in the microcode configuration information 1, connect the data output interface 1 of the FFT operator unit 305 to the data input interface of the descrambling operator unit 304, connect the data output interface of the descrambling operator unit 304 to the data input interface 2 of the FFT operator unit 305, and connect the data output interface 2 of the FFT operator unit 305 to the data input interface 2 of the zero erase operator unit 305. The data input interface of the zero operation operator unit 306 is connected, the data output interface of the zero operation operator unit 306 is connected to the data input interface 3 of the FFT operator unit 305, and the data output interface 3 of the FFT operator unit 305 is connected to the data input port of the data storage unit 303, thereby forming a combination operator unit of data storage unit 303 - FFT operator unit 305 - descrambling operator unit 304 - FFT operator unit 305 - zero operation operator unit 306 - FFT operator unit 305 - data storage unit 303.

[0112] The central processing unit 301 configures the data memory 303, the FFT operator unit 305, the descrambling operator unit 304, and the zero operation operator unit 306 accordingly according to the hardware unit configuration information 1.

[0113] The FFT operator unit 305 reads the received data from the data memory 303 according to the configuration of the FFT operator unit 305 and the configuration of the data memory 303, and performs corresponding data processing on the primary synchronization signal in the received data.

[0114] The descrambling operator unit 304 performs corresponding data processing on the data output by the FFT operator unit 305 according to the configuration of the descrambling operator unit 304 .

[0115] The FFT operator unit 305 performs corresponding data processing on the data output by the descrambling operator unit 304 according to the configuration of the FFT operator unit 305 .

[0116] The zero-wiping operator unit 306 performs corresponding data processing according to the configuration of the zero-wiping operator unit 306 .

[0117] The FFT operator unit 305 performs corresponding data processing on the data output by the zero operation operator unit 306 according to the configuration of the FFT operator unit 305 .

[0118] The FFT operator unit 305 stores the data output by the FFT operator unit 305 , that is, the channel estimation result, in the data memory 303 according to the configuration of the FFT operator unit 305 and the configuration of the data memory 303 .

[0119] The central processing unit 301 reads the microcode configuration information 2, and connects the data output interface of the storage 303 to the data input interface 1 of the FFT operator unit 305 through the cross switch 302 according to the hardware connection configuration information 2 in the microcode configuration information 2, connects the data output interface 1 of the FFT operator unit 305 to the data input interface of the equalization operator unit 307, and connects the data output interface of the equalization operator unit 307 to the data input port of the memory 303, thereby forming a combination operator unit of the memory 303 - FFT operator unit 305 - equalization operator unit 307 - memory 303.

[0120] The central processing unit 301 configures the data memory 303 , the FFT operator unit 305 , and the equalization operator unit 307 accordingly according to the hardware unit configuration information 2 .

[0121] The FFT operator unit 305 reads the received data from the data memory 303 according to the configuration of the FFT operator unit 305 and the configuration of the data memory 303, and performs corresponding data processing on the secondary synchronization signal in the received data.

[0122] The equalization operator unit 307 performs corresponding data processing on the data output by the FFT operator unit 305 and the channel estimation result according to the configuration of the equalization operator unit 307 .

[0123] The equalizer unit 307 stores the data output by the equalizer unit 307 , that is, the secondary synchronization signal after equalization processing, in the data memory 303 according to the configuration of the equalizer unit 307 and the configuration of the data memory 303 .

[0124] The central processing unit 301 reads the microcode configuration information 3, and connects the data output interface of the storage 303 to the data input interface of the descrambling operator unit 304 through the cross switch 302 according to the hardware connection configuration information 3 in the microcode configuration information 3, and connects the data output interface of the descrambling operator unit 304 to the data input port of the memory 303, thereby forming a combination operator unit of the memory 303 - the descrambling operator unit 304 - the memory 303.

[0125] The central processing unit 301 configures the memory 303 and the descrambling operator unit 304 accordingly according to the hardware unit configuration information 3 .

[0126] The descrambling operator unit 304 reads the secondary synchronization signal after equalization from the data memory 303 according to the configuration of the descrambling operator unit 304 and the configuration of the data memory 303, and performs corresponding data processing on the secondary synchronization signal after equalization and one of the possible secondary synchronization signals.

[0127] The descrambling operator unit 304 stores the data output by the descrambling operator unit 304 in the data memory 303 according to the configuration of the descrambling operator unit 304 and the configuration of the data memory 303 .

[0128] The above process is repeated to obtain 336 possible output data corresponding to the auxiliary synchronization signals.

[0129] The output data corresponding to the 336 possible auxiliary synchronization signals are reported to the software, which sorts them and decides one of the output data corresponding to the 336 possible auxiliary synchronization signals as the blind detection result of the auxiliary synchronization signal.

[0130] Example 2

[0131] This example describes a process of implementing an auxiliary synchronization signal blind detection algorithm by a device implementing a wireless communication algorithm.

[0132] like Figure 4 As shown, the device for implementing the wireless communication algorithm includes: an algorithm implementation module 401, an algorithm implementation module 402, and an algorithm implementation module 403.

[0133] Among them, the algorithm implementation module 401 includes: a central processing unit 4011, a cross switch 4012, a data storage unit 4013, a descrambling operator unit 4014, a fast Fourier transform (FFT) operator unit 4015, a zero operation operator unit 4016, and an equalization operator unit 4017.

[0134] The algorithm implementation module 402 includes: a central processing unit 4021, a cross switch 4022, a data storage unit 4023, a descrambling operator unit 4024, a FFT operator unit 4025, a zero operation operator unit 4026, and an equalization operator unit 4027.

[0135] The algorithm implementation module 403 includes: a central processing unit 4031, a cross switch 4032, a data storage unit 4033, a descrambling operator unit 4034, a FFT operator unit 4035, a zero operation operator unit 4036, and an equalization operator unit 4037.

[0136] The descrambling operator unit is used to implement the descrambling algorithm.

[0137] The FFT operator unit is used to implement the FFT algorithm or the IFFT algorithm.

[0138] The zero-wiping operator unit is used to implement the zero-wiping algorithm, that is, to set the middle part of the input data to 0, and the starting position and the ending position of the middle part can be configured.

[0139] The equalization operator unit is used to implement the equalization algorithm.

[0140] In this example, the auxiliary synchronization signal blind detection algorithm includes: a channel estimation process, a channel equalization process and a blind detection process.

[0141] Among them, the channel estimation process uses the known primary synchronization signal to estimate the channel condition, the channel equalization process uses the channel estimation result of the primary synchronization signal to equalize the received secondary synchronization signal, and the blind detection process uses 336 possible secondary synchronization signals to perform de-scrambling and comparison on the equalized secondary synchronization signal, and takes the closest ones to report to the software for decision-making.

[0142] There are three microcode configuration information corresponding to the auxiliary synchronization signal blind detection algorithm, namely, microcode configuration information 1 corresponding to the channel estimation process, microcode configuration information 2 corresponding to the channel equalization process, and microcode configuration information 3 corresponding to the blind detection process.

[0143] Microcode configuration information 1 includes hardware connection configuration information 1 and hardware unit configuration information 1.

[0144] The microcode configuration information 2 includes hardware connection configuration information 2 and hardware unit configuration information 2.

[0145] The microcode configuration information 3 includes hardware connection configuration information 3 and hardware unit configuration information 3 .

[0146] The central processing unit 4011 reads the microcode configuration information 1, and controls the cross switch 4012 to connect the data output interface of the data storage 4013 to the data input interface 1 of the FFT operator unit 4015 according to the hardware connection configuration information 1 in the microcode configuration information 1, connect the data output interface 1 of the FFT operator unit 4015 to the data input interface of the descrambling operator unit 4014, connect the data output interface of the descrambling operator unit 4014 to the data input interface 2 of the FFT operator unit 4015, and connect the data output interface 2 of the FFT operator unit 4015 to the data input interface 2 of the zero operation operator unit 4015. The data input interface of the subunit 4016 connects the data output interface of the zero operation operator unit 4016 to the data input interface 3 of the FFT operator unit 4015, and the data output interface 3 of the FFT operator unit 4015 is connected to the data input port of the data storage unit 4013, thereby forming a combination operator unit of data storage unit 4013 - FFT operator unit 4015 - descrambling operator unit 4014 - FFT operator unit 4015 - zero operation operator unit 4016 - FFT operator unit 4015 - data storage unit 4013.

[0147] The central processing unit 4011 configures the data memory 4013, the FFT operator unit 4015, the descrambling operator unit 4014, and the zero operation operator unit 4016 accordingly according to the hardware unit configuration information 1.

[0148] The FFT operator unit 4015 reads the received data from the data memory 4013 according to the configuration of the FFT operator unit 4015 and the configuration of the data memory 4013, and performs corresponding data processing on the main synchronization signal in the received data.

[0149] The descrambling operator unit 4014 performs corresponding data processing on the data output by the FFT operator unit 4015 according to the configuration of the descrambling operator unit 4014 .

[0150] The FFT operator unit 4015 performs corresponding data processing on the data output by the descrambling operator unit 4014 according to the configuration of the FFT operator unit 4015 .

[0151] The zero-wiping operator unit 4016 performs corresponding data processing according to the configuration of the zero-wiping operator unit 4016.

[0152] The FFT operator unit 4015 performs corresponding data processing on the data output by the zero operation operator unit 4016 according to the configuration of the FFT operator unit 4015.

[0153] The FFT operator unit 4015 stores the data output by the FFT operator unit 4015 , that is, the channel estimation result, in the data memory 4013 according to the configuration of the FFT operator unit 4015 and the configuration of the data memory 4013 .

[0154] The central processing unit 4021 reads the microcode configuration information 2, and controls the cross switch 4022 to connect the data output interface of the data storage 4023 to the data input interface 1 of the FFT operator unit 4025 according to the hardware connection configuration information 2 in the microcode configuration information 2, connects the data output interface 1 of the FFT operator unit 4025 to the data input interface of the equalization operator unit 4027, and connects the data output interface of the equalization operator unit 4027 to the data input port of the data storage 4023, thereby forming a combination operator unit of data storage 4023 - FFT operator unit 4025 - equalization operator unit 4027 - data storage 4023.

[0155] The central processing unit 4021 configures the data memory 4023, the FFT operator unit 4025, and the equalization operator unit 4027 accordingly according to the hardware unit configuration information 2.

[0156] The FFT operator unit 4025 reads the received data from the data memory 4023 according to the configuration of the FFT operator unit 4025 and the configuration of the data memory 4023, and performs corresponding data processing on the auxiliary synchronization signal in the received data.

[0157] The equalization operator unit 4027 performs corresponding data processing on the data output by the FFT operator unit 4025 and the channel estimation result according to the configuration of the equalization operator unit 4027 .

[0158] The equalizer unit 4027 stores the data output by the equalizer unit 4027 , that is, the secondary synchronization signal after equalization processing, in the data memory 4023 according to the configuration of the equalizer unit 4027 and the configuration of the data memory 4023 .

[0159] The central processing unit 4033 reads the microcode configuration information 3, and controls the cross switch 4032 to connect the data output interface of the data memory 4033 to the data input interface of the descrambling operator unit 4034 according to the hardware connection configuration information 3 in the microcode configuration information 3, and connects the data output interface of the descrambling operator unit 4034 to the data input port of the memory 4033, thereby forming a combination operator unit of the memory 4033 - the descrambling operator unit 4034 - the memory 4033.

[0160] The central processing unit 4031 configures the data memory 4033 and the descrambling operator unit 4034 accordingly according to the hardware unit configuration information 3.

[0161] The descrambling operator unit 4034 reads the secondary synchronization signal after equalization from the data memory 4033 according to the configuration of the descrambling operator unit 4034 and the configuration of the data memory 4033, and performs corresponding data processing on the secondary synchronization signal after equalization and one of the possible secondary synchronization signals.

[0162] The descrambling operator unit 4034 stores the data output by the descrambling operator unit 4034 into the data memory 4033 according to the configuration of the descrambling operator unit 4034 and the configuration of the data memory 4033 .

[0163] The above process is repeated to obtain 336 possible output data corresponding to the auxiliary synchronization signals.

[0164] The output data corresponding to the 336 possible auxiliary synchronization signals are reported to the software, which sorts them and decides one of the output data corresponding to the 336 possible auxiliary synchronization signals as the blind detection result of the auxiliary synchronization signal.

[0165] In a third aspect, another embodiment of the present application provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any of the above-mentioned methods for implementing a wireless communication algorithm.

[0166] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0167] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present application as set forth in the appended claims.

Claims

1. A device for implementing a wireless communication algorithm, comprising: At least one algorithm implementation module; The algorithm implementation module includes: at least one central processing unit, a cross switch and at least one operator unit; wherein the operator unit implements the corresponding data processing algorithm through hardware; Wherein, the central processing unit is configured as: Reading microcode configuration information corresponding to the wireless communication algorithm; wherein the microcode configuration information includes: hardware connection configuration information and hardware unit configuration information; Controlling the cross switch to connect part or all of the operator units into a combined operator unit according to the hardware connection configuration information; Configuring an operator unit in the combination operator unit according to the hardware unit configuration information so that the combination operator unit can implement a corresponding data processing algorithm; The combinatorial operator unit is configured to: acquire the data to be processed according to the configuration of the combinatorial operator unit and perform corresponding data processing to obtain output data.

2. The apparatus for implementing a wireless communication algorithm according to claim 1, further comprising a data storage device, wherein the central processing unit is further configured to: Controlling the data storage to be connected to an operator unit in the combination operator unit according to the hardware connection configuration; configuring a data storage connected to an operator unit in the combination operator unit according to the hardware unit configuration information; The combinatorial operator unit is specifically configured as follows: according to the configuration of the combinatorial operator unit and the configuration of the data storage, after reading the data to be processed from the data storage connected to the first operator unit in the combinatorial operator unit and performing corresponding data processing to obtain output data, the output data is stored in the data storage connected to the last operator unit in the combinatorial operator unit.

3. The device for implementing a wireless communication algorithm according to claim 2, wherein: Different algorithm implementation modules share the same data storage; Alternatively, the data storage devices in different algorithm implementation modules are different.

4. The device for implementing a wireless communication algorithm according to claim 1, wherein the central processing unit is further configured to: Determining whether there is unprocessed microcode configuration information in the microcode configuration information corresponding to the wireless communication algorithm; In the case that there is unprocessed microcode configuration information, the step of reading the next microcode configuration information is continued until all the microcode configuration information in the microcode configuration information corresponding to the wireless communication algorithm is processed.

5. The device for implementing a wireless communication algorithm according to any one of claims 1 to 4, wherein: Different algorithm implementation modules share the same central processing unit; Alternatively, the central processing units in different algorithm implementation modules are different.

6. The device for implementing a wireless communication algorithm according to any one of claims 1 to 4, wherein: The output data of the ith algorithm implementation module is the data to be processed by the (i+1)th algorithm implementation module; wherein i is any integer between 1 and N, and N is the number of the algorithm implementation modules.

7. A method for implementing a wireless communication algorithm, comprising: Reading microcode configuration information corresponding to the wireless communication algorithm; wherein the microcode configuration information includes: hardware connection configuration information and hardware unit configuration information; Controlling the crossbar switch to connect part or all of the operator units into a combined operator unit according to the hardware connection configuration information; configuring the operator unit in the combination operator unit according to the hardware unit configuration information so that the combination operator unit can implement the corresponding data processing algorithm; wherein the operator unit implements the corresponding data processing algorithm through hardware; The combinatorial operator unit acquires the data to be processed according to the configuration of the combinatorial operator unit and performs corresponding data processing to obtain output data.

8. The method for implementing a wireless communication algorithm according to claim 7, before controlling the combinatorial operator unit to obtain the data to be processed and inputting it into the combinatorial operator unit for corresponding processing to obtain output data, the method further comprises: Controlling the data storage to be connected to an operator unit in the combination operator unit according to the hardware connection configuration; configuring a data storage connected to an operator unit in the combination operator unit according to the hardware unit configuration information; After the combinatorial operator unit reads the data to be processed from the data storage connected to the first operator unit in the combinatorial operator unit according to the configuration of the combinatorial operator unit and the configuration of the data storage and performs corresponding processing to obtain output data, the method further includes: The combined operator unit stores the output data in a data memory connected to the last operator unit in the combined operator unit.

9. The method for implementing a wireless communication algorithm according to claim 7, after controlling the combinatorial operator unit to obtain the data to be processed according to the configuration of the combinatorial operator unit and performing corresponding data processing to obtain output data, the method further comprises: Determining whether there is unprocessed microcode configuration information in the microcode configuration information corresponding to the wireless communication algorithm; In the case that there is unprocessed microcode configuration information, the step of reading the next microcode configuration information is continued until all the microcode configuration information in the microcode configuration information corresponding to the wireless communication algorithm is processed.

10. The method for implementing a wireless communication algorithm according to any one of claims 7 to 9, before reading microcode configuration information corresponding to the wireless communication algorithm, the method further comprises: Generate microcode configuration information corresponding to the wireless communication algorithm; The microcode configuration information corresponding to the wireless communication algorithm is stored in a microcode memory.

11. A computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method for implementing a wireless communication algorithm according to any one of claims 7 to 10.

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