Preparation method of flash memory

Abstract

The invention provides a flash memory and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; forming a hard mask layer, wherein the hard mask layer at least covers the side wall surface of the isolation layer; the formed first side wall is located on the side wall surface of the hard mask layer; forming stacked floating gates and control gates at two sides of each word line; the formed second side wall oxide layer at least covers the side surfaces of the floating gate and the control gate and extends upwards to cover the side surface of the first side wall; the formed second side wall nitride layer covers the side surface of the second side wall oxide layer. According to the steps of forming the floating gate and the control gate, after the first side wall is formed and before the second side wall oxide layer is formed, due to the protection of the hard mask layer and the first side wall at the junction of the control gate and the isolation layer, no step is formed at the junction, and the first side wall does not need to be formed on the step, so that the first side wall is not disconnected any more; the size of the side wall on the outer side of the flash memory cell is reduced, and the side wall is thinned, so that the depth-to-width ratio of the interlayer dielectric layer is reduced, and the filling window is increased.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a method for preparing a flash memory. Background Art

[0002] Flash memory has an increasingly important position in the field of non-volatile memory due to its low cost, low power consumption, fast access speed and other performance advantages. With the development of technology, the application of data storage media has also shifted from some traditional non-volatile memories to flash memory. Large-capacity solid-state storage devices with flash memory as the main storage medium have become one of the mainstream solutions for data storage today.

[0003] Figure 1 Schematic diagram of a flash memory structure, such as Figure 1 As shown, the flash memory includes a substrate 100, a word line 103 located on the substrate 100, a floating gate layer 101 and a control gate layer 102 stacked on both sides of the word line 103, and an oxide layer 104 (made of polysilicon) covering the word line 103 and the control gate layer 102. In the process of etching to form the control gate layer 102, since polysilicon and the oxide layer 104 have a certain selectivity ratio during wet etching and dry etching, a step will be generated at the junction of the control gate layer 102 and the oxide layer 104 away from the word line 103. The step will lift up the first sidewall 105 of the flash memory, and the subsequent dry etching will cause the first sidewall 105 to be disconnected at the step coverage (circle). As the outer second sidewall 106 is thinned, the frequency of this situation will increase significantly, and then acid, etching gas, charged substances or other contaminants will enter the disconnection of the first sidewall 105, causing yield and even reliability problems, thereby affecting the performance of the flash memory. Summary of the invention

[0004] The purpose of the present invention is to provide a flash memory and a method for preparing the same, wherein the first sidewall is no longer disconnected, thereby improving the yield and quality of the flash memory. The size of the sidewall outside the flash memory cell is reduced, and the thinning of the sidewall reduces the aspect ratio of the interlayer dielectric layer and increases the filling window.

[0005] The present invention provides a method for preparing a flash memory, comprising:

[0006] Providing a substrate, on which a floating gate material layer, a control gate material layer and a plurality of word lines penetrating the control gate material layer and the floating gate material layer are formed; an isolation layer is formed above each of the word lines, and the isolation layer covers the word line and the control gate material layer in adjacent areas on both sides of the word line;

[0007] forming a hard mask layer, wherein the hard mask layer at least covers a sidewall surface of the isolation layer that is perpendicular to the control gate material layer;

[0008] forming a first sidewall spacer, wherein the first sidewall spacer is located on a sidewall surface of the hard mask layer;

[0009] Etching the control gate material layer and the floating gate material layer exposed by the isolation layer to form a stacked floating gate and a control gate located on both sides of each word line;

[0010] forming a second spacer oxide layer, wherein the second spacer oxide layer at least covers the side surfaces of the floating gate and the control gate and extends upward to cover the side surface of the first spacer;

[0011] A second sidewall nitride layer is formed, wherein the second sidewall nitride layer covers a side surface of the second sidewall oxide layer.

[0012] Furthermore, forming the hard mask layer and the first sidewall spacer specifically includes:

[0013] forming a hard mask material layer, wherein the hard mask material layer covers the isolation layer and the control gate material layer;

[0014] forming a first spacer material layer, wherein the first spacer material layer covers the hard mask material layer;

[0015] The first spacer material layer and the hard mask material layer are etched without a mask, and the first spacer material layer remaining after etching forms the first spacer; and the hard mask material layer remaining after etching forms the hard mask layer.

[0016] Furthermore, the material of the second sidewall oxide layer is silicon oxide; the process of forming the second sidewall oxide layer is a thermal oxidation process; and the process parameters of the thermal oxidation process include: 2 The flow rate is 12 sccm to 220 sccm, and the temperature of the reaction chamber is 680° C. to 1000° C.

[0017] Furthermore, the formed flash memory includes a plurality of flash memory cells, and the flash memory cells include the word line, the stacked floating gate and the control gate on both sides of the word line, the isolation layer and the sidewall;

[0018] The spacer includes, in order from a side close to the word line to a side far from the word line: the hard mask layer, the first spacer, the second spacer oxide layer and the second spacer nitride layer.

[0019] Furthermore, after forming the second sidewall nitride layer, the preparation method further includes:

[0020] An interlayer dielectric layer is formed, wherein the interlayer dielectric layer fills the gaps between adjacent flash memory cells and covers the flash memory cells.

[0021] Furthermore, the thickness of the second sidewall oxide layer is 150-200 angstroms.

[0022] Furthermore, the thickness of the second sidewall nitride layer is 350 to 500 angstroms.

[0023] The present invention also provides a flash memory, comprising:

[0024] A substrate, on which a word line and a floating gate and a control gate stacked on both sides of the word line are formed; an isolation layer is formed above the word line, and the isolation layer covers the word line and the control gates on both sides of the word line;

[0025] a hard mask layer, wherein the hard mask layer at least covers a sidewall surface of the isolation layer that is perpendicular to the control gate;

[0026] A first spacer, wherein the first spacer is located on a sidewall surface of the hard mask layer;

[0027] A second spacer oxide layer, wherein the second spacer oxide layer at least covers the side surfaces of the floating gate and the control gate and extends upward to cover the side surface of the first spacer;

[0028] A second sidewall nitride layer, wherein the second sidewall nitride layer covers a side surface of the second sidewall oxide layer.

[0029] Furthermore, the flash memory includes a plurality of flash memory cells, and the flash memory cells include the word line, the stacked floating gate and the control gate on both sides of the word line, the isolation layer and the sidewall;

[0030] The spacer includes, in order from a side close to the word line to a side far from the word line: the hard mask layer, the first spacer, the second spacer oxide layer and the second spacer nitride layer.

[0031] Furthermore, the flash memory further includes: an interlayer dielectric layer, wherein the interlayer dielectric layer fills the gaps between adjacent flash memory cells and covers the flash memory cells.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The invention provides a flash memory and a preparation method thereof, the preparation method comprising: providing a substrate, on which a floating gate material layer, a control gate material layer and a plurality of word lines are formed; forming an isolation layer above each word line; forming a hard mask layer, the hard mask layer at least covers the side wall surface of the isolation layer perpendicular to the control gate material layer; forming a first side wall, the first side wall is located on the side wall surface of the hard mask layer; etching the control gate material layer and the floating gate material layer exposed by the isolation layer to form stacked floating gates and control gates located on both sides of each word line; forming a second side wall oxide layer, the second side wall oxide layer at least covers the side surfaces of the floating gate and the control gate and extends upward to cover the side surface of the first side wall; forming a second side wall nitride layer, the second side wall nitride layer covers the side surface of the second side wall oxide layer. The steps of forming the floating gate and the control gate of the present invention are arranged after forming the first sidewall and before forming the second sidewall oxide layer. In this way, the junction between the control gate and the isolation layer away from the word line is protected by the first sidewall, and no step is formed at the junction. The first sidewall does not need to be formed on the step, so the first sidewall is no longer disconnected, the size of the sidewall outside the flash memory cell is reduced, and at the same time, the thinning of the sidewall reduces the aspect ratio of the interlayer dielectric layer and increases the filling window. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The figure is a schematic diagram of the structure of a flash memory.

[0035] Figures 2 to 6 A schematic diagram of the steps of the attempted improved flash memory formation method.

[0036] Figure 7 The present invention is a flowchart of a method for preparing a flash memory according to an embodiment of the present invention.

[0037] Figures 8 to 14 Schematic diagram of each step of a method for preparing a flash memory according to an embodiment of the present invention.

[0038] Fig.15 for Fig.14 An enlarged schematic diagram of the middle side wall.

[0039] Fig.16 for Figure 6 An enlarged schematic diagram of the middle side wall.

[0040] The reference numerals are as follows:

[0041] exist Figure 1 Middle: 100 - substrate; 101 - floating gate layer; 102 - control gate layer; 103 - word line; 104 - oxide layer; 105 - first spacer; 106 - second spacer;

[0042] exist Figures 2 to 6Middle: 200-substrate; 201-floating gate material layer; 210-floating gate; 202-control gate material layer; 220-control gate; 203-word line; 204-isolation layer; 205-hard mask layer; 206-first sidewall; 207-second sidewall oxide layer; 208-second sidewall nitride layer;

[0043] exist Figures 8 to 14 In the figure: 300-substrate; 301-floating gate material layer; 310-floating gate; 302-control gate material layer; 320-control gate; 303-word line; 304-isolation layer; 350-hard mask material layer; 305-hard mask layer; 306-first sidewall material layer; 360-first sidewall; 307-second sidewall oxide layer; 308-second sidewall nitride material layer; 380-second sidewall nitride layer. DETAILED DESCRIPTION

[0044] In view of the problem that the first sidewall of flash memory in the background art is easily disconnected at the step, an improved method for forming flash memory is attempted to be developed. Figures 2 to 6 The steps of an improved method for forming a flash memory are described in detail.

[0045] like Figure 2 As shown, a substrate 200 is provided, on which a floating gate material layer 201, a control gate material layer 202 and a plurality of word lines 203 penetrating the control gate material layer 202 and the floating gate material layer 201 are formed; an isolation layer 204 is formed above each word line 203, and the isolation layer 204 covers the word line 203 and the control gate material layer 202 in the adjacent areas on both sides of the word line 203.

[0046] like Figure 3 As shown, the control gate material layer 202 and the floating gate material layer 201 exposed by etching the isolation layer 204 are formed to form a stacked floating gate 210 and a control gate 220 located on both sides of each word line.

[0047] like Figure 4 As shown, a hard mask material layer is formed, and the hard mask material layer is etched to form a hard mask layer 205; the hard mask material layer covers the isolation layer 204, the side surfaces of the floating gate 210 and the control gate 220 and the upper surface of the substrate 200, and the remaining hard mask material layer is etched to form the hard mask layer 205; the hard mask layer 205 covers the side surfaces of the floating gate 210 and the control gate 220 and extends to cover the side wall surface of the isolation layer 204.

[0048] like Figure 5As shown, a first spacer material layer is formed, and the first spacer material layer is etched to form a first spacer 206; the first spacer material layer covers the isolation layer 204, the side surfaces of the hard mask layer 205 and the upper surface of the substrate 200, and the remaining first spacer material layer is etched to form the first spacer 206; the first spacer 206 covers the side surfaces of the hard mask layer 205.

[0049] like Figure 6 As shown, a second spacer oxide layer 207 is formed, and the second spacer oxide layer 207 covers the sidewall surface of the first spacer 206. A second spacer nitride layer 208 is formed, and the second spacer nitride layer 208 covers the sidewall surface of the second spacer oxide layer 207. The sidewalls of the flash memory cell include, from the inside to the outside, a hard mask layer 205, a first spacer 206, a second spacer oxide layer 207, and a second spacer nitride layer 208.

[0050] In the improved flash memory formation method attempted, the control gate material layer 202 and the floating gate material layer 201 are first etched to form the floating gate 210 and the control gate 220, and then the hard mask layer 205 is formed. The hard mask layer 205 covers the side surfaces of the floating gate 210 and the control gate 220 and extends upward to cover the side wall surface of the isolation layer 204. The thicker hard mask layer 205 makes the step at the junction of the control gate 220 and the isolation layer 204 away from the word line 203 gentler, and the first sidewall spacer 206 covers the side surface of the hard mask layer 205. The first sidewall spacer 206 avoids disconnection at the junction of the control gate 220 and the isolation layer 204 away from the word line 203.

[0051] The improved formation method of the attempted flash memory has the advantages that the hard mask layer 205 slows down the step at the junction of the control gate 220 and the isolation layer 204, and the first sidewall 206 is no longer disconnected. Disadvantages: The sidewalls outside the flash memory cell increase the thickness of the hard mask layer 205, occupying the space of the floating gate, word line and contact hole, which is not conducive to the reduction of the flash memory cell; in addition, the hard mask layer 205 is generally a PETEOS (plasma enhanced tetraethyl orthosilicate) film, which is formed by using TEOS (tetraethyl orthosilicate) and oxygen as raw materials and a PECVD (plasma enhanced chemical vapor deposition) process. One of the advantages of using TEOS and oxygen as raw materials to grow PETEOS film is good step coverage, because the mobility of its TEOS surface is large, which can avoid the generation of low-density areas or voids. However, another feature of the formation process of the hard mask layer 205, PETEOS, is that it needs to be activated by plasma, and plasma bombardment will cause physical damage to the gate oxide of the flash memory. Charging effect.

[0052] In the improved flash memory formation method attempted, although the first sidewall 206 is no longer disconnected, the hard mask layer 205 occupies the space of the floating gate, word line and contact hole, which is not conducive to the reduction of the flash memory cell. The inventor further studied this problem and provided a flash memory preparation method of the present invention.

[0053] The following is a further detailed description of a flash memory manufacturing method provided by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0054] For ease of description, some embodiments of the present application may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "below" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first", "second", etc. below are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms used in this way are interchangeable where appropriate.

[0055] The embodiment of the present invention provides a method for preparing a flash memory, such as Figure 7 As shown, including:

[0056] Step S1, providing a substrate, on which a floating gate material layer, a control gate material layer, and a plurality of word lines penetrating the control gate material layer and the floating gate material layer are formed; an isolation layer is formed above each word line, and the isolation layer covers the word line and the control gate material layer in adjacent areas on both sides of the word line;

[0057] Step S2, forming a hard mask layer, wherein the hard mask layer at least covers the side wall surface of the isolation layer that is perpendicular to the control gate material layer;

[0058] Step S3, forming a first sidewall spacer, wherein the first sidewall spacer is located on a sidewall surface of the hard mask layer;

[0059] Step S4, etching the control gate material layer and the floating gate material layer exposed by the isolation layer to form stacked floating gates and control gates located on both sides of each word line;

[0060] Step S5, forming a second spacer oxide layer, wherein the second spacer oxide layer at least covers the side surfaces of the floating gate and the control gate and extends upward to cover the side surface of the first spacer;

[0061] Step S6, forming a second sidewall nitride layer, wherein the second sidewall nitride layer covers the side surface of the second sidewall oxide layer.

[0062] Combine the following Figures 8 to 15 The accompanying drawings illustrate in detail the steps of the method for preparing the flash memory of the present invention.

[0063] like Figure 8 As shown, a substrate 300 is provided, and the substrate 300 provides a process platform for forming a flash memory. The material of the substrate 300 can be silicon, germanium or silicon germanium. The substrate 300 can also be silicon on insulator (SOI), germanium on insulator (GeOI) or silicon germanium on insulator (SiGeOI). In this embodiment, the material of the substrate 300 is, for example, single crystal silicon. A floating gate material layer 301, a control gate material layer 302 and a plurality of word lines 303 that penetrate the control gate material layer 302 and the floating gate material layer 301 are formed on the substrate 300; an isolation layer 304 is formed above each word line 303, and the isolation layer 304 covers the word line 303 and the control gate material layer 302 in the adjacent areas on both sides of the word line 303. The material of the isolation layer 304 is, for example, an oxide layer.

[0064] like Fig. 9 As shown, a hard mask material layer 350 is formed, and the hard mask material layer 350 covers the isolation layer 304 and the control gate material layer 302. The material of the hard mask material layer 350 can be silicon nitride.

[0065] like Fig.10 As shown, a first spacer material layer 306 is formed, and the first spacer material layer 306 covers the hard mask material layer 350 . The material for forming the first spacer material layer 306 may be silicon nitride.

[0066] like Fig.11 As shown, the first spacer material layer 306 and the hard mask material layer 350 are etched without a mask, and the remaining first spacer material layer 306 is etched to form a first spacer 360; the remaining hard mask material layer 350 is etched to form a hard mask layer 305. The hard mask layer 305 covers the sidewall surface of the isolation layer 304 and is perpendicular to the control gate material layer 302; the first spacer 360 is located on the sidewall surface of the hard mask layer 305. The maskless etching process can be a plasma dry etching process.

[0067] like Fig.12 As shown, the control gate material layer 302 and the floating gate material layer 301 exposed by the isolation layer 304 are etched to form a stacked floating gate 310 and a control gate 320 located on both sides of each word line; the process of etching to form the floating gate 310 and the control gate 320 can be a plasma dry etching process. Next, a second sidewall oxide layer 307 is formed, and the second sidewall oxide layer 307 covers the isolation layer 304, the side surface of the first sidewall 360, the side surface of the floating gate 310 and the control gate 320, and the upper surface of the substrate 300. The material of the second sidewall oxide layer 307 can be silicon oxide; the process of forming the second sidewall oxide layer 307 can be a thermal oxidation process. In this embodiment, the process parameters of the thermal oxidation process include: 2The flow rate is 12 sccm to 220 sccm, and the temperature of the reaction chamber is 680° C. to 1000° C. The second sidewall oxide layer 307 does not require a PETEOS process, thereby avoiding the gate oxide physical damage charging effect caused by plasma bombardment on the flash memory.

[0068] like Fig.13 As shown, a second spacer nitride material layer 308 is formed, and the second spacer nitride material layer 308 covers the surface of the second spacer oxide layer 307 .

[0069] like Fig.14 As shown, the second side wall nitride material layer 308 and the second side wall oxide layer 307 are etched without a mask, and the remaining second side wall oxide layer 307 is etched to cover the side surfaces of the floating gate 310 and the control gate 320 and the side surface of the first side wall 360; the remaining second side wall nitride material layer 308 is etched to form a second side wall nitride layer 380, and the second side wall nitride layer 380 covers the side surface of the remaining second side wall oxide layer 307.

[0070] The formed flash memory includes a number of flash memory cells, and the flash memory cells include a word line 303, a stacked floating gate 310 and a control gate 320 on both sides of the word line, an isolation layer 304, and a sidewall; the sidewall includes, from the side close to the word line 303 to the side away from the word line 303, a hard mask layer 305, a first sidewall 360, a second sidewall oxide layer 307, and a second sidewall nitride layer 380. A groove or gap for making a flash memory lead-out structure is formed between two adjacent flash memory cells. After forming the second sidewall nitride layer, the preparation method further includes: forming an interlayer dielectric layer (not shown), the interlayer dielectric layer fills the gap between adjacent flash memory cells and covers the flash memory cells.

[0071] Fig.15 for Fig.14 An enlarged schematic diagram of the middle side wall. Fig.16 for Figure 6 An enlarged schematic diagram of the middle side wall. Fig.16 As shown, the improved formation method of the attempted flash memory, the hard mask layer 205 slows down the step at the junction of the control gate 220 and the isolation layer 204, and the first sidewall 206 is no longer disconnected. Disadvantages: The sidewall outside the flash memory cell increases the thickness of the hard mask layer 205, which squeezes the space of the floating gate, word line and contact hole, which is not conducive to the reduction of the flash memory cell. Fig.15 The width of the two dashed lines in Fig.16 The two dashed lines in are of equal width. Fig.16 The width of the two dotted lines in is the width of the side wall. Fig.15As shown, the step of etching the control gate material layer 302 and the floating gate material layer 301 to form the floating gate 310 and the control gate 320 is arranged after forming the first sidewall 360 and before forming the second sidewall oxide layer 307. In this way, the junction between the control gate 320 and the isolation layer 304 away from the word line 303 is protected by the hard mask layer 305 and the first sidewall 360, and no step is formed at the junction. The first sidewall 360 does not need to be formed on the step, so the first sidewall 360 is no longer disconnected, and the size of the outer sidewall of the flash memory cell is reduced. At the same time, the thinning of the sidewall reduces the aspect ratio of the interlayer dielectric layer and increases the filling window; moreover, the second sidewall oxide layer 307 does not require the PETEOS process, so the gate oxide physical damage charging effect caused by plasma bombardment on the flash memory is also avoided.

[0072] In summary, the present invention provides a flash memory and a preparation method thereof, the preparation method comprising: providing a substrate, on which a floating gate material layer, a control gate material layer and a plurality of word lines are formed; forming an isolation layer above each word line; forming a hard mask layer, the hard mask layer at least covers the side wall surface of the isolation layer perpendicular to the control gate material layer; forming a first side wall, the first side wall is located on the side wall surface of the hard mask layer; etching the control gate material layer and the floating gate material layer exposed by the isolation layer to form stacked floating gates and control gates located on both sides of each word line; forming a second side wall oxide layer, the second side wall oxide layer at least covers the side surfaces of the floating gate and the control gate and extends upward to cover the side surface of the first side wall; forming a second side wall nitride layer, the second side wall nitride layer covers the side surface of the second side wall oxide layer. The steps of forming the floating gate and the control gate of the present invention are arranged after forming the first sidewall and before forming the second sidewall oxide layer. In this way, the junction between the control gate and the isolation layer away from the word line is protected by the first sidewall, and no step is formed at the junction. The first sidewall does not need to be formed on the step, so the first sidewall is no longer disconnected, the size of the sidewall outside the flash memory cell is reduced, and at the same time, the thinning of the sidewall reduces the aspect ratio of the interlayer dielectric layer and increases the filling window.

[0073] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the device disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0074] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a flash memory, characterized in that: include: Providing a substrate, on which a floating gate material layer, a control gate material layer, and a plurality of word lines penetrating the control gate material layer and the floating gate material layer are formed; An isolation layer is formed above each word line, and the isolation layer covers the word line and the control gate material layer in adjacent areas on both sides of the word line; forming a hard mask layer, wherein the hard mask layer at least covers a sidewall surface of the isolation layer that is perpendicular to the control gate material layer; forming a first sidewall spacer, wherein the first sidewall spacer is located on a sidewall surface of the hard mask layer; Etching the control gate material layer and the floating gate material layer exposed by the isolation layer to form a stacked floating gate and a control gate located on both sides of each word line; forming a second spacer oxide layer, wherein the second spacer oxide layer at least covers the side surfaces of the floating gate and the control gate and extends upward to cover the side surface of the first spacer; A second sidewall nitride layer is formed, wherein the second sidewall nitride layer covers a side surface of the second sidewall oxide layer.

2. The method for preparing a flash memory according to claim 1, wherein: Forming the hard mask layer and the first sidewall specifically includes: forming a hard mask material layer, wherein the hard mask material layer covers the isolation layer and the control gate material layer; forming a first spacer material layer, wherein the first spacer material layer covers the hard mask material layer; The first spacer material layer and the hard mask material layer are etched without a mask, and the first spacer material layer remaining after etching forms the first spacer; and the hard mask material layer remaining after etching forms the hard mask layer.

3. The method for preparing a flash memory according to claim 1, wherein: The material of the second sidewall oxide layer is silicon oxide; The process for forming the second sidewall oxide layer is a thermal oxidation process; the parameters of the thermal oxidation process include: an O2 flow rate of 12 sccm to 220 sccm, and a reaction chamber temperature of 680° C. to 1000° C.

4. The method for preparing a flash memory according to claim 1, wherein: The formed flash memory includes a plurality of flash memory cells, and the flash memory cells include the word line, the stacked floating gate and the control gate on both sides of the word line, the isolation layer and the sidewall; The spacer includes, in order from a side close to the word line to a side far from the word line: the hard mask layer, the first spacer, the second spacer oxide layer and the second spacer nitride layer.

5. The method for preparing a flash memory according to claim 4, characterized in that: After forming the second sidewall nitride layer, the preparation method further includes: An interlayer dielectric layer is formed, wherein the interlayer dielectric layer fills the gaps between adjacent flash memory cells and covers the flash memory cells.

6. The method for preparing a flash memory according to claim 1, wherein: The thickness of the second sidewall oxide layer is 150-200 angstroms.

7. The method for preparing a flash memory according to claim 1, wherein: The thickness of the second sidewall nitride layer is 350-500 angstroms.

8. A flash memory, characterized in that: include: A substrate, on which a word line and a floating gate and a control gate stacked on both sides of the word line are formed; an isolation layer is formed above the word line, and the isolation layer covers the word line and the control gates on both sides of the word line; a hard mask layer, wherein the hard mask layer at least covers a sidewall surface of the isolation layer that is perpendicular to the control gate; A first spacer, wherein the first spacer is located on a sidewall surface of the hard mask layer; A second spacer oxide layer, wherein the second spacer oxide layer at least covers the side surfaces of the floating gate and the control gate and extends upward to cover the side surface of the first spacer; A second sidewall nitride layer, wherein the second sidewall nitride layer covers a side surface of the second sidewall oxide layer.

9. The flash memory according to claim 8, wherein: The flash memory includes a plurality of flash memory cells, and the flash memory cells include the word line, the stacked floating gate and the control gate on both sides of the word line, the isolation layer and the spacer; The spacer includes, in order from a side close to the word line to a side far from the word line: the hard mask layer, the first spacer, the second spacer oxide layer and the second spacer nitride layer.

10. The flash memory according to claim 9, wherein: The flash memory further includes an interlayer dielectric layer, wherein the interlayer dielectric layer fills the gaps between adjacent flash memory cells and covers the flash memory cells.

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