Dynamic element matching of bipolar junction transistors for improved voltage determination proportional to absolute temperature

Abstract

The invention relates to dynamic element matching of bipolar junction transistors for improved voltage determination proportional to absolute temperature. An integrated circuit includes a current source, a plurality of parallel transistors, a plurality of switches, a switch control circuit, and a measurement circuit. Each switch selectively couples a current source to a respective transistor. The switch control circuit is configured to, at different times, close all the switches and, for each transistor, respectively close the switch associated with each transistor while open all the other switches. The measurement circuit is configured to measure, for each transistor, a base-emitter voltage (VBE) when all switches are closed and a VBE when only a switch associated with each transistor is closed, respectively, a delta VBE for each transistor of the plurality of transistors is determined by calculating a difference between the VBE when only the switch associated with each transistor is closed and the VBE when all the switches are closed, and an average of all the delta VBE is calculated.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application Serial No. 63 / 525,036, filed on July 5, 2023, entitled “DYNAMIC ELEMENT MATCHING OF BIPOLAR JUNCTION TRANSISTORS FOR IMPROVED PROPORTIONAL TO ABSOLUTETEMPERATURE VOLTAGE DETERMINATION,” which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate generally to electronic circuits and, more particularly, to dynamic component matching for integrated circuits. Background Art

[0004] Applicants have discovered many technical challenges and difficulties associated with using a voltage proportional to absolute temperature for temperature measurement. Through hard work, ingenuity, and innovation, Applicants have solved the problems associated with using a voltage proportional to absolute temperature for temperature measurement by developing the solutions embodied in the present disclosure, which are described in detail below. Summary of the invention

[0005] Various embodiments described herein relate to systems, devices, products, and methods for temperature measurement using a PTAT voltage.

[0006] According to some embodiments of the present disclosure, an example integrated circuit is provided. In some embodiments, the example integrated circuit includes a current source, a plurality of transistors arranged in parallel, a plurality of switches, a switch control circuit, and a measurement circuit. Each of the plurality of transistors has an emitter and a base. Each of the plurality of switches selectively couples a current source to the emitter of a corresponding transistor in the plurality of transistors, so that when the corresponding one or more switches are closed, a bias current flows from the current source to the emitter of the corresponding one or more transistors in the plurality of transistors. The switch control circuit is configured to close all switches at different times, and for each transistor, respectively close the switch associated with each transistor while opening all other switches. The measurement circuit is coupled to each of the plurality of transistors between each corresponding switch and the emitter of each corresponding transistor. The measurement circuit is configured to measure, for each of the plurality of transistors, a base-emitter voltage (VBE) when all switches are closed and a VBE when only the switch associated with each transistor is closed. The measurement circuit is further configured to determine a ΔVBE for each of the plurality of transistors by calculating, for each of the plurality of transistors, a difference between a VBE when only a switch associated with each transistor is closed and a VBE when all switches are closed. The measurement circuit is further configured to calculate an average of all determined ΔVBEs.

[0007] In some embodiments, the measurement circuit is further configured to calculate the temperature based on a calculated average of all determined ΔVBEs.

[0008] In some embodiments, the measurement circuit includes an analog-to-digital converter for converting the calculated average of all determined ΔVBEs from an analog value to a digital value.

[0009] In some embodiments, each transistor of the plurality of transistors comprises a bipolar junction transistor.

[0010] In some embodiments, each of the plurality of bipolar junction transistors comprises a parasitic bipolar junction transistor of complementary metal oxide semiconductor (CMOS) technology.

[0011] In some embodiments, the plurality of transistors includes four to eight transistors.

[0012] In some embodiments, the bias current from the current source is selected to be within an operating region of the plurality of transistors.

[0013] In some embodiments, the bias current from the current source is selected to be between a high injection region and a low injection region of the plurality of transistors.

[0014] According to some embodiments of the present disclosure, an example method is provided. In some embodiments, the example method includes, for each transistor of a plurality of transistors arranged in parallel, each transistor of the plurality of transistors has an emitter and a base, the emitter of each transistor of the plurality of transistors is selectively coupled to a current source via a corresponding switch of a plurality of switches, so that when the corresponding one or more switches are closed, a bias current flows from the current source to the emitter of the corresponding one or more transistors of the plurality of transistors, respectively measuring a base-emitter voltage (VBE) when all switches are closed and a VBE when only a switch associated with each transistor is closed; determining a ΔVBE of each transistor of the plurality of transistors by calculating the difference between the VBE when only a switch associated with each transistor is closed and the VBE when all switches are closed for each transistor of the plurality of transistors; calculating an average of all determined ΔVBEs; and calculating a temperature using the average of all determined ΔVBEs.

[0015] In some embodiments, the method further includes converting each of the measured VBEs from an analog value to a digital value.

[0016] In some embodiments, each transistor of the plurality of transistors comprises a bipolar junction transistor.

[0017] In some embodiments, each of the plurality of bipolar junction transistors comprises a parasitic bipolar junction transistor of CMOS technology.

[0018] In some embodiments, the plurality of transistors includes four to eight transistors.

[0019] In some embodiments, the bias current from the current source is selected to be within an operating region of the plurality of transistors.

[0020] In some embodiments, the bias current from the current source is selected to be between a high injection region and a low injection region of the plurality of transistors.

[0021] According to some embodiments of the present disclosure, an example temperature sensor is provided. In some embodiments, the example temperature sensor includes a current source, a plurality of transistors arranged in parallel, a plurality of switches, a switch control circuit, and a measurement circuit. Each of the plurality of transistors has an emitter and a base. Each of the plurality of switches selectively couples a current source to the emitter of a corresponding transistor in the plurality of transistors, so that when the corresponding one or more switches are closed, a bias current flows from the current source to the emitter of the corresponding one or more transistors in the plurality of transistors. The switch control circuit is configured to close all switches at different times, and for each transistor, respectively close the switch associated with each transistor while opening all other switches. The measurement circuit is coupled to each of the plurality of transistors between each corresponding switch and the emitter of each corresponding transistor. The measurement circuit is configured to measure, for each of the plurality of transistors, a base-emitter voltage (VBE) when all switches are closed and a VBE when only the switch associated with each transistor is closed. The measurement circuit is further configured to determine a ΔVBE for each of the plurality of transistors by calculating, for each of the plurality of transistors, a difference between a VBE when only a switch associated with each transistor is closed and a VBE when all switches are closed. The measurement circuit is further configured to calculate an average of all determined ΔVBEs.

[0022] In some embodiments, the measurement circuit is further configured to calculate the temperature based on a calculated average of all determined ΔVBEs.

[0023] In some embodiments, the measurement circuit includes an analog-to-digital converter for converting the calculated average of all determined ΔVBEs from an analog value to a digital value. Alternatively, each ΔVBE may be sampled, amplified, and digitized by the ADC, and its digital value may be stored. Once all amplified ΔVBEs are digitized, all amplified ΔVBEs may be averaged in the digital domain.

[0024] In some embodiments, each transistor of the plurality of transistors comprises a bipolar junction transistor.

[0025] In some embodiments, the bias current from the current source is selected to be within an operating region of the plurality of transistors.

[0026] The above overview is provided only for the purpose of summarizing some example embodiments to provide a basic understanding of certain aspects of the present disclosure. Therefore, it will be understood that the above embodiments are merely examples and should not be interpreted as narrowing the scope or spirit of the present disclosure in any way. It will also be appreciated that the scope of the present disclosure also includes many potential embodiments in addition to those embodiments summarized here, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The description of the illustrative embodiments may be read in conjunction with the accompanying drawings. It should be understood that for simplicity and clarity of illustration, the elements illustrated in the drawings are not necessarily drawn to scale unless otherwise described. For example, the size of some elements may be exaggerated relative to other elements unless otherwise described. Embodiments incorporating the teachings of the present disclosure are shown and described in conjunction with the accompanying drawings set forth herein, in which:

[0028] Figure 1 illustrates a block diagram of an example system for temperature measurement using a voltage proportional to absolute temperature according to an example embodiment of the present disclosure;

[0029] Figure 2 illustrates a circuit diagram of dynamic element matching of a bipolar junction transistor according to an example embodiment of the present disclosure;

[0030] Figure 3 is an example flow chart illustrating an example method of temperature measurement using a PTAT voltage according to an example embodiment of the present disclosure; and

[0031] Figure 4-Figure 7 FIG. 1 illustrates various states of an implementation of an example method for temperature measurement using a PTAT voltage according to an example embodiment of the present disclosure. Figure 2 circuit. DETAILED DESCRIPTION

[0032] Some embodiments of the present disclosure will now be described more fully below in conjunction with the accompanying drawings, in which some but not all embodiments of the present disclosure are shown. In fact, these disclosures may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will satisfy applicable legal requirements. The same reference numerals identify the same elements throughout.

[0033] As used herein, terms such as "front", "rear", "top", etc. are used for explanatory purposes in the examples provided below to describe the relative positions of certain components or parts of components. In addition, based on this disclosure, it will be apparent to those of ordinary skill in the art that the terms "substantially" and "approximately" mean that the referenced elements or associated descriptions are accurate within applicable engineering tolerances.

[0034] As used herein, the term "comprising" means including but not limited to, and should be interpreted in the manner commonly used in a patent context. The use of broader terms such as including, comprising, and having should be understood to provide support for narrower terms such as consisting of, consisting substantially of, and consisting essentially of.

[0035] The phrases "in one embodiment," "according to one embodiment," and the like generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, these phrases are not necessarily referring to the same embodiment).

[0036] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0037] If the specification states that a component or feature "may", "could", "might", "should", "would", "preferably", "likely", "usually", "optionally", "for example", "often", or "might" (or other such language) be included or have a property, then the particular component or feature is not required to be included or have the property. Such components or features may optionally be included in some embodiments, or may be excluded.

[0038] As integrated circuit (IC) density and operating speeds increase, among other things, it is important in some cases to monitor the temperature of the integrated circuit. If the temperature is too high (e.g., above 85 degrees Celsius), the IC may be damaged. If it is sensed that the temperature of the IC is increasing, remedial measures may be taken to reduce the temperature. For example, in some cases, the remedial measures may include reducing the frequency and / or voltage of the IC.

[0039] One approach that has been used to determine the temperature of an IC uses a proportional to absolute temperature (PTAT) voltage. When using a PTAT voltage for temperature sensing, it is important to be able to determine the PTAT voltage with a desired accuracy. One approach that has been used to determine the PTAT voltage is to calculate the difference between the base-emitter voltages of two bipolar junction transistors (BJTs) biased at different current densities. However, the accuracy of this approach is limited by the accuracy of the bias current ratio, which is sensitive to mismatch errors.

[0040] Errors due to mismatches between current sources and transistors can be reduced by swapping them dynamically. This technique is called dynamic element matching (DEM). One approach that has been used implements DEM in the current sources that bias the BJT. Since MOS (metal oxide semiconductor) current sources have very high mismatches to begin with, the residual inaccuracy may not be low enough even after DEM of these current sources. In addition, previous attempts to implement DEM in BJTs while using only one current source were prone to switch IR drop mismatches, further degrading performance.

[0041] Various embodiments of the present disclosure overcome the above technical challenges and difficulties, and provide a variety of technical improvements and advantages. For example, various embodiments of the present disclosure provide an example system for generating a PTAT voltage using dynamic element matching of a BJT in a manner where the accuracy is not limited by switch resistance or current source mismatch, thereby achieving better accuracy than other schemes that have been used. Various embodiments of the present disclosure at least provide an integrated circuit, method, and temperature sensor for obtaining a more accurate ΔVBE.

[0042] Various embodiments of the present disclosure use only one current source, thereby eliminating current source mismatch. In addition, various embodiments of the present disclosure sample the base-emitter voltage (VBE) of the same BJT at different current densities. In addition, various embodiments of the present disclosure sample the VBE at the emitter of each BJT (at different current densities), thereby eliminating switch IR drop mismatch.

[0043] Various embodiments of the present disclosure obtain a higher current density VBE1 by causing the entire bias current to flow in one BJT, and a lower current density VBE2 by causing the bias current to flow through multiple such BJTs (as described below, the number of BJTs can vary and can be represented as "p") arranged in parallel. Various embodiments of the present disclosure reduce BJT mismatch by sampling all such VBE pairs from different BJTs, thereby producing p different ΔVBE. Various embodiments of the present disclosure average the p different ΔVBE to obtain a ΔVBEavg value. Averaging ΔVBE greatly reduces the impact of BJT mismatch in the resulting ΔVBEavg. In various embodiments of the present disclosure, the ΔVBEavg value is the PTAT value used for temperature calculations.

[0044] Compared to some solutions that have been used, various embodiments of the present disclosure provide a more accurate PTAT voltage and have a smaller footprint because fewer components are used (eg, only one current source).

[0045] Reference now Figure 1, a block diagram of an example system 100 for temperature measurement using a PTAT voltage is illustrated, according to an example embodiment of the present disclosure. The example system 100 may include a controller 102, a dynamic element matching circuit 104, a VBE sampling / PTAT amplification circuit 114, and an analog-to-digital converter (ADC) 112. The example system 100 may be implemented as part of an IC to perform temperature measurement of the IC. Such an IC may be any IC for which temperature measurement is desired, such as, but not limited to, a multi-core processor, a central processing unit, a graphics processing unit, a digital signal processor, a computationally intensive application specific integrated circuit, and the like.

[0046] As combined with the following Figure 2 As further described, in some embodiments, the dynamic element matching circuit 104 includes a current source 106, a plurality of switches 108, and a plurality of transistors 110. In some embodiments, each of the plurality of switches 108 selectively couples the current source 106 to an emitter of a corresponding transistor in the plurality of transistors 110, such that when one or more of the plurality of switches 108 are closed, a bias current flows from the current source 106 to the emitter of one or more of the plurality of transistors 110.

[0047] In some embodiments, the plurality of transistors include a plurality of bipolar junction transistors. In some embodiments, the plurality of bipolar junction transistors include a plurality of parasitic bipolar junction transistors of complementary metal oxide semiconductor (CMOS) technology. In some embodiments, the current source 106 is a single current source. In some embodiments, the bias current from the current source is selected to be within the operating region of the plurality of transistors. In some embodiments, the bias current from the current source is selected to be between the high injection region and the low injection region of the plurality of transistors.

[0048] like Figure 1As shown, an example system 100 for temperature measurement using a PTAT voltage includes a controller 102. The controller 102 may include one or more processors, input / output circuits, data storage media, communication circuits, and / or other components configured to perform computing operations. In some embodiments, the data storage medium may be configured to store information, data, content, applications, instructions, etc., for enabling the controller 102 to perform a variety of functions. Therefore, in some embodiments, the controller 102 may be referred to as functional logic. The controller 102 may be implemented in a variety of different ways, for example, in some embodiments, the controller 102 may include one or more processing devices configured to execute independently. Additionally or alternatively, in some embodiments, the controller 102 may include one or more processors that are configured in tandem via a bus to enable independent execution of instructions, pipelines, and / or multithreading. The use of the terms "controller", "processor", and "processing circuit" should be understood to include a single-core processor, a multi-core processor, multiple processors within the controller 102, and / or one or more remote or "cloud" processors outside the controller 102.

[0049] In an example embodiment, the controller 102 may be configured to execute instructions stored in a data storage medium or otherwise accessible to the processor. Alternatively or additionally, in some embodiments, the controller 102 is configured to execute hard-coded functionality. Therefore, whether configured by hardware or software methods, or by a combination thereof, the controller 102 represents an entity (e.g., physically implemented in a circuit) that is capable of performing operations in accordance with the embodiments of the present disclosure and is configured accordingly. Alternatively or additionally, as another example, in some example embodiments, when the controller 102 is implemented as an executor of software instructions, the instructions specifically configure the controller 102 to perform algorithms implemented in the specific operations described herein when executing these instructions.

[0050] In some embodiments, Figure 1As shown, the controller 102 includes a current switch control circuit 116 and a measurement circuit 118. When one or more of the plurality of switches 108 are closed, a bias voltage (not shown) biases the current source 106 to provide a fixed current value. In some embodiments, the switch control circuit 116 includes hardware, software, firmware, and / or a combination thereof for selectively opening or closing each of the plurality of switches 108, thereby causing the bias current from the current source 106 to flow to one or more of the plurality of transistors 110 depending on the state of the switch (i.e., open or closed), as further described below. In some embodiments, the VBE sampling / PTAT amplification circuit 114 includes hardware, software, firmware, and / or a combination thereof for sampling and storing the base-emitter voltage (VBE) of each of the plurality of transistors 110 (such as in a switched capacitor arrangement), determining a ΔVBE for each of the plurality of transistors, calculating an average of all the determined ΔVBEs, as further described below, and amplifying the PTAT voltage to feed it in the ADC 112 for digitization. In some embodiments, the VBE sampling / PTAT amplification circuit 114 measures (or samples) the base-emitter voltage (VBE) of each of the plurality of transistors 110 at low current density and high current density, thereby determining ΔVBE, as described below. In some embodiments, the measurement circuit 118 includes hardware, software, firmware, and / or a combination thereof for receiving and storing the digitized PTAT voltage relative to a reference voltage (Vref) from the ADC 112, controlling the timing / sequence of the VBE sampling / PTAT amplification circuit 114 and the ADC 112 to calculate the temperature (in degrees Celsius), and providing a digitized temperature output. In some alternative embodiments, all ΔVBE are sampled and stored together by the VBE sampling / PTAT amplification circuit 114. In this regard, the result is p*ΔVBE, which is the sum of all ΔVBE, thereby achieving both amplification and averaging. In some alternative embodiments, each ΔVBE sample (with or without amplification) may be fed to a delta-sigma (delta-sum) based ADC (DEM) in a random order for digitization, thereby exploiting the oversampling nature of the ADC to achieve averaging.

[0051] Although the components are described in conjunction with functional limitations, it should be understood that specific implementations necessarily include the use of specific hardware. It should also be understood that certain components described herein may include similar or common hardware. For example, both sets of circuits may fully utilize the same processor, network interface, storage medium, etc. to perform their associated functions, so that no duplicate hardware is required for each set of circuits.

[0052] The term "circuitry" as used herein with respect to components of an apparatus should be understood to include specific hardware configured to perform the functions associated with the specific circuits described herein. The term "circuitry" should be broadly understood to include hardware, and in some embodiments, software for configuring the hardware. For example, in some embodiments, a "circuitry" may include processing circuitry, storage media, network interfaces, input / output devices, and the like.

[0053] Although Figure 1 The example block diagram of FIG. 1 illustrates an example system 100 for temperature measurement using a PTAT voltage, but note that the scope of the present disclosure is not limited to Figure 1 In some embodiments, the example system for temperature measurement using a PTAT voltage may include one or more additional or alternative components.

[0054] Reference now Figure 2 , illustrates a circuit schematic diagram for dynamic element matching of a bipolar junction transistor according to an example embodiment of the present disclosure. Figure 2 As shown, the dynamic element matching circuit 104 includes a current source 106 , a plurality of transistors 110 arranged in parallel, and a plurality of switches 108 therebetween.

[0055] In some embodiments, the number of transistors in the dynamic element matching circuit 104 can vary. A smaller number of transistors provides a relatively shorter cycle time, but is more susceptible to noise. Conversely, a larger number of transistors is less susceptible to noise, but will have a longer cycle time. In some embodiments, the number of transistors is between four and eight. As described herein, the number of transistors may be represented as "p". In the illustrated embodiment, each of the plurality of transistors 110 is individually labeled Q1 to Qp to indicate the number of potential variations of the transistor.

[0056] Each of the plurality of switches 108 selectively couples the current source 106 to the emitter of a corresponding transistor in the plurality of transistors 110. As such, when the corresponding one or more switches 108 are closed, a bias current ("Ibias") flows from the current source 106 to the emitter of the corresponding one or more transistors in the plurality of transistors 110. In the illustrated embodiment, each of the plurality of switches 108 is individually labeled S1 to Sp to indicate the number of potential variations of the switches. As shown, switch S1 selectively couples transistor Q1 to the current source 106, switch S2 selectively couples transistor Q2 to the current source 106, switch S3 selectively couples transistor Q3 to the current source 106, and so on.

[0057] In some embodiments, Figure 2As shown, there is a connection point at or adjacent to the emitter of each transistor that is used to measure the VBE of each corresponding transistor. In the illustrated embodiment, each of the plurality of connection points is individually labeled VBE1 to VBEp to indicate the number of potential changes in the connection point (based on the number of changes in the transistor). Although not shown, in some embodiments, each of the connection points VBE1 to VBEp is coupled to ADC 112 to enable VBE to be converted from analog to digital for use in measurement circuit 118.

[0058] Figure 4-Figure 7 The present disclosure is illustrated in various states of implementation. Figure 2 For simplicity, reference numerals 108 and 110 are Figure 4-Figure 7 Omitted in .

[0059] Reference now Figure 3 , provides an example flow chart illustrating an example method according to some embodiments of the present disclosure.

[0060] It is worth noting that each block of the flowchart and the combination of blocks in the flowchart can be implemented in a variety of ways, such as hardware, firmware, circuits and / or other devices associated with executing software including one or more programming instructions. Figure 3 One or more methods described in the present disclosure may be implemented by programming instructions, which may be stored in a non-transitory memory component of a device using an embodiment of the present disclosure and executed by one or more processing components in the device. These programming instructions may direct the processing component or other programmable device to work in a specific manner so that the instructions stored in the non-transitory memory component produce an article of manufacture that performs the functions specified in the (one or more) flowchart blocks.

[0061] As described above, and as will be understood based on the present disclosure, the embodiments of the present disclosure may be configured as methods, devices, etc. Therefore, the embodiments may include a variety of schemes (means) that completely include hardware or include any combination of software and hardware. In addition, the embodiments may take the form of a computer program product on at least one non-transitory computer-readable storage medium, and the non-transitory storage medium has computer-readable program instructions (e.g., computer software) implemented in the storage medium. Similarly, the embodiments may take the form of a computer program code stored on at least one non-transitory computer-readable storage medium. Any suitable computer-readable storage medium may be used, including a non-transitory hard disk, a CD-ROM, a flash memory, an optical storage device, or a magnetic storage device.

[0062] Reference now Figure 3, illustrates an example method 300 according to some embodiments of the present disclosure. In particular, the example method 300 illustrates example steps / operations for calculating temperature using a dynamic element matching circuit according to some embodiments of the present disclosure.

[0063] At step / operation 302, a controller (such as, but not limited to, the controller described above) Figure 1 Controller 102 of system 100 described above sets counter n to 1. In some embodiments, this counter is used to ensure that VBE is determined for each transistor in dynamic element matching circuit 104.

[0064] At step / operation 304, a controller (such as, but not limited to, the controller described above with respect to Figure 1 The controller 102 of the system 100 described above, in cooperation with the switch control circuit 116, closes the nth switch (S1 in this case) while opening all other switches. Figure 4 , illustrates the dynamic element matching circuit 104 with switch S1 closed and all other switches (S2 to Sp) open.

[0065] Now return to Figure 3 At step / operation 306, due to the closing of switch S1, the bias current flows out of the current source 106. Since only switch S1 is closed at this time, Figure 4 As shown, the entire bias current flows through switch S1 to transistor Q1.

[0066] Now return to Figure 3 At step / operation 308, a controller (such as, but not limited to, the controller described above) Figure 1 The controller 102 of the described system 100, in cooperation with the measurement circuit 118, measures (or samples) the base-emitter voltage at the emitter of the transistor Q1, and stores the measured / sampled value. In some embodiments, the measured (or sampled) VBE is referred to as VBE1,1 because it is the first VBE measurement through the first transistor. The VBE measurement provides a higher current density for the transistor.

[0067] At step / operation 310, a controller (such as, but not limited to, the controller described above) Figure 1 The controller 102 of the described system 100, in conjunction with the switch control circuit 116, causes all switches to close. Figure 5 , illustrates the dynamic element matching circuit 104 , where all switches S1 to Sp are closed.

[0068] Return now Figure 3At step / operation 312, due to the closing of all switches, bias current flows out of current source 106. Since all switches are closed at this time, bias current flows through all switches to all transistors, such as Figure 5 Because the transistors are arranged in parallel, the bias current flowing to each transistor is nominally Ibias / p.

[0069] Now return to Figure 3 At step / operation 314, a controller (such as, but not limited to, the controller described above) Figure 1 The controller 102 of the described system 100, in conjunction with the measurement circuit 118, measures (or samples) the base-emitter voltage at the emitter of the transistor Q1, and stores the measured / sampled value. In some embodiments, the measured (or sampled) VBE is referred to as VBE2,1 because it is the second VBE measurement through the first transistor. The VBE measurement provides a lower current density for the transistor.

[0070] At step / operation 316, a controller (such as, but not limited to, the controller described above with respect to Figure 1 The controller 102 of the described system 100, in conjunction with the measurement circuit 118, calculates the ΔVBE of the transistor Q1 by subtracting VBE2,1 from VBE1,1, and saves this value (which may be referred to as ΔVBE1) in a memory. Alternatively, this ΔVBE1 (VBE1,1-VBE2,1) may be stored in a switched capacitor arrangement (and possibly amplified) and may be digitized for storage.

[0071] At step / operation 318, a controller (such as, but not limited to, the controller described above with respect to Figure 1 The controller 102 of the system 100 described above determines whether the counter value n is equal to the number p of transistors in the dynamic element matching circuit 104. If it is determined at step / operation 318 that the counter value n is not equal to the number p of transistors, then the example method 300 proceeds to step / operation 320. At this point in the process, the counter n is equal to 1, so the example method 300 proceeds to step / operation 320.

[0072] At step / operation 320, a controller (such as, but not limited to, Figure 1 The controller 102 of the described system 100 increases the counter by 1 and the example method 300 returns to step / operation 304.

[0073] At step / operation 304, a controller (such as, but not limited to, the controller described above with respect to Figure 1 The controller 102 of the described system 100, in conjunction with the switch control circuit 116, closes the nth switch (S2 in this case) while opening all other switches. Figure 6 , illustrates the dynamic element matching circuit 104 with switch S2 closed and all other switches (S1 and S3 to Sp) open.

[0074] Return now Figure 3 At step / operation 306, due to the closing of switch S2, the bias current flows out of the current source 106. Since only switch S2 is closed at this time, Figure 6 As shown, the entire bias current flows through switch S2 to transistor Q2.

[0075] Now return to Figure 3 At step / operation 308, a controller (such as, but not limited to, the controller described above) Figure 1 The controller 102 of the described system 100, in conjunction with the measurement circuit 118, measures (or samples) the base-emitter voltage at the emitter of transistor Q2. In some embodiments, the measured (or sampled) VBE is referred to as VBE1,2 because it is the first VBE measurement through the second transistor. The VBE measurement provides a higher current density for the transistor.

[0076] At step / operation 310, a controller (such as, but not limited to, the controller described above) Figure 1 The controller 102 of the described system 100, in conjunction with the switch control circuit 116, causes all switches to close. Figure 7 , illustrates the dynamic element matching circuit 104 , where all switches S1 to Sp are closed.

[0077] Return now Figure 3 At step / operation 312, due to the closing of all switches, the bias current flows out of the current source 106. Since all switches are closed at this time, the bias current flows through all switches to all transistors, such as Figure 7 Because the transistors are arranged in parallel, the bias current flowing to each transistor is nominally Ibias / p.

[0078] Now return to Figure 3 At step / operation 314, a controller (such as, but not limited to, the controller described above) Figure 1 The controller 102 of the described system 100, in conjunction with the measurement circuit 118, measures (or samples) the base-emitter voltage at the emitter of transistor Q2. In some embodiments, the measured (or sampled) VBE is referred to as VBE2,2 because it is a second VBE measurement through the second transistor. The VBE measurement provides a lower current density for the transistor.

[0079] At step / operation 316, a controller (such as, but not limited to, the controller described above with respect to Figure 1The controller 102 of the described system 100, in conjunction with the measurement circuit 118, calculates the ΔVBE of transistor Q2 by subtracting VBE2,2 from VBE1,2, and saves this value (which may be referred to as ΔVBE2) in memory. Alternatively, this ΔVBE2 (VBE1,2-VBE2,2) may be stored in a switched capacitor arrangement (and possibly amplified) and may be digitized for storage.

[0080] At step / operation 318, a controller (such as, but not limited to, the controller described above with respect to Figure 1 The controller 102 of the described system 100 determines whether the counter value n is equal to the number p of transistors in the dynamic element matching circuit 104. If it is determined at step / operation 318 that the counter value n is not equal to the number p of transistors, then the example method 300 proceeds to step / operation 320. At this point in the process, the counter n=2, so the example method 300 proceeds to step / operation 320.

[0081] Steps / operations 304 through 318 will repeat until the counter value n equals the number of transistors p. That is, in some embodiments, steps / operations 304 through 318 will repeat until ΔVBE is determined for each transistor in the dynamic element matching circuit 104. In some embodiments, these values ​​of ΔVBE are referred to as ΔVBE1 through ΔVBEp. If it is determined at step / operation 318 that the counter value n equals the number of transistors p, then the example method 300 proceeds to step / operation 322.

[0082] At step / operation 322, a controller (such as, but not limited to, the controller described above with respect to Figure 1 The controller 102 of the described system 100, in conjunction with the measurement circuit 118, calculates the average of all ΔVBE values ​​(ΔVBE1 to ΔVBEp). The average of all ΔVBE values ​​may be referred to as ΔVBEavg and may be calculated using the formula:

[0083] At step / operation 324, a controller (such as, but not limited to, the controller described above with respect to Figure 1 The controller 102 of the system 100 described above, in conjunction with the measurement circuit 118, uses ΔVBEavg as the PTAT voltage to calculate the temperature of the IC. The process of calculating the temperature based on the PTAT voltage is conventionally known. In some embodiments, the conventionally known formula is used. to calculate the temperature T. Since k, q, and ln(p) in this formula are constants, ΔVBEavg is multiplied by a conventional known scalar value and then converted from degrees Kelvin to degrees Celsius.

[0084] in conclusion

[0085] With the benefit of the teachings given in the above description and the related drawings, those skilled in the art to which the present disclosure belongs will think of many modifications and other embodiments of the present disclosure set forth herein. Although the drawings only show certain components of the devices and systems described herein, it should be understood that a variety of other components can be used in conjunction with the system. Therefore, it should be understood that the present disclosure is not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included within the scope of the appended claims. In addition, the steps in the above method may not necessarily occur in the order shown in the drawings, and in some cases, one or more of the steps shown may occur substantially simultaneously, or may involve additional steps. Although specific terms are used herein, they are used only in a general and descriptive sense, and not for the purpose of limitation.

[0086] Although various embodiments according to the principles disclosed herein have been shown and described above, those skilled in the art may modify them without departing from the spirit and teachings of the present disclosure. The embodiments described herein are representative only and are not intended to be limiting. Many variations, combinations and modifications are possible and within the scope of the present disclosure. Alternative embodiments produced by combining, integrating and / or omitting the features of (one or more) embodiments are also within the scope of the present disclosure. Therefore, the scope of protection is not limited by the above description.

[0087] Additionally, the section headings used herein are provided to be consistent with the recommendations under 37 CFR 1.77, or to otherwise provide a hint of the organizational structure of this document. These headings shall not limit or characterize the disclosure set forth in any claim(s) that may arise from this disclosure.

[0088] Although the detailed description sets forth some embodiments of the present disclosure, the appended claims cover other embodiments of the present disclosure that differ from the described embodiments according to various modifications and improvements. For example, the appended claims may cover any form of integrated circuits where temperature measurement is desired, such as but not limited to multi-core processors, digital signal processors, application specific integrated circuits, etc.

[0089] In the following claims, unless the specific terms "means for" or "step for" are used in a given claim, it is not intended that the claim be interpreted under 35 USC 112, paragraph 6.

Claims

1. An integrated circuit, comprising: Current source; a plurality of transistors arranged in parallel, each transistor of the plurality of transistors having an emitter and a base; a plurality of switches, each switch of the plurality of switches selectively coupling a current source to an emitter of a corresponding transistor of the plurality of transistors such that when the corresponding one or more switches are closed, a bias current flows from the current source to the emitter of the corresponding one or more transistors of the plurality of transistors; a switch control circuit configured to, at different times, close all switches and, for each transistor separately, close a switch associated with each transistor while opening all other switches; and A measurement circuit is coupled to each of the plurality of transistors between each corresponding switch and an emitter of each corresponding transistor, the measurement circuit being configured to measure, for each of the plurality of transistors, a base-emitter voltage VBE when all switches are closed and a base-emitter voltage VBE when only a switch associated with each transistor is closed, respectively, the measurement circuit being further configured to determine a ΔVBE of each of the plurality of transistors by calculating, for each of the plurality of transistors, a difference between the base-emitter voltage VBE when only a switch associated with each transistor is closed and the base-emitter voltage VBE when all switches are closed, the measurement circuit being further configured to calculate an average of all determined ΔVBEs. 2 . The integrated circuit of claim 1 , wherein the measurement circuit is further configured to calculate the temperature based on a calculated average of all determined ΔVBEs.

3. The integrated circuit of claim 1, wherein the measuring circuit comprises an analog-to-digital converter for converting the calculated average of all determined ΔVBEs from an analog value to a digital value. 4 . The integrated circuit of claim 1 , wherein each transistor of the plurality of transistors comprises a bipolar junction transistor. 5 . The integrated circuit of claim 4 , wherein each of the plurality of bipolar junction transistors comprises a parasitic bipolar junction transistor.

6. The integrated circuit of claim 1, wherein the plurality of transistors comprises four to eight transistors.

7. The integrated circuit of claim 1, wherein the bias current from the current source is selected to be within an operating region of the plurality of transistors.

8. The integrated circuit of claim 7, wherein the bias current from the current source is selected to be between a high injection region and a low injection region of the plurality of transistors.

9. A method for determining temperature, the method comprising: for each transistor of a plurality of transistors arranged in parallel, each transistor of the plurality of transistors having an emitter and a base, the emitter of each transistor of the plurality of transistors being selectively coupled to a current source via a corresponding switch of a plurality of switches so that when the corresponding one or more switches are closed, a bias current flows from the current source to the emitter of the corresponding one or more transistors of the plurality of transistors, respectively measuring a base-emitter voltage VBE when all switches are closed and a base-emitter voltage VBE when only the switch associated with each transistor is closed; determining a ΔVBE for each of the plurality of transistors by calculating, for each of the plurality of transistors, a difference between a base-emitter voltage VBE when only a switch associated with each transistor is closed and a base-emitter voltage VBE when all switches are closed; Calculate the average of all determined ΔVBE; and The temperature is calculated using the average of all determined ΔVBEs. 10 . The method of claim 9 , further comprising converting each of the measured base-emitter voltages VBE from an analog value to a digital value.

11. The method of claim 9, wherein each transistor of the plurality of transistors comprises a bipolar junction transistor. 12 . The method of claim 11 , wherein each of the plurality of bipolar junction transistors comprises a parasitic bipolar junction transistor.

13. The method of claim 9, wherein the plurality of transistors comprises four to eight transistors.

14. The method of claim 9, wherein the bias current from the current source is selected to be within an operating region of the plurality of transistors.

15. The method of claim 14, wherein the bias current from the current source is selected to be between a high injection region and a low injection region of the plurality of transistors.

16. A temperature sensor, comprising: Current source; a plurality of transistors arranged in parallel, each transistor in the plurality of transistors having an emitter and a base; a plurality of switches, each switch of the plurality of switches selectively coupling a current source to an emitter of a corresponding transistor of the plurality of transistors such that when the corresponding one or more switches are closed, a bias current flows from the current source to the emitter of the corresponding one or more transistors of the plurality of transistors; a switch control circuit configured to, at different times, close all switches and, for each transistor separately, close a switch associated with each transistor while opening all other switches; and A measurement circuit is coupled to each of the plurality of transistors between each corresponding switch and an emitter of each corresponding transistor, the measurement circuit being configured to measure, for each of the plurality of transistors, a base-emitter voltage VBE when all switches are closed and a base-emitter voltage VBE when only a switch associated with each transistor is closed, respectively, the measurement circuit being further configured to determine a ΔVBE of each of the plurality of transistors by calculating, for each of the plurality of transistors, a difference between the base-emitter voltage VBE when only a switch associated with each transistor is closed and the base-emitter voltage VBE when all switches are closed, the measurement circuit being further configured to calculate an average of all determined ΔVBEs.

17. The temperature sensor according to claim 16, wherein: The measurement circuit is further configured to calculate the temperature based on the calculated average of all determined ΔVBEs.

18. The temperature sensor according to claim 16, wherein: The measuring circuit comprises an analog-to-digital converter for converting the calculated average of all determined ΔVBEs from an analog value into a digital value.

19. The temperature sensor of claim 16, wherein each transistor of the plurality of transistors comprises a bipolar junction transistor.

20. The temperature sensor of claim 16, wherein the bias current from the current source is selected to be within an operating region of the plurality of transistors.

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