A general test sampling circuit for high-speed serial IO interface receiving end

Abstract

The application provides a general test sampling circuit for a high-speed serial IO interface receiving end, which comprises a first low-pass filter, a second low-pass filter, a first RX test sampling circuit, a second RX test sampling circuit, a first comparator, a second comparator, and an RX test bias circuit for providing reference voltage and bias voltage for the two RX test sampling circuits and the two comparators; the general test sampling circuit can respectively test and sample each of two differential signal paths of the high-speed serial IO interface receiving end, and judge whether short circuit, open circuit exists in the PCB circuit board, the pressure welding point and the IO according to the received signal. The general test sampling circuit is suitable for the differential receiving end in the high-speed data transmission rate serial interface (above 10G baud rate), and can work in direct current mode and alternating current mode through mode selection signal, and can sample direct current signal and alternating current signal.

Description

Technical Field

[0001] This invention belongs to the field of interface test sampling technology, and relates to a general test sampling circuit for a high-speed serial IO interface receiver. Background Technology

[0002] Figure 1 This shows a PCB circuit board containing multiple chips. With the rapid development of VLSI manufacturing technology, today's electronic system boards contain many high-density devices, and the spacing between devices is getting smaller and smaller. Traditional probe-based contact testing methods cannot be used. Therefore, many devices now include boundary scan test circuits, which can be used for manufacturing testing, detection and diagnosis of faults, such as broken solder joints, short circuits and missing devices.

[0003] High-speed serial I / O interfaces, as an emerging and advanced information transmission I / O technology, use various termination resistors and capacitors in the signal transmission path to avoid signal integrity problems such as reflections caused by high-speed signals. This means that the transmission line can no longer be simply regarded as a small resistor model, but forms a new type of transmission line network model. The problem is that traditional boundary scan test circuits cannot handle the AC signals in it. Summary of the Invention

[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a universal test sampling circuit for a high-speed serial I / O interface receiver, which can perform test sampling on each of the two differential signal paths of the high-speed serial I / O interface receiver.

[0005] The technical solution of this invention is:

[0006] This invention discloses a universal test sampling circuit for a high-speed serial I / O interface receiver, comprising a first low-pass filter, a second low-pass filter, a first RX test sampling circuit, a second RX test sampling circuit, a first comparator, a second comparator, and an RX test bias circuit providing reference voltages and bias voltages for the two test sampling circuits and the two comparators: wherein,

[0007] The input of the first low-pass filter is connected to the RXP of the high-speed serial IO interface receiver, and the output is connected to the first data input rx of the first RX test sampling circuit, which serves to filter out spike noise on the RXP signal line.

[0008] The input of the second low-pass filter is connected to the RXN of the high-speed serial IO interface receiver, and the output is connected to the first data input rx of the second RX test sampling circuit, which serves to filter out spike noise on the RXN signal line.

[0009] The second data input terminal feedback of the first RX test sampling circuit is connected to the second output terminal feedback of the first comparator; the first data output terminal outp of the first RX test sampling circuit is connected to the inp input terminal of the first comparator; the second data output terminal outn of the first RX test sampling circuit is connected to the inn input terminal of the first comparator; the first bias voltage input terminal Vrm, the second bias voltage input terminal Vdc, and the third bias voltage input terminal Vrp are respectively connected to the first bias voltage output terminal, the second bias voltage output terminal, and the third bias voltage output terminal of the RX test bias circuit.

[0010] The second data input terminal feedback of the second RX test sampling circuit is connected to the second output terminal feedback of the second comparator. The first data output terminal outp of the second RX test sampling circuit is connected to the inp input terminal of the second comparator. The second data output terminal outn of the second RX test sampling circuit is connected to the inn input terminal of the second comparator. The first bias voltage input terminal Vrm, the second bias voltage input terminal Vdc, and the third bias voltage input terminal Vrp are respectively connected to the first bias voltage output terminal, the second bias voltage output terminal, and the third bias voltage output terminal of the RX test bias circuit.

[0011] The first control signal input terminal (mode) and the second control signal input terminal (test_init) of the first RX test sampling circuit and the second RX test sampling circuit are both connected to the mode selection signal (mode) and the test initialization signal (test_init) generated by the external digital control logic.

[0012] The first comparator, as a high-gain operational amplifier, is used to compare the magnitudes of the first data input terminal inp and the second data input terminal inn, which are marked as positive and negative respectively, and generate a large-swing output signal. The bias voltage input terminal nbias of the first comparator is connected to the fourth bias voltage output terminal of the RX test bias circuit. The first data output terminal OUTP of the first comparator is sent as the compared output value to the subsequent digital logic for analysis and processing.

[0013] The second comparator has the same internal structure as the first comparator; the bias voltage input terminal nbias of the second comparator is connected to the fourth bias voltage output terminal of the RX test bias circuit; the first data output terminal OUTN of the second comparator is used as the compared output value and sent to subsequent digital logic for analysis and processing.

[0014] Furthermore, in the above sampling circuit,

[0015] The internal circuit structure of the second RX test sampling circuit is the same as that of the first RX test sampling circuit.

[0016] The internal circuit structure of the first comparator is the same as that of the second comparator.

[0017] Furthermore, in the above sampling circuit,

[0018] The RX test bias circuit is turned on or off under the control of the test enable signal test_en generated by the external digital control logic. It receives a stable current source iref_test from the external power bias circuit and generates four stable voltage biases Vrm, Vdc, Vrp and Vbias to provide to the first RX test sampling circuit, the second RX test sampling circuit, the first comparator and the second comparator.

[0019] Furthermore, in the above sampling circuit, under the control of the mode selection signal mode, it can operate in two test modes: when mode=1, it operates in AC mode and samples AC signals; when mode=0, it operates in DC mode and samples DC signals.

[0020] Further, in the above sampling circuit, the first RX test sampling circuit includes: a first capacitor C1, a P-type transistor M1, a second capacitor C2, a first resistor R1, an N-type transistor M2, a P-type transistor M3, an inverter I1, a P-type transistor M4, a P-type transistor M5, a P-type transistor M6, a second resistor R2, an N-type transistor M7, an N-type transistor M8, and an N-type transistor M9; wherein,

[0021] The first data input terminal rx is connected to one end of the first capacitor C1 and simultaneously to the gate of the P-type transistor M1. The drain of transistor M1 is connected to ground level VS, and the source of transistor M1 is connected to the other end of the first capacitor C1, as well as the input of the second capacitor C2 and the input of the first resistor R1. The output of the first resistor R1 is connected to the stable current source iref_test provided by the external power supply bias circuit; this connection point is denoted as Vif. The output of the second capacitor C2 is connected to the first data output terminal outp. The drain of transistor M2 and the source of transistor M3 are connected at the connection point Vif. The source of transistor M2 and the drain of transistor M3 are connected to the first data output terminal outp. The first control signal input terminal mode is connected to the input of inverter I1, and the output signal of inverter I1 is denoted as mode_N. The gate of transistor M3 is connected to the first control signal input terminal mode, and the gate of transistor M2 is connected to the inverter... The output terminal of inverter I1 is mode_N; the gates of transistors M4, M5, and M6 are connected together and connected to the output terminal mode_N of inverter I1; the source terminal of transistor M4 is connected to the input terminal of the second resistor R2, and the connection point is denoted as vnod2; the drain terminal of transistor M4 is connected to the source terminal of transistor M5; the drain terminal of transistor M5 is connected to the source terminal of transistor M6; the drain terminal of transistor M6 is connected to the second bias voltage input terminal Vdc; the gates of transistors M7, M8, and M9 are connected together and connected to the first control signal input terminal mode; the drain terminal of transistor M7 is connected to the connection point vnod2; the source terminal of transistor M7 is connected to the drain terminal of transistor M8; the source terminal of transistor M8 is connected to the drain terminal of transistor M9; the source terminal of transistor M9 is connected to the second bias voltage input terminal Vdc; the output terminal of the second resistor R2 is connected to the first data output terminal outp;

[0022] Furthermore, in the above sampling circuit, the first RX test sampling circuit further includes a high-level active latch LAT1, a second inverter I2, a P-type transistor M10, and a P-type transistor M11; wherein, latch LAT1 includes a first data input terminal D, a first clock input terminal CP, a first high-level set terminal CD, and a first data output terminal Q; the first data input terminal D of latch LAT1 is connected to the second data input terminal feedback of the first RX test sampling circuit, the first clock input terminal CP of latch LAT1 is connected to the first control signal input terminal mode, and the first... The high-level set terminal CD is connected to the second control signal input terminal test_init. The first data output terminal Q of latch LAT1 is connected to the input terminal of the second inverter I2. This connection point is denoted as sel. The output terminal of the second inverter I2 is connected to the gate of P-type transistor M10. This connection point is denoted as sel_N. The source terminal of transistor M10 is connected to the first bias voltage input terminal Vrm. The source terminal of transistor M11 is connected to the first bias voltage input terminal Vrp. The gate terminal of transistor M11 is connected to the connection point sel. The drain terminal of transistor M10 and the drain terminal of transistor M11 are connected to the second data output terminal outn.

[0023] Further, in the above sampling circuit, the first comparator includes N-type transistors M101, M102, M103, and M104, P-type transistors M105, M106, and M107, inverters INV1, INV2, and INV3; wherein, the first data input terminal inp serves as the positive input of the comparator and is connected to the gate of N-type transistor M104, and the second data input terminal inn serves as the negative input of the comparator and is connected to the gate of N-type transistor M103; the source terminals of transistors M103 and M104 are connected to the drain terminals of N-type transistor M101; the gate of transistor M101 is connected to the bias voltage input terminal nbias, and the source terminal of transistor M101 is connected to ground VS; transistor M105... The source terminal of transistor M106 is connected to power supply VP. The drain and gate terminals of transistor M105 are connected to the drain terminal of transistor M103 and the gate terminal of transistor M106. The drain terminal of transistor M106 is connected to the drain terminal of transistor M104 and the gate terminal of P-type transistor M107. The source terminal of transistor M107 is connected to power supply VP. The drain terminal of transistor M107 is connected to the drain terminal of transistor M102 and the input terminal of inverter INV1. The gate terminal of transistor M102 is connected to the bias voltage input terminal nbias. The source terminal of transistor M102 is connected to ground VS. The output terminal of inverter INV1 is connected to the input terminals of inverters INV2 and INV3. The output terminal of inverter INV2 is connected to the first data output terminal out. The output terminal of inverter INV3 is connected to the second data output terminal feedback.

[0024] Further, in the above sampling circuit, the RX test bias circuit includes a P-type transistor M204, resistors R203 and R202, a P-type transistor M201, an N-type transistor M202, an N-type transistor M203, and resistor R201; wherein, the gate and drain of transistor M204 are connected to ground VS, the source of transistor M204 is connected to the output of resistor R203, serving as the first bias voltage output terminal Vrm; the input of resistor R203 is connected to the output of resistor R202, serving as the second bias voltage output terminal Vdc, and the input of resistor R202 receives a stable current source iref_test provided by an external power supply bias circuit. The potential generated here serves as the third bias voltage output terminal Vrp; the source terminal of transistor M201 is connected to the power supply VP, and the gate terminal of transistor M201 is connected to the test enable signal test_en generated by the external digital control logic; the drain terminal of transistor M201 is connected to the input terminal of resistor R201, and the output terminal of resistor R201 is connected to the drain terminal and gate terminal of transistor M202, serving as the fourth bias voltage output terminal Vbias; the source terminal of transistor M202 is grounded to VS; the gate terminal of transistor M203 is connected to the test enable signal test_en generated by the external digital control logic, the source terminal of transistor M203 is grounded to VS, and the drain terminal of transistor M203 is connected to the fourth bias voltage output terminal Vbias.

[0025] Furthermore, in the above sampling circuit, when the first high-level set terminal CD of the high-level active latch LAT1 is at a low potential and the first clock input terminal CP is at a high potential, the output of the first data output terminal Q is consistent with the first data input terminal D; when the first high-level set terminal CD is at a low potential and the first clock input terminal CP is at a low potential, the output of the first data output terminal Q retains the previous valid value; when the first high-level set terminal CD is high, the first data output terminal Q is at a high potential.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] (1) The present invention provides a general test sampling circuit for the receiver of a high-speed serial IO interface. It is applied to test and sample the signal of the receiver of the high-speed serial IO interface. The sampled value is transmitted to the boundary scan logic in the chip. After logic analysis, various conduction defects that may be introduced in the PCB circuit board manufacturing, chip assembly and packaging process can be detected and diagnosed.

[0028] (2) The general test sampling circuit of the present invention, by adding test sampling and comparator circuits, independently tests and samples each of the two differential signal paths of the high-speed serial IO interface receiver, which can improve the effectiveness of testing the differential input terminal and avoid some of its unique manufacturing defects from being covered up.

[0029] (3) The general test sampling circuit of the present invention can sample the effective transition edge of the AC signal by means of the capacitor passing high frequency signal in the RX test sampling circuit, which solves the problem that the traditional boundary scan test circuit cannot test the AC signal in high-speed serial IO.

[0030] (4) The general test sampling circuit of the present invention introduces a sampling mode selection signal, which enables the present invention to simultaneously meet the two working modes of DC test and AC test, making it widely applicable and improving the test throughput when both DC test and AC test are performed.

[0031] (5) In AC test mode, the general test sampling circuit of the present invention adopts a feedback mechanism, which selects whether the reference voltage of the comparator becomes high or low according to the sampling logic value output by the current comparator, which cleverly simplifies the design of the comparator.

[0032] (6) This invention can test and sample each of the two differential signal paths of the high-speed serial IO interface receiver, and can work in both DC mode and AC mode by means of the mode selection signal. It can sample both DC signals and AC signals, analyze the received signals, and diagnose the continuity of the PCB circuit board, solder joints and IO internals.

[0033] (7) This invention provides a universal test sampling circuit for high-speed serial I / O interfaces that can operate in both DC and AC modes depending on the input control signal settings. It can sample both DC and AC signals, solving the problem that traditional boundary scan test circuits cannot test AC signals in high-speed serial I / O interfaces. Moreover, it performs test sampling on each of the two differential signal paths at the receiving end of the high-speed serial I / O interface. This makes it easy, accurate and complete to detect and diagnose various conduction defects that may be introduced into the PCB manufacturing, chip assembly and packaging process of chips that use differential and AC signal transmission. Attached Figure Description

[0034] Figure 1 A simplified schematic diagram of a PCB circuit board containing multiple chips;

[0035] Figure 2 This is a structural diagram of a general-purpose test sampling circuit for a high-speed serial I / O interface receiver according to the present invention;

[0036] Figure 3 (a) is a schematic diagram of the RX test sampling circuit of the present invention; (b) is a schematic diagram of the receiving data sampling path;

[0037] Figure 4 This is a schematic diagram of the comparator in this invention;

[0038] Figure 5 This is a schematic diagram of the RX test bias circuit of the present invention;

[0039] Figure 6 This is a simulation waveform diagram of the present invention in AC working mode;

[0040] Figure 7 This is a simulation waveform diagram of the present invention in DC operating mode. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0042] The technical solution of this invention is as follows: a general-purpose test sampling circuit for a high-speed serial I / O interface receiver, comprising a first low-pass filter, a second low-pass filter, a first RX test sampling circuit, a second RX test sampling circuit, a first comparator, a second comparator, and an RX test bias circuit providing reference voltage and bias voltage for the two test sampling circuits and the two comparators. The first low-pass filter is a common RC low-pass filter, composed of resistors and capacitors, mainly used to filter spike noise on the RXP signal line; the second low-pass filter has the same internal composition as the first low-pass filter and is mainly used to filter spike noise on the RXN signal line.

[0043] The first data input terminal rx of the first RX test sampling circuit receives the input signal filtered by the first low-pass filter to remove spike noise. Depending on the mode of the first control signal input terminal, it samples the input DC or AC signal. The sampling result is reflected in the second data output terminal outp, which is further sent to the positive input terminal inp of the first comparator. The second data input terminal feedback of the first RX test sampling circuit is connected to the second data output terminal feedback of the first comparator. Based on the current comparator output result, it selects between its first bias voltage input terminal Vrm and third bias voltage input terminal Vrp. After passing through a P-type transistor for lossless transmission of high level, it is transmitted to the second data output terminal outn, which is further sent to the negative input terminal inn of the first comparator. The first comparator compares and amplifies the small swing signals of the two input terminals. The swing of the output OUTP signal is between the power supply and ground, completing the process of sampling the AC signal at the RXP terminal and converting it into a digital logic signal.

[0044] The second RX test sampling circuit and the second comparator operate on the same principle as the second RX test sampling circuit and the second comparator described above, completing the process of sampling the AC signal at the RXN terminal and converting it into a digital logic signal.

[0045] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0046] A general-purpose test sampling circuit for the receiver of a high-speed serial I / O interface, such as... Figure 2 As shown, it includes a first low-pass filter, a second low-pass filter, a first RX test sampling circuit, a second RX test sampling circuit, a first comparator, a second comparator, and an RX test bias circuit that provides reference voltages and bias voltages for the two test sampling circuits and the two comparators.

[0047] The first low-pass filter includes an input terminal and an output terminal. The input terminal is connected to the RXP of the high-speed serial IO interface receiver, and the output terminal is connected to the first data input terminal rx of the first RX test sampling circuit, which serves to filter out spike noise on the RXP signal line.

[0048] The second low-pass filter includes an input terminal and an output terminal. The input terminal is connected to the RXN of the high-speed serial IO interface receiver, and the output terminal is connected to the first data input terminal rx of the second RX test sampling circuit, which serves to filter out spike noise on the RXN signal line.

[0049] The first RX test sampling circuit includes a first data input terminal rx, a second data input terminal feedback, a first data output terminal outp, a second data output terminal outn, a first control signal input terminal mode, a second control signal input terminal test_init, a first bias voltage input terminal Vrm, a second bias voltage input terminal Vdc, and a third bias voltage input terminal Vrp. Depending on the input control signal settings, it can operate in both DC mode and AC mode, and can sample both DC and AC signals.

[0050] The second RX test sampling circuit has the same internal structure as the first RX test sampling circuit, and also includes a first data input terminal rx, a second data input terminal feedback, a first data output terminal outp, a first data output terminal outn, a first control signal input terminal mode, a second control signal input terminal test_init, a first bias voltage input terminal Vrm, a second bias voltage input terminal Vdc, and a third bias voltage input terminal Vrp.

[0051] The first comparator includes a first data input terminal inp, a second data input terminal inn, a first data output terminal out, a second data output terminal feedback, and a bias voltage input terminal nbias. As a high-gain operational amplifier, it is used to compare the magnitudes of the first data input terminal inp and the second data input terminal inn, which are respectively marked as positive and negative, and generate a large-swing output signal. Its first data input terminal inp is connected to the first data output terminal outp of the first RX test sampling circuit, its second data input terminal inn is connected to the second data output terminal outn of the first RX test sampling circuit, and the bias voltage input terminal nbias is connected to the fourth bias voltage output terminal of the RX test bias circuit. The connection is denoted as Vbias. Its first data output terminal out is sent as the compared output value to subsequent digital logic for analysis and processing. The second data output terminal feedback is connected to the feedback terminal of the first RX test sampling circuit. The connection is denoted as feed_p.

[0052] The second comparator has the same internal structure as the first comparator circuit, including a first data input terminal inp, a second data input terminal inn, a first data output terminal out, a second data output terminal feedback, and a bias voltage input terminal nbias. It is also a high-gain operational amplifier used to compare the magnitudes of the first data input terminal inp and the second data input terminal inn, which are marked as positive and negative respectively, and to generate a large-swing output signal. Its first data input terminal inp is connected to the first data output terminal outp of the second RX test sampling circuit, its second data input terminal inn is connected to the second data output terminal outn of the second RX test sampling circuit, and the bias voltage input terminal nbias is connected to the fourth bias voltage output terminal of the RX test bias circuit. The connection is denoted as Vbias. Its first data output terminal out is sent as the compared output value to the subsequent digital logic for analysis and processing, and the second data output terminal feedback is connected to the feedback terminal of the second RX test sampling circuit. The connection is denoted as feed_n.

[0053] The RX test bias circuit includes a control signal input terminal, a bias current input terminal, a first bias voltage output terminal, a second bias voltage output terminal, a third bias voltage output terminal, and a fourth bias voltage output terminal. It is turned on or off under the control of the test enable signal test_en generated by the external digital control logic. It receives a stable current source iref_test provided by the external power supply bias circuit and generates four stable voltage biases Vrm, Vdc, Vrp, and Vbias, which are provided to the first RX test sampling circuit and the second RX test sampling circuit, as well as the first comparator and the second comparator mentioned above.

[0054] The first data input terminal rx of the first RX test sampling circuit is connected to the output terminal of the first low-pass filter, the second data input terminal feedback is connected to the second output terminal feedback of the first comparator, the first data output terminal outp of the first RX test sampling circuit is connected to the input terminal inp of the first comparator, the second data output terminal outn of the first RX test sampling circuit is connected to the input terminal inn of the first comparator, and the first bias voltage input terminal Vrm, the second bias voltage input terminal Vdc, and the third bias voltage input terminal Vrp are respectively connected to the first bias voltage output terminal, the second bias voltage output terminal, and the third bias voltage input terminal of the RX test bias circuit, with the connections labeled Vrm, Vdc, and Vrp respectively.

[0055] The first data input terminal rx of the second RX test sampling circuit is connected to the output terminal of the second low-pass filter, the second data input terminal feedback is connected to the second output terminal feedback of the second comparator, the first data output terminal outp of the second RX test sampling circuit is connected to the input terminal inp of the second comparator, the second data output terminal outn of the second RX test sampling circuit is connected to the input terminal inn of the second comparator, and the first bias voltage input terminal Vrm, the second bias voltage input terminal Vdc, and the third bias voltage input terminal Vrp are respectively connected to the first bias voltage output terminal, the second bias voltage output terminal, and the third bias voltage output terminal of the RX test bias circuit, and the connections are labeled Vrm, Vdc, and Vrp respectively.

[0056] The first control signal input terminal (mode) and the second control signal input terminal (test_init) of the first RX test sampling circuit and the second RX test sampling circuit are both connected to the mode selection signal (mode) and the test initialization signal (test_init) generated by the external digital control logic.

[0057] The general test sampling circuit described above, with the first low-pass filter and the second low-pass filter, typically consists of a resistor connected in series between the input and output terminals of the low-pass filter, and a capacitor connected simultaneously between the output terminal of the low-pass filter and ground, or the output terminal and power supply, or the output terminal and both power supply and ground. The specific configuration can be determined by the designer based on the process and layout area.

[0058] The first RX test sampling circuit and the second RX test sampling circuit have the same internal circuit structure, such as... Figure 3As shown, its first data input terminal rx is connected to one end of the first capacitor C1, and simultaneously connected to the first gate of the P-type transistor M1. Transistor M1 includes a first source, a first drain, and a first gate. The first drain of transistor M1 is connected to ground level VS. The first source of transistor M1 is connected to the other end of the first capacitor C1, and simultaneously connected to one end of the second capacitor C2 and one end of the first resistor R1. This connection point is denoted as vnod1. The other end of the first resistor R1 is connected to the stable current source iref_test provided by the external power supply bias circuit. This connection point is denoted as Vif. The other end of the second capacitor C2 is connected to the first data output terminal outp. The N-type transistor M2 includes a first source, a first drain, and a first gate. A P-type transistor M3 includes a first source, a first drain, and a first gate. The first drain of transistor M2 is connected to the first source of transistor M3 at the aforementioned connection point Vif. The first source of transistor M2 and the first drain of transistor M3 are connected to the first data output terminal outp. The first control signal input terminal mode is connected to the input terminal of inverter I1. The output signal of inverter I1 is denoted as mode_N. The first gate of transistor M3 is connected to the first control signal input terminal mode. The first gate of transistor M2 is connected to the output terminal mode_N of inverter I1. A P-type transistor M4 includes a first source, a first drain, and a first gate. A P-type crystal... Transistor M5 includes a first source, a first drain, and a first gate. P-type transistor M6 includes a first source, a first drain, and a first gate. The first gates of transistors M4, M5, and M6 are connected together and connected to the output terminal mode_N of inverter I1. The first source of transistor M4 is connected to one end of the second resistor R2, and this connection point is denoted as vnod2. The first drain of transistor M4 is connected to the first source of transistor M5, and the first drain of transistor M5 is connected to the first source of transistor M6. The first drain of transistor M6 is connected to the second bias voltage input terminal Vdc. N-type transistor M7 includes a first source, a first drain, and a first gate. The N-type transistor M8 includes a first source, a first drain, and a first gate; the N-type transistor M9 includes a first source, a first drain, and a first gate. The first gate of transistor M7 is connected together with the first gates of transistors M8 and M9, and is connected to the first control signal input terminal mode. The first drain of transistor M7 is connected to one end of the second resistor R2 (i.e., point vnod2). The first source of transistor M7 is connected to the first drain of transistor M8. The first source of transistor M8 is connected to the first drain of transistor M9. The first source of transistor M9 is connected to the second bias voltage input terminal Vdc. The other end of the second resistor R2 is connected to the first data output terminal outp. Figure 3 As shown.

[0059] The RX test sampling circuit also includes a high-level active latch LAT1. LAT1 includes a first data input D, a first clock input CP, a first high-level set input CD, and a first data output Q. The first data input D of LAT1 is connected to the second data input feedback. The first clock input CP of LAT1 is connected to the first control signal input mode. The first high-level set input CD of LAT1 is connected to the second control signal input test_init. The first data output Q of LAT1 is connected to the input of the second inverter I2. The connection point is denoted as the sel signal. The output of the second inverter I2 is connected to the first gate of the P-type transistor M10, denoted as sel_N. The P-type transistor M10 includes a first source, a first drain, and a first gate. The P-type transistor M11 includes a first source, a first drain, and a first gate. The first source of transistor M10 is connected to the first bias voltage input terminal Vrm. The first source of transistor M11 is connected to the first bias voltage input terminal Vrp. The first gate of transistor M11 is connected to the sel signal. The first drain of transistor M10 and the first drain of transistor M11 are connected to the second data output terminal outn.

[0060] The first comparator and the second comparator (with identical internal circuit structures), such as Figure 4As shown, its first data input terminal inp serves as the positive input of the comparator and is connected to the first gate of N-type transistor M104. N-type transistor M104 includes a first source, a first drain, and a first gate. Its second data input terminal inn serves as the negative input of the comparator and is connected to the first gate of N-type transistor M103. N-type transistor M103 includes a first source, a first drain, and a first gate. The first source of transistor M103 and the first source of M104 are connected to the first drain of N-type transistor M101. N-type transistor M101 includes a first source, a first drain, and a first gate. The first gate of transistor M101 is connected to the bias voltage input terminal nbias. The first source of transistor M101 is connected to ground VS. P-type transistor M105 includes a first source, a first drain, and a first gate. P-type transistor M106 includes a first source, a first drain, and a first gate. The first source of transistors M105 and M106 are connected to the power supply VP. The first drain and first gate of transistor M105 are connected to the first drain of transistor M103 and the first gate of transistor M106. The first drain of transistor M106 is connected to the first drain of transistor M104 and the first gate of P-type transistor M107. P-type transistor M107 includes a first source, a first drain, and a first gate. The first source of transistor M107 is connected to power supply VP. The first drain of transistor M107 is connected to the first drain of transistor M102 and the input of inverter INV1. N-type transistor M102 includes a first source, a first drain, and a first gate. The first gate of transistor M102 is connected to the bias voltage input terminal nbias. The first source of transistor M101 is connected to ground VS. The output of inverter INV1 is connected to the inputs of inverters INV2 and INV3. The output of inverter INV2 is connected to the first data output terminal out. The output of inverter INV3 is connected to the second data output terminal feedback.

[0061] RX test bias circuit, such as Figure 5As shown, the circuit includes a P-type transistor M204, which has a first source, a first drain, and a first gate. The first gate and the first drain of transistor M204 are connected to ground VS. The first source of transistor M204 is connected to one end of resistor R203 as the first bias voltage output terminal Vrm. The other end of resistor R203 is connected to one end of resistor R202 as the second bias voltage output terminal Vdc. The other end of resistor R202 receives a stable current source iref_test provided by an external power supply bias circuit, and the potential generated here serves as the third bias voltage output terminal Vrp. The RX test bias circuit also includes a P-type transistor M201, an N-type transistor M202, an N-type transistor M203, and resistor R201. Transistor M201 has a first source, a first drain, and a first gate. The first gate of transistor M202 includes a first source, a first drain, and a first gate. Transistor M203 includes a first source, a first drain, and a first gate. The first source of transistor M201 is connected to power supply VP. The first gate of M201 is connected to the test enable signal test_en generated by external digital control logic. The first drain of transistor M201 is connected to one end of resistor R201. The other end of resistor R201 is connected to the first drain and the first gate of transistor M202 as the fourth bias voltage output terminal Vbias. The first source of transistor M202 is grounded to VS. The first gate of transistor M203 is connected to the test enable signal test_en generated by external digital control logic. The first source of transistor M203 is grounded to VS. The first drain of transistor M203 is connected to the fourth bias voltage output terminal Vbias.

[0062] The general-purpose test sampling circuit designed in this invention for the receiver of a high-speed serial I / O interface operates as follows:

[0063] After the chip is powered on, the power bias circuit of the high-speed serial I / O interface provides a stable current source, iref_test, to the general-purpose test sampling circuit at its receiving end. After the current flows into the RX test bias circuit, it is converted into three bias voltages, Vrp, Vdc, and Vrm, through the fixed series resistors R202 and R203 in the bias circuit. Vdc is generally set to half of the power supply voltage, Vrm is generally set to Vdc-Vth (the threshold voltage of an N-type transistor), and Vrp is generally set to Vdc+Vth. When the test enable signal test_en is low, the P-type transistor M201 in the RX test bias circuit is turned on, and current flows through resistor R201. The resulting bias voltage Vbias provides bias voltage for the first and second comparators.

[0064] When the mode selection signal (mode) generated by the external digital control logic is high, both the first RX test sampling circuit and the second RX test sampling circuit operate in AC test mode, such as... Figure 3 As shown, transistors M2 and M3 are both off, while transistors M4, M5, M6, M7, M8, and M9 are all on. At this time, the rx terminal of the RX test sampling circuit receives an AC signal. When the AC signal changes from low to high, transistor M1 is off, and the potential at vnod1 is pulled high by resistor R1. The high-frequency components in the rising edge of rx are coupled to the first data output terminal outp through capacitors C1 and C2. Figure 6 The simulation waveform shows that the output signal of outp generates a peak at the rising edge. When the mode signal is high, the high-level active latch LAT1 in the RX test sampling circuit is at a high level because its clock CP terminal is connected to the mode signal, and its data terminal D is connected to the comparator's feedback signal. Therefore, the output of latch LAT1 is the comparator's comparison value. When the comparator's current output is high, Figure 3 The P-type transistor M10 in the circuit is turned on, and Vrm is transmitted to the negative input of the comparator, where it is compared with the sampled signal at the positive input. When the current output of the comparator is low, Figure 3 When the P-type transistor M11 in the circuit is turned on, Vrp is transmitted to the negative input terminal of the comparator and compared with the sampled signal at the positive input terminal. By using this form of determining the different potentials of the reference voltage connected to the negative input terminal of the comparator based on the comparator output as the feedback voltage, the design of the comparator can be simplified to handle the stable value of the input signal after the rising edge peak signal.

[0065] When the mode selection signal (mode) generated by the external digital control logic is low, both the first RX test sampling circuit and the second RX test sampling circuit operate in DC test mode, such as... Figure 3 As shown, transistors M2 and M3 are both turned on, while transistors M4, M5, M6, M7, M8, and M9 are all turned off. The operating state is relatively simple at this time. The first data output terminal, outp, of the RX test sampling circuit directly "copies" the signal received at the RX terminal. When the mode signal is low, the output of the high-level active latch LAT1 in the RX test sampling circuit is determined by the second control signal input terminal, test_init. LAT1 is in the set state at this time, and its output terminal Q is at a high potential. P-type transistor M10 is turned on, and Vrm is transmitted to the second data output terminal, outn, of the RX test sampling circuit. The comparator compares the positive and negative inputs to generate the final sampled output signal, as shown... Figure 7 As shown.

[0066] This invention provides a universal test sampling circuit for a high-speed serial I / O interface receiver, which can operate in both DC and AC modes depending on the input control signal settings. It can sample both DC and AC signals, solving the problem that traditional boundary scan test circuits cannot test AC signals in high-speed serial I / O interfaces. Furthermore, it samples each of the two differential signal paths in the high-speed serial I / O interface receiver separately. This allows for easy, accurate, and comprehensive detection and diagnosis of various continuity defects that may be introduced during PCB manufacturing, chip assembly, and packaging of chips using differential and AC signal transmission.

[0067] The contents not described in detail in this specification are common knowledge to those skilled in the art.

[0068] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A universal test sampling circuit for a high-speed serial I / O interface receiver, characterized in that, It includes a first low-pass filter, a second low-pass filter, a first RX test sampling circuit, a second RX test sampling circuit, a first comparator, a second comparator, and an RX test bias circuit that provides reference voltage and bias voltage for the two test sampling circuits and the two comparators: wherein, The input of the first low-pass filter is connected to the RXP of the high-speed serial IO interface receiver, and the output is connected to the first data input rx of the first RX test sampling circuit, which serves to filter out spike noise on the RXP signal line. The input of the second low-pass filter is connected to the RXN of the high-speed serial IO interface receiver, and the output is connected to the first data input rx of the second RX test sampling circuit, which serves to filter out spike noise on the RXN signal line. The second data input terminal feedback of the first RX test sampling circuit is connected to the second output terminal feedback of the first comparator; the first data output terminal outp of the first RX test sampling circuit is connected to the inp input terminal of the first comparator; the second data output terminal outn of the first RX test sampling circuit is connected to the inn input terminal of the first comparator; the first bias voltage input terminal Vrm, the second bias voltage input terminal Vdc, and the third bias voltage input terminal Vrp of the first RX test sampling circuit are respectively connected to the first bias voltage output terminal, the second bias voltage output terminal, and the third bias voltage output terminal of the RX test bias circuit. The second data input terminal feedback of the second RX test sampling circuit is connected to the second output terminal feedback of the second comparator. The first data output terminal outp of the second RX test sampling circuit is connected to the inp input terminal of the second comparator. The second data output terminal outn of the second RX test sampling circuit is connected to the inn input terminal of the second comparator. The first bias voltage input terminal Vrm, the second bias voltage input terminal Vdc, and the third bias voltage input terminal Vrp of the second RX test sampling circuit are respectively connected to the first bias voltage output terminal, the second bias voltage output terminal, and the third bias voltage output terminal of the RX test bias circuit. The first control signal input terminal (mode) and the second control signal input terminal (test_init) of the first RX test sampling circuit and the second RX test sampling circuit are both connected to the mode selection signal (mode) and the test initialization signal (test_init) generated by the external digital control logic. The first comparator, as a high-gain operational amplifier, is used to compare the magnitudes of the first data input terminal inp and the second data input terminal inn, which are marked as positive and negative respectively, and generate a large-swing output signal. The bias voltage input terminal nbias of the first comparator is connected to the fourth bias voltage output terminal of the RX test bias circuit. The first data output terminal OUTP of the first comparator is sent as the compared output value to the subsequent digital logic for analysis and processing. The second comparator has the same internal structure as the first comparator; the bias voltage input terminal nbias of the second comparator is connected to the fourth bias voltage output terminal of the RX test bias circuit; the first data output terminal OUTN of the second comparator is used as the compared output value and sent to the subsequent digital logic for analysis and processing. The internal circuit structure of the second RX test sampling circuit is the same as that of the first RX test sampling circuit. The first data input terminal rx of the first RX test sampling circuit receives the input signal filtered by the first low-pass filter to remove spike noise. It samples the input DC or AC signal according to the different modes of the first control signal input terminal, and the sampling result is reflected in the first data output terminal outp. The second data input terminal feedback of the first RX test sampling circuit is connected to the second data output terminal feedback of the first comparator. According to the current comparator output result, it selects between its first bias voltage input terminal Vrm and third bias voltage input terminal Vrp, and transmits the signal to the second data output terminal outn through a P-type transistor that transmits high-level signals without loss.

2. The universal test sampling circuit for a high-speed serial I / O interface receiver according to claim 1, characterized in that: The RX test bias circuit is turned on or off under the control of the test enable signal test_en generated by the external digital control logic. It receives a stable current source iref_test from the external power bias circuit and generates four stable voltage biases Vrm, Vdc, Vrp and Vbias to provide to the first RX test sampling circuit, the second RX test sampling circuit, the first comparator and the second comparator.

3. The universal test sampling circuit for a high-speed serial I / O interface receiver according to claim 1, characterized in that: Under the control of the mode selection signal mode, it can work in two test modes: when mode=1, it works in AC mode and samples AC signals; when mode=0, it works in DC mode and samples DC signals.

4. A general-purpose test sampling circuit for a high-speed serial I / O interface receiver according to claim 1, characterized in that: The first RX test sampling circuit includes: a first capacitor C1, a P-type transistor M1, a second capacitor C2, a first resistor R1, an N-type transistor M2, a P-type transistor M3, an inverter I1, a P-type transistor M4, a P-type transistor M5, a P-type transistor M6, a second resistor R2, an N-type transistor M7, an N-type transistor M8, and an N-type transistor M9; wherein, The first data input terminal rx is connected to one end of the first capacitor C1 and simultaneously to the gate of the P-type transistor M1. The drain of transistor M1 is connected to ground level VS, and the source of transistor M1 is connected to the other end of the first capacitor C1, as well as the input of the second capacitor C2 and the input of the first resistor R1. The output of the first resistor R1 is connected to the stable current source iref_test provided by the external power supply bias circuit; this connection point is denoted as Vif. The output of the second capacitor C2 is connected to the first data output terminal outp. The drain of transistor M2 and the source of transistor M3 are connected at the connection point Vif. The source of transistor M2 and the drain of transistor M3 are connected to the first data output terminal outp. The first control signal input terminal mode is connected to the input of inverter I1, and the output signal of inverter I1 is denoted as mode_N. The gate of transistor M3 is connected to the first control signal input terminal mode, and the gate of transistor M2 is connected to the inverter... The output terminal of inverter I1 is mode_N; the gates of transistors M4, M5, and M6 are connected together and connected to the output terminal mode_N of inverter I1; the source terminal of transistor M4 is connected to the input terminal of the second resistor R2, and the connection point is denoted as vnod2; the drain terminal of transistor M4 is connected to the source terminal of transistor M5; the drain terminal of transistor M5 is connected to the source terminal of transistor M6; the drain terminal of transistor M6 is connected to the second bias voltage input terminal Vdc; the gates of transistors M7, M8, and M9 are connected together and connected to the first control signal input terminal mode; the drain terminal of transistor M7 is connected to the connection point vnod2; the source terminal of transistor M7 is connected to the drain terminal of transistor M8; the source terminal of transistor M8 is connected to the drain terminal of transistor M9; the source terminal of transistor M9 is connected to the second bias voltage input terminal Vdc; the output terminal of the second resistor R2 is connected to the first data output terminal outp; 5. A general-purpose test sampling circuit for a high-speed serial I / O interface receiver according to claim 1, characterized in that: The first RX test sampling circuit further includes a high-level active latch LAT1, a second inverter I2, a P-type transistor M10, and a P-type transistor M11; wherein, latch LAT1 includes a first data input terminal D, a first clock input terminal CP, a first high-level set terminal CD, and a first data output terminal Q; the first data input terminal D of latch LAT1 is connected to the second data input terminal feedback of the first RX test sampling circuit, the first clock input terminal CP of latch LAT1 is connected to the first control signal input terminal mode, and the first high-level set terminal CD of latch LAT1... D is connected to the second control signal input terminal test_init. The first data output terminal Q of latch LAT1 is connected to the input terminal of the second inverter I2. This connection point is denoted as sel. The output terminal of the second inverter I2 is connected to the gate of P-type transistor M10. This connection point is denoted as sel_N. The source terminal of transistor M10 is connected to the first bias voltage input terminal Vrm. The source terminal of transistor M11 is connected to the third bias voltage input terminal Vrp. The gate terminal of transistor M11 is connected to the connection point sel. The drain terminal of transistor M10 and the drain terminal of transistor M11 are connected to the second data output terminal outn.

6. A general-purpose test sampling circuit for a high-speed serial I / O interface receiver according to claim 1, characterized in that: The first comparator includes N-type transistors M101, M102, M103, and M104, P-type transistors M105, M106, and M107, and inverters INV1, INV2, and INV3. The first data input terminal inp serves as the positive input of the comparator and is connected to the gate of N-type transistor M104. The second data input terminal inn serves as the negative input of the comparator and is connected to the gate of N-type transistor M103. The source terminals of transistors M103 and M104 are connected to the drain terminal of N-type transistor M101. The gate of transistor M101 is connected to the bias voltage input terminal nbias, and the source terminal of transistor M101 is connected to ground VS. The source terminals of transistors M105 and M106 are connected to the power supply VP, and the drain and gate terminals of transistor M105 are connected to transistor M107. The drain of transistor M103 is connected to the gate of transistor M106; the drain of transistor M106 is connected to the drain of transistor M104 and the gate of P-type transistor M107; the source of transistor M107 is connected to power supply VP; the drain of transistor M107 is connected to the drain of transistor M102 and the input of inverter INV1; the gate of transistor M102 is connected to the bias voltage input terminal nbias; the source of transistor M102 is connected to ground VS; the output of inverter INV1 is connected to the inputs of inverters INV2 and INV3; the output of inverter INV2 is connected to the first data output terminal OUTP; and the output of inverter INV3 is connected to the second data output terminal feedback.

7. A general-purpose test sampling circuit for a high-speed serial I / O interface receiver according to claim 1, characterized in that: The RX test bias circuit includes a P-type transistor M204, resistors R203 and R202, a P-type transistor M201, an N-type transistor M202, an N-type transistor M203, and resistor R201. The gate and drain of transistor M204 are connected to ground VS. The source of transistor M204 is connected to the output of resistor R203, serving as the first bias voltage output Vrm. The input of resistor R203 is connected to the output of resistor R202, serving as the second bias voltage output Vdc. The input of resistor R202 receives a stable current source iref_test from an external power supply bias circuit. The current generated here... The third bias voltage output terminal Vrp is used; the source terminal of transistor M201 is connected to the power supply VP, and the gate terminal of transistor M201 is connected to the test enable signal test_en generated by the external digital control logic; the drain terminal of transistor M201 is connected to the input terminal of resistor R201, and the output terminal of resistor R201 is connected to the drain terminal and gate terminal of transistor M202, serving as the fourth bias voltage output terminal Vbias; the source terminal of transistor M202 is grounded to VS; the gate terminal of transistor M203 is connected to the test enable signal test_en generated by the external digital control logic, the source terminal of transistor M203 is grounded to VS, and the drain terminal of transistor M203 is connected to the fourth bias voltage output terminal Vbias.

8. A general-purpose test sampling circuit for a high-speed serial I / O interface receiver according to claim 5, characterized in that: When the first high-level set terminal CD of the latch LAT1 is low and the first clock input terminal CP is high, the output of the first data output terminal Q is consistent with the output of the first data input terminal D. When the first high-level set terminal CD is low and the first clock input terminal CP is low, the output of the first data output terminal Q retains the previous valid value. When the first high-level set terminal CD is high, the first data output terminal Q is high.

Images