FPGA large-point pulse compression method based on airborne radar signal processing module

Abstract

The invention belongs to the technical field of airborne radar signal processing, and particularly relates to a large-point pulse compression method based on an airborne radar signal processing module FPGA, and the method comprises the steps: S1, enabling a processing module FPGA chip to receive original data transmitted from a down-conversion module through an Aurora interface, and enabling a reference function transmitted from a signal processing module DSP chip through an SRIO interface; s2, a processing module FPGA chip performs conversion from a fixed point number to a floating point number on the original data; s3, the processing module FPGA chip carries out pulse pressure calculation on the original data after fixed floating rotation according to the received reference function; and S4, the processing module FPGA chip performs modulo operation on the result after pulse pressure operation and then transmits the result to the DSP, and the DSP performs SAR imaging on the result after pulse pressure operation. According to the invention, the number of DSP chips is greatly reduced. The system complexity is reduced, large-point pulse pressure imaging can be completed in a radar processing system with only two DSPs, and clear imaging can be achieved in a miniaturized radar.

Description

Technical Field

[0001] The present application belongs to the technical field of airborne radar signal processing, and in particular relates to a large-point pulse compression method based on an airborne radar signal processing module FPGA. Background Art

[0002] In the military aviation field, especially airborne radar systems, the radar system is required to be able to clearly image the target, so the signal processing module needs to have a large number of pulse compression functions. In the past, this function was implemented by the DSP chip inside the signal processing module. Due to the limitations of the DSP itself, the pulse compression processing results have limited processing speed and poor real-time performance. In addition, the entire system requires a large number of DSP chips, which in turn increases the complexity of the system and makes it impossible to reduce the size and weight of the airborne radar. Therefore, in some miniaturized radars, it is impossible to clearly present the target image.

[0003] According to the current situation, there are the following problems:

[0004] (1) DSP processes large number of pulse pressures, but the real-time performance is poor and the processing speed is slow

[0005] (2) Large-point pulse compression requires a large number of DSPs, which increases the complexity of the entire radar processing system, making it impossible to reduce the size and weight of the radar. In addition, large-point pulse compression operations cannot be implemented on some miniaturized radars, resulting in unclear radar images of targets. Summary of the invention

[0006] In order to solve the above problems, the present application provides a large-point pulse compression method based on an airborne radar signal processing module FPGA, comprising:

[0007] Step S1: The processing module FPGA chip receives the original data transmitted from the down-conversion module through the Aurora interface and the reference function transmitted from the signal processing module DSP chip through the SRIO interface;

[0008] Step S2: The processing module FPGA chip converts the original data from fixed-point numbers to floating-point numbers;

[0009] Step S3: The FPGA chip of the processing module calculates the pulse pressure of the raw data after fixed floating rotation according to the received reference function;

[0010] Step S4: The processing module FPGA chip performs a modulo operation on the result after the pulse pressure calculation and transmits it to the DSP, and the DSP performs SAR imaging on the result after the pulse pressure calculation.

[0011] Preferably, the specific steps of calculating the pulse pressure of the raw data after the fixed floating rotation include:

[0012] Step S31: Setting the IP core and presetting parameters for the IP core;

[0013] Step S32: changing the amount of raw data after fixed floating required for each pulse pressure calculation according to the preset parameters;

[0014] Step S33: The FPGA chip of the processing module performs segmented calculation on the original data after fixed floating conversion according to the reference function and the requirements of a single calculation.

[0015] Preferably, the FPGA chip of the processing module performs FFT operation on the original data after fixed-floating conversion based on the reference function, and performs inverse FFT transformation on the FFT operation result to obtain the result after pulse pressure operation.

[0016] Preferably, step S2 further comprises: storing the original data after fixed-floating conversion in a two-dimensional matrix mode.

[0017] Preferably, the preset parameter changes the number of rows and columns of the two-dimensional matrix.

[0018] Preferably, in step S1, the processing module FPGA chip receives the reference function from the DSP chip via the SRIO protocol, and the processing module FPGA chip receives the original data from the digital down-conversion module via the Aurora protocol.

[0019] This method mainly solves the following problems:

[0020] (1) Since FPGA programs have high real-time performance and can perform parallel operations, using FPGA for large-point pulse pressure calculations will overcome the shortcomings of DSP's limited processing speed and poor real-time performance.

[0021] (2) The large number of pulse pressure is mainly handled by FPGA, and the DSP chip only needs to calculate the reference function, which greatly reduces the number of DSP chips. This reduces the system complexity and can complete large number of pulse pressure imaging in a radar processing system with only two DSPs, allowing clear imaging in miniaturized radars.

[0022] The present invention has the following advantages:

[0023] (1) FPGA has high real-time performance and can perform parallel operations, overcoming the shortcomings of poor real-time performance and limited processing speed brought by DSP operations;

[0024] (2) Using FPGA to realize large-point pulse compression can reduce the number of DSPs used, thereby reducing the complexity and volume of the airborne radar processing system. At the same time, large-point pulse compression can also be realized in a small radar processing system with only two DSPs + FPGAs, thereby achieving the function of clearly displaying the target. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a flow chart of FPGA large-point pulse compression technology in a preferred implementation mode of the present application. DETAILED DESCRIPTION

[0026] In order to make the technical solution and advantages of the present application clearer, the technical solution of the present application will be further described in detail in detail and in detail in conjunction with the accompanying drawings. It can be understood that the specific embodiments described here are only partial embodiments of the present application, which are only used to explain the present application, not to limit the present application. It should be noted that, for the convenience of description, only the parts related to the present application are shown in the accompanying drawings, and other related parts can refer to the general design. In the absence of conflict, the embodiments in the present application and the technical features in the embodiments can be combined with each other to obtain new embodiments.

[0027] like Figure 1 As shown, step S1: the processing module FPGA chip receives the original data transmitted from the down-conversion module through the Aurora interface and the reference function transmitted from the signal processing module DSP chip through the SRIO interface;

[0028] Step S2: The processing module FPGA chip converts the original data from fixed-point numbers to floating-point numbers;

[0029] Step S3: The FPGA chip of the processing module calculates the pulse pressure of the raw data after fixed floating rotation according to the received reference function;

[0030] Step S4: The processing module FPGA chip performs a modulo operation on the result after the pulse pressure calculation and transmits it to the DSP, and the DSP performs SAR imaging on the result after the pulse pressure calculation.

[0031] In some optional implementations, the specific steps of calculating the pulse pressure of the raw data after the fixed floating rotation include:

[0032] Step S31: Setting the IP core and presetting parameters for the IP core;

[0033] Step S32: changing the amount of raw data after fixed floating required for each pulse pressure calculation according to the preset parameters;

[0034] Step S33: The FPGA chip of the processing module performs segmented calculation on the original data after fixed floating conversion according to the reference function and the requirements of a single calculation.

[0035] In some optional implementations, the processing module FPGA chip performs FFT operation on the original data after fixed-floating conversion based on a reference function, performs inverse FFT transformation on the FFT operation result, and obtains the result after pulse pressure operation.

[0036] In some optional implementations, step S2 further includes: storing the original data after fixed-floating conversion in a two-dimensional matrix mode.

[0037] In some optional implementations, the preset parameter changes the number of rows and columns of the two-dimensional matrix.

[0038] In some optional implementations, in step S1, the processing module FPGA chip receives a reference function from the DSP chip via the SRIO protocol, and the processing module FPGA chip receives raw data from the digital down-conversion module via the Aurora protocol.

[0039] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A large-point pulse compression method based on FPGA of airborne radar signal processing module, characterized in that: include: Step S1: The processing module FPGA chip receives the original data transmitted from the down-conversion module through the Aurora interface and the reference function transmitted from the signal processing module DSP chip through the SRIO interface; Step S2: The processing module FPGA chip converts the original data from fixed-point numbers to floating-point numbers; Step S3: The FPGA chip of the processing module calculates the pulse pressure of the raw data after fixed floating rotation according to the received reference function; Step S4: The processing module FPGA chip performs a modulo operation on the result after the pulse pressure calculation and transmits it to the DSP, and the DSP performs SAR imaging on the result after the pulse pressure calculation.

2. The large-point pulse compression method based on the airborne radar signal processing module FPGA as claimed in claim 1 is characterized in that: The specific steps of calculating pulse pressure on the original data after fixed floating rotation include: Step S31: Setting the IP core and presetting parameters for the IP core; Step S32: changing the amount of raw data after fixed floating required for each pulse pressure calculation according to the preset parameters; Step S33: The FPGA chip of the processing module performs segmented calculation on the original data after fixed floating conversion according to the reference function and the requirements of a single calculation.

3. The large-point pulse compression method based on the airborne radar signal processing module FPGA as claimed in claim 2 is characterized in that: The FPGA chip of the processing module performs FFT operation on the original data after fixed-floating conversion based on the reference function, performs inverse FFT transformation on the FFT operation result, and obtains the result after pulse pressure operation.

4. The large-point pulse compression method based on the airborne radar signal processing module FPGA as claimed in claim 2 is characterized in that: Step S2 also includes: storing the original data after fixed-floating conversion in a two-dimensional matrix mode.

5. The large-point pulse compression method based on the airborne radar signal processing module FPGA as claimed in claim 4 is characterized in that: The preset parameters change the number of rows and columns of the two-dimensional matrix.

6. The large-point pulse compression method based on the airborne radar signal processing module FPGA as claimed in claim 4 is characterized in that: In step S1, the processing module FPGA chip receives a reference function from the DSP chip via the SRIO protocol, and the processing module FPGA chip receives raw data from the digital down-conversion module via the Aurora protocol.

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