Driving backboard, preparation method thereof and display device

Abstract

The invention discloses a driving backboard, a preparation method thereof and a display device, and relates to the technical field of display. The driving backboard comprises a substrate and a pixel driving layer located on one side of the substrate. The pixel driving layer comprises a plurality of pixel circuits, and a storage capacitor in each pixel circuit comprises a first capacitor plate, a second capacitor plate and a third capacitor plate. The storage capacitor comprises three capacitor plates, so that the storage capacitor is a double-layer capacitor, the capacitance of the storage capacitor can be improved, the storage capacitor can be ensured to keep the charged voltage to the next picture updating time, and the reliability of the driving backboard is ensured. Moreover, one side, close to the first insulating layer, of the second capacitor plate of the storage capacitor is provided with the target protection pattern, so that the adhesion of the second capacitor plate caused by poor surface flatness of the first insulating layer can be avoided, the second capacitor plate is prevented from falling off, and the yield of the driving backboard is ensured.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving backplane and a preparation method thereof, and a display device. Background Art

[0002] Electronic paper has the advantages of low power consumption, foldability, high color contrast and high resolution, and is therefore widely used in various application scenarios.

[0003] In the related art, the working principle of electronic paper is based on electrophoretic display (EPD) technology. This technology controls the movement of colored charged balls in a liquid environment through an external electric field, thereby presenting the required text or image. In order to ensure the display effect, touch sensitivity and service life of electronic paper, the capacitor in the driving backplane included in the electronic paper needs to be a double-layer capacitor.

[0004] However, the design of double-layer capacitors easily leads to static electricity accumulation and stress concentration, which in turn affects the yield of the driver backplane. Summary of the invention

[0005] The present application provides a driving backplane and a method for manufacturing the same, and a display device, which can solve the problem of low yield of the driving backplane in the related art. The technical solution is as follows:

[0006] In one aspect, a driving backplane is provided, the driving backplane comprising:

[0007] A base substrate, the base substrate comprising a display area;

[0008] and a pixel driving layer located on one side of the base substrate, the pixel driving layer comprising a plurality of pixel circuits located in the display area and arranged in an array, the pixel circuits comprising a storage capacitor, the storage capacitor comprising: a first capacitor plate, a second capacitor plate and a third capacitor plate;

[0009] Among them, the pixel driving layer includes a first conductive layer, a first insulating layer, a target protection layer, a second conductive layer, a second insulating layer and a third conductive layer, the first conductive layer includes the first capacitor plate, the target protection layer includes a target protection pattern, the orthographic projection of the target protection pattern on the substrate and the orthographic projection of the first capacitor plate on the substrate overlap, the second conductive layer includes the second capacitor plate, the orthographic projection of the second capacitor plate on the substrate is located within the orthographic projection of the target protection pattern on the substrate, the third conductive layer includes the third capacitor plate, the orthographic projection of the third capacitor plate on the substrate overlaps with the orthographic projections of the first capacitor plate and the second capacitor plate on the substrate, and the third capacitor plate is connected to the first capacitor plate through vias in the second insulating layer and the first insulating layer.

[0010] Optionally, the pixel circuit further includes a switching transistor, the switching transistor includes a gate, a source and a drain, and the drain is connected to the first capacitor plate and the third capacitor plate;

[0011] Among them, the first conductive layer also includes a gate pattern, the gate pattern and the first capacitor plate are spaced apart, at least a portion of the gate pattern serves as the gate of the switching transistor, the target protection layer is an active layer, the active layer also includes an active pattern, the active pattern and the target protection pattern are spaced apart, the orthographic projection of the active pattern on the base substrate and the orthographic projection of the gate pattern on the base substrate overlap, the second conductive layer also includes a source pattern and a drain pattern spaced apart, at least a portion of the source pattern serves as the source of the switching transistor, at least a portion of the drain pattern serves as the drain of the switching transistor, the source pattern and the drain pattern are both spaced apart from the second capacitor plate, and the source pattern and the drain pattern are both connected to the active pattern.

[0012] Optionally, the first insulating layer has a first via hole exposing the first capacitor plate, the drain pattern is also located in the first via hole, and the drain pattern is connected to the first capacitor plate through the first via hole;

[0013] The second insulating layer has a second via hole exposing the drain pattern, the third capacitor plate is also located in the second via hole, and the third capacitor plate is connected to the drain pattern through the second via hole.

[0014] Optionally, an orthographic projection of the second via hole on the base substrate overlaps with an orthographic projection of the first via hole on the base substrate.

[0015] Optionally, the active layer includes a stacked first sublayer and a second sublayer, the material of the first sublayer includes a main material, the material of the second sublayer includes a main material and a doping material doped in the main material, the main material includes amorphous silicon, and the doping material includes boron or phosphorus;

[0016] The first sublayer and the second sublayer both include the active pattern, and at least one of the first sublayer and the second sublayer includes the target protection pattern;

[0017] The active pattern of the second sub-layer includes a first sub-active pattern and a second sub-active pattern which are arranged at intervals, and the orthographic projection of the first sub-active pattern on the base substrate and the orthographic projection of the second sub-active pattern on the base substrate both overlap with the orthographic projection of the active pattern of the first sub-layer on the base substrate;

[0018] The source pattern is connected to the first sub-active pattern, and the drain pattern is connected to the second sub-active pattern.

[0019] Optionally, the active pattern and the target protection pattern included in the first sub-layer form an integrated structure and entirely cover the base substrate.

[0020] Optionally, the material of the active layer includes metal oxide.

[0021] Optionally, the base substrate further includes a peripheral area surrounding the display area, and the peripheral area includes a target area located on one side of the display area; the driving backplane further includes:

[0022] a plurality of gate signal lines, the plurality of gate signal lines are arranged along a first direction and extend along a second direction, each of the gate signal lines comprises a gate signal line body and a plurality of gate patterns connected to the gate signal line body and arranged at intervals along the second direction, at least a portion of each of the gate patterns serves as a gate of a switch transistor of one of the plurality of pixel circuits arranged along the second direction, the second direction intersecting the first direction; one of the two ends of the gate signal line in the second direction is located in the target area;

[0023] a plurality of data connection lines and a plurality of data signal lines corresponding to the plurality of data connection lines, the plurality of data connection lines are arranged along the first direction and extend along the second direction, the plurality of data signal lines are arranged along the second direction and extend along the first direction, each of the data signal lines is connected to a corresponding one of the data connection lines, and each of the data signal lines is connected to source electrodes of switch transistors in a plurality of pixel circuits arranged along the first direction; one of the two ends of the data connection line in the second direction is located in the target area;

[0024] A driving chip is located in the target area, and the end of the gate signal line located in the target area and the end of the data connection line located in the target area are both connected to the driving chip, and the driving chip is used to provide a gate signal for the gate signal line and to provide a data signal for the data connection line.

[0025] Optionally, the plurality of gate signal lines and the plurality of data connection lines are all located in the first conductive layer;

[0026] The plurality of data signal lines are located in the second conductive layer, and the data signal lines include a data signal line body and a plurality of source patterns connected to the data signal line body and spaced apart along the first direction;

[0027] Wherein, the data signal line is connected to the corresponding data connection line at least through a via hole in the first insulating layer.

[0028] Optionally, the second insulating layer includes a stacked first sub-insulating layer and a second sub-insulating layer;

[0029] The orthographic projection of the first sub-insulating layer on the base substrate and the orthographic projection of the storage capacitor on the base substrate do not overlap, and the orthographic projection of the first sub-insulating layer on the base substrate covers the orthographic projection of the switch transistor in the pixel circuit on the base substrate;

[0030] The orthographic projection of the second sub-insulating layer on the base substrate overlaps with the orthographic projections of the storage capacitor and the switch transistor on the base substrate;

[0031] The material of the first sub-insulating layer is an organic material, and the material of the second sub-insulating layer is an inorganic material.

[0032] Optionally, the second conductive layer further includes a plurality of common capacitor signal lines arranged along a second direction and extending along the first direction, and the second direction intersects the first direction;

[0033] Each of the common capacitance signal lines is an integrated structure with the second capacitance plates of the storage capacitors of the multiple pixel circuits arranged along the first direction, and provides a common capacitance signal for the second capacitance plates of the storage capacitors of the multiple pixel circuits arranged along the first direction.

[0034] Optionally, the third conductive layer includes a first sub-conductive layer and a second sub-conductive layer; the material of the first sub-conductive layer includes metal or metal alloy, and the material of the second sub-conductive layer includes metal oxide;

[0035] The first sub-conductive layer includes multiple first capacitor patterns, the second sub-conductive layer includes multiple second capacitor patterns corresponding to the multiple first capacitor patterns, the orthographic projections of the second capacitor patterns on the base substrate cover the orthographic projections of the corresponding first capacitor patterns on the base substrate, and the third capacitor plate includes the first capacitor patterns and the corresponding second capacitor patterns.

[0036] In another aspect, a method for preparing a driving backplane is provided, the method comprising:

[0037] providing a substrate substrate, the substrate substrate comprising a display area;

[0038] forming a pixel driving layer on one side of the base substrate;

[0039] Wherein, the pixel driving layer includes a plurality of pixel circuits located in the display area and arranged in an array, the pixel circuit includes a storage capacitor, and the storage capacitor includes: a first capacitor plate, a second capacitor plate and a third capacitor plate;

[0040] The pixel driving layer includes a first conductive layer, a first insulating layer, a target protection layer, a second conductive layer, a second insulating layer and a third conductive layer, the first conductive layer includes the first capacitor plate, the target protection layer includes a target protection pattern, the orthographic projection of the target protection pattern on the substrate substrate and the orthographic projection of the first capacitor plate on the substrate substrate overlap, the second conductive layer includes the second capacitor plate, the orthographic projection of the second capacitor plate on the substrate substrate is located within the orthographic projection of the target protection pattern on the substrate substrate, the third conductive layer includes the third capacitor plate, the orthographic projection of the third capacitor plate on the substrate substrate overlaps with the orthographic projections of the first capacitor plate and the second capacitor plate on the substrate substrate, and the third capacitor plate is connected to the first capacitor plate through vias in the second insulating layer and the first insulating layer.

[0041] In yet another aspect, a display device is provided, the display device comprising: a display component and a driving backplane as described in the above aspect;

[0042] The display component is located on one side of the driving backplane, and the driving backplane is used to drive the display component to display an image.

[0043] Optionally, the display component is an electronic paper film.

[0044] The beneficial effects of the technical solution provided by this application include at least:

[0045] The present application provides a driving backplane and a preparation method thereof, and a display device, wherein the driving backplane includes a substrate substrate and a pixel driving layer located on one side of the substrate substrate. The pixel driving layer includes a plurality of pixel circuits, and the storage capacitor in the pixel circuit includes a first capacitor plate, a second capacitor plate, and a third capacitor plate. Since the storage capacitor includes three capacitor plates, the storage capacitor is a double-layer capacitor, which can increase the capacitance of the storage capacitor, ensure that the storage capacitor can keep the charged voltage until the next time the screen is updated, and ensure the reliability of the driving backplane. In addition, a target protection pattern is provided on the side of the second capacitor plate of the storage capacitor close to the first insulating layer, so that the adhesion of the second capacitor plate caused by the poor surface flatness of the first insulating layer can be avoided, thereby avoiding the second capacitor plate from falling off, and ensuring the yield of the driving backplane. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 is a partial top view of a driving backplane provided in an embodiment of the present application;

[0048] Figure 2 is a cross-sectional schematic diagram of a driving backplane provided in an embodiment of the present application;

[0049] Figure 3 is a top view of a substrate provided in an embodiment of the present application;

[0050] Figure 4 is a partial top view of another driving backplane provided in an embodiment of the present application;

[0051] Figure 5 is a cross-sectional schematic diagram of another driving backplane provided in an embodiment of the present application;

[0052] Figure 6 is a partial top view of a first conductive layer provided in an embodiment of the present application;

[0053] Figure 7 is a partial top view of a second conductive layer provided in an embodiment of the present application;

[0054] Figure 8 is a partial top view of a third conductive layer provided in an embodiment of the present application;

[0055] Fig. 9 is a flow chart of a method for preparing a driving backplane provided in an embodiment of the present application;

[0056] Fig.10 is a flow chart of forming a pixel driving layer provided by an embodiment of the present application;

[0057] Fig.11 is a partial top view of forming a first conductive layer provided by an embodiment of the present application;

[0058] Fig.12 is a cross-sectional schematic diagram of forming a first conductive layer provided in an embodiment of the present application;

[0059] Fig.13 It is a cross-sectional schematic diagram of forming a first insulating film, a first sub-layer film and a second sub-layer film provided in an embodiment of the present application;

[0060] Fig.14 It is a partial top view of forming a first conductive layer, a first insulating layer and an active layer provided by an embodiment of the present application;

[0061] Fig.15 It is a cross-sectional schematic diagram of forming a first conductive layer, a first insulating film and an active layer provided in an embodiment of the present application;

[0062] Fig.16 It is a cross-sectional schematic diagram of forming a first conductive layer, a first insulating layer and an active layer provided in an embodiment of the present application;

[0063] Fig.17 It is a partial top view of forming a first conductive layer, a first insulating layer, an active layer and a second conductive layer provided by an embodiment of the present application;

[0064] Fig.18 It is a cross-sectional schematic diagram of forming a first conductive layer, a first insulating layer, an active layer and a second conductive layer provided in an embodiment of the present application;

[0065] Fig.19 It is a partial top view of forming a first conductive layer, a first insulating layer, an active layer, a second conductive layer and a first sub-insulating layer provided by an embodiment of the present application;

[0066] Fig. 20It is a cross-sectional schematic diagram of forming a first conductive layer, a first insulating layer, an active layer, a second conductive layer and a first sub-insulating layer provided in an embodiment of the present application;

[0067] Fig.21 It is a partial top view of forming a first conductive layer, a first insulating layer, an active layer, a second conductive layer and a second insulating layer provided by an embodiment of the present application;

[0068] Fig. 22 It is a cross-sectional schematic diagram of forming a first conductive layer, a first insulating layer, an active layer, a second conductive layer and a second insulating layer provided in an embodiment of the present application;

[0069] Fig.23 It is a partial top view of forming a first conductive layer, a first insulating layer, an active layer, a second conductive layer, a second insulating layer and a first sub-conductive layer provided by an embodiment of the present application;

[0070] Fig.24 It is a cross-sectional schematic diagram of forming a first conductive layer, a first insulating layer, an active layer, a second conductive layer, a second insulating layer and a first sub-conductive layer provided by an embodiment of the present application;

[0071] Fig.25 is another flow chart of forming a pixel driving layer provided by an embodiment of the present application;

[0072] Fig.26 is a partial top view of forming a first conductive layer provided by an embodiment of the present application;

[0073] Fig. 27 is a cross-sectional schematic diagram of forming a first conductive layer provided in an embodiment of the present application;

[0074] Fig.28 It is a cross-sectional schematic diagram of forming a first insulating film, a first sub-layer film and a second sub-layer film provided in an embodiment of the present application;

[0075] Fig.29 It is a partial top view of forming a first conductive layer, a first insulating layer and an active layer provided by an embodiment of the present application;

[0076] Fig.30 It is a cross-sectional schematic diagram of forming a first conductive layer, a first insulating film and an active layer provided by an embodiment of the present application;

[0077] Fig.31 It is a partial top view of forming a first conductive layer, a first insulating layer, an active layer and a second conductive layer provided by an embodiment of the present application;

[0078] Fig.32 It is a cross-sectional schematic diagram of forming a first conductive layer, a first insulating layer, an active layer and a second conductive layer provided in an embodiment of the present application;

[0079] Fig.33 It is a partial top view of forming a first conductive layer, a first insulating layer, an active layer, a second conductive layer and a first sub-insulating layer provided by an embodiment of the present application;

[0080] Fig.34 It is a cross-sectional schematic diagram of forming a first conductive layer, a first insulating layer, an active layer, a second conductive layer and a first sub-insulating layer provided in an embodiment of the present application;

[0081] Fig.35 It is a partial top view of forming a first conductive layer, a first insulating layer, an active layer, a second conductive layer and a second insulating layer provided by an embodiment of the present application;

[0082] Fig.36 It is a cross-sectional schematic diagram of forming a first conductive layer, a first insulating layer, an active layer, a second conductive layer and a second insulating layer provided in an embodiment of the present application;

[0083] Fig.37 It is a partial top view of forming a first conductive layer, a first insulating layer, an active layer, a second conductive layer, a second insulating layer and a first sub-conductive layer provided by an embodiment of the present application;

[0084] Fig.38 It is a cross-sectional schematic diagram of forming a first conductive layer, a first insulating layer, an active layer, a second conductive layer, a second insulating layer and a first sub-conductive layer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0085] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0086] Figure 1 It is a partial top view of a driving backplane provided in an embodiment of the present application. Figure 2 is a cross-sectional schematic diagram of a driving backplane provided in an embodiment of the present application. Figure 1 and Figure 2 The driving backplane 100 includes: a base substrate 101 and a pixel driving layer 102 located on one side of the base substrate 101 .

[0087] Figure 3 is a top view of a substrate provided in an embodiment of the present application. Figure 3, the base substrate 101 includes a display area 101a. Among them, the pixel driving layer 102 includes a plurality of pixel circuits 1021 located in the display area 101a and arranged in an array. The pixel circuit 1021 includes a storage capacitor Cst, and the storage capacitor Cst includes: a first capacitor plate Cst1, a second capacitor plate Cst2, and a third capacitor plate Cst3. Since the storage capacitor Cst includes three capacitor plates, the first capacitor plate Cst1 and the second capacitor plate Cst2 can form a layer of capacitor, and the second capacitor plate Cst2 and the third capacitor plate Cst3 can form a layer of capacitor, that is, the storage capacitor Cst can be a double-layer capacitor. , Since the storage capacitor Cst is a double-layer capacitor, the capacitance of the storage capacitor Cst can be increased, thereby ensuring that the storage capacitor Cst can keep the charged voltage until the next screen update, thereby ensuring the reliability of the driving backplane 100.

[0088] refer to Figure 2 , the pixel driving layer 102 includes a first conductive layer n1, a first insulating layer n2, a target protection layer n3, a second conductive layer n4, a second insulating layer n5 and a third conductive layer n6. The first conductive layer n1 includes a first capacitor plate Cst1. The target protection layer n3 protects a target protection pattern n3a. The orthographic projection of the target protection pattern n3a on the substrate 101 overlaps with the orthographic projection of the first capacitor plate Cst1 on the substrate 101. The second conductive layer n4 includes a second capacitor plate Cst2, and the orthographic projection of the second capacitor plate Cst2 on the substrate 101 is located within the orthographic projection of the target protection pattern n3a on the substrate 101. The third conductive layer n6 includes a third capacitor plate Cst3, and the orthographic projection of the third capacitor plate Cst3 on the substrate 101 overlaps with the orthographic projections of the first capacitor plate Cst1 and the second capacitor plate Cst2 on the substrate 101. The third capacitor plate Cst3 is connected to the first capacitor plate Cst1 through the second insulating layer n5 and the via holes in the first insulating layer n2.

[0089] Since the third capacitor plate Cst3 is connected to the first capacitor plate Cst1, the signals transmitted by the first capacitor plate Cst1 and the third capacitor plate Cst3 can be the same, so that the storage capacitor Cst can realize the function of a double-layer capacitor by adjusting the signal received by the second capacitor plate Cst2.

[0090] In the embodiment of the present application, since the target protection pattern n3a is set on the side of the second capacitor plate Cst2 of the storage capacitor Cst close to the first insulating layer n2, the adhesion of the second capacitor plate Cst2 caused by the poor surface flatness of the first insulating layer n2 can be avoided, thereby avoiding the second capacitor plate Cst2 from falling off, thereby ensuring the yield of the storage capacitor Cst.

[0091] In summary, the embodiment of the present application provides a driving backplane, which includes a substrate substrate and a pixel driving layer located on one side of the substrate substrate. The pixel driving layer includes a plurality of pixel circuits, and the storage capacitor in the pixel circuit includes a first capacitor plate, a second capacitor plate and a third capacitor plate. Since the storage capacitor includes three capacitor plates, the storage capacitor is a double-layer capacitor, which can increase the capacitance of the storage capacitor, ensure that the storage capacitor can keep the charged voltage until the next time the screen is updated, and ensure the reliability of the driving backplane. In addition, a target protection pattern is set on the side of the second capacitor plate of the storage capacitor close to the first insulating layer, so that the adhesion of the second capacitor plate caused by the poor surface flatness of the first insulating layer can be avoided, thereby avoiding the second capacitor plate from falling off, and ensuring the yield of the driving backplane.

[0092] refer to Figure 1 and Figure 2 , the pixel circuit 1021 also includes a switching transistor T. The switching transistor T includes a gate, a source and a drain. The drain is connected to the first capacitor plate Cst1 and the third capacitor plate Cst3. Thus, when the switching transistor T is in an on state, the signal received by the source of the switching transistor T is transmitted to the first capacitor plate Cst1 and the third capacitor plate Cst3 through the drain of the switching transistor T, thereby charging the storage capacitor Cst.

[0093] In the embodiment of the present application, the first conductive layer n1 may be a gate layer, and the first conductive layer n1 further includes a gate pattern n11. At least a portion of the gate pattern n11 serves as a gate of the switch transistor T, and the gate pattern n11 and the first capacitor plate Cst1 are spaced apart.

[0094] The target protection layer n3 can be an active (poly) layer. That is, the target protection pattern n3a included in the target protection layer n3 is a part of the active layer. In this case, when forming the active layer of the driving backplane 100, there is no need to etch and remove the material of the active layer above the first capacitor plate Cst1, but the material of the active layer above the first capacitor plate Cst1 is retained as the target protection pattern n3a. Avoid the first insulating layer n2 under the second capacitor plate Cst2 being damaged when etching the active layer, resulting in poor surface flatness of the first insulating layer n2. If the second capacitor plate Cst2 is directly formed on the first insulating layer n2 with poor flatness, it will cause the second capacitor plate Cst2 and the first insulating layer n2 to have poor adhesion. In the embodiment of the present application, there is no need to etch the material of the active layer above the first capacitor plate Cst1. Therefore, when the second capacitor plate Cst2 is formed above the active layer, the adhesion between the formed second capacitor plate Cst2 and the active layer can be ensured to prevent the second capacitor plate Cst2 from falling off and affecting the yield of the driving backplane 100.

[0095] refer to Figure 2 In addition to the target protection pattern n3a, the active layer also includes an active pattern n3b. The active pattern n3b and the target protection pattern n3a are arranged alternately. The orthographic projection of the active pattern n3b on the base substrate 101 and the orthographic projection of the gate pattern n11 on the base substrate 101 overlap. The overlapping area of ​​the active pattern n3b and the gate pattern n11 can constitute a channel of the switch transistor T.

[0096] refer to Figure 2 , the second conductive layer n4 can also be a source-drain layer. The second conductive layer n4 also includes a source pattern n41 and a drain pattern n42 that are spaced apart. The source pattern n41 and the drain pattern n42 are both connected to the active pattern n3b. At least a portion of the pattern of the source pattern n41 can be used as the source of the switching transistor T, and at least a portion of the pattern of the drain pattern n42 can be used as the drain of the switching transistor T. In addition, the second capacitor plate Cst2 is also located in the second conductive layer n4. In order to avoid the source pattern n41 and the drain pattern n42 from affecting the second capacitor plate Cst2, the source pattern n41 and the drain pattern n42 need to be spaced apart from the second capacitor plate Cst2.

[0097] refer to Figure 2 It can be seen that the first insulating layer n2 has a first via K1 exposing the first capacitor plate Cst1, the drain pattern n42 is also located in the first via K1, and the drain pattern n42 is connected to the first capacitor plate Cst1 through the first via K1. The second insulating layer n5 has a second via K2 exposing the drain pattern n42, the third capacitor plate Cst3 is also located in the second via K2, and the third capacitor plate Cst3 is connected to the drain pattern n42 through the second via K2. That is, the first capacitor plate Cst1 and the third capacitor plate Cst3 can be connected through the commonly connected drain pattern n42.

[0098] In the embodiment of the present application, the orthographic projection of the second via K2 on the base substrate 101 overlaps with the orthographic projection of the first via K1 on the base substrate 101. This can reduce the size of the total space occupied by the first via K1 and the second via K2 on the plane, which is beneficial to the improvement of the opening ratio of the product. Of course, the orthographic projection of the second via K2 on the base substrate 101 and the orthographic projection of the first via K1 on the base substrate 101 may not overlap. The embodiment of the present application does not specifically limit the projection relationship between the first via K1 and the second via K2. It is only necessary to ensure that the first capacitor plate Cst1 and the drain pattern n42, as well as the drain pattern n42 and the third capacitor plate Cst3 are connected.

[0099] In the embodiment of the present application, the first insulating layer n2 may be a gate insulating layer, and the material of the first insulating layer n2 may be an inorganic material, for example, the material of the first insulating layer n2 is at least one of silicon nitride (SiNx), silicon oxide (SiOx) and silicon oxynitride (SiON).

[0100] Since the target protection pattern n3a of the active layer is arranged between the first capacitor plate Cst1 and the second capacitor plate Cst2, the distance between the first capacitor plate Cst1 and the second capacitor plate Cst2 will increase, which may cause the capacitance of the storage capacitor Cst to decrease. However, the dielectric constant of the active layer is usually larger than the dielectric constant of the first insulating layer n2. Therefore, even if the active layer is arranged between the first capacitor plate Cst1 and the second capacitor plate Cst2, the reduction of the storage capacitor Cst can be offset by the large dielectric constant of the active layer, which can meet the design requirements of the double-layer capacitor driving the backplane in the electronic paper product.

[0101] Optionally, when the material of the first insulating layer n2 is silicon nitride (SiNx), the dielectric constant of the first insulating layer n2 is approximately 6.5. When the material of the active layer includes amorphous silicon (a-Si), the dielectric constant of the active layer is approximately 30. It can be seen that the dielectric constant of the active layer is greater than the dielectric constant of the first insulating layer n2.

[0102] Optionally, a film layer with a higher dielectric constant has a stronger antistatic capability, so the antistatic capability of the storage capacitor Cst can be improved by retaining the material of the active layer on the gate insulating layer in the area where the storage capacitor Cst is located.

[0103] As an optional implementation, refer to Figure 2 The active layer n3 includes a first sublayer n31 and a second sublayer n32 stacked together. The material of the first sublayer n31 includes a main material, and the material of the second sublayer n32 includes a main material and a doping material doped in the main material. The main material includes amorphous silicon (a-Si), and the doping material includes boron (B) or phosphorus (P).

[0104] Optionally, if the doping material includes boron, the second sublayer n32 may be a P-type semiconductor layer, and the corresponding switch transistor T may be a P-type transistor. If the doping material includes phosphorus, the second sublayer n32 may be an N-type semiconductor layer, and the corresponding switch transistor T may be an N-type transistor.

[0105] Optionally, both the first sublayer n31 and the second sublayer n32 include an active pattern n3b so that the switch transistor T can realize its own function. At least one of the first sublayer n31 and the second sublayer n32 includes a target protection pattern n3a, which can protect the underlying first insulating layer n2 and ensure the preparation reliability of the second capacitor plate Cst2.

[0106] Optionally, the second sublayer n32 may be a heavily doped active layer, that is, the second sublayer n32 may be used as an ohmic contact layer to improve the performance of the switch transistor T. Figure 2 , the active pattern n3b of the second sub-layer n32 includes a first sub-active pattern n3b1 and a second sub-active pattern n3b2 which are arranged at intervals. The orthographic projection of the first sub-active pattern n3b1 on the base substrate 101 and the orthographic projection of the second sub-active pattern n3b2 on the base substrate 101 overlap with the orthographic projection of the active pattern n3b of the first sub-layer n31 on the base substrate 101. The source pattern n41 is connected to the first sub-active pattern n3b1, and the drain pattern n42 is connected to the second sub-active pattern n3b2. Moreover, by the first sub-active pattern n3b1 and the second sub-active pattern n3b2 which are arranged at intervals, it is prevented that the first sub-active pattern n3b1 and the second sub-active pattern n3b2 directly turn on the source pattern n41 and the drain pattern n42, thereby ensuring the normal function of the switch transistor T.

[0107] In the examples of this application, refer to Figure 4 and Figure 5 , the active pattern n3b and the target protection pattern n3a included in the first sub-layer n31 can also be an integrated structure and cover the base substrate 101 in an entire layer. In this case, the material of the first sub-layer n31 includes a main material, and the material of the second sub-layer n32 includes a main material and a doping material doped in the main material. The main material includes amorphous silicon, and the doping material includes boron or phosphorus.

[0108] As another optional implementation, the material of the active layer includes metal oxide. For example, the material of the active layer includes indium zinc oxide (IGZO). In this case, the active layer n3 may include active patterns n3b and target protection patterns n3a that are spaced apart.

[0109] In the examples of this application, refer to Figure 3 The base substrate 101 further includes a peripheral region 101b surrounding the display region 101a. The peripheral region 101b includes a target region located on one side of the display region 101a. That is, the target region is a region of the peripheral region 101b located on one side of the display region 101a.

[0110] Optional, reference Figure 1 and Figure 4 The driving backplane 100 may include: a plurality of gate signal lines 103 , a plurality of data connection lines 104 , and a plurality of data signal lines 105 corresponding to the plurality of data connection lines 104 .

[0111] refer to Figure 1 and Figure 4, a plurality of gate signal lines 103 are arranged along a first direction X and extend along a second direction Y. Figure 6 Each gate signal line 103 includes a gate signal line body 1031 and a plurality of gate patterns n11 connected to the gate signal line body 1031 and arranged at intervals along the second direction Y. The gate signal line 103 extending along the second direction Y may refer to the gate signal line body 1031 in the gate signal line 103 extending substantially along the second direction Y. At least a portion of each gate pattern n11 serves as a gate of a switch transistor T of one of the plurality of pixel circuits 1021 arranged along the second direction Y.

[0112] A plurality of data connection lines 104 are arranged along a first direction X and extend along a second direction Y. A plurality of data signal lines 105 are arranged along the second direction Y and extend along the first direction X. Each data signal line 105 is connected to a corresponding data connection line 104. Each data signal line 105 is connected to a source electrode of a switch transistor T in a plurality of pixel circuits 1021 arranged along the first direction X. The extension of the data connection line 104 along the second direction Y may refer to that the data connection line 104 extends approximately along the second direction Y, and the extension of the data signal line 105 along the first direction X may refer to that the data signal line 105 extends approximately along the first direction X.

[0113] Optionally, the line extending substantially in a certain direction may mean that the line may be in a bent shape, a curved shape, a straight shape, etc., and the overall extending direction is a certain specific direction. Figure 6 Among the multiple data connection lines 104, some of the data connection lines 104 are in a straight line shape, and another part of the data connection lines 104 are in a broken line shape.

[0114] By setting the data connection line 104 that is roughly consistent with the extension direction of the gate signal line 103, one of the two ends of the gate signal line 103 in the second direction Y, and one of the two ends of the data connection line 104 in the second direction Y can be located in the target area. Thus, the drive backplane can include a driver chip located in the target area, and the driver chip and the gate signal line 103 are located at the end of the target area, and the end of the data connection line 104 located in the target area is connected to the driver chip. The driver chip can be used to provide a gate signal to the gate signal line 103, so that the switch transistor T is turned on or off under the drive of the gate signal. The driver chip can also be used to provide a data signal to the data connection line 104, so that the data connection line 104 transmits the data signal to the source of the switch transistor T through the data signal line 105. When the switch transistor T is in the on state, the data signal line 105 can transmit the data signal to the drain of the switch transistor T.

[0115] In the case where the driving backplane does not include the data connection line 104, since the extension direction of the gate signal line 103 intersects with the extension direction of the data signal line 105, the driving backplane needs to be provided with two driving chips. One of the driving chips is located in the region where the end of the gate signal line 103 is located, so as to be connected to the gate signal line 103. The other driving chip is located in the region where the end of the data signal line 105 is located, so as to be connected to the data signal line 105.

[0116] In the embodiment of the present application, by setting the data connection line 104 whose extension direction is roughly consistent with the gate signal line 103, it is only necessary to set one driving chip in the target area to realize the transmission of gate signals and data signals, thereby saving the number of driving chips required to set the driving backplane 100 and reducing the preparation cost of the driving backplane 100.

[0117] Optionally, the plurality of gate signal lines 103 and the plurality of data connection lines 104 are all located in the first conductive layer n1. The plurality of data signal lines 105 are located in the second conductive layer n4. Figure 7 The data signal line 105 includes a data signal line body 1051 and a plurality of source patterns n41 connected to the data signal line body 1051 and spaced apart along the first direction X. The data signal line 105 extending along the first direction X may mean that the data signal line body 1051 extends substantially along the first direction X.

[0118] The data signal line 105 is connected to the corresponding data connection line 104 at least through the via K3 in the first insulating layer n2. For example, the via K3 may be located in the overlapping region of the orthographic projection of the data signal line body 1051 on the base substrate 101 and the orthographic projection of the corresponding data connection line 104 on the base substrate 101, so that the data signal line body 1051 and the corresponding data connection line 104 are connected in the overlapping region.

[0119] In the examples of this application, refer to Figure 2 and Figure 5 The second insulating layer n5 includes a stacked first sub-insulating layer n51 and a second sub-insulating layer n52, wherein the material of the first sub-insulating layer n51 may be an organic material, and the material of the second sub-insulating layer n52 may be an inorganic material.

[0120] For example, the first sub-insulating layer n51 can be made of a resin material. The resin can be a thermoplastic resin or a thermoplastic resin, the thermoplastic resin can include an acrylic (PMMA) resin, and the thermosetting resin can include an epoxy resin. The second sub-insulating layer n52 can be made of one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide) and SiOxNy (silicon oxynitride).

[0121] Optionally, the orthographic projection of the first sub-insulating layer n51 on the base substrate 101 and the orthographic projection of the storage capacitor Cst on the base substrate 101 do not overlap, and the orthographic projection of the first sub-insulating layer n51 on the base substrate 101 covers the orthographic projection of the switching transistor T in the pixel circuit 1021 on the base substrate 101.

[0122] By providing the first sub-insulating layer n51 above the switch transistor T, the distance between the switch transistor T and the upper device can be increased, thereby reducing the large parasitic capacitance generated between the switch transistor T and the upper device, thereby ensuring the reliability of the switch transistor T. In addition, by removing the first sub-insulating layer above the storage capacitor Cst, it is possible to avoid the distance between the third capacitor plate Cst3 and the second capacitor plate Cst2 being too large due to the presence of the first sub-insulating layer n51, thereby avoiding the capacitance of the storage capacitor Cst being affected by the presence of the first sub-insulating layer n51, thereby ensuring the reliability of the storage capacitor Cst.

[0123] The orthographic projection of the second sub-insulating layer n52 on the base substrate 101 overlaps with the orthographic projection of the storage capacitor Cst and the gate tube of the switching transistor T on the base substrate 101. Since inorganic materials are more effective in isolating water and oxygen than organic materials, the second sub-insulating layer n52 is arranged above the first sub-insulating layer n51, so that the second sub-insulating layer n52 can protect the first sub-insulating layer n51. At the same time, the second sub-insulating layer n52 is also arranged above the second capacitor plate Cst2 in the storage capacitor Cst, and can be used to insulate the third capacitor plate Cst3 from the second capacitor plate Cst2.

[0124] In the embodiment of the present application, the driving backplane 100 further includes a plurality of common capacitor signal lines 106. Figure 7 , a plurality of common capacitor signal lines 106 are located in the second conductive layer n4, and the plurality of common capacitor signal lines 106 are arranged along the second direction Y and extend along the first direction X. Each common capacitor signal line 106 and the second capacitor plate Cst2 of the storage capacitor Cst of the plurality of pixel circuits 1021 arranged along the first direction X are an integrated structure, and provide a common capacitor signal for the second capacitor plate Cst2 of the storage capacitor Cst of the plurality of pixel circuits 1021 arranged along the first direction X. For example, the common capacitor signal line 106 can provide a common signal of a fixed potential for the second capacitor plate Cst2 of the storage capacitor Cst of the plurality of pixel circuits 1021.

[0125] Figure 8 is a partial top view of a third conductive layer provided in an embodiment of the present application. Figure 8, the third conductive layer n6 includes a first sub-conductive layer n61 and a second sub-conductive layer n62. The first sub-conductive layer n61 includes a plurality of first capacitor patterns Cst3-1, and the second sub-conductive layer n62 includes a plurality of second capacitor patterns Cst3-2 corresponding to the plurality of first capacitor patterns Cst3-1. The orthographic projection of the second capacitor pattern Cst3-2 on the base substrate 101 covers the orthographic projection of the corresponding first capacitor pattern Cst3-1 on the base substrate 101. The third capacitor plate Cst3 includes a first capacitor pattern Cst3-1 and a corresponding second capacitor pattern Cst3-2. That is, the third capacitor plate Cst3 of the storage capacitor Cst may include two layers of patterns.

[0126] Among them, the material of the first sub-conductive layer n61 includes metal or metal alloy, that is, the material of the first capacitor pattern Cst3-1 included in the first sub-conductive layer n61 also includes metal or metal alloy, which is used to ensure the capacitance of the storage capacitor Cst. Optionally, the material of the first sub-conductive layer n61 may include at least one of copper (Cu), aluminum (Al), molybdenum (Mo), molybdenum-niobium alloy, and molybdenum-nickel-titanium alloy. For example, the material of the first sub-conductive layer n61 may be molybdenum, and the thickness of the first sub-conductive layer n61 may range from 100nm (nanometers) to 200 nanometers.

[0127] The material of the second sub-conductive layer n62 includes metal oxide, that is, the material of the second capacitor pattern Cst3-2 included in the second sub-conductive layer n62 also includes metal oxide. The second capacitor pattern Cst3-2 covers the first capacitor pattern Cst3-1 to prevent the first capacitor pattern Cst3-1 from being corroded. Optionally, the thickness of the second sub-conductive layer n62 can range from 20nm to 60nm. For example, the material of the second sub-conductive layer n62 can be indium tin oxide (ITO), and the thickness of the second sub-conductive layer n62 can be 40nm.

[0128] In summary, the embodiment of the present application provides a driving backplane, which includes a substrate substrate and a pixel driving layer located on one side of the substrate substrate. The pixel driving layer includes a plurality of pixel circuits, and the storage capacitor in the pixel circuit includes a first capacitor plate, a second capacitor plate and a third capacitor plate. Since the storage capacitor includes three capacitor plates, the storage capacitor is a double-layer capacitor, which can increase the capacitance of the storage capacitor, ensure that the storage capacitor can keep the charged voltage until the next time the screen is updated, and ensure the reliability of the driving backplane. In addition, a target protection pattern is set on the side of the second capacitor plate of the storage capacitor close to the first insulating layer, so that the adhesion of the second capacitor plate caused by the poor surface flatness of the first insulating layer can be avoided, thereby avoiding the second capacitor plate from falling off, and ensuring the yield of the driving backplane.

[0129] Fig. 91 is a flow chart of a method for preparing a driving backplane provided in an embodiment of the present application. Fig. 9 , the method comprising:

[0130] Step S101: providing a substrate.

[0131] In the embodiment of the present application, the base substrate 101 may be a glass substrate or a flexible substrate. Optionally, the glass substrate may be alkali-free glass, alkali-containing glass, and tempered glass. The flexible substrate may be a composite material of yellow polyimide (YPI) and silicon dioxide.

[0132] Step S102: forming a pixel driving layer on one side of the base substrate.

[0133] In the embodiment of the present application, the pixel driving layer 102 includes a plurality of pixel circuits 1021 located in the display area 101a and arranged in an array. The pixel circuit 1021 includes a storage capacitor Cst and a switch transistor T. The storage capacitor Cst includes: a first capacitor plate Cst1, a second capacitor plate Cst2 and a third capacitor plate Cst3.

[0134] by Figure 1 and Figure 2 Taking the driving backplane shown in FIG. 1 as an example, the formation of the pixel driving layer 102 is described. Fig.10 , the method for forming the pixel driving layer 102 includes:

[0135] Step S1021a: forming a first conductive layer on one side of the base substrate.

[0136] refer to Fig.11 and Fig.12 , a first conductive layer n1 (gate layer) is formed on one side of the base substrate 101 by magnetron sputtering. The first conductive layer n1 includes a plurality of gate signal lines 103, a plurality of data connection lines 104, and a first capacitor plate Cst1 of a storage capacitor Cst. Among them, there are intervals between the gate signal lines 103, the data connection lines 104, and the first capacitor plate Cst1, that is, the gate signal lines 103, the data signal lines 105, and the first capacitor plate Cst1 are all separately arranged to ensure their respective functions.

[0137] Optionally, the material of the first conductive layer n1 may be at least one of copper (Cu), aluminum (Al), molybdenum (Mo), molybdenum-niobium alloy and molybdenum-nickel-titanium alloy. The thickness of the first conductive layer n1 ranges from 200 nm to 500 nm.

[0138] Optionally, the gate signal line 103 includes a gate signal line body 1031 and a gate pattern n11. At least a portion of the gate pattern n11 can be used as a gate of the switch transistor T.

[0139] Step S1022a, forming a first insulating film, a first sub-layer film and a second sub-layer film on a side of the first conductive layer away from the base substrate, and processing the first insulating film, the first sub-layer film and the second sub-layer film to obtain a first insulating layer, a first sub-layer and a second sub-layer.

[0140] refer to Fig.13 , a first insulating film, a first sub-layer film and a second sub-layer film are formed by coating the first conductive layer n1 on a side away from the substrate 101 by a chemical vapor deposition method. The material of the first insulating film may be an inorganic non-metallic material, for example, the material of the first insulating film may include one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide) and SiOxNy (silicon oxynitride). The thickness of the first insulating film may range from 300nm to 400nm.

[0141] The material of the first sub-layer film may include amorphous silicon, and the second sub-layer film may be a heavily doped active material.

[0142] refer to Fig.14 and Fig.15 , the first sub-layer film and the second sub-layer film are processed by a photolithography process to obtain a first sub-layer n31 and a second sub-layer n32. The first sub-layer n31 and the second sub-layer n32 can together constitute an active layer. The first sub-layer n31 includes an active pattern n3b and a target protection pattern n3a. The second sub-layer n32 includes an active pattern n3b and a target protection pattern n3a. The active pattern n3b of the second sub-layer n32 includes a first sub-active pattern n3b1 and a second sub-active pattern n3b2 that are spaced apart. The photolithography process may include: photoresist coating, exposure, development, etching, and removal of the photoresist.

[0143] refer to Fig.14 and Fig.16 , the first insulating film is processed by photolithography to obtain the first insulating layer n2. The first insulating layer n2 may have a first via K1, and the first via K1 may be used to expose a portion of the first capacitor plate Cst1, so that the drain pattern n42 formed subsequently is connected to the first capacitor plate Cst1. In addition, the first insulating layer n2 may also have a via K3 exposing the data connection line 104, so that the data signal line 105 formed in thickness is connected to the data connection line 104.

[0144] Step S1023a: forming a second conductive layer on a side of the active layer away from the substrate.

[0145] refer to Fig.17 and Fig.18, a second conductive layer n4 is formed on the side of the active layer away from the base substrate 101 through coating and photolithography processes. The second conductive layer n4 includes a plurality of data signal lines 105, a second capacitor plate Cst2, and a common capacitor signal line 106. And the data signal line 105 of the second conductive layer n4 may include a data signal line body 1051 and a source pattern n41. The second conductive layer n4 also includes a drain pattern n42 spaced apart from the source pattern n41. Among them, at least a portion of the source pattern n41 can be used as the source of the switching transistor T, and at least a portion of the drain pattern n42 can be used as the drain of the switching transistor T. The common capacitor signal line 106 can be an integrated structure with the second capacitor plate Cst2.

[0146] Optionally, the material of the second conductive layer n4 may be at least one of copper (Cu), aluminum (Al), molybdenum (Mo), molybdenum-niobium alloy and molybdenum-nickel-titanium alloy. The thickness of the second conductive layer n4 ranges from 200 nm to 500 nm.

[0147] Step S1024a, forming a first sub-insulating layer of the second insulating layer on a side of the second conductive layer away from the base substrate.

[0148] refer to Fig.19 and Fig. 20 , a layer of organic material film is coated on the side of the second conductive layer n4 away from the base substrate 101 by slit or hanging coating. The thickness of the organic material film ranges from 2μm (micrometer) to 6μm, for example, 3μm. After the organic material film is formed, the organic material film is pre-cured under certain temperature conditions (the temperature range can be 100°C to 110°C) (the pre-curing time can be 60 seconds). After the organic material film is developed, the organic material film is subjected to an annealing and curing process, and the temperature range can be 200°C to 250°C, for example, 230°C. The orthographic projection of the first sub-insulating layer n51 prepared by the organic material film on the base substrate 101 and the orthographic projection of the storage capacitor Cst on the base substrate 101 do not overlap, and the orthographic projection of the first sub-insulating layer n51 on the base substrate 101 covers the orthographic projection of the switch transistor T in the pixel circuit 1021 on the base substrate 101. That is, the portion of the first sub-insulating layer n51 located above the second capacitor plate Cst2 can be developed away, thereby exposing the second capacitor plate Cst2. Fig.19 In the figure, a filling pattern is used to indicate the area where the first sub-insulating layer n51 is dug out, and other areas not filled with patterns are used to indicate the area where the first insulating layer n51 has solid material.

[0149] By providing the first sub-insulating layer n51 above the switch transistor T, the distance between the switch transistor T and the upper device can be increased, thereby reducing the large parasitic capacitance generated between the switch transistor T and the upper device, thereby ensuring the reliability of the switch transistor T. In addition, by removing the first sub-insulating layer above the storage capacitor Cst, it is possible to avoid the distance between the third capacitor plate Cst3 and the second capacitor plate Cst2 being too large due to the presence of the first sub-insulating layer n51, thereby avoiding the capacitance of the storage capacitor Cst being affected by the presence of the first sub-insulating layer n51, thereby ensuring the reliability of the storage capacitor Cst.

[0150] Step S1025a: forming a second sub-insulating layer of the second insulating layer on a side of the first sub-insulating layer away from the base substrate.

[0151] The second sub-insulating film is obtained by coating the first sub-insulating layer n51 on the side away from the substrate 101 by chemical vapor deposition. The material of the second sub-insulating film can be an inorganic non-metallic material, for example, the material of the second sub-insulating film can include one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide) and SiOxNy (silicon oxynitride). The thickness of the second sub-insulating film can range from 200nm to 400nm.

[0152] refer to Fig.21 and Fig. 22 , the second sub-insulating film is processed by photolithography to obtain the second sub-insulating layer n52. The second sub-insulating layer n52 includes a second via K2, and the second via K2 can expose a portion of the drain pattern n42 so that the third capacitor plate Cst3 formed subsequently is connected to the drain pattern n42. Optionally, the orthographic projection of the second via K2 on the base substrate 101 overlaps with the orthographic projection of the first via K1 on the base substrate 101.

[0153] Step S1026a, forming a third conductive layer on a side of the second insulating layer away from the base substrate.

[0154] refer to Fig.23 and Fig.24 , a first sub-conductive layer n61 is formed on a side of the second insulating layer n5 away from the base substrate 101 by magnetron sputtering. The first sub-conductive layer n61 includes a plurality of first capacitor patterns Cst3-1, and the first capacitor patterns Cst3-1 may be block patterns. The orthographic projection of the first capacitor pattern Cst3-1 on the base substrate 101 covers the orthographic projection of the switch transistor T and the second capacitor plate Cst2 on the base substrate 101.

[0155] Among them, the material of the first sub-conductive layer n61 may include at least one of copper (Cu), aluminum (Al), molybdenum (Mo), molybdenum-niobium alloy, and molybdenum-nickel-titanium alloy. For example, the material of the first sub-conductive layer n61 may be molybdenum, and the thickness of the first sub-conductive layer n61 ranges from 100nm to 200nm. Since the material of the first capacitor pattern Cst3-1 includes metal or metal alloy, the first sub-conductive layer n61 can play a certain light-shielding role, so that the first capacitor pattern Cst3-1 covers the switch transistor T, which can avoid the problem of large light-induced leakage current of the switch transistor T due to the influence of light.

[0156] Optionally, the first capacitor pattern Cst3-1 can cover the second via K2 in the second sub-insulating layer n52 of the second insulating layer n5, thereby avoiding the corrosion of the drain pattern n42 under the second via K2 caused by the penetration of etching solution when forming the first capacitor pattern Cst3-1, thereby ensuring the reliability of the driving backplane.

[0157] refer to Figure 1 and Figure 2 , a second sub-conductive layer n62 is formed on the side of the first sub-conductive layer n61 away from the base substrate 101 by using coating and photolithography processes. The material of the second sub-conductive layer n62 can be a transparent material, and the second sub-conductive layer n62 includes a plurality of second capacitor patterns Cst3-2, and the second capacitor pattern Cst3-2 can be a block pattern. Optionally, the orthographic projection of the second capacitor pattern Cst3-2 on the base substrate 101 covers the orthographic projection of the first capacitor pattern Cst3-1 on the base substrate 101, so as to prevent the first capacitor pattern Cst3-1 from being corroded. Optionally, the size of the orthographic projection of the second capacitor pattern Cst3-2 on the base substrate 101 can be comparable to (e.g., approximately the same as) the size of the pixel of the display device.

[0158] Optionally, the material of the second sub-conductive layer n62 includes metal oxide, that is, the material of the second capacitor pattern Cst3-2 included in the second sub-conductive layer n62 also includes metal oxide. The second capacitor pattern Cst3-2 covers the first capacitor pattern Cst3-1 to prevent the first capacitor pattern Cst3-1 from being corroded. Optionally, the thickness of the second sub-conductive layer n62 can range from 20nm to 60nm. For example, the material of the second sub-conductive layer n62 can be indium tin oxide (ITO), and the thickness of the second sub-conductive layer n62 can be 40nm.

[0159] by Figure 4 and Figure 5 Taking the driving backplane shown in FIG. 1 as an example, the formation of the pixel driving layer 102 is described. Fig.25 , the method for forming the pixel driving layer 102 includes:

[0160] Step S1021b: forming a first conductive layer on one side of the base substrate.

[0161] refer to Fig.26 and Fig. 27 , a first conductive layer n1 (gate layer) is formed on one side of the base substrate 101 by magnetron sputtering. The first conductive layer n1 includes a plurality of gate signal lines 103, a plurality of data connection lines 104, and a first capacitor plate Cst1 of a storage capacitor Cst. Among them, there are intervals between the gate signal lines 103, the data connection lines 104, and the first capacitor plate Cst1, that is, the gate signal lines 103, the data signal lines 105, and the first capacitor plate Cst1 are all separately arranged to ensure their respective functions.

[0162] Optionally, the material of the first conductive layer n1 may be at least one of copper (Cu), aluminum (Al), molybdenum (Mo), molybdenum-niobium alloy and molybdenum-nickel-titanium alloy. The thickness of the first conductive layer n1 ranges from 200 nm to 500 nm.

[0163] Optionally, the gate signal line 103 includes a gate signal line body 1031 and a gate pattern n11. At least a portion of the gate pattern n11 can be used as a gate of the switch transistor T.

[0164] Step S1022b, forming a first insulating film, a first sub-layer film and a second sub-layer film on a side of the first conductive layer away from the base substrate, and processing the first insulating film, the first sub-layer film and the second sub-layer film to obtain a first insulating layer, a first sub-layer and a second sub-layer.

[0165] refer to Fig.28 , a first insulating film, a first sub-layer film and a second sub-layer film are formed by coating the first conductive layer n1 on a side away from the substrate 101 by a chemical vapor deposition method. The material of the first insulating film may be an inorganic non-metallic material, for example, the material of the first insulating film may include one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide) and SiOxNy (silicon oxynitride). The thickness of the first insulating film may range from 300nm to 400nm.

[0166] The material of the first sub-layer film may include amorphous silicon, and the second sub-layer film may be a heavily doped active material.

[0167] refer to Fig.29 and Fig.30 The second sub-layer film is processed by photolithography to obtain the second sub-layer n32. The active pattern n3b of the second sub-layer n32 includes a first sub-active pattern n3b1 and a second sub-active pattern n3b2 which are arranged at intervals. The photolithography process may include: photoresist coating, exposure, development, etching and removal of photoresist.

[0168] Optionally, the second sublayer n32 may also include a target protection pattern n3a located above the first capacitor plate Cst1, or may not include a target protection pattern n3a located above the first capacitor plate Cst1, and the embodiment of the present application does not limit this. For example, in order to prevent the second capacitor plate Cst2 or other signal lines from contacting the second sublayer n32 of the active layer and causing signal writing errors, the second capacitor plate Cst2 and the second sublayer n32 above the signal line may be removed, and only the second sublayer n32 at the channel of the switching transistor T may be retained.

[0169] refer to Fig.30 , the first insulating film and the first sub-layer film are processed by photolithography to obtain the first insulating layer n2 and the first sub-layer n31. The first insulating layer n2 and the first sub-layer n31 may have a first via K1, and the first via K1 may be used to expose a portion of the first capacitor plate Cst1, so that the drain pattern n42 formed subsequently is connected to the first capacitor plate Cst1. In addition, the first insulating layer n2 may also have a via hole exposing the data connection line 104, so that the data signal line 105 formed in thickness is connected to the data connection line 104.

[0170] The first sub-layer n31 includes an active pattern n3b and a target protection pattern n3a, and the active pattern n3b and the target protection pattern n3a included in the first sub-layer n31 form an integrated structure and form a whole film layer.

[0171] Optionally, in the process of forming the first via hole K1 in the first insulating layer n2 and the first sub-layer n31, the etching can be divided into two steps: using SF 6 (sulfur hexafluoride) and Cl 2 The first sub-layer film is etched by a mixed gas of (chlorine) and the etching gas SF 6 and Cl 2 The ratio can range from 1:5 to 1:10. Then, SF 6 and O 2 The first insulating film is etched by a mixed gas of (oxygen) and the etching gas SF 6 and O 2 The ratio can range from 1:1 to 1:2.

[0172] Step S1023b: forming a second conductive layer on a side of the active layer away from the substrate.

[0173] refer to Fig.31 and Fig.32, a second conductive layer n4 is formed on the side of the active layer away from the base substrate 101 through coating and photolithography processes. The second conductive layer n4 includes a plurality of data signal lines 105, a second capacitor plate Cst2, and a common capacitor signal line 106. And the data signal line 105 of the second conductive layer n4 may include a data signal line body 1051 and a source pattern n41. The second conductive layer n4 also includes a drain pattern n42 spaced apart from the source pattern n41. Among them, at least a portion of the source pattern n41 can be used as the source of the switching transistor T, and at least a portion of the drain pattern n42 can be used as the drain of the switching transistor T. The common capacitor signal line 106 can be an integrated structure with the second capacitor plate Cst2.

[0174] Optionally, the material of the second conductive layer n4 may be at least one of copper (Cu), aluminum (Al), molybdenum (Mo), molybdenum-niobium alloy and molybdenum-nickel-titanium alloy. The thickness of the second conductive layer n4 ranges from 200 nm to 500 nm.

[0175] Step S1024b: forming a first sub-insulating layer of the second insulating layer on a side of the second conductive layer away from the base substrate.

[0176] refer to Fig.33 and Fig.34 , a layer of organic material film is coated on the side of the second conductive layer n4 away from the base substrate 101 by slit or hanging coating. The thickness of the organic material film ranges from 2μm (micrometer) to 6μm, for example, 3μm. After the organic material film is formed, the organic material film is pre-cured under certain temperature conditions (the temperature range can be 100°C to 110°C) (the pre-curing time can be 60 seconds). After the organic material film is developed, the organic material film is subjected to an annealing and curing process, and the temperature range can be 200°C to 250°C, for example, 230°C. The orthographic projection of the first sub-insulating layer n51 prepared by the organic material film on the base substrate 101 and the orthographic projection of the storage capacitor Cst on the base substrate 101 do not overlap, and the orthographic projection of the first sub-insulating layer n51 on the base substrate 101 covers the orthographic projection of the switch transistor T in the pixel circuit 1021 on the base substrate 101. That is, the portion of the first sub-insulating layer n51 located above the second capacitor plate Cst2 can be developed away, thereby exposing the second capacitor plate Cst2. Fig.33 In the figure, a filling pattern is used to indicate the area where the first sub-insulating layer n51 is dug out, and other areas not filled with patterns are used to indicate the area where the first insulating layer n51 has solid material.

[0177] By providing the first sub-insulating layer n51 above the switch transistor T, the distance between the switch transistor T and the upper device can be increased, thereby reducing the large parasitic capacitance generated between the switch transistor T and the upper device, thereby ensuring the reliability of the switch transistor T. In addition, by removing the first sub-insulating layer above the storage capacitor Cst, it is possible to avoid the distance between the third capacitor plate Cst3 and the second capacitor plate Cst2 being too large due to the presence of the first sub-insulating layer n51, thereby avoiding the capacitance of the storage capacitor Cst being affected by the presence of the first sub-insulating layer n51, thereby ensuring the reliability of the storage capacitor Cst.

[0178] Step S1025b: forming a second sub-insulating layer of the second insulating layer on a side of the first sub-insulating layer away from the base substrate.

[0179] The second sub-insulating film is obtained by coating the first sub-insulating layer n51 on the side away from the substrate 101 by chemical vapor deposition. The material of the second sub-insulating film can be an inorganic non-metallic material, for example, the material of the second sub-insulating film can include one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide) and SiOxNy (silicon oxynitride). The thickness of the second sub-insulating film can range from 200nm to 400nm.

[0180] refer to Fig.35 and Fig.36 , the second sub-insulating film is processed by photolithography to obtain the second sub-insulating layer n52. The second sub-insulating layer n52 includes a second via K2, and the second via K2 can expose a portion of the drain pattern n42 so that the third capacitor plate Cst3 formed subsequently is connected to the drain pattern n42. Optionally, the orthographic projection of the second via K2 on the base substrate 101 overlaps with the orthographic projection of the first via K1 on the base substrate 101.

[0181] Step S1026b: forming a third conductive layer on a side of the second insulating layer away from the base substrate.

[0182] refer to Fig.37 and Fig.38 , a first sub-conductive layer n61 is formed on a side of the second insulating layer n5 away from the base substrate 101 by magnetron sputtering. The first sub-conductive layer n61 includes a plurality of first capacitor patterns Cst3-1, and the first capacitor patterns Cst3-1 may be block patterns. The orthographic projection of the first capacitor pattern Cst3-1 on the base substrate 101 covers the orthographic projection of the switch transistor T and the second capacitor plate Cst2 on the base substrate 101.

[0183] Among them, the material of the first sub-conductive layer n61 may include at least one of copper (Cu), aluminum (Al), molybdenum (Mo), molybdenum-niobium alloy, and molybdenum-nickel-titanium alloy. For example, the material of the first sub-conductive layer n61 may be molybdenum, and the thickness of the first sub-conductive layer n61 ranges from 100nm to 200nm. Since the material of the first capacitor pattern Cst3-1 includes metal or metal alloy, the first sub-conductive layer n61 can play a certain light-shielding role, so that the first capacitor pattern Cst3-1 covers the switch transistor T, which can avoid the problem of large light-induced leakage current of the switch transistor T due to the influence of light.

[0184] Optionally, the first capacitor pattern Cst3-1 can cover the second via K2 in the second sub-insulating layer n52 of the second insulating layer n5, thereby avoiding the corrosion of the drain pattern n42 under the second via K2 caused by the penetration of etching solution when forming the first capacitor pattern Cst3-1, thereby ensuring the reliability of the driving backplane.

[0185] refer to Figure 4 and Figure 5 , a second sub-conductive layer n62 is formed on the side of the first sub-conductive layer n61 away from the base substrate 101 by using coating and photolithography processes. The material of the second sub-conductive layer n62 can be a transparent material, and the second sub-conductive layer n62 includes a plurality of second capacitor patterns Cst3-2, and the second capacitor pattern Cst3-2 can be a block pattern. Optionally, the orthographic projection of the second capacitor pattern Cst3-2 on the base substrate 101 covers the orthographic projection of the first capacitor pattern Cst3-1 on the base substrate 101, so as to prevent the first capacitor pattern Cst3-1 from being corroded. Optionally, the size of the orthographic projection of the second capacitor pattern Cst3-2 on the base substrate 101 can be comparable to (e.g., approximately the same as) the size of the pixel of the display device.

[0186] Optionally, the material of the second sub-conductive layer n62 includes metal oxide, that is, the material of the second capacitor pattern Cst3-2 included in the second sub-conductive layer n62 also includes metal oxide. The second capacitor pattern Cst3-2 covers the first capacitor pattern Cst3-1 to prevent the first capacitor pattern Cst3-1 from being corroded. Optionally, the thickness of the second sub-conductive layer n62 can range from 20nm to 60nm. For example, the material of the second sub-conductive layer n62 can be indium tin oxide (ITO), and the thickness of the second sub-conductive layer n62 can be 40nm.

[0187] In summary, the embodiment of the present application provides a method for preparing a driving backplane, and the driving backplane prepared by the method includes a substrate substrate and a pixel driving layer located on one side of the substrate substrate. The pixel driving layer includes a plurality of pixel circuits, and the storage capacitor in the pixel circuit includes a first capacitor plate, a second capacitor plate and a third capacitor plate. Since the storage capacitor includes three capacitor plates, the storage capacitor is a double-layer capacitor, which can increase the capacitance of the storage capacitor, ensure that the storage capacitor can keep the charged voltage until the next time the screen is updated, and ensure the reliability of the driving backplane. In addition, a target protection pattern is set on the side of the second capacitor plate of the storage capacitor close to the first insulating layer, so that the adhesion of the second capacitor plate caused by the poor surface flatness of the first insulating layer can be avoided, thereby avoiding the second capacitor plate from falling off, and ensuring the yield of the driving backplane.

[0188] The embodiment of the present application also provides a display device, which includes a display component and a driving backplane as provided in the above embodiment. The display component can be located on one side of the driving backplane, and the driving backplane can be used to drive the display component to display an image.

[0189] Optionally, the display component may be an electronic paper film, and the corresponding display device may be an electronic paper display device. Alternatively, the display component may also be other types of display components, such as a liquid crystal display panel or an organic light emitting diode display panel, etc. The embodiment of the present application does not specifically limit the display component.

[0190] Optionally, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

[0191] Since the display device can have substantially the same technical effects as the driving backplane described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0192] The terms used in the embodiments of this application are only used to explain the embodiments of this application, and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should be the common meanings understood by people with general skills in the field to which this application belongs.

[0193] The implementation method section of the present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0194] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0195] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0196] In the drawings, the size, thickness or region of one or more components may be exaggerated for clarity. In addition, the drawings schematically show ideal examples, and one embodiment of the present application is not limited to the shapes or numerical values ​​shown in the drawings.

[0197] The ordinal numbers such as "first", "second", "third" and the like in this specification are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in this application means two or more.

[0198] The thickness range of the film layer in this specification is A to B, which is used to indicate that the thickness is between A and B, and includes the two endpoint values ​​of A and B.

[0199] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the present application. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the circumstances.

[0200] In this specification, a transistor refers to an element including at least three terminals: a gate electrode (gate), a drain electrode (drain electrode terminal, drain region or drain), and a source electrode (source electrode terminal, source region or source). The transistor has a channel region between the drain electrode and the source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0201] In this specification, the first electrode of a transistor may be a drain electrode, and the second electrode of a transistor may be a source electrode, or the first electrode of a transistor may be a source electrode, and the second electrode of a transistor may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0202] In this specification, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this application can be understood according to the circumstances.

[0203] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0204] In the present application, "thickness" and "height" refer to the vertical distance between the surface of the film layer away from the substrate and the surface of the film layer close to the substrate.

[0205] The term "about" in this application refers to a numerical value that is not strictly limited to a limit and allows for process and measurement errors.

[0206] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A driving backplane, characterized in that: The driving backplane comprises: A base substrate, the base substrate comprising a display area; and a pixel driving layer located on one side of the base substrate, the pixel driving layer comprising a plurality of pixel circuits located in the display area and arranged in an array, the pixel circuits comprising a storage capacitor, the storage capacitor comprising: a first capacitor plate, a second capacitor plate and a third capacitor plate; Among them, the pixel driving layer includes a first conductive layer, a first insulating layer, a target protection layer, a second conductive layer, a second insulating layer and a third conductive layer, the first conductive layer includes the first capacitor plate, the target protection layer includes a target protection pattern, the orthographic projection of the target protection pattern on the substrate and the orthographic projection of the first capacitor plate on the substrate overlap, the second conductive layer includes the second capacitor plate, the orthographic projection of the second capacitor plate on the substrate is located within the orthographic projection of the target protection pattern on the substrate, the third conductive layer includes the third capacitor plate, the orthographic projection of the third capacitor plate on the substrate overlaps with the orthographic projections of the first capacitor plate and the second capacitor plate on the substrate, and the third capacitor plate is connected to the first capacitor plate through vias in the second insulating layer and the first insulating layer.

2. The driving backplane according to claim 1, characterized in that: The pixel circuit further includes a switch transistor, the switch transistor includes a gate, a source and a drain, the drain is connected to the first capacitor plate and the third capacitor plate; Among them, the first conductive layer also includes a gate pattern, the gate pattern and the first capacitor plate are spaced apart, at least a portion of the gate pattern serves as the gate of the switching transistor, the target protection layer is an active layer, the active layer also includes an active pattern, the active pattern and the target protection pattern are spaced apart, the orthographic projection of the active pattern on the base substrate and the orthographic projection of the gate pattern on the base substrate overlap, the second conductive layer also includes a source pattern and a drain pattern spaced apart, at least a portion of the source pattern serves as the source of the switching transistor, at least a portion of the drain pattern serves as the drain of the switching transistor, the source pattern and the drain pattern are both spaced apart from the second capacitor plate, and the source pattern and the drain pattern are both connected to the active pattern.

3. The driving backplane according to claim 2, characterized in that: The first insulating layer has a first via hole exposing the first capacitor plate, the drain pattern is also located in the first via hole, and the drain pattern is connected to the first capacitor plate through the first via hole; The second insulating layer has a second via hole exposing the drain pattern, the third capacitor plate is also located in the second via hole, and the third capacitor plate is connected to the drain pattern through the second via hole.

4. The driving backplane according to claim 3, characterized in that: An orthographic projection of the second via hole on the base substrate overlaps with an orthographic projection of the first via hole on the base substrate.

5. The driving backplane according to any one of claims 2 to 4, characterized in that: The active layer comprises a first sublayer and a second sublayer stacked together, the material of the first sublayer comprises a main material, the material of the second sublayer comprises a main material and a doping material doped in the main material, the main material comprises amorphous silicon, and the doping material comprises boron or phosphorus; The first sublayer and the second sublayer both include the active pattern, and at least one of the first sublayer and the second sublayer includes the target protection pattern; The active pattern of the second sub-layer includes a first sub-active pattern and a second sub-active pattern which are arranged at intervals, and the orthographic projection of the first sub-active pattern on the base substrate and the orthographic projection of the second sub-active pattern on the base substrate both overlap with the orthographic projection of the active pattern of the first sub-layer on the base substrate; The source pattern is connected to the first sub-active pattern, and the drain pattern is connected to the second sub-active pattern.

6. The driving backplane according to claim 5, characterized in that: The active pattern and the target protection pattern included in the first sub-layer form an integrated structure and entirely cover the base substrate.

7. The driving backplane according to any one of claims 2 to 4, characterized in that: The material of the active layer includes metal oxide.

8. The driving backplane according to any one of claims 2 to 4, characterized in that: The base substrate further includes a peripheral area surrounding the display area, wherein the peripheral area includes a target area located on one side of the display area; the driving backplane further includes: a plurality of gate signal lines, the plurality of gate signal lines are arranged along a first direction and extend along a second direction, each of the gate signal lines comprises a gate signal line body and a plurality of gate patterns connected to the gate signal line body and arranged at intervals along the second direction, at least a portion of each of the gate patterns serves as a gate of a switch transistor of one of the plurality of pixel circuits arranged along the second direction, the second direction intersecting the first direction; one of the two ends of the gate signal line in the second direction is located in the target area; a plurality of data connection lines and a plurality of data signal lines corresponding to the plurality of data connection lines, the plurality of data connection lines are arranged along the first direction and extend along the second direction, the plurality of data signal lines are arranged along the second direction and extend along the first direction, each of the data signal lines is connected to a corresponding one of the data connection lines, and each of the data signal lines is connected to source electrodes of switch transistors in a plurality of pixel circuits arranged along the first direction; one of the two ends of the data connection line in the second direction is located in the target area; A driving chip is located in the target area, and the end of the gate signal line located in the target area and the end of the data connection line located in the target area are both connected to the driving chip, and the driving chip is used to provide a gate signal for the gate signal line and to provide a data signal for the data connection line.

9. The driving backplane according to claim 8, characterized in that: The plurality of gate signal lines and the plurality of data connection lines are all located in the first conductive layer; The plurality of data signal lines are located in the second conductive layer, and the data signal lines include a data signal line body and a plurality of source patterns connected to the data signal line body and spaced apart along the first direction; Wherein, the data signal line is connected to the corresponding data connection line at least through a via hole in the first insulating layer.

10. The driving backplane according to any one of claims 1 to 4, characterized in that: The second insulating layer includes a first sub-insulating layer and a second sub-insulating layer stacked; The orthographic projection of the first sub-insulating layer on the base substrate and the orthographic projection of the storage capacitor on the base substrate do not overlap, and the orthographic projection of the first sub-insulating layer on the base substrate covers the orthographic projection of the switch transistor in the pixel circuit on the base substrate; The orthographic projection of the second sub-insulating layer on the base substrate overlaps with the orthographic projections of the storage capacitor and the switch transistor on the base substrate; The material of the first sub-insulating layer is an organic material, and the material of the second sub-insulating layer is an inorganic material.

11. The driving backplane according to any one of claims 1 to 4, characterized in that: The second conductive layer further includes a plurality of common capacitor signal lines arranged along a second direction and extending along the first direction, wherein the second direction intersects the first direction; Each of the common capacitance signal lines is an integrated structure with the second capacitance plates of the storage capacitors of the multiple pixel circuits arranged along the first direction, and provides a common capacitance signal for the second capacitance plates of the storage capacitors of the multiple pixel circuits arranged along the first direction.

12. The driving backplane according to any one of claims 1 to 4, characterized in that: The third conductive layer includes a first sub-conductive layer and a second sub-conductive layer; the material of the first sub-conductive layer includes metal or metal alloy, and the material of the second sub-conductive layer includes metal oxide; The first sub-conductive layer includes multiple first capacitor patterns, the second sub-conductive layer includes multiple second capacitor patterns corresponding to the multiple first capacitor patterns, the orthographic projections of the second capacitor patterns on the base substrate cover the orthographic projections of the corresponding first capacitor patterns on the base substrate, and the third capacitor plate includes the first capacitor patterns and the corresponding second capacitor patterns.

13. A method for preparing a driving backplane, characterized in that: The method comprises: providing a substrate substrate, the substrate substrate comprising a display area; forming a pixel driving layer on one side of the base substrate; Wherein, the pixel driving layer includes a plurality of pixel circuits located in the display area and arranged in an array, the pixel circuit includes a storage capacitor, and the storage capacitor includes: a first capacitor plate, a second capacitor plate and a third capacitor plate; The pixel driving layer includes a first conductive layer, a first insulating layer, a target protection layer, a second conductive layer, a second insulating layer and a third conductive layer, the first conductive layer includes the first capacitor plate, the target protection layer includes a target protection pattern, the orthographic projection of the target protection pattern on the substrate substrate and the orthographic projection of the first capacitor plate on the substrate substrate overlap, the second conductive layer includes the second capacitor plate, the orthographic projection of the second capacitor plate on the substrate substrate is located within the orthographic projection of the target protection pattern on the substrate substrate, the third conductive layer includes the third capacitor plate, the orthographic projection of the third capacitor plate on the substrate substrate overlaps with the orthographic projections of the first capacitor plate and the second capacitor plate on the substrate substrate, and the third capacitor plate is connected to the first capacitor plate through vias in the second insulating layer and the first insulating layer.

14. A display device, characterized in that: The display device comprises: a display component and a driving backplane according to any one of claims 1 to 12; The display component is located on one side of the driving backplane, and the driving backplane is used to drive the display component to display an image.

15. The display device according to claim 14, characterized in that: The display component is an electronic paper film.

Images