Compensation circuit

Abstract

The application discloses a compensation circuit, which comprises a first current source, a second current source and a third current source, each of which is connected with a power voltage; a first voltage dividing unit connected between the second end of the second current source and a PGND pin and outputting a sampling voltage at a first node; a second voltage dividing unit connected between the second end of the first current source and the PGND pin and outputting an induced voltage at a second node, the second node being connected with a CS pin; a comparison unit connected with the first voltage dividing unit and the second voltage dividing unit, the comparison unit comprising a comparator, the first input end of the comparator being connected with the second end of the first current source, the second input end being connected with the second end of the second current source, and the output end being connected with a GATE pin; and a DC cancellation unit connected with the second end of the third current source, the PGND pin and the second node. The application can cancel the DC at the CS pin, ensure the accuracy of measuring the voltage at the CS pin and accurately measure the current flowing through the first inductor.

Description

Technical Field

[0001] The present invention belongs to the technical field of power supply circuits, and in particular relates to a compensation circuit. Background Art

[0002] like Figure 1 The figure shows a circuit diagram of a conventional DCDC control circuit, including a first MOS transistor M1, a first inductor L1, and a sensing resistor R1. The first end of the first inductor L1 is connected to the BIAS pin of the DCDC controller, the control end of the first MOS transistor M1 is connected to the GATE pin of the DCDC controller, the first end is connected to the CS pin of the DCDC controller and the first end of the sensing resistor R1, respectively, and the second end is connected to the second end of the first inductor L1. The second end of the sensing resistor R1 is connected to the PGND pin of the DCDC controller and a reference potential, respectively. In the DCDC control circuit, the peak value of the maximum current in the first inductor L needs to be determined through the sensing resistor R1 and applied to other parts of the DCDC control circuit. Therefore, it is necessary to accurately measure the voltage V on the CS pin of the DCDC controller. CS .

[0003] Although the compensation circuit in the prior art can obtain the voltage V CS However, there is a DC current flowing out of the CS pin because the DCDC control circuit needs to control the first MOS tube M1 to be turned on, which causes the induced voltage V CS The absolute value of the sampling calculation is too large, which leads to the difference between the current obtained by sampling calculation and the actual current flowing through the first inductor I L1 Relatively large.

[0004] The information disclosed in this background technology section is only intended to enhance understanding of the overall background of the invention and should not be regarded as an admission or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the Invention

[0005] The object of the present invention is to provide a compensation circuit, which can solve the technical problem in the prior art that the measured current of the first inductor is larger than the actual current flowing through the first inductor due to DC interference.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides a compensation circuit, which is applied to a DCDC control circuit. The DCDC control circuit includes a first inductor, a first MOS transistor, and a sensing resistor. The first end of the first inductor is connected to the BIAS pin, the control end of the first MOS transistor is connected to the GATE pin, and the second end is connected to the second end of the first inductor. The first end of the sensing resistor is connected to the CS pin and the second end of the first MOS transistor, respectively, and the second end of the sensing resistor is connected to the PGND pin. The compensation circuit includes:

[0007] a first current source having a first terminal connected to a power supply voltage;

[0008] a second current source having a first terminal connected to a power supply voltage;

[0009] a third current source having a first terminal connected to the power supply voltage;

[0010] A first voltage dividing unit is connected between the second end of the second current source and the PGND pin, and outputs a sampling voltage at a first node;

[0011] A second voltage dividing unit is connected between the second end of the first current source and the PGND pin, and outputs a sensed voltage at a second node, the second node being connected to the CS pin;

[0012] a comparison unit connected to the first voltage divider unit and the second voltage divider unit, respectively, the comparison unit comprising a comparator, a first input terminal of the comparator being connected to the second terminal of the first current source, a second input terminal being connected to the second terminal of the second current source, and an output terminal being connected to the GATE pin;

[0013] The DC offset unit is respectively connected to the second end of the third current source, the PGND pin and the second node or the second end of the second current source, and is used to offset the DC current flowing out of the second current source from the second node.

[0014] In one or more embodiments of the present invention, the DC offset unit includes a second MOS transistor and a third MOS transistor, wherein:

[0015] A first end of the second MOS transistor is connected to the PGND pin, and a second end is connected to the second node;

[0016] The control end of the third MOS tube is connected to the control end of the second MOS tube and the second end of the third MOS tube respectively, the first end of the third MOS tube is connected to the PGND pin, and the second end of the third MOS tube is connected to the second end of the third current source.

[0017] In one or more embodiments of the present invention, the DC offset unit includes a second MOS transistor, a third MOS transistor and a fourth MOS transistor, wherein:

[0018] The first end of the second MOS tube is connected with the PGND pin, and the second end is connected with the second end of the second current source;

[0019] The control end of the third MOS tube is connected with the control end of the second MOS tube and the second end of the third MOS tube respectively, the first end of the third MOS tube is connected with the PGND pin, and the second end of the third MOS tube is connected with the second end of the third current source;

[0020] The control end of the fourth MOS tube is connected with the control end of the second MOS tube, the first end of the fourth MOS tube is connected with the PGND pin, and the second end of the fourth MOS tube is connected with the second end of the first current source.

[0021] In one or more embodiments of the present application, the compensation circuit further comprises a sampling unit connected between the sampling voltage and the power supply voltage.

[0022] In one or more embodiments of the present application, the first voltage dividing unit comprises a fifth resistor and a seventh resistor, wherein,

[0023] The first end of the fifth resistor is connected with the second end of the second transistor,

[0024] The first end of the seventh resistor is connected with the second end of the fifth resistor, and the second end of the seventh resistor is connected with the second node.

[0025] In one or more embodiments of the present application, the second voltage dividing unit comprises a fourth resistor and a sixth resistor, wherein,

[0026] The first end of the fourth resistor is connected with the second end of the first transistor, and the second end of the fourth resistor is connected with the first node;

[0027] The first end of the sixth resistor is connected with the first node, and the second end is connected with the PGND pin.

[0028] In one or more embodiments of the present application, the first voltage dividing unit comprises a fifth resistor, a fifth MOS tube and a seventh resistor, wherein,

[0029] The first end of the fifth resistor is connected with the second end of the second current source;

[0030] The control end of the fifth MOS tube is connected with the second end of the fifth MOS tube, the second end is connected with the second end of the fifth resistor, and the first end of the fifth MOS tube is connected with the second node;

[0031] The first end of the seventh resistor is connected with the second node, and the second end is connected with the PGND pin.

[0032] In one or more embodiments of the present invention, the second voltage dividing unit includes a fourth resistor, a sixth MOS transistor and a sixth resistor, wherein:

[0033] The first end of the fourth resistor is connected to the second end of the first current source;

[0034] The control end of the sixth MOS transistor is connected to the second end of the sixth MOS transistor, the second end is connected to the second end of the fourth resistor, and the first end of the sixth MOS transistor is connected to the node C;

[0035] A first end of the sixth resistor is connected to the first node, and a second end thereof is connected to the PGND pin.

[0036] In one or more embodiments of the present invention, the comparison unit further includes a first transistor, a second transistor, a second resistor, and a third resistor, wherein:

[0037] The control end of the first transistor is connected to the fourth node, the first end of the first transistor is connected to the first end of the first current source, and the second end of the first transistor is connected to the first end of the fourth resistor;

[0038] The control terminal of the second transistor is connected to the fourth node, the first terminal of the second transistor is connected to the second terminal of the second current source, and the second terminal of the second transistor is connected to the first terminal of the fifth resistor;

[0039] The second resistor is connected between the second end of the first current source and the third node;

[0040] The third resistor is connected between the second end of the second current source and the third node;

[0041] The third node is connected to the fourth node.

[0042] Another aspect of the present invention provides a compensation circuit applied to a DCDC control circuit. The DCDC control circuit includes a first inductor, a first MOS transistor, and a sensing resistor. The first end of the first inductor is connected to the BIAS pin, the control end of the first MOS transistor is connected to the GATE pin, and the second end is connected to the second end of the first inductor. The first end of the sensing resistor is connected to the CS pin and the second end of the first MOS transistor, respectively, and the second end of the sensing resistor is connected to the PGND pin. The compensation circuit includes:

[0043] a first current source having a first terminal connected to a power supply voltage;

[0044] a second current source having a first terminal connected to a power supply voltage;

[0045] a DC offset unit connected to the second end of the first current source, the second end of the second current source, the CS pin, and the PGND pin, respectively, and outputting a sensed voltage at the CS pin and a sampled voltage at the first node;

[0046] A comparison unit is connected to the DC offset unit, and the comparison unit includes a comparator, a first input end of the comparator is connected to the second end of the first current source, a second input end of the comparator is connected to the second end of the second current source, and an output end is connected to the GATE pin.

[0047] In one or more embodiments of the present invention, the DC offset unit includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh MOS transistor and an eighth MOS transistor, wherein:

[0048] The first end of the fifth resistor is connected to the second end of the second transistor;

[0049] The control end of the seventh MOS transistor is connected to the pin CS, the second end is connected to the pin PGND, and the first end is connected to the second end of the fifth resistor;

[0050] The first end of the fourth resistor is connected to the second end of the first transistor;

[0051] The control end of the eighth MOS transistor is connected to the first node, the second end is connected to the pin PGND, and the first end is connected to the second end of the fourth resistor;

[0052] A first end of the sixth resistor is connected to the first node, and a second end thereof is connected to the pin PGND.

[0053] In one or more embodiments of the present invention, the compensation circuit further includes a sampling unit connected between the sampling voltage and the power supply voltage.

[0054] In one or more embodiments of the present invention, the comparison unit further includes a first transistor, a second transistor, a second resistor, and a third resistor, wherein:

[0055] The control end of the first transistor is connected to the fourth node, the first end of the first transistor is connected to the first end of the first current source, and the second end of the first transistor is connected to the first end of the fourth resistor;

[0056] The control terminal of the second transistor is connected to the fourth node, the first terminal of the second transistor is connected to the second terminal of the second current source, and the second terminal of the second transistor is connected to the first terminal of the fifth resistor;

[0057] The second resistor is connected between the second end of the first current source and the third node;

[0058] The third resistor is connected between the second end of the second current source and the third node;

[0059] The third node is connected to the fourth node.

[0060] Compared with the prior art, the compensation circuit of the present invention can offset the DC current flowing out of the pin CS through the DC offset unit, so that the measured voltage of the pin CS is equal to the voltage on the sensing resistor, thereby accurately measuring the current flowing through the first inductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments described in the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0062] Figure 1 It is a circuit diagram of a DCDC control circuit in the prior art;

[0063] Figure 2 A circuit diagram of a compensation circuit in the prior art;

[0064] Figure 3 is a circuit diagram of a compensation circuit in Embodiment 1 of the present invention;

[0065] Figure 4 is a circuit diagram of a compensation circuit in a second embodiment of the present invention;

[0066] Figure 5 This is a circuit diagram of the compensation circuit in Example 3 of the present invention. DETAILED DESCRIPTION

[0067] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0068] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have a parasitic first inductance or parasitic capacitance. An indirect connection may also include a connection through other active or passive devices, such as switches, follower circuits, or other circuits or components, to achieve the same or similar functional objectives. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0069] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals designate like parts throughout, and wherein exemplary embodiments that may be implemented are shown by way of example. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be construed in a limiting sense.

[0070] The various operations in the specification may be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0071] Various components and devices may be referred to or shown herein in the singular, but this is merely for ease of discussion, and any element referred to in the singular may include a plurality of such elements in accordance with the teachings herein.

[0072] The specification uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," which can each refer to one or more of the same or different embodiments. In addition, the terms "including," "comprising," "having," etc. used with respect to the embodiments of the present disclosure are synonymous.

[0073] like Figure 2 The figure shows a circuit diagram of a compensation circuit in the prior art. Although the compensation circuit can obtain the induced voltage V CS However, there is a DC current flowing out of the second current source I2 at the pin CS, which causes the induced voltage V CS The absolute value of the current flowing through the first inductor I L1 Too big.

[0074] In view of the above problems, the present invention discloses a compensation circuit, which is applied to Figure 1 The DCDC control circuit shown in FIG. 1 includes a first MOS transistor M1, a first inductor L1, and a sensing resistor R1. The first end of the first inductor L1 is connected to the BIAS pin of the DCDC controller, the control end of the first MOS transistor M1 is connected to the GATE pin of the DCDC controller, the first end of the first MOS transistor M1 is connected to the CS pin of the DCDC controller and the first end of the sensing resistor R1, respectively. The second end of the first MOS transistor M1 is connected to the second end of the first inductor L1, and the second end of the sensing resistor R1 is connected to the PGND pin of the DCDC controller and the reference potential, respectively. The compensation circuit in the present invention includes:

[0075] a first current source having a first terminal connected to a power supply voltage;

[0076] a second current source having a first terminal connected to a power supply voltage;

[0077] a third current source having a first terminal connected to the power supply voltage;

[0078] A first voltage dividing unit is connected between the second end of the second current source and the PGND pin, and outputs a sampling voltage at a first node;

[0079] A second voltage dividing unit is connected between the second end of the first current source and the PGND pin, and outputs a sensed voltage at a second node, wherein the second node is connected to the CS pin;

[0080] a comparison unit connected to the first voltage divider unit and the second voltage divider unit respectively, the comparison unit comprising a comparator, a first input terminal of the comparator being connected to the second terminal of the first current source, a second input terminal being connected to the second terminal of the second current source, and an output terminal being connected to the GATE pin;

[0081] The DC offset unit is respectively connected to the second end of the third current source, the PGND pin and the second node or the second end of the second current source, and is used to offset the DC current flowing out of the second node from the second current source.

[0082] The comparison unit is connected to the GATE pin through the output terminal to control the on or off of the first MOS tube M1; the DC offset unit offsets the second current originating from the DC current flowing out of the second node, so that the voltage at the CS pin is equal to the voltage drop of the sensing resistor, so as to ensure that the inductor current at the measurement point on the first inductor L1 is equal to the current actually flowing through the first inductor L1. When the current I L1 When the signal peak value is reached, the comparison unit turns off the first MOS tube, so that the current I L1Applied to other parts of the DCDC control circuit. According to the different circuit structures, the present invention elaborates on the DC offset unit through the first and second embodiments, and elaborates on another implementation of the three pairs of compensation circuits.

[0083] Example 1

[0084] like Figure 3 As shown, in this embodiment, the compensation circuit includes:

[0085] A first current source I1, a first terminal of which is connected to a power supply voltage VCC;

[0086] A second current source I2, a first terminal of which is connected to a power supply voltage VCC;

[0087] A third current source I3, a first end of which is connected to the power supply voltage VCC;

[0088] The first voltage dividing unit 20 is connected between the second terminal of the second current source I2 and the PGND pin, and outputs a sampling voltage V at the first node A. A ;

[0089] The second voltage divider 30 is connected between the second terminal of the first current source I1 and the PGND pin, and outputs the induced voltage V at the second node B. CS , the second node B is connected to the CS pin;

[0090] A comparison unit 10 is connected to the first voltage divider unit 20 and the second voltage divider unit 30 respectively. The comparison unit 10 includes a comparator U1. The first input terminal of the comparator U1 is connected to the second terminal of the first current source I1, the second input terminal is connected to the second terminal of the second current source I2, and the output terminal is connected to the GATE pin.

[0091] The DC offset unit 40 is connected to the second end of the third current source I3 , the PGND pin, and the second node B, respectively, and is configured to offset the DC current flowing out of the second current source I2 at the second node B.

[0092] The DC offset unit 40 in this embodiment includes a second MOS transistor M2 and a third MOS transistor M3, wherein:

[0093] A first end of the second MOS transistor M2 is connected to the PGND pin, and a second end is connected to the second node B;

[0094] The control end of the third MOS transistor M3 is connected to the control end of the second MOS transistor M2 and the second end of the third MOS transistor M3 respectively. The first end of the third MOS transistor M3 is connected to the PGND pin. The second end of the third MOS transistor M3 is connected to the second end of the third current source I3.

[0095] Among them, because the first control terminal of the third MOS transistor M3 is respectively connected to the second terminal and the control terminal of the second MOS transistor M2 and forms a current mirror, the size of the second MOS transistor M2 is equal to the size of the third MOS transistor M3. Therefore, after the second MOS transistor M2 is turned on, the current flowing through the second MOS transistor M2 is equal to the third current source I3. Moreover, because the second current source I2 connected to the first terminal of the second MOS transistor M2 and the third current source I3 connected to the first terminal of the third MOS transistor M3 satisfy I2=I3, the CS pin connected to the second node B does not receive any current from the second current source I2, and therefore no DC current flows out of the CS pin.

[0096] Preferably, the first voltage dividing unit 20 in this embodiment includes a fifth resistor R5 and a seventh resistor R7, wherein:

[0097] The first end of the fifth resistor R5 is connected to the second end of the second transistor Q2.

[0098] A first end of the seventh resistor R7 is connected to the second end of the fifth resistor R5 , and a second end of the seventh resistor R7 is connected to the second node B.

[0099] Preferably, the second voltage dividing unit 30 in this embodiment includes a fourth resistor R4 and a sixth resistor R6, wherein:

[0100] A first end of the fourth resistor R4 is connected to the second end of the first transistor Q1, and a second end of the fourth resistor R4 is connected to the first node A;

[0101] A first end of the sixth resistor R6 is connected to the first node A, and a second end thereof is connected to the pin PGND.

[0102] Optionally, the compensation circuit in this embodiment further includes a sampling unit 50, which is connected to the sampling voltage V A and the power supply voltage VCC.

[0103] Since the current value of the first current source I1 is equal to the current value of the second current source I2, the two branches including the first current source I1 and the second current source I2 satisfy:

[0104] I1·(R4+R6)+I CON R6=I2·(R5+R7)+V CS , where I CON The sampling current is the current of the first inductor L1;

[0105] Since the resistances of the fourth resistor R4 and the fifth resistor R5 are equal, and the resistances of the sixth resistor R6 and the seventh resistor R7 are equal, the sampling voltage V at the first node A is A The induced voltage V at the second node B CS are equal, so the induced voltage VCS Satisfaction: V CS =V A =I CON R6, at this time I CON R6 is the voltage at the CS pin, so the induced current in the first inductor L1 is:

[0106]

[0107] The comparison unit 10 in this embodiment includes a first transistor Q1, a second transistor Q2, a second resistor R2, and a third resistor R3, wherein:

[0108] A control end of the first transistor Q1 is connected to the fourth node D, a first end of the first transistor Q1 is connected to the first end of the first current source I1, and a second end of the first transistor Q1 is connected to the first end of the fourth resistor R4;

[0109] A control end of the second transistor Q2 is connected to the fourth node D, a first end of the second transistor Q2 is connected to the second end of the second current source I2, and a second end of the second transistor Q2 is connected to the first end of the fifth resistor R5;

[0110] The second resistor R2 is connected between the second end of the first current source I1 and the third node C;

[0111] The third resistor R3 is connected between the second end of the second current source I2 and the third node C;

[0112] The third node C is connected to the fourth node D.

[0113] In this embodiment, the first MOS transistor M1 , the second MOS transistor M2 and the third MOS transistor M3 are all N-channel transistors, wherein the first end of the transistor is a source, the second end is a drain, and the control end is a gate.

[0114] Example 2

[0115] like Figure 4 As shown, in this embodiment, the compensation circuit includes:

[0116] A first current source I1, a first terminal of which is connected to a power supply voltage VCC;

[0117] A second current source I2, a first terminal of which is connected to a power supply voltage VCC;

[0118] A third current source I3, a first end of which is connected to the power supply voltage VCC;

[0119] The first voltage dividing unit 20 is connected between the second terminal of the second current source I2 and the PGND pin, and outputs a sampling voltage V at the first node A. A ;

[0120] The second voltage divider 30 is connected between the second terminal of the first current source I1 and the PGND pin, and outputs the induced voltage V at the second node B. CS , the second node B is connected to the CS pin;

[0121] A comparison unit 10 is connected to the first voltage divider unit 20 and the second voltage divider unit 30 respectively. The comparison unit 10 includes a comparator U1. The first input terminal of the comparator U1 is connected to the second terminal of the first current source I1, the second input terminal is connected to the second terminal of the second current source I2, and the output terminal is connected to the GATE pin.

[0122] The DC offset unit 40 is connected to the second end of the third current source I3 , the PGND pin, and the second end of the second current source I2 , and is configured to offset the DC current flowing out of the second current source I2 at the second node B.

[0123] The DC offset unit 40 in this embodiment includes a second MOS transistor M2, a third MOS transistor M3 and a fourth MOS transistor M4, wherein:

[0124] A first end of the second MOS transistor M2 is connected to the PGND pin, and a second end is connected to the second end of the second current source I2;

[0125] The control end of the third MOS transistor M3 is connected to the control end of the second MOS transistor M2 and the second end of the third MOS transistor M3 respectively. The first end of the third MOS transistor M3 is connected to the PGND pin, and the second end of the third MOS transistor M3 is connected to the second end of the third current source I3.

[0126] A control end of the fourth MOS transistor M4 is connected to the control end of the second MOS transistor M2 , a first end of the fourth MOS transistor M4 is connected to the PGND pin, and a second end of the fourth MOS transistor M4 is connected to the second end of the first current source I1 .

[0127] Among them, because the first end and the control end of the third MOS transistor M3 are respectively connected to the second end, the control end of the second MOS transistor M2, and the control end of the fourth MOS transistor M4 to form a current mirror, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 have the same size. Therefore, after the second MOS transistor M2 is turned on, the current flowing through it is equal to the third current source I3. In addition, the first current source I1 connected to the first end of the fourth MOS transistor M4, the second current source I2 connected to the first end of the second MOS transistor M2, and the third current source I3 connected to the first end of the third MOS transistor M3 satisfy I1=I2=I3. No direct current flows out of the second current source I2 at the second node B. Therefore, the CS pin connected to the second node B does not receive the current of the second current source I2, and therefore no direct current flows out of the CS pin.

[0128] Preferably, the first voltage dividing unit 20 in this embodiment includes a fifth resistor R5, a fifth MOS transistor M5 and a seventh resistor R7, wherein:

[0129] The first end of the fifth resistor R5 is connected to the second end of the second current source I2.

[0130] The control end of the fifth MOS transistor M5 is connected to the second end of the fifth MOS transistor M5 , the second end is connected to the second end of the fifth resistor R5 , and the first end of the fifth MOS transistor M5 is connected to the second node B;

[0131] A first end of the seventh resistor R7 is connected to the second node B, and a second end thereof is connected to the PGND pin.

[0132] Preferably, the second voltage dividing unit 30 in this embodiment includes a fourth resistor R4, a sixth MOS transistor M6 and a sixth resistor R6, wherein:

[0133] The first end of the fourth resistor R4 is connected to the second end of the first current source I1.

[0134] The control end of the sixth MOS transistor M6 is connected to the second end of the sixth MOS transistor M6 , the second end is connected to the second end of the fourth resistor R4 , and the first end of the sixth MOS transistor M6 is connected to the node C;

[0135] A first end of the sixth resistor R6 is connected to the first node A, and a second end thereof is connected to the PGND pin.

[0136] Optionally, the compensation circuit in this embodiment further includes a sampling unit 50 connected to the sampling voltage V A and the power supply voltage VCC.

[0137] The comparison unit 10 in this embodiment includes a first transistor Q1, a second transistor Q2, a second resistor R2, a third resistor R3 and a comparator U1, wherein:

[0138] A control end of the first transistor Q1 is connected to the fourth node D, a first end of the first transistor Q1 is connected to the first end of the first current source I1, and a second end of the first transistor Q1 is connected to the first end of the fourth resistor R4;

[0139] A control end of the second transistor Q2 is connected to the fourth node D, a first end of the second transistor Q2 is connected to the second end of the second current source I2, and a second end of the second transistor Q2 is connected to the first end of the fifth resistor R5;

[0140] The second resistor R2 is connected between the second end of the first current source I1 and the third node C;

[0141] The third resistor R3 is connected between the second end of the second current source I2 and the third node C;

[0142] The third node C is connected to the fourth node D;

[0143] The second input terminal of the comparator U1 is connected to the second terminal of the second current source I2 , the first input terminal is connected to the first current source I1 , and the output terminal is connected to the GATE pin.

[0144] In this embodiment, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the sixth MOS transistor M6 are all N-channel transistors, and the fourth MOS transistor M4 and the fifth MOS transistor M5 are P-channel transistors. The first end of the above transistors is the source, the second end is the drain, and the control end is the gate.

[0145] Compared with the first embodiment, the second end of the second MOS transistor M2 in the second embodiment is pulled up to a position close to the power supply voltage VCC. In the second embodiment, the following conditions are satisfied: V DS2 =I2·(R5+R7)+V GS5 , because V in Example 2 DS2 Therefore, the current mirror can work in the saturation region, and the third current source I3 and the current flowing through the second MOS tube M2 are proportionally replicated, so that the current flowing through the fourth MOS tube M4 and the current flowing through the second MOS tube are the same as the current of the third current source I3. Therefore, the two branches including the first current source I1 and the second current source I2 meet the following requirements: I1·R4+V GS6 +I CON R6=I2·R5+V CS +V GS5 , where I CON For sampling current, the fifth MOS tube M5 and the sixth MOS tube M6 have the same size, so any of the following conditions can be met in the second embodiment: V CS =V A =I CON R6, at this time I CON R6 is the voltage at the CS pin, so the induced current in the first inductor L1 is:

[0146]

[0147] Example 3

[0148] like Figure 5 As shown, the compensation circuit in this embodiment includes:

[0149] A first current source I1, a first terminal of which is connected to a power supply voltage VCC;

[0150] A second current source I2, a first terminal of which is connected to a power supply voltage VCC;

[0151] The DC offset unit 40 is connected to the second end of the first current source I1, the second end of the second current source I2, the CS pin and the PGND pin respectively, and outputs the induced voltage V at the CS pin. CS , outputs the sampling voltage V at the first node A A ;

[0152] The comparison unit 10 is connected to the DC offset unit 40. The comparison unit 10 includes a comparator U1. The first input terminal of the comparator U1 is connected to the second terminal of the first current source I1, the second input terminal of the comparator U1 is connected to the second terminal of the second current source I2, and the output terminal is connected to the GATE pin.

[0153] The DC offset unit 40 in this embodiment includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh MOS transistor M7 and an eighth MOS transistor M8, wherein:

[0154] A first end of the fifth resistor R5 is connected to the second end of the second transistor Q2;

[0155] The control end of the seventh MOS transistor M7 is connected to the pin CS, the second end is connected to the pin PGND, and the first end is connected to the second end of the fifth resistor R5;

[0156] A first end of the fourth resistor R4 is connected to the second end of the first transistor Q1;

[0157] The control end of the eighth MOS transistor M8 is connected to the first node A, the second end is connected to the pin PGND, and the first end is connected to the second end of the fourth resistor R4;

[0158] A first end of the sixth resistor R6 is connected to the first node A, and a second end thereof is connected to the pin PGND.

[0159] The seventh MOS transistor M7 blocks the path of the second current source I2, and the eighth MOS transistor M8 blocks the path of the first current source I1. The seventh MOS transistor M7 and the eighth MOS transistor M8 have the same size. Therefore, the second current source I2 including the seventh MOS transistor M7 and the first current source I1 including the eighth MOS transistor M8 satisfy the following conditions:

[0160] I1·R4+V GS8 +I CON R6=I2·R5+V CS +V GS7 , so in this embodiment the induced voltage V CS Any satisfaction: V CS =V A =I CON R6, at this time I CON R6 is the voltage at the CS pin, so the induced current in the first inductor L1 is:

[0161]

[0162] Optionally, the compensation circuit in this embodiment further includes a sampling unit 50, which is connected to the sampling voltage V A and the power supply voltage VCC.

[0163] The comparison unit 10 in this embodiment further includes a first transistor Q1, a second transistor Q2, a second resistor R2, and a third resistor R3, wherein:

[0164] A control end of the first transistor Q1 is connected to the fourth node D, a first end of the first transistor Q1 is connected to the first end of the first current source I1, and a second end of the first transistor Q1 is connected to the first end of the fourth resistor R4;

[0165] A control end of the second transistor Q2 is connected to the fourth node D, a first end of the second transistor Q2 is connected to the second end of the second current source I2, and a second end of the second transistor Q2 is connected to the first end of the fifth resistor R5;

[0166] The second resistor R2 is connected between the second end of the first current source I1 and the third node C;

[0167] The third resistor R3 is connected between the second end of the second current source I2 and the third node C;

[0168] The third node C is connected to the fourth node D.

[0169] In this embodiment, the first MOS transistor M1 is an N-channel transistor, the seventh MOS transistor M7 and the eighth MOS transistor M8 are P-channel transistors, the first end of the transistor is the source, the second end is the drain, and the control end is the gate.

[0170] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0171] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A compensation circuit, applied to a DC-DC control circuit, comprising a first inductor, a first MOS transistor, and a sensing resistor, wherein a first end of the first inductor is connected to a BIAS pin, a control end of the first MOS transistor is connected to a GATE pin, and a second end of the first inductor is connected to a second end of the first inductor, a first end of the sensing resistor is connected to a CS pin and a second end of the first MOS transistor, respectively, and a second end of the sensing resistor is connected to a PGND pin, wherein: The compensation circuit comprises: a first current source having a first terminal connected to a power supply voltage; a second current source having a first terminal connected to a power supply voltage; a third current source having a first terminal connected to the power supply voltage; A first voltage dividing unit is connected between the second end of the second current source and the PGND pin, and outputs a sampling voltage at a first node; A second voltage dividing unit is connected between the second end of the first current source and the PGND pin, and outputs a sensed voltage at a second node, the second node being connected to the CS pin; a comparison unit connected to the first voltage divider unit and the second voltage divider unit, respectively, the comparison unit comprising a comparator, a first input terminal of the comparator being connected to the second terminal of the first current source, a second input terminal being connected to the second terminal of the second current source, and an output terminal being connected to the GATE pin; The DC offset unit is respectively connected to the second end of the third current source, the PGND pin and the second node or the second end of the second current source, and is used to offset the DC current flowing out of the second current source from the second node.

2. The compensation circuit according to claim 1, wherein: The DC offset unit includes a second MOS transistor and a third MOS transistor, wherein: A first end of the second MOS transistor is connected to the PGND pin, and a second end is connected to the second node; The control end of the third MOS tube is connected to the control end of the second MOS tube and the second end of the third MOS tube respectively, the first end of the third MOS tube is connected to the PGND pin, and the second end of the third MOS tube is connected to the second end of the third current source.

3. The compensation circuit according to claim 1, wherein: The DC offset unit includes a second MOS transistor, a third MOS transistor and a fourth MOS transistor, wherein: A first end of the second MOS transistor is connected to the PGND pin, and a second end thereof is connected to the second end of the second current source; The control end of the third MOS transistor is connected to the control end of the second MOS transistor and the second end of the third MOS transistor respectively, the first end of the third MOS transistor is connected to the PGND pin, and the second end of the third MOS transistor is connected to the second end of the third current source; The control end of the fourth MOS tube is connected to the control end of the second MOS tube, the first end of the fourth MOS tube is connected to the PGND pin, and the second end of the fourth MOS tube is connected to the second end of the first current source.

4. The compensation circuit according to claim 1, wherein: The compensation circuit further includes a sampling unit connected between the sampling voltage and a power supply voltage.

5. The compensation circuit according to claim 2, wherein: The first voltage dividing unit includes a fifth resistor and a seventh resistor, wherein: The first end of the fifth resistor is connected to the second end of the second transistor, The first end of the seventh resistor is connected to the second end of the fifth resistor, and the second end of the seventh resistor is connected to the second node.

6. The compensation circuit according to claim 2, wherein: The second voltage dividing unit includes a fourth resistor and a sixth resistor, wherein: The first end of the fourth resistor is connected to the second end of the first transistor, and the second end of the fourth resistor is connected to the first node; A first end of the sixth resistor is connected to the first node, and a second end thereof is connected to the pin PGND.

7. The compensation circuit according to claim 3, characterized in that: The first voltage dividing unit includes a fifth resistor, a fifth MOS tube and a seventh resistor, wherein: The first end of the fifth resistor is connected to the second end of the second current source; The control end of the fifth MOS transistor is connected to the second end of the fifth MOS transistor, the second end is connected to the second end of the fifth resistor, and the first end of the fifth MOS transistor is connected to the second node; The first end of the seventh resistor is connected to the second node, and the second end is connected to the PGND pin.

8. The compensation circuit according to claim 3, wherein: The second voltage dividing unit includes a fourth resistor, a sixth MOS tube and a sixth resistor, wherein: The first end of the fourth resistor is connected to the second end of the first current source; The control end of the sixth MOS transistor is connected to the second end of the sixth MOS transistor, the second end is connected to the second end of the fourth resistor, and the first end of the sixth MOS transistor is connected to the node C; A first end of the sixth resistor is connected to the first node, and a second end thereof is connected to the PGND pin.

9. The compensation circuit according to any one of claims 2 or 3, characterized in that: The comparison unit further includes a first transistor, a second transistor, a second resistor, and a third resistor, wherein: The control end of the first transistor is connected to the fourth node, the first end of the first transistor is connected to the first end of the first current source, and the second end of the first transistor is connected to the first end of the fourth resistor; The control terminal of the second transistor is connected to the fourth node, the first terminal of the second transistor is connected to the second terminal of the second current source, and the second terminal of the second transistor is connected to the first terminal of the fifth resistor; The second resistor is connected between the second end of the first current source and the third node; The third resistor is connected between the second end of the second current source and the third node; The third node is connected to the fourth node.

10. A compensation circuit, applied to a DC-DC control circuit, comprising a first inductor, a first MOS transistor, and a sensing resistor, wherein a first end of the first inductor is connected to a BIAS pin, a control end of the first MOS transistor is connected to a GATE pin, and a second end of the first inductor is connected to a second end of the first inductor, a first end of the sensing resistor is connected to a CS pin and a second end of the first MOS transistor, respectively, and a second end of the sensing resistor is connected to a PGND pin, wherein: The compensation circuit comprises: a first current source having a first terminal connected to a power supply voltage; a second current source having a first terminal connected to a power supply voltage; a DC offset unit connected to the second end of the first current source, the second end of the second current source, the CS pin, and the PGND pin, respectively, and outputting a sensed voltage at the CS pin and a sampled voltage at the first node; A comparison unit is connected to the DC offset unit, and the comparison unit includes a comparator, a first input end of the comparator is connected to the second end of the first current source, a second input end of the comparator is connected to the second end of the second current source, and an output end is connected to the GATE pin.

11. The compensation circuit according to claim 10, characterized in that: The DC offset unit includes a fourth resistor, a fifth resistor, a sixth resistor, a seventh MOS transistor and an eighth MOS transistor, wherein: The first end of the fifth resistor is connected to the second end of the second transistor; The control end of the seventh MOS transistor is connected to the pin CS, the second end is connected to the pin PGND, and the first end is connected to the second end of the fifth resistor; The first end of the fourth resistor is connected to the second end of the first transistor; The control end of the eighth MOS transistor is connected to the first node, the second end is connected to the pin PGND, and the first end is connected to the second end of the fourth resistor; A first end of the sixth resistor is connected to the first node, and a second end thereof is connected to the pin PGND.

12. The compensation circuit according to claim 10, wherein: The compensation circuit further includes a sampling unit connected between the sampling voltage and the power supply voltage.

13. The compensation circuit according to claim 11, wherein: The comparison unit further includes a first transistor, a second transistor, a second resistor, and a third resistor, wherein: The control end of the first transistor is connected to the fourth node, the first end of the first transistor is connected to the first end of the first current source, and the second end of the first transistor is connected to the first end of the fourth resistor; The control terminal of the second transistor is connected to the fourth node, the first terminal of the second transistor is connected to the second terminal of the second current source, and the second terminal of the second transistor is connected to the first terminal of the fifth resistor; The second resistor is connected between the second end of the first current source and the third node; The third resistor is connected between the second end of the second current source and the third node; The third node is connected to the fourth node.

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