Binary adjustment band-gap reference temperature drift and output voltage circuit

Abstract

The invention discloses a binary regulation band-gap reference temperature drift and output voltage circuit, which belongs to the field of integrated circuits and comprises a band-gap reference circuit, a current regulation and control path, a first current mirror network and a second current mirror network. The band-gap reference circuit can generate Vout output voltage according to the structure of the band-gap reference circuit, if the output voltage Vout deviates from an ideal value, current on the resistor R3 and the triode Q4 can be adjusted through the first current mirror network, the second current mirror network and the current regulation and control access, and finally the output voltage Vout changes to reach the ideal value. The current source Ibias1 and the current source Ibias2 can be set according to needs, and the circuit is reliable in structure, rapid in response and capable of effectively protecting circuit work.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a binary regulation bandgap reference temperature drift and output voltage circuit. Background Art

[0002] Bandgap reference voltage plays an important role in electronic devices and integrated circuit design. When an accurate reference voltage is needed in the power management circuit to provide a stable and reliable reference voltage for other modules, such as analog-to-digital converters such as ADC (analog-to-digital converter) and DAC (digital-to-analog converter), a high-precision and low-temperature drift reference voltage is very important to ensure that these converters can achieve accurate signal sampling and output. Summary of the invention

[0003] The object of the present invention is to provide a binary adjustment bandgap reference temperature drift and output voltage circuit to solve the problems in the background technology.

[0004] In order to solve the above technical problems, the present invention provides a binary adjustment bandgap reference temperature drift and output voltage circuit, comprising: a bandgap reference circuit, a current control path, a first current mirror network and a second current mirror network;

[0005] The bandgap reference circuit generates a reference output voltage Vout through its own circuit structure;

[0006] The current control path has two control paths, and the current in the bandgap reference circuit is changed according to the two control paths to achieve the regulation of the temperature drift of the bandgap reference and the output voltage;

[0007] The first current mirror network mirrors a proportional current according to the magnitude of its own first bias current, and then controls the current path in the first current mirror network to be turned on or off according to the level of the control signal to obtain a first current;

[0008] The second current mirror network mirrors a proportional current according to the magnitude of its own second bias current, and then controls the current path in the second current mirror network to be turned on or off according to the level of the control signal to obtain a second current.

[0009] In one embodiment, the bandgap reference circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, an operational amplifier, a first resistor, a second resistor, a third resistor, a first triode, a second triode, a third triode, and a fourth triode;

[0010] The source end of the first PMOS tube, the source end of the second PMOS tube, the source end of the third PMOS tube, and the source end of the fourth PMOS tube are all connected to the power supply voltage VDD, and the gate end of the first PMOS tube, the gate end of the second PMOS tube, the gate end of the third PMOS tube, and the gate end of the fourth PMOS tube are all connected to the output end of the operational amplifier;

[0011] The drain end of the first PMOS tube is connected to the base of the second transistor and the emitter of the first transistor at the same time; the drain end of the second PMOS tube is connected to the emitter of the second transistor and the inverting input end of the operational amplifier at the same time; the drain end of the third PMOS tube is connected to the non-inverting input end of the operational amplifier and the first end of the first resistor at the same time; the drain end of the fourth PMOS tube is connected to the first end of the second resistor, and the drain end output voltage is Vout;

[0012] The second end of the first resistor is connected to the emitter of the third transistor; the second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the base of the third transistor and the emitter of the fourth transistor at the same time; the base of the first transistor is grounded, and the collector is grounded; the collector of the second transistor is grounded; the base of the third transistor is connected to the emitter of the fourth transistor and the second end of the third resistor, the emitter is connected to the second end of the first resistor, and the collector is grounded; the base of the fourth transistor is grounded, the emitter is connected to the second end of the third resistor, the base of the third transistor, and the collector is grounded.

[0013] In one embodiment, the current control path includes a current source I11, a current source I12, a current source I21, a current source I22, a first switch CK <0> , the second switch CK <0> and the first switch CKN <0> , the second switch CKN <0> , a first inverter and a second inverter;

[0014] One end of the current source I11 is connected to the power supply VDD, and the other end is connected to the first switch CK <0> The first end of the first inverter, the input end of the first switch CK <0> The second terminal is connected to the first switch CKN <0> The first end of the current source I12 is connected to the output end of the second inverter and the first end of the third resistor; one end of the current source I12 is connected to the first switch CKN <0> The second end of the current source I12 is grounded;

[0015] One end of the current source I21 is connected to the power supply VDD, and the other end is connected to the second switch CKN <0> The first end of the second switch CKN <0> The second end is connected to the output end of the first inverter, the first end of the third resistor, and the second switch CK <0> The first end of the current source I22 is connected to the second switch CK <0> The second end of the current source I12 is connected to the input end of the second inverter, and the other end of the current source I12 is grounded.

[0016] In one implementation, the first current mirror network includes a first current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a first current;

[0017] Wherein, one end of the first current source is connected to the power supply VDD, and the other end is connected to the gate and drain of the first NMOS tube, the gate of the first NMOS tube is simultaneously connected to its own drain, the gate of the second NMOS tube, the gate of the third NMOS tube, and the gate of the fourth NMOS tube, and the source of the first NMOS tube is grounded; the drain of the second NMOS tube is connected to the source of the fifth NMOS tube, and the source is grounded; the drain of the third NMOS tube is connected to the source of the sixth NMOS tube, and the source is grounded; the drain of the fourth NMOS tube is connected to the source of the seventh NMOS tube, and the source is grounded;

[0018] The first end of the first current is connected to the power supply VDD, the second end is connected to the drain end of the fifth NMOS tube, the drain end of the sixth NMOS tube, and the drain end of the seventh NMOS tube, and the gate end of the fifth NMOS tube is connected to the control signal CK <1> The gate terminal of the sixth NMOS tube is connected to the control signal CK <2> The gate terminal of the seventh NMOS tube is connected to the control signal CK <3> .

[0019] In one implementation, the second current mirror network includes a second current source, an eighth NMOS transistor NM8, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a second current;

[0020] Among them, one end of the second current source is connected to the power supply VDD, and the other end is connected to the gate and drain of the eighth NMOS tube. The gate of the eighth NMOS tube is simultaneously connected to its own drain, the gate of the ninth NMOS tube, the gate of the tenth NMOS tube, and the gate of the eleventh NMOS tube. The source of the eighth NMOS tube is grounded; the drain of the ninth NMOS tube is connected to the source of the twelfth NMOS tube, and the source is grounded; the drain of the tenth NMOS tube is connected to the source of the thirteenth NMOS tube, and the source is grounded; the drain of the eleventh NMOS tube is connected to the source of the fourteenth NMOS tube, and the source is grounded;

[0021] The first end of the second current is connected to the power supply VDD, the second end is connected to the drain end of the twelfth NMOS tube, the drain end of the thirteenth NMOS tube, and the drain end of the fourteenth NMOS tube, and the gate end of the twelfth NMOS tube is connected to the control signal CK <1> , the gate terminal of the thirteenth NMOS tube is connected to the control signal CK <2> The gate terminal of the fourteenth NMOS tube is connected to the control signal CK <3> .

[0022] The invention provides a binary adjustment bandgap reference temperature drift and output voltage circuit, which can realize low temperature drift and stable reference voltage at different temperatures. The invention has a simple structure, and the circuit can be used to provide reference voltage for high-precision circuits, and can be widely used in analog-to-digital converters and digital-to-analog converters; by re-controlling the current flowing through the resistor R3 and the transistor Q4, the temperature drift is further reduced, and the output voltage reaches an ideal value. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural schematic diagram of the bandgap reference circuit and the current control path in the present invention.

[0024] Figure 2 It is a schematic diagram of the structure of the first current mirror network in the present invention.

[0025] Figure 3 It is a schematic diagram of the structure of the second current mirror network in the present invention. DETAILED DESCRIPTION

[0026] The following is a further detailed description of a binary adjustment bandgap reference temperature drift and output voltage circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0027] The present invention provides a binary adjustment bandgap reference temperature drift and output circuit, the structure of which is as follows: Figure 1 , Figure 2 and Figure 3 As shown, it includes a bandgap reference circuit, a current control path, a current mirror network 1 and a current mirror network 2.

[0028] The bandgap reference circuit generates a reference output Vout through a circuit structure; the current control path has two control paths, and the currents of the resistor R3 and the transistor Q4 in the bandgap reference circuit are changed according to the two control paths, thereby realizing the regulation of the temperature drift of the bandgap reference and the output voltage; the current mirror network 1 mirrors the proportional current according to the size of the current source Ibias1, and then controls the current path in the current mirror network 1 to be turned on or off according to the high and low levels of the CK signal, thereby obtaining the current I1; the current mirror network 2 mirrors the proportional current according to the size of the current source Ibias2, and then controls the current path in the current mirror network 2 to be turned on or off according to the high and low levels of the CK signal, thereby obtaining the current I2.

[0029] The bandgap reference circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, an operational amplifier opamp, a first resistor R1, a second resistor R2, a third resistor R3, a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4.

[0030] The source terminal of the first PMOS tube PM1 is connected to the power supply voltage VDD, the gate terminal is connected to the gate terminal of the second PMOS tube PM2, the gate terminal of the third PMOS tube PM3, and the gate terminal of the fourth PMOS tube PM4, and the drain terminal is connected to the base of the second transistor Q2 and the emitter of the first transistor Q1. The source terminal of the second PMOS tube PM2 is connected to the power supply voltage VDD, the gate terminal is connected to the gate terminal of the first PMOS tube PM1, the gate terminal of the third PMOS tube PM3, and the gate terminal of the fourth PMOS tube PM4, and the drain terminal is connected to the emitter of the second transistor Q2 and the inverting input terminal of the operational amplifier opamp. The source terminal of the third PMOS tube PM3 is connected to the power supply voltage VDD, the gate terminal is connected to the gate terminal of the first PMOS tube PM1, the gate terminal of the second PMOS tube PM2, and the gate terminal of the fourth PMOS tube PM4, and the drain terminal is connected to the non-inverting input terminal of the operational amplifier opamp and the first end of the first resistor R1. The source terminal of the fourth PMOS transistor PM4 is connected to the power supply voltage VDD, the gate terminal is connected to the gate terminal of the first PMOS transistor PM1, the gate terminal of the second PMOS transistor PM2, and the gate terminal of the third PMOS transistor PM3 at the same time, the drain terminal is connected to the first end of the second resistor R2, and the drain terminal output voltage is Vout. The in-phase input terminal of the operational amplifier opamp is connected to the first end of the resistor R1, the inverting input terminal is connected to the emitter of the second transistor Q2, and the output terminal is connected to the gate of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the gate of the third PMOS transistor PM3, and the gate of the fourth PMOS transistor PM4 at the same time. The first terminal of the first resistor R1 is connected to the in-phase input terminal of the operational amplifier opamp, and the second terminal is connected to the emitter of the third transistor Q3. The first terminal of the second resistor R2 is connected to the drain terminal of the fourth PMOS transistor PM4 and the output voltage Vout, the second terminal is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is connected to the base of the third transistor Q3 and the emitter of the fourth transistor Q4 at the same time. The base of the first transistor Q1 is grounded, the collector is grounded, and the emitter is connected to the drain of the first PMOS transistor PM1 and the base of the second transistor Q2. The base of the second transistor Q2 is connected to the drain of the first PMOS transistor PM1 and the emitter of the first transistor Q1, the collector is grounded, and the emitter is connected to the drain of the second PMOS transistor PM2 and the inverting input terminal of the operational amplifier opamp. The base of the third transistor Q3 is connected to the emitter of the fourth transistor Q4 and the second end of the third resistor R3, the emitter is connected to the second end of the first resistor R1, and the collector is grounded. The base of the fourth transistor Q4 is grounded, the emitter is connected to the second end of the third resistor R3 and the base of the third transistor Q3, and the collector is grounded.

[0031] The current control path includes current sources I11, I12, I21, and I22, and the first switch CK <0> , the second switch CK <0> and the first switch CKN <0> , the second switch CKN <0> , inverter INV1 and inverter INV2; one end of the current source I11 is connected to the power supply VDD, and the other end is connected to the first switch CK <0> The first end of the first switch CK <0> The second terminal is connected to the first switch CKN <0> The first end of the current source I12 is connected to the first switch CKN <0> The second end of the current source I12 is connected to the ground. One end of the current source I21 is connected to the power supply VDD, and the other end is connected to the second switch CKN <0> The first end of the second switch CKN <0> The second end is connected to the output end of the inverter INV1, the first end of the third resistor R3, and the second switch CK <0> The first end of the current source I22 is connected to the second switch CK <0> The second end of the current source I12 is connected to the input end of the inverter INV2, and the other end of the current source I12 is grounded.

[0032] like Figure 2 As shown, the current mirror network 1 includes a current source Ibias1, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, and a current I1.

[0033] One end of the current source Ibias1 is connected to the power supply VDD, and the other end is connected to the gate and drain of the first NMOS tube NM1. The gate of the first NMOS tube NM1 is simultaneously connected to the drain of the first NMOS tube NM1, the gate of the second NMOS tube NM2, the gate of the third NMOS tube NM3, and the gate of the fourth NMOS tube NM4, and the source of the first NMOS tube NM1 is grounded.

[0034] The drain terminal of the second NMOS tube NM2 is connected to the source terminal of the fifth NMOS tube NM5, the gate terminal of the second NMOS tube NM2 is simultaneously connected to the gate terminal of the first NMOS tube NM1, the gate terminal of the third NMOS tube NM3, and the gate terminal of the fourth NMOS tube NM4, and the source terminal of the second NMOS tube NM2 is grounded.

[0035] The drain terminal of the third NMOS tube NM3 is connected to the source terminal of the sixth NMOS tube NM6, the gate terminal of the third NMOS tube NM3 is simultaneously connected to the gate terminal of the first NMOS tube NM1, the gate terminal of the second NMOS tube NM2, and the gate terminal of the fourth NMOS tube NM4, and the source terminal of the third NMOS tube NM3 is grounded.

[0036] The drain terminal of the fourth NMOS tube NM4 is connected to the source terminal of the seventh NMOS tube NM7, the gate terminal of the fourth NMOS tube NM4 is simultaneously connected to the gate terminal of the first NMOS tube NM1, the gate terminal of the second NMOS tube NM2, and the gate terminal of the third NMOS tube NM3, and the source terminal of the fourth NMOS tube NM4 is grounded.

[0037] The first end of the current I1 is connected to the power supply VDD, and the second end is connected to the drain end of the fifth NMOS tube NM5, the drain end of the sixth NMOS tube NM6, and the drain end of the seventh NMOS tube NM7. The gate end of the fifth NMOS tube NM5 is connected to the control signal CK. <1> The source terminal of the fifth NMOS tube NM5 is connected to the drain terminal of the second NMOS tube; the gate terminal of the sixth NMOS tube NM6 is connected to the control signal CK <2> The source terminal of the sixth NMOS tube NM6 is connected to the drain terminal of the third NMOS tube; the gate terminal of the seventh NMOS tube NM7 is connected to the control signal CK <3> , the source terminal of the seventh NMOS tube NM7 is connected to the drain terminal of the fourth NMOS tube.

[0038] like Figure 3 As shown, similar to the structure of the current mirror network 1, the current mirror network 2 includes a current source Ibias2, an eighth NMOS tube NM8, a ninth NMOS tube NM9, a tenth NMOS tube NM10, an eleventh NMOS tube NM11, a twelfth NMOS tube NM12, a thirteenth NMOS tube NM13, a fourteenth NMOS tube NM14, and a current I2.

[0039] One end of the current source Ibias2 is connected to the power supply VDD, and the other end is connected to the gate and drain of the eighth NMOS transistor NM8. The gate of the eighth NMOS transistor NM8 is simultaneously connected to the gate of the ninth NMOS transistor NM9, the gate of the tenth NMOS transistor NM10, and the gate of the eleventh NMOS transistor NM11, and the source of the eighth NMOS transistor NM8 is grounded.

[0040] The drain terminal of the ninth NMOS tube NM9 is connected to the source terminal of the twelfth NMOS tube NM12, the gate terminal of the ninth NMOS tube NM9 is simultaneously connected to the gate terminals of the eighth NMOS tube NM8, the tenth NMOS tube NM10, and the eleventh NMOS tube NM11, and the source terminal of the ninth NMOS tube NM9 is grounded.

[0041] The drain terminal of the tenth NMOS tube NM10 is connected to the source terminal of the thirteenth NMOS tube NM13, the gate terminal of the tenth NMOS tube NM10 is simultaneously connected to the gate terminals of the eighth NMOS tube NM8, the ninth NMOS tube NM9, and the eleventh NMOS tube NM11, and the source terminal of the tenth NMOS tube NM10 is grounded.

[0042] The drain terminal of the eleventh NMOS tube NM11 is connected to the source terminal of the fourteenth NMOS tube NM14, the gate terminal of the eleventh NMOS tube NM11 is simultaneously connected to the gate terminal of the eighth NMOS tube NM8, the gate terminal of the ninth NMOS tube NM9, and the gate terminal of the tenth NMOS tube NM10, and the source terminal of the eleventh NMOS tube NM11 is grounded.

[0043] One end of the current I2 is connected to the power supply VDD, and the other end is connected to the drain end of the twelfth NMOS tube NM12, the drain end of the thirteenth NMOS tube NM13, and the drain end of the fourteenth NMOS tube NM14. The gate end of the twelfth NMOS tube NM12 is connected to the control signal CK. <1> The source terminal of the twelfth NMOS tube NM12 is connected to the drain terminal of the ninth NMOS tube NM9; the gate terminal of the thirteenth NMOS tube NM13 is connected to the control signal CK <2> The source terminal of the thirteenth NMOS tube NM13 is connected to the drain terminal of the tenth NMOS tube NM10; the gate terminal of the fourteenth NMOS tube NM14 is connected to the control signal CK <3> , the source terminal of the fourteenth NMOS tube NM14 is connected to the drain terminal of the eleventh NMOS tube NM11.

[0044] The detailed working process of the present invention is as follows:

[0045] The control signal is CK <0> , CK <1> , CK <2> , CK <3> The circuit output voltage Vout is generated by the bandgap reference circuit structure. The basic principle is that when the reference circuit works normally, the bipolar transistors Q2 and Q3 work at different current densities, and the difference between their base-collector voltages has a positive temperature coefficient; the base-emitter voltage of the bipolar transistor has a negative temperature coefficient, and the linear combination of the two may form a voltage with a zero temperature coefficient. The clamping effect of the op amp makes V + =V-. Therefore, the current flowing through the resistor R1 is:

[0046]

[0047] Where V T is the thermal voltage with a positive temperature coefficient; N is the ratio of the emitter area of ​​Q2 (Q2 = Q1) to that of Q3 (Q3 = Q4), V EB1 is the difference between the emitter and base voltages of the first transistor Q1, V EB2 is the difference between the emitter and base voltages of the second transistor Q2, V EB3 is the emitter-base voltage difference of the third transistor Q3, V EB4 It is the difference between the emitter and base voltages of the fourth transistor Q4.

[0048] Because PM1 to PM4 transistors form a current mirror structure and have the same width-to-length ratio, the currents in each branch are almost equal, so the output reference voltage is:

[0049]

[0050] The output voltage can be obtained by the bandgap reference circuit according to the above formula. However, in actual applications, due to manufacturing or process deviations, the output voltage and temperature drift will deviate from the ideal value. At this time, the control signal can be adjusted as needed.

[0051] It is mainly composed of a current control path, and the control signal CK <0> When the control signal CK is high, the switch can be turned off, and the current sources I11 and I12 in the current control path are equal to the current source I1 in the current mirror network 1; the current sources I21 and I22 are equal to the current source I2 in the current mirror network 2. <0> is a high level, and the power supply, current source I11, current source I22, and ground in the current control path form a current path; and because the current source I11 and the current source I22 are not equal, the remaining current will flow into the resistor R3 and the transistor Q4 through the node, or the remaining current will flow into the current source I22 through the node.

[0052] For example, if the control signal CK <0> is high level, the power supply, current source I11, current source I22 and ground in the current control path form a current path. If the current source I11 is greater than the current source I22, then ΔI=I 11 -I 22 ; will be injected into the resistor R3 and transistor Q4, thus causing the temperature drift and output voltage Vout to change. Similarly, if the control signal CK <0> CKN is low level. <0> CK <0> The inverted signal in the current control path, the power supply, current source I21, current source I12, and ground form a current path. The current source I21 is smaller than the current source I12, then ΔI=I 12 -I 21 , the current flowing through the resistor R3 and the transistor Q4 will decrease by ΔI, causing the temperature drift and the output voltage Vout to change.

[0053] In the current mirror network 1, the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4 form a current mirror. According to the width-to-length ratio of NM1 to NM2, NM3, and NM4, the width-to-length ratio of NM1 to NM2, NM3, and NM4 is set to Q:J:K:M=1:4:2:1, and the control signal CK <1> , control signal CK <2> , control signal CK <3> When it is at a high level, the corresponding NMOS tube can be controlled to be turned on, thereby controlling the size of the current flowing through the current source I1.

[0054] The sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, and the ninth NMOS transistor NM9 in the current mirror network 2 form a current mirror. According to the width-to-length ratio of NM6 to NM7, NM8, and NM9, the width-to-length ratio of NM6 to NM7, NM8, and NM9 is set to Q:J:K:M=1:4:2:1, and the control signal CK <1> , control signal CK <2> , control signal CK <3> When it is at a high level, the corresponding NMOS tube can be controlled to be turned on, thereby controlling the size of the current flowing through the current source I2.

[0055] For a clearer explanation, the present invention cites the binary adjustment bandgap reference temperature drift and the output voltage change when the binary changes in the output voltage circuit. According to the circuit structure characteristics, for the convenience of description, here we take R3 = 1kΩ, Q:J:K:M = 1:4:2:1, and the current I bias1 =10uA>I bias2 =5uA, the current flowing through transistor Q4 is assumed to be 10uA, and the output voltage Vout is set to 1.2V.

[0056] Then, when the control signal changes from 0000 to 0111, the output voltage is:

[0057] ΔV out =ΔI*R3+ΔV BE4

[0058] Here ΔI=I bias1 -I bias2 =5μA, R3=1kΩ, Here we assume that I C1 =10uA, The β of the transistor is set to 20, and the initial Vout = 1.2V. Here I C1 is the current flowing through the fourth transistor Q4 when the current control path is not turned on, I C2 is the current flowing through the fourth transistor Q4 after the current control path is turned on, and the base current is ignored here; β is the current amplification factor of the transistor.

[0059] Table 1 lists the control signals CK <0> :CK <1> :CK <2> :CK <3> When the output voltage Vout changes from 0000 to 01111, CK <0> = 0, the power supply, I21, I12, and ground maintain the path, and the flow I bias1 =10uA>I bias2 =5uA, the current flowing through resistor R3 and transistor Q4 decreases, and Vout decreases by 5.658mV for each step of adjustment, thereby adjusting the situation where the output voltage deviates from the ideal value due to manufacturing or process deviation.

[0060]

[0061]

[0062] Table 1 Adjustment to reduce the output voltage

[0063] Table 2 lists the control signals CK <0> :CK <1> :CK <2> :CK <3> When the value changes from 1000 to 11111, the output voltage Vout changes, CK <0> =1, the power supply, I12, I21, and ground maintain the path, and the flow I bias1 =10uA>I bias2 =5uA, the current flowing through resistor R3 and transistor Q4 increases, and Vout increases by 4.358mV for each step of adjustment, thereby adjusting the situation where the output voltage deviates from the ideal value due to manufacturing or process deviation.

[0064] CK<0>:<1>:<2>:<3> Output voltage Vout / V Adjustment / mV 1000 1.2 0 1001 1.204358 +4.358 1010 1.208716 +8.716 1011 1.213074 +13.074 1100 1.217432 +17.432 1101 1.22179 +21.79 1110 1.226148 +26.148 1111 1.230506 +30.506

[0065] Table 2 Adjustment to increase the output voltage

[0066] It can be seen that the adjustment step can be controlled by controlling the size of Ibias1 and Ibias2, and the current flowing through the resistor R3 and the transistor Q4 can be controlled by controlling the high and low levels of the control signal, thereby controlling the size of the output voltage Vout. It can be analyzed from the above table that if I bias1 >I bias2 , then CK <0> =0 can reduce the output voltage; CK <0> =1 can increase the output voltage.

[0067] Binary enables the mirror ratio of the current mirror to achieve CK <1> , CK <2> , CK <3> The current in the path is 4:2:1, thereby realizing binary current regulation. Finally, the binary current is reflected in the output Vout, and the output Vout is regulated.

[0068] This circuit structure also has an impact on temperature drift, but temperature drift requires specific analysis of the actual circuit and its output voltage changes with temperature. It is calculated based on the simulation of the actual circuit, but its idea is basically the same as above, so it will not be repeated here.

[0069] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A binary adjustment bandgap reference temperature drift and output voltage circuit, characterized in that: include: A bandgap reference circuit, a current control path, a first current mirror network and a second current mirror network; The bandgap reference circuit generates a reference output voltage Vout through its own circuit structure; The current control path has two control paths, and the current in the bandgap reference circuit is changed according to the two control paths to achieve the regulation of the temperature drift of the bandgap reference and the output voltage; The first current mirror network mirrors a proportional current according to the magnitude of its own first bias current, and then controls the current path in the first current mirror network to be turned on or off according to the level of the control signal to obtain a first current; The second current mirror network mirrors a proportional current according to the magnitude of its own second bias current, and then controls the current path in the second current mirror network to be turned on or off according to the level of the control signal to obtain a second current.

2. The binary adjustable bandgap reference temperature drift and output voltage circuit according to claim 1, characterized in that: The bandgap reference circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, an operational amplifier, a first resistor, a second resistor, a third resistor, a first triode, a second triode, a third triode, and a fourth triode; The source end of the first PMOS tube, the source end of the second PMOS tube, the source end of the third PMOS tube, and the source end of the fourth PMOS tube are all connected to the power supply voltage VDD, and the gate end of the first PMOS tube, the gate end of the second PMOS tube, the gate end of the third PMOS tube, and the gate end of the fourth PMOS tube are all connected to the output end of the operational amplifier; The drain end of the first PMOS tube is connected to the base of the second transistor and the emitter of the first transistor at the same time; the drain end of the second PMOS tube is connected to the emitter of the second transistor and the inverting input end of the operational amplifier at the same time; the drain end of the third PMOS tube is connected to the non-inverting input end of the operational amplifier and the first end of the first resistor at the same time; the drain end of the fourth PMOS tube is connected to the first end of the second resistor, and the drain end output voltage is Vout; The second end of the first resistor is connected to the emitter of the third transistor; the second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the base of the third transistor and the emitter of the fourth transistor at the same time; the base of the first transistor is grounded, and the collector is grounded; the collector of the second transistor is grounded; the base of the third transistor is connected to the emitter of the fourth transistor and the second end of the third resistor, the emitter is connected to the second end of the first resistor, and the collector is grounded; the base of the fourth transistor is grounded, the emitter is connected to the second end of the third resistor, the base of the third transistor, and the collector is grounded.

3. The binary adjustable bandgap reference temperature drift and output voltage circuit according to claim 1, characterized in that: The current control path includes current sources I11, I12, I21, and I22, and a first switch CK <0> , the second switch CK <0> and the first switch CKN <0> , the second switch CKN <0> , a first inverter and a second inverter; One end of the current source I11 is connected to the power supply VDD, and the other end is connected to the first switch CK <0> The first end of the first inverter, the input end of the first switch CK <0> The second terminal is connected to the first switch CKN <0> The first end of the current source I12 is connected to the output end of the second inverter and the first end of the third resistor; one end of the current source I12 is connected to the first switch CKN <0> The second end of the current source I12 is grounded; One end of the current source I21 is connected to the power supply VDD, and the other end is connected to the second switch CKN <0> The first end of the second switch CKN <0> The second end is connected to the output end of the first inverter and the second switch CK <0> The first end of the current source I22 is connected to the second switch CK <0> The second end of the current source I12 is connected to the input end of the second inverter, and the other end of the current source I12 is grounded.

4. The binary adjustment bandgap reference temperature drift and output voltage circuit according to claim 1, characterized in that: The first current mirror network includes a first current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a first current; Wherein, one end of the first current source is connected to the power supply VDD, and the other end is connected to the gate and drain of the first NMOS tube, the gate of the first NMOS tube is simultaneously connected to its own drain, the gate of the second NMOS tube, the gate of the third NMOS tube, and the gate of the fourth NMOS tube, and the source of the first NMOS tube is grounded; the drain of the second NMOS tube is connected to the source of the fifth NMOS tube, and the source is grounded; the drain of the third NMOS tube is connected to the source of the sixth NMOS tube, and the source is grounded; the drain of the fourth NMOS tube is connected to the source of the seventh NMOS tube, and the source is grounded; The first end of the first current is connected to the power supply VDD, the second end is connected to the drain end of the fifth NMOS tube, the drain end of the sixth NMOS tube, and the drain end of the seventh NMOS tube, and the gate end of the fifth NMOS tube is connected to the control signal CK <1> The gate terminal of the sixth NMOS tube is connected to the control signal CK <2> The gate terminal of the seventh NMOS tube is connected to the control signal CK <3> .

5. The binary adjustable bandgap reference temperature drift and output voltage circuit according to claim 1, characterized in that: The second current mirror network includes a second current source, an eighth NMOS tube NM8, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, and a second current; Among them, one end of the second current source is connected to the power supply VDD, and the other end is connected to the gate and drain of the eighth NMOS tube. The gate of the eighth NMOS tube is simultaneously connected to its own drain, the gate of the ninth NMOS tube, the gate of the tenth NMOS tube, and the gate of the eleventh NMOS tube. The source of the eighth NMOS tube is grounded; the drain of the ninth NMOS tube is connected to the source of the twelfth NMOS tube, and the source is grounded; the drain of the tenth NMOS tube is connected to the source of the thirteenth NMOS tube, and the source is grounded; the drain of the eleventh NMOS tube is connected to the source of the fourteenth NMOS tube, and the source is grounded; The first end of the second current is connected to the power supply VDD, the second end is connected to the drain end of the twelfth NMOS tube, the drain end of the thirteenth NMOS tube, and the drain end of the fourteenth NMOS tube, and the gate end of the twelfth NMOS tube is connected to the control signal CK <1> , the gate terminal of the thirteenth NMOS tube is connected to the control signal CK <2> The gate terminal of the fourteenth NMOS tube is connected to the control signal CK <3> .

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