Accumulator and method for accumulator, integrated circuit chip and computing device

Abstract

The present invention provides an accumulator and a method for an accumulator, an integrated circuit chip and a computing device, comprising: a main input data selection unit, a secondary input data selection unit, and a data accumulation feedback unit, wherein the main input data selection unit is used to receive external input data and second accumulation intermediate result data from the cache of the data accumulation feedback unit, and output the external data or the second accumulation intermediate result data to the data accumulation feedback unit; the secondary input data selection unit receives the first accumulation intermediate result data output from the data accumulation feedback unit according to the clock cycle and outputs it to the data accumulation feedback unit; the data accumulation feedback unit performs an accumulation operation. The technical solution according to the present invention enables the accumulator to reduce the time consumption of accumulation operation on the basis of adapting to the chip operating frequency, and significantly improves the efficiency of accumulation operation.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit accumulators, and in particular to an accumulator and a method for an accumulator, an integrated circuit chip and a computing device. Background Art

[0002] An accumulator is a commonly used digital logic circuit that is used to accumulate input data. The core of an accumulator is an adder, which accumulates the primary input by returning the output to the secondary input of the adder.

[0003] In the prior art, because the addition time is prolonged, the calculation that can be completed in the same time is only half of the ideal design (a design that can get the addition result in 1 clock cycle). Similarly, for the same amount of input data, if the number of clock cycles for addition increases, the total time of the operation will increase exponentially accordingly, greatly reducing the operation efficiency. For today's rapidly developing chip design, this operation efficiency problem is becoming more and more prominent.

[0004] Therefore, a technical solution is needed that can reduce the time consumption of accumulation operation and significantly improve the efficiency of accumulation operation on the basis of adapting to the operating frequency of the chip. Summary of the invention

[0005] The present invention aims to provide an accumulator and a method and computing device for the accumulator, which can reduce the time consumption of accumulation operation and significantly improve the efficiency of accumulation operation on the basis of adapting to the working frequency of the chip.

[0006] According to one aspect of the present invention, an accumulator is provided, comprising: a primary input data selection unit, a secondary input data selection unit, and a data accumulation feedback unit, wherein:

[0007] The main input data selection unit is used to receive external input data and second accumulated intermediate result data from the data accumulation feedback unit cache, and output the external data to the data accumulation feedback unit in a state of receiving external data in each clock cycle, and output the second accumulated intermediate result data to the data accumulation feedback unit after the external data input is completed;

[0008] The secondary input data selection unit receives the first accumulated intermediate result data outputted from the data accumulation feedback unit according to the clock cycle and outputs the first accumulated intermediate result data to the data accumulation feedback unit;

[0009] The data accumulation feedback unit performs an accumulation operation, obtains the first accumulated intermediate result data after at least two clock cycles and outputs the first accumulated intermediate result data to the secondary input data selection unit, caches the selected first accumulated intermediate result data after the external data input is completed, and outputs the cached first accumulated intermediate result data as the second accumulated intermediate result data to the main input data selection unit so that the data accumulation feedback unit accumulates the first accumulated intermediate result data and the second accumulated intermediate result data in subsequent clock cycles.

[0010] According to some embodiments, while the main input data selection unit starts to receive external input data, the secondary input data selection unit inputs N zeros to the data accumulation feedback unit in N consecutive clock cycles, wherein the value of N is the same as the number of clock cycles required for the accumulator to complete a single accumulation operation.

[0011] According to some embodiments, the data accumulation feedback unit includes a data accumulation unit and a feedback storage unit, wherein:

[0012] The data accumulation unit performs an accumulation operation, and after the external data input is completed, outputs the selected first accumulation intermediate result data to the feedback register unit;

[0013] The feedback register unit caches the received first accumulated intermediate result data, uses the cached first accumulated intermediate result data as the second accumulated intermediate result data, and outputs the second accumulated intermediate result data to the main input data selection unit according to a predetermined clock cycle.

[0014] According to some embodiments, the data accumulation unit is configured as:

[0015] receiving input data in a first clock cycle, outputting the first accumulated intermediate result data in an N+1th clock cycle, and outputting the first accumulated intermediate result data to the secondary input data selection unit, where N is an integer greater than 1;

[0016] The first accumulated intermediate result data is output to the feedback register unit in the next clock cycle after the external data input is completed.

[0017] According to some embodiments, the feedback register unit is configured to output the cached first accumulated intermediate result data as the second accumulated intermediate result data to the main input data selection unit in a subsequent clock cycle or according to a predetermined clock cycle after caching the first accumulated intermediate result data, so that the first accumulated intermediate result data and the second accumulated intermediate result data are aligned and accumulated by the data accumulation unit.

[0018] According to some embodiments, the main input data selection unit further receives an input of data 0, and if the external input data input during the external data input period is invalid data, the main input data selection unit outputs 0 to the data accumulation feedback unit.

[0019] According to some embodiments, the main input data selection unit also receives an input of data 0. If the external input data is non-continuous data during external data input, the main input data selection unit outputs 0 to the data accumulation feedback unit corresponding to the non-continuous data position.

[0020] According to another aspect of the present invention, there is provided a method for an accumulator, the accumulator comprising a first data channel and a second data channel, the method comprising:

[0021] Get the number of clock cycles required for the accumulator to perform a single accumulation operation;

[0022] Acquire input data to be accumulated, and send the input data to be accumulated to a first data channel of the accumulator, and synchronously input a number of zeros equal to the number of clock cycles required for the accumulator to perform a single accumulation operation to a second data channel of the accumulator;

[0023] Performing an accumulation operation to obtain first accumulated intermediate result data, and feeding the first accumulated intermediate result data back to the second data channel of the accumulator;

[0024] After the input data to be accumulated is inputted, the selected first accumulated intermediate result data is cached and fed back to the first data channel of the accumulator as second accumulated intermediate result data for subsequent accumulation.

[0025] According to another aspect of the present invention, there is provided an integrated circuit chip, comprising the accumulator according to any one of the above items.

[0026] According to another aspect of the present invention, there is provided a computing device, comprising:

[0027] Processor; and

[0028] A memory storing a computer program, which, when executed by the processor, enables the processor to execute any of the methods described above.

[0029] According to another aspect of the present invention, there is provided a non-transitory computer-readable storage medium having computer-readable instructions stored thereon, and when the instructions are executed by a processor, the processor is caused to execute any of the above methods.

[0030] According to an embodiment of the present invention, by selecting data and adapting to the clock cycle of a single accumulation operation of the accumulator, the grouped accumulation of the external input data is realized to obtain an intermediate accumulation result, and the intermediate accumulation result is cached and fed back to the data accumulation feedback unit, and the intermediate accumulation result is accumulated in the data accumulation feedback unit to finally obtain the accumulation result data, so that the accumulator can reduce the time consumption of the accumulation operation on the basis of adapting to the working frequency of the chip circuit, and significantly improve the efficiency of the accumulation operation. In particular, in the processing of large-scale data accumulation operations, the speed-up effect is more obvious, and the data processing efficiency is doubled.

[0031] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below.

[0033] Figure 1 A schematic diagram of the structure of an accumulator in the prior art is shown.

[0034] Figure 2 The figure shows an ideal timing diagram of the accumulator completing the addition operation in one clock cycle in the prior art.

[0035] Figure 3 The figure shows an ideal timing diagram of the accumulator completing the addition operation in two clock cycles in the prior art.

[0036] Figure 4 A schematic diagram of an accumulator is shown according to an example embodiment.

[0037] Figure 5 A diagram of an accumulator structure according to an example embodiment is shown.

[0038] Figure 6 A flow chart of a method for an accumulator according to an example embodiment is shown.

[0039] Figure 7 A schematic diagram of a method for an accumulator according to an example embodiment is shown.

[0040] Figure 8 An ideal timing diagram showing an accumulator completing an addition operation in 2 clock cycles according to an example embodiment is shown.

[0041] Fig. 9 An ideal timing diagram showing an accumulator completing an addition operation in three clock cycles according to another example embodiment is shown.

[0042] Fig.10An ideal timing diagram showing an accumulator completing an addition operation in 2 clock cycles when input is discontinuous according to another example embodiment.

[0043] Fig.11 A block diagram of a computing device according to an example embodiment of the invention is shown. DETAILED DESCRIPTION

[0044] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0045] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0046] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0047] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0048] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first component discussed below can be referred to as the second component without departing from the teachings of the present inventive concept. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more.

[0049] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0050] Those skilled in the art will appreciate that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present invention, and therefore cannot be used to limit the protection scope of the present invention.

[0051] With the rapid development of AI, complex data and image processing such as image recognition and image classification have put forward higher requirements on current data processing and computing speed. Among them, in convolutional neural network calculations, accumulation is one of the main computing processes. How to improve the efficiency of accumulation calculation is a key technology in data flow chip architecture.

[0052] Figure 1 A schematic diagram of the structure of an accumulator in the prior art is shown.

[0053] See also Figure 1 , B is the output of the accumulator, and is also the result of the addition calculation performed by the adder. Figure 1 As shown, the adder has two data inputs, Figure 1 The main input is A, and the other is the secondary input, which is the selection result of 0 and B. When the first A data is input, the secondary input selects 0, and the first result B=A+0=A is obtained by addition. Then the secondary input continues to select B until the accumulation ends. As the main input A is continuously updated, B is also updated by addition, and B is added to the main input A as the secondary input, thus realizing the accumulation of the main input A and obtaining the final accumulation result B. Such a design can complete the accumulation calculation in the shortest time, with the highest efficiency, and is an ideal design. However, the prerequisite is that a timing requirement must be met, that is, this design takes 1 clock cycle to complete the addition calculation.

[0054] Figure 2 The figure shows an ideal timing diagram of the accumulator completing the addition operation in one clock cycle in the prior art.

[0055] See also Figure 2, the figure shows the ideal timing of the accumulator completing the addition operation in one clock cycle in the prior art. Generally speaking, the input data or output result will be synchronously accompanied by an independent valid indication signal valid, and participate in the transmission and calculation together. The high level (1) indicates that the data at this moment is valid, and the low level (0) indicates that the data at this moment is invalid. At time T1, the first data A1 is input, and the secondary input is 0. If the timing requirements are met, the first addition result B=A1+0=A1 is obtained at time T2. At time T2, the B input is switched to the adder and added with the second data A2, and the result B=A1+A2 is obtained at time T3. And so on, finally at time T8, the result B=A1+A2+A3+A4+A5+A6+A7 is obtained. Obviously, when the timing requirements are met, the addition result can be generated in the next cycle of the main input data, which is the most efficient.

[0056] As the operating frequency of the chip becomes higher and higher, the clock cycle becomes shorter and shorter, and it is likely that the addition calculation cannot be completed with only one clock cycle.

[0057] Figure 3 FIG. 2 shows an ideal timing diagram of the accumulator completing the addition operation in two clock cycles in the prior art. Figure 3 , the figure shows the ideal timing of the accumulator completing the addition operation in 2 clock cycles in the prior art. Assume that the adder cannot produce the result in 1 clock cycle and needs 2 clock cycles. Then, according to the above design idea, see Figure 3 In the middle sequence, the first data A1 is input at time T1, and the second input is 0. Because the addition takes 2 clock cycles, the first result B=A1+0=A1 can only be obtained at time T3. At time T3, A2 is input and added to B, and the second result B=A1+A2 is obtained at time T5.

[0058] As mentioned above, in the existing accumulator design, the addition operation takes longer, resulting in only half of the calculation that can be completed in the same time as the ideal design (a design that can get the addition result in 1 clock cycle). Similarly, for the same amount of input data, if the number of clock cycles for addition increases, the total time of the operation will increase exponentially accordingly, greatly reducing the operation efficiency. For today's rapidly developing chip design, this operation efficiency problem is becoming more and more prominent.

[0059] Therefore, the present invention proposes an accumulator and a method and computing device for an accumulator, which can reduce the time consumption of accumulation operation and significantly improve the efficiency of accumulation operation on the basis of adapting to the operating frequency of the chip. According to the embodiment, by selecting data and adapting to the clock cycle completed by a single accumulation operation of the accumulator, the grouped accumulation of the external input data is realized to obtain the accumulated intermediate result, and the accumulated intermediate result is cached and fed back to the data accumulation feedback unit, and the accumulated intermediate result is accumulated in the data accumulation feedback unit, and finally the accumulated result data is obtained, so that the accumulator can reduce the time consumption of accumulation operation and significantly improve the efficiency of accumulation operation on the basis of adapting to the operating frequency of the chip circuit. In particular, in the processing of large-scale data accumulation operations, the speed-up effect is more obvious, and the data processing efficiency is doubled.

[0060] Exemplary embodiments of the present invention are described below with reference to the accompanying drawings.

[0061] Figure 4 A schematic diagram of an accumulator is shown according to an example embodiment.

[0062] See also Figure 4 , the figure shows an accumulator according to an example embodiment, the accumulator comprises: a primary input data selection unit 01, a secondary input data selection unit 02, a data accumulation feedback unit 03, wherein,

[0063] The main input data selection unit 01 is used to receive external input data and second accumulated intermediate result data from the data accumulation feedback unit 03 cache, and output the external data to the data accumulation feedback unit 03 in a state of receiving external data in each clock cycle. After the external data input is completed, the second accumulated intermediate result data is output to the data accumulation feedback unit 03; the secondary input data selection unit 02 receives the first accumulated intermediate result data output from the data accumulation feedback unit 03 in accordance with the clock cycle and outputs it to the data accumulation feedback unit 03; the data accumulation feedback unit 03 performs an accumulation operation, obtains the first accumulated intermediate result data after at least two clock cycles, and outputs the first accumulated intermediate result data to the secondary input data selection unit 02. After the external data input is completed, the selected first accumulated intermediate result data is cached, and the cached first accumulated intermediate result data is output as the second accumulated intermediate result data to the main input data selection unit 01, so that the accumulation feedback unit accumulates the first accumulated intermediate result data and the second accumulated intermediate data in subsequent clock cycles.

[0064] According to some embodiments, the main input data selection unit 01 selects external input data or the second accumulated intermediate result data fed back from the data accumulation feedback unit 03 as the main input data. This is usually implemented by a multiplexer (MUX), which can select an input path as output according to a control signal.

[0065] According to some embodiments, the secondary input data selection unit 02 selects the first accumulated intermediate result data accumulated last time or zero as the secondary input data. Similarly, a multiplexer may be used to implement the method.

[0066] According to some embodiments, the data accumulation feedback unit 03 performs an actual addition operation, adds the primary input data to the secondary input data, and generates new first accumulated intermediate result data. It is usually composed of an adder, which can handle the addition operation of binary numbers. In modern designs, the adder can be a full adder, which can handle the carry problem and ensure the accuracy of the calculation.

[0067] According to some embodiments, when the main input data selection unit 01 starts to receive external input data, the secondary input data selection unit 02 inputs N zeros to the data accumulation feedback unit 03 in N consecutive clock cycles, wherein the value of N is the same as the number of clock cycles required for the accumulator to complete a single accumulation operation. In this way, the clock cycle required for the accumulation operation of the accumulator device itself is matched to realize group accumulation, thereby improving the efficiency of data accumulation operation.

[0068] Figure 5 A diagram of an accumulator structure according to an example embodiment is shown.

[0069] See also Figure 5 , the figure shows an accumulator structure according to an example embodiment, wherein the main input data selection unit 01 includes: a first multiplexer 0101, the first multiplexer 0101 is used to select the external input data or the second accumulated intermediate result data stored in the data accumulation feedback unit as the main input data to be output to the data accumulation feedback unit 03; or directly select 0 as the main input data to be output to the data accumulation feedback unit 03.

[0070] According to some embodiments, specifically, the main input data selection unit 01 includes a first multiplexer 0101. When new data needs to be added to the accumulation process, the first multiplexer 0101 can be made to select external input data as the main input data through a control signal. Alternatively, in the process of continuous accumulation, in order to maintain the continuity of accumulation, the accumulation result of the previous cycle stored in the feedback register unit can be selected as the main input data, which helps to realize the function of continuous accumulation.

[0071] According to some embodiments, the main input data selection unit also receives an input of data 0, and if the external input data is invalid data during the external input data input period, the main input data selection unit outputs 0 to the data accumulation feedback unit 03. If the external input data is discontinuous data during the external data input period, the main input data selection unit outputs 0 to the data accumulation feedback unit 03 corresponding to the discontinuous data position. When the external input data is discontinuous or invalid data appears or a new accumulation process is started, the accumulator needs to be reset. At this time, the first multiplexer 0101 selects 0 as the main input data. Selecting 0 can effectively clear the accumulator so that it starts a new accumulation operation from zero. The first multiplexer 0101 of the main input data selection unit 01 is an important component in the accumulator design. It provides the accumulator with the necessary flexibility and functionality by selecting different input data.

[0072] According to some embodiments, the secondary input data selection unit 02 includes: a second multiplexer 0201, the second multiplexer 0201 is used to output the first accumulation result data from the data accumulation feedback unit 03 as the secondary input data to the data accumulation feedback unit 03; or directly select 0 as the secondary input data to output to the data accumulation feedback unit 03. The second multiplexer 0201 outputs the first accumulation intermediate result data from the data accumulation feedback unit 03 as the secondary input data to the data accumulation feedback unit 03. When it is necessary to start a new accumulation process from zero, the second multiplexer 0201 selects 0 as the secondary input data. In this way, the current accumulation intermediate result of the accumulator will be cleared to start a new accumulation operation.

[0073] According to some embodiments, in a programmable logic device (such as an FPGA) or a microcontroller, the selection logic of the first and second multiplexers 0201 can be configured by a programming language, so as to flexibly change the selection logic to adapt to different application scenarios. Alternatively, the selection logic of the first and second multiplexers can be controlled by a control signal. By flexibly selecting input data, a variety of different calculation modes can be effectively supported, thereby improving the versatility and flexibility of the accumulator.

[0074] According to some embodiments, the data accumulation feedback unit 03 includes a data accumulation unit and a feedback register unit, wherein the data accumulation unit performs an accumulation operation, and after the external data input is completed, outputs the selected first accumulated intermediate result data to the feedback register unit; the feedback register unit caches the received first accumulated intermediate result data, uses the cached first accumulated intermediate result data as the second accumulated intermediate result data, and outputs the second accumulated intermediate result data to the main input data selection unit according to a predetermined clock cycle. The data accumulation unit includes: an adder 0301, the adder 0301 performs an addition operation of the main input data and the secondary input data, obtains the result of the addition operation, namely, the first accumulated intermediate result data and the second accumulated intermediate result data, and outputs the first accumulated intermediate result data to the secondary input data selection unit 02, and outputs the second accumulated intermediate result data to the feedback register unit. The adder is used to perform an accumulation operation, and after the external data input is completed, outputs the selected first accumulated intermediate result data to the feedback register unit; the feedback register unit caches the received first accumulated intermediate result data and uses it as the second accumulated intermediate result data, and outputs the second accumulated intermediate result data to the main input data selection unit according to a predetermined clock cycle.

[0075] According to some embodiments, the data accumulation unit is configured to: receive input data in a first clock cycle, output the first accumulated intermediate result data in the N+1th clock cycle, and output it to the secondary input data selection unit 02, where N is an integer greater than 1; and output the first accumulated intermediate result data to the feedback register unit in the next clock cycle after the external data input is completed.

[0076] According to some embodiments, the feedback register unit is used to store the first accumulated intermediate result so as to output it to the main input data selection unit as the second accumulated result number in the next clock cycle. The feedback register unit includes: a register 0303, and the register 0303 is used to cache the first accumulated intermediate result data and output it to the main input data unit. It can be implemented by register 0303, and register 0303 can save data under the triggering of the clock signal. In this way, when the system is in a stable state, the value in register 0303 will not change until a new accumulated result is written. Generally speaking, the register 0303 can be implemented by a D flip-flop (D Flip-Flop), which can store and output data under the control of the clock signal.

[0077] According to some embodiments, the feedback register unit is configured to: after caching the first accumulated intermediate result data, output the cached first accumulated intermediate result data as the second accumulated intermediate result data to the main input data selection unit 01 in a subsequent clock cycle or according to a predetermined clock cycle, so that the first accumulated intermediate result data and the second accumulated intermediate result data are aligned and accumulated through the data accumulation unit. By designing the predetermined clock cycle of the register 0303, the accumulator can cooperate with the working frequency of the chip circuit to realize the grouped accumulation of external input data, thereby greatly improving the data processing capability and efficiency of large-scale accumulation operations.

[0078] Figure 6 A flow chart of a method for an accumulator according to an example embodiment is shown.

[0079] Figure 7 A schematic diagram of a method for an accumulator according to an example embodiment is shown.

[0080] See also Figure 6 as well as Figure 7 , a flow chart of a method for an accumulator according to an example embodiment is shown, the accumulator comprising a first data channel and a second data channel, the method comprising:

[0081] At S601, the number of clock cycles required for the accumulator to perform a single accumulation operation is obtained.

[0082] According to some embodiments, the adder time, that is, the number of clock cycles from input to output, is determined by the specific design of the adder and the chip process. Once the design is stable and the process is selected, it can be considered fixed and assumed to be N.

[0083] In S603, the input data to be accumulated is obtained and sent to the first data channel of the accumulator, and synchronously, the same number of zeros as the number of clock cycles required for the accumulator to perform a single accumulation operation is input to the second data channel of the accumulator.

[0084] According to some embodiments, the accumulator is initialized, and the input data to be accumulated is input into the first data channel of the accumulator. Synchronously, assuming that the number of clock cycles required for the accumulator to perform a single accumulation operation is N, it is ensured that the input in the second data channel of the accumulator is always 0 within the first N clock cycles.

[0085] In S605, an accumulation operation is performed to obtain first accumulated intermediate result data, and the first accumulated intermediate result data is fed back to the second data channel of the accumulator.

[0086] According to some embodiments, the accumulator performs an addition operation to generate the first accumulated intermediate result, and feeds back the first accumulated intermediate result data to the second data channel.

[0087] In S607, the accumulation operation process is repeated until the input of the input data to be accumulated is completed.

[0088] According to some embodiments, the accumulation operation of S605 is continued until all input data to be accumulated have been input.

[0089] In S609, after the input data to be accumulated is input, the selected first accumulated intermediate result data is cached and fed back to the first data channel of the accumulator as second accumulated intermediate result data for subsequent accumulation.

[0090] According to some embodiments, the first accumulated intermediate result data is cached as the second accumulated intermediate result data, and a final accumulation operation is prepared. The first accumulated intermediate result data is cached in a register, and the cached first accumulated intermediate result data is fed back to the first data channel as the second accumulated intermediate result data.

[0091] In S611, the previous step is repeated until all the accumulated intermediate result data are accumulated to obtain the final accumulated result data.

[0092] According to some embodiments, the accumulation operation of the accumulated intermediate results is continued until all accumulated intermediate results have been accumulated to obtain a final accumulated result.

[0093] According to some embodiments, see Figure 7 Specifically, first, determine the number of clock cycles required for the accumulator to perform a single accumulation operation, that is, the adder time, that is, the number of clock cycles from input to output. It is determined by the specific design of the adder and the chip process. Once the design is stable and the process is selected, it can be considered fixed and assumed to be N. After that, start the accumulation and input the data to be accumulated into the accumulator. This data is the main input of the adder. Synchronously select 0 for the secondary input of the adder, repeat the above steps to input a total of N 0s, and select the accumulation result to the secondary input.

[0094] According to some embodiments, before the data to be accumulated is input, if invalid data appears at a certain moment, it is replaced by 0 and assigned to the main input. In general, each data to be accumulated has an independent data valid indication signal, which is synchronously transmitted or calculated with the data. For example, if this indication signal is 1, it means that the data is valid at this moment, and if it is 0, it means that the data is invalid at this moment. If there is no such indication signal, then before inputting the data, the accumulator must first insert 0 into the invalid moment, or squeeze out the invalid moment so that all the data are closely adjacent. For example, if there is no such indication signal, you want to accumulate 7 data, but the 7 data are not consecutively adjacent, such as A1, C1, A2, A3, A4, A5, A6, A7, and the result is A1+C1+A2+A3+A4+A5+A6+A7. Obviously, the result is wrong, unless C1=0, or C1 is removed first, so that A1 and A2 are in adjacent clock cycles.

[0095] According to some embodiments, if all data have been input, the next step is performed, otherwise the accumulation operation is repeated. The accumulator calculation will generate corresponding calculation results in sequence, and the intermediate results are stored in registers. The register is selected to the main input of the accumulator to obtain a new addition intermediate result. Until all the intermediate results have been accumulated, the final accumulation result is obtained, and the calculation is completed.

[0096] Figure 8 An ideal timing diagram showing an accumulator completing an addition operation in 2 clock cycles according to an example embodiment is shown.

[0097] See also Figure 5 From the example of the accumulator in FIG. 1 , it is not difficult to see that the design of the present invention does not change much compared with the ideal design of the prior art. Among them, the main input of the adder is no longer fixed to A, but may also be the register B_reg output by B or 0. Assume that the accumulator takes 2 clock cycles to complete the addition calculation, see Figure 8 In the middle timing, a total of 7 data (assuming they are A1, A2, A3, A4, A5, A6, and A7) are accumulated. The first data A1 is input at time T1, and the secondary input is 0. Because the accumulator addition takes 2 clock cycles, the corresponding addition result B=A1+0=A1 is obtained at time T3. Data A2 continues to be input at time T2, and the secondary input is still 0, so the corresponding addition result B=A2+0=A2 is obtained at time T4. The third data A3 is input at time T3, and the secondary input is switched to B, so the corresponding addition result B=A1+A3 is obtained at time T5. Similarly, A7 is input at time T7, and the corresponding addition result B=A1+A3+A5+A7 is obtained at time T9. The 7 A data have been input, and no data will be input from time T8.

[0098] According to some embodiments, any value position in the diagram can be replaced by 0, or it can be left unchanged and use the old value by default. For example, any value + B of T8 will get the result in T10, but this design does not use the result of T10, so T8 allows the main input to be any value. Similarly, the result of T10 is also regarded as any value.

[0099] At time T8, the addition result B=A2+A4+A6 is obtained. At this time, the result is saved in a register, that is, B_reg=A2+A4+A6 at time T9. At time T9, the main input of the adder selects B_reg, so the two inputs of the adder at time T9 are B_reg=A2+A4+A6 and B=A1+A3+A5+A7, and the corresponding addition result B=A1+A3+A5+A7+A2+A4+A6 is obtained at time T11, completing the accumulation.

[0100] It also takes 2 clock cycles to complete the cumulative calculation. Compared with the conventional design that obtains the cumulative result at T15, the design of the present invention can obtain the cumulative result at T11, and the efficiency is improved by about 27%. Moreover, after the input data to be accumulated is input, the time consumption of the later 4 clock cycles is fixed and will not increase with the increase of the amount of A data. That is to say, no matter how many A data there are in total, as long as it is all input, it will only take 4 clock cycles to get the final cumulative result. Assuming a total of 100 A data, the result will be obtained at T104, while the result of the conventional design is obtained at T201. In comparison, the cumulative efficiency of the design of the present invention is improved by about 50%.

[0101] Fig. 9 An ideal timing diagram showing an accumulator completing an addition operation in three clock cycles according to another example embodiment is shown.

[0102] See also Figure 5 In the example, assume that the accumulator takes 3 clock cycles to complete the addition calculation, see Fig. 9 In the timing of , 7 data are still input to A. The design scheme according to the present invention can obtain the result at time T15, while the conventional design according to the prior art obtains the result at time T22. In comparison, the design scheme of the present invention improves the cumulative efficiency by about 32%.

[0103] Fig.10 An ideal timing diagram showing an accumulator completing an addition operation in 2 clock cycles when input is discontinuous according to another example embodiment.

[0104] See also Fig.10, the figure shows the ideal timing for the accumulator to complete the addition operation in 2 clock cycles when the input is discontinuous according to another example embodiment, wherein the method further includes: if the input data to be accumulated is non-continuous data, the discontinuous positions of the input data to be accumulated are filled with 0 and input into the first data channel of the accumulator. Ensure the continuity of the input data. Determine the position where the data is discontinuous, fill the discontinuous position with 0, and send the filled data to the first data channel. In all the above examples, the data A to be accumulated is completely continuous, which is basically impossible to appear in the actual operation process. The real A should be discontinuous. When A is discontinuous, 0 should be selected for the main input of the adder.

[0105] According to some embodiments, the method further comprises: if the input data to be accumulated at a certain moment is invalid data, directly replacing the input data to be accumulated with 0 and inputting it into the first data channel of the accumulator. To ensure the validity of the input data, if the input data is invalid data, replace the invalid data with 0, and send the valid or replaced data to the first data channel. When A is discontinuous, that is, when A is an invalid value at a certain moment, select 0 as the main input of the adder, that is, use 0 for accumulation. See Fig.10 , the last data A to be accumulated appears at time T16, and the accumulated result is still generated at time T20 after 4 clock cycles. It is also easy to understand from a mathematical point of view. If 7 valid data are input, even if 10 zeros are added, the final accumulated result must be equal. Before the main input ends, invalid values ​​are replaced with 0. After the main input is completed, the intermediate results are transferred to the main input and the iterative accumulation continues. As long as N is not a very large value (usually the addition time is not very long, otherwise either the adder must be redesigned or the chip technology is too backward), and the amount of data in the main input is not a very small value, this design will be more efficient than the conventional design, and the larger the amount of data in the main input, the more obvious the efficiency improvement.

[0106] According to some embodiments, the design of the present invention assigns N zeros to the secondary input of the accumulator, where N is the number of clock cycles required for the accumulator to perform a single accumulation operation, and the number of clock cycles is determined by the specific design of the accumulator and the chip process, and is a fixed value for the chip. In the design of the present invention, a method that adapts to the execution clock cycle of the accumulator is used to implement the interval accumulation of the data to be accumulated, replacing the traditional sequential accumulation, which greatly improves the efficiency of the accumulation operation.

[0107] According to some embodiments, the design scheme of the present invention can be applied to the design of an integrated circuit chip, wherein the chip circuit includes the accumulator as described above, which can reduce the time consumption of accumulation operation and significantly improve the efficiency of accumulation operation on the basis of adapting to the operating frequency of the chip circuit.

[0108] According to some embodiments, the design scheme of the present invention is aimed at accumulators that cannot complete addition calculations in 1 clock cycle. It does not need to align the intermediate results and the data to be accumulated, and the operation is simple, which can significantly reduce the total calculation time. Before the data to be accumulated is input, 0 is used to replace the invalid data for normal accumulation, and the input of the accumulator is accumulated in batches. After the input is completed, the intermediate results are iteratively accumulated. Compared with the accumulator of the prior art, it can better adapt to the operating frequency of the chip circuit and improve the processing efficiency of large batches of data to be accumulated.

[0109] Fig.11 A block diagram of a computing device according to an example embodiment of the invention is shown.

[0110] like Fig.11 As shown, computing device 30 includes processor 12 and memory 14. Computing device 30 may also include bus 22, network interface 16, and I / O interface 18. Processor 12, memory 14, network interface 16, and I / O interface 18 may communicate with each other via bus 22.

[0111] The processor 12 may include one or more general-purpose CPUs (Central Processing Units, processors), microprocessors, or application-specific integrated circuits, etc., for executing relevant program instructions. According to some embodiments, the computing device 30 may also include a high-performance graphics card (GPU) 20 for accelerating the processor 12.

[0112] The memory 14 may include a machine system readable medium in the form of a volatile memory, such as a random access memory (RAM), a read-only memory (ROM) and / or a cache memory. The memory 14 is used to store one or more programs including instructions and data. The processor 12 may read the instructions stored in the memory 14 to execute the above-mentioned method according to the embodiment of the present invention.

[0113] The computing device 30 may also communicate with one or more networks via the network interface 16. The network interface 16 may be a wireless network interface.

[0114] The bus 22 may include an address bus, a data bus, a control bus, etc. The bus 22 provides a path for exchanging information between components.

[0115] It should be noted that, in the specific implementation process, the computing device 30 may also include other components necessary for normal operation. In addition, those skilled in the art may understand that the above device may only include components necessary for implementing the embodiments of this specification, and need not include all components shown in the figure.

[0116] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when the program is executed by a processor. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a micro drive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), a network storage device, a cloud storage device, or any type of medium or device suitable for storing instructions and / or data.

[0117] An embodiment of the present invention also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute part or all of the steps of any method recorded in the above method embodiments.

[0118] Those skilled in the art can clearly understand that the technical solution of the present invention can be implemented with the help of software and / or hardware. "Unit" and "module" in this specification refer to software and / or hardware that can independently complete or cooperate with other components to complete specific functions, where the hardware can be, for example, a field programmable gate array, an integrated circuit, etc.

[0119] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0120] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0121] In the several embodiments provided by the present invention, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0122] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0123] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0124] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention.

[0125] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0126] The exemplary embodiments of the present invention are specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present invention is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended clauses.

Claims

1. An accumulator, characterized in that: include: A main input data selection unit, a secondary input data selection unit, and a data accumulation feedback unit, wherein: The main input data selection unit is used to receive external input data and second accumulated intermediate result data from the data accumulation feedback unit cache, and output the external data to the data accumulation feedback unit in a state of receiving external data in each clock cycle, and output the second accumulated intermediate result data to the data accumulation feedback unit after the external data input is completed; The secondary input data selection unit receives the first accumulated intermediate result data outputted from the data accumulation feedback unit according to the clock cycle and outputs the first accumulated intermediate result data to the data accumulation feedback unit; The data accumulation feedback unit performs an accumulation operation, obtains the first accumulated intermediate result data after at least two clock cycles, and outputs the first accumulated intermediate result data to the secondary input data selection unit. After the external data input is completed, the selected first accumulated intermediate result data is cached, and the cached first accumulated intermediate result data is output as the second accumulated intermediate result data to the main input data selection unit, so that the data accumulation feedback unit accumulates the first accumulated intermediate result data and the second accumulated intermediate result data in subsequent clock cycles. The data accumulation feedback unit includes a data accumulation unit and a feedback storage unit, wherein: The data accumulation unit performs an accumulation operation, and after the external data input is completed, outputs the selected first accumulation intermediate result data to the feedback register unit; The feedback register unit caches the received first accumulated intermediate result data, uses the cached first accumulated intermediate result data as the second accumulated intermediate result data, and outputs the second accumulated intermediate result data to the main input data selection unit according to a predetermined clock cycle.

2. The accumulator according to claim 1, characterized in that When the main input data selection unit starts to receive external input data, the secondary input data selection unit inputs N zeros to the data accumulation feedback unit in N consecutive clock cycles, wherein the value of N is the same as the number of clock cycles required for the accumulator to complete a single accumulation operation.

3. The accumulator according to claim 1, characterized in that The data accumulation unit is configured as follows: receiving input data in a first clock cycle, outputting the first accumulated intermediate result data in an N+1th clock cycle, and outputting the first accumulated intermediate result data to the secondary input data selection unit, where N is an integer greater than 1; The first accumulated intermediate result data is output to the feedback register unit in the next clock cycle after the external data input is completed.

4. The accumulator according to claim 3, characterized in that The feedback register unit is configured to output the cached first accumulated intermediate result data as the second accumulated intermediate result data to the main input data selection unit in a subsequent clock cycle or according to a predetermined clock cycle after caching the first accumulated intermediate result data, so that the first accumulated intermediate result data and the second accumulated intermediate result data are aligned and accumulated by the data accumulation unit.

5. The accumulator according to claim 1, characterized in that: The main input data selection unit also receives an input of data 0. If the external input data input during the external data input period is invalid data, the main input data selection unit outputs 0 to the data accumulation feedback unit.

6. The accumulator according to claim 1, characterized in that: The main input data selection unit also receives an input of data 0. If the external input data is non-continuous data during the external data input period, the main input data selection unit outputs 0 to the data accumulation feedback unit corresponding to the non-continuous data position.

7. A method for an accumulator according to any one of claims 1 to 6, characterized in that The accumulator includes a first data channel and a second data channel, and the method includes: Get the number of clock cycles required for the accumulator to perform a single accumulation operation; Acquire input data to be accumulated, and send the input data to be accumulated to a first data channel of the accumulator, and synchronously input a number of zeros equal to the number of clock cycles required for the accumulator to perform a single accumulation operation to a second data channel of the accumulator; Performing an accumulation operation to obtain first accumulated intermediate result data, and feeding the first accumulated intermediate result data back to the second data channel of the accumulator; After the input data to be accumulated is inputted, the selected first accumulated intermediate result data is cached and fed back to the first data channel of the accumulator as second accumulated intermediate result data for subsequent accumulation.

8. An integrated circuit chip, characterized in that: Comprising an accumulator according to any one of claims 1-6.

9. A computing device, characterized in that include: processor; as well as A memory storing a computer program, which, when executed by the processor, causes the processor to execute the method as claimed in claim 7.

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