Data processing system, method and processor

Abstract

The invention discloses a data processing system and method and a processor. The system relates to the field of processors and comprises an instruction caching module, an instruction decoding module, an instruction distribution module and an instruction execution module, and the instruction caching module is connected with a scalar core and used for receiving and caching an instruction payload sent by the scalar core; the instruction decoding module is connected with the instruction caching module and is used for decoding and splitting at least one vector instruction contained in the instruction effective load to obtain instruction data of the at least one vector instruction; the instruction distribution module is connected with the instruction decoding module and is used for distributing the instruction data to at least one instruction execution module based on the data characteristics of the instruction data; and the instruction execution module is used for executing the received instruction data. The technical problem that the vector instruction processing efficiency is affected due to the fact that the expandability of a processor is poor in the related technology is solved.

Description

Technical Field

[0001] The present application relates to the field of processors, and in particular, to a data processing system, method and processor. Background Art

[0002] As the demand for AI (Artificial Intelligence) applications continues to grow, the computing power requirements of processors are also increasing. When the processor processes vector instructions in different scenarios, the computing power required is also different. Processors configured according to conventional parameters may not be able to effectively process vector instructions with large computing power requirements, and when processing vector instructions with small computing power requirements, processing resources may be wasted, affecting the efficiency of processing different vector instructions.

[0003] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0004] The embodiments of the present application provide a data processing system, method and processor to at least solve the technical problem in the related art that the scalability of the processor is poor, which affects the efficiency of processing vector instructions.

[0005] According to one aspect of an embodiment of the present application, a data processing system is provided, including: an instruction cache module, connected to a scalar core, for receiving and caching an instruction payload sent by the scalar core; an instruction decoding module, connected to the instruction cache module, for decoding and splitting at least one vector instruction contained in the instruction payload to obtain instruction data of at least one vector instruction; an instruction allocation module, connected to the instruction decoding module, for allocating instruction data to at least one instruction execution module based on data features of the instruction data, wherein the number of instruction execution modules and the register width of the instruction execution modules are determined by the computing power requirements of the processor; and an instruction execution module, for executing the received instruction data.

[0006] According to another aspect of an embodiment of the present application, a data processing method is also provided, including: receiving an instruction payload sent by a scalar core; decoding and splitting at least one vector instruction contained in the instruction payload to obtain at least one instruction data; based on data characteristics of the instruction data, allocating the instruction data to at least one instruction execution module, wherein the number of instruction execution modules and the register width of the instruction execution modules are determined by the computing power requirements of the processor; and executing the instruction data based on the instruction execution module.

[0007] According to another aspect of an embodiment of the present application, a data processing method is also provided, including: receiving an instruction payload sent by a scalar core by calling a first interface; decoding and splitting at least one vector instruction contained in the instruction payload to obtain at least one instruction data; based on data characteristics of the instruction data, allocating the instruction data to at least one instruction execution module, wherein the number of instruction execution modules and the register width of the instruction execution modules are determined by the computing power requirements of the processor; executing the instruction data based on the instruction execution module; and outputting the execution result of the instruction data by calling a second interface.

[0008] According to another aspect of an embodiment of the present application, a processor is also provided, comprising any one of the data processing systems described above.

[0009] According to another aspect of an embodiment of the present application, a system on chip is also provided, comprising any one of the data processing systems described above.

[0010] According to another aspect of an embodiment of the present application, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored executable program, wherein when the executable program is running, the device where the computer-readable storage medium is located is controlled to execute the methods in each embodiment of the present application.

[0011] According to another aspect of the embodiments of the present application, a computer program product is also provided, including a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present application is implemented.

[0012] According to another aspect of an embodiment of the present application, a computer program product is also provided, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method in each embodiment of the present application is implemented.

[0013] According to another aspect of the embodiments of the present application, a computer program is also provided, and when the computer program is executed by a processor, the methods in the various embodiments of the present application are implemented.

[0014] In an embodiment of the present application, a data processing system including an instruction cache module, an instruction decoding module, an instruction allocation module and an instruction execution module is adopted. The number and register width of the instruction execution modules are adaptively changed according to the computing power requirements of the processor, which can effectively improve the matching degree between the instruction execution modules and the vector instructions, thereby solving the technical problem that the scalability of the processor in the related technology is poor, which affects the efficiency of processing vector instructions.

[0015] It is easy to notice that the above general description and the following detailed description are only for the purpose of exemplifying and explaining the present application, and do not constitute a limitation of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 is a structural block diagram of a data processing system according to the present application;

[0018] Figure 2 It is a schematic diagram of a design structure of an instruction execution module according to the present application;

[0019] Figure 3 is a structural block diagram of an instruction execution module according to the present application;

[0020] Figure 4 is a schematic diagram of a vector instruction splitting result shown in the present application;

[0021] Figure 5 is a schematic diagram of a vector instruction execution process shown in the present application;

[0022] Figure 6 is a schematic diagram of a register device connection structure according to the present application;

[0023] Figure 7 is a schematic diagram of a detailed structure of a data processing system according to the present application;

[0024] Figure 8 is a schematic diagram of a processor structure according to the present application;

[0025] Fig. 9 It is a hardware structure block diagram of a RISC-V system for implementing a data processing method according to the present application;

[0026] Fig.10 It is a schematic diagram of a system on a chip of a RISC-V architecture shown in the present application;

[0027] Fig.11 is a flow chart of a data processing method according to the present application;

[0028] Fig.12 It is a flowchart of another data processing method according to the present application. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following explanations:

[0032] Scalar Core: A scalar core is an execution unit that processes scalar instructions, such as instructions that can process scalar integer or scalar floating-point types.

[0033] Vector Unit: A vector unit is an execution unit used to process vector instructions, such as computing instructions and memory access instructions.

[0034] GIU: General Interface Unit, a general interface unit used to output data generated by different processing units, such as scalar cores and vector units.

[0035] According to an embodiment of the present application, a data processing system is provided. The data processing system may be a vector unit for processing vector instructions. Figure 1 is a structural block diagram of a data processing system according to the present application, such as Figure 1 As shown, the data processing system may include:

[0036] The instruction cache module 102 is connected to the scalar core 104 and is used to receive and cache instruction payloads sent by the scalar core 104 .

[0037] In an optional scheme of the present embodiment, in order to improve the efficiency of the processor in processing different instructions, different processing units in the processor can be used to perform different processing tasks. For example, the processor can send scalar instructions such as addition and subtraction, logical operations, etc. to the scalar core for processing, and send vector instructions such as vector reduction, displacement, dot product, etc. to the vector unit for processing, so as to improve the efficiency of the processor in processing different instructions. Correspondingly, in order to ensure that the vector unit can smoothly execute vector instructions, when receiving a vector instruction, the scalar core can send the load of the vector instruction, such as the operands and operation types corresponding to the vector instruction, to the vector unit to assist the vector unit in executing the corresponding vector instruction. In order to ensure the efficiency of the vector unit in processing the vector instructions stored in the instruction payload and the related data of the vector execution, the above-mentioned instruction cache module Instruction Buffer can be configured in the vector unit, and the instruction cache module can be connected to the scalar core. When the scalar core sends the load of the vector instruction to the vector unit, the instruction cache module in the vector unit can receive and cache the instruction payload, and perform instruction prefetch operations on the instruction payload in the instruction cache module, thereby reducing the events of the vector unit loading the data in the instruction payload, thereby improving the efficiency of the vector unit in executing vector instructions.

[0038] The instruction decoding module 106 is connected to the instruction cache module 102 and is used to decode and split at least one vector instruction included in the instruction payload to obtain instruction data of the at least one vector instruction.

[0039] In an optional scheme of the present embodiment, in order to accurately perform vector execution, the above-mentioned instruction decoding module can also be configured in the vector unit, and the instruction decoding module can be connected to the instruction cache module. After the instruction cache module receives and caches the instruction payload sent by the scalar core, the vector unit can use the instruction decoding module to decode and split the at least one vector instruction contained in the instruction payload to obtain the instruction data of the at least one vector instruction.

[0040] The instruction allocation module 108 is connected to the instruction decoding module 106 and is used to allocate the instruction data to at least one instruction execution module 110 based on data characteristics of the instruction data.

[0041] The number of instruction execution modules 110 and the register width of the instruction execution modules are determined by the computing power requirements of the processor.

[0042] In an optional scheme of the present embodiment, in order to improve the efficiency of executing vector instructions, the above-mentioned instruction dispatch module Instruction Dispatch and the instruction execution module LANE for processing different instruction data can be configured in the vector unit. Correspondingly, the instruction dispatch module can be connected to the instruction decoding module and the instruction execution module. After the vector unit uses the instruction decoding module to decode and split the instruction payload to obtain instruction data, the instruction dispatch module can be further used to distribute the obtained instruction data to different instruction execution modules, so that the vector unit can process multiple vector instructions in parallel, thereby improving the parallel processing capability and throughput of the processor while making full use of processing resources. Considering that different vector instructions may have different operands, data types or operation types, different processing resources may be consumed accordingly, and the efficiency of different instruction execution modules in processing different instruction data may be different, and the corresponding processing resources available in the instruction execution modules may also be different. Therefore, in order to improve the efficiency of using instruction execution modules to process instruction data of different vector instructions, the vector unit can be used in the instruction allocation module to perform feature extraction on the obtained instruction data to obtain data features of different instruction data, and then allocate different instruction data to appropriate instruction execution modules according to the extracted data features to ensure the efficiency of using the instruction execution module to process the received instruction data.

[0043] In an optional solution of this embodiment, considering that the computing power requirements of the processor are different when processing different vector instructions, in order to match the vector instructions with appropriate instruction execution modules to improve the efficiency of processing vector instructions and avoid wasting processing resources, the number and register width of the above instruction execution modules can be determined by the computing power requirements of the processor. For ease of understanding, Figure 2 is a schematic diagram of a design structure of an instruction execution module according to the present application, such as Figure 2 As shown, when the processor currently needs a 512-bit Vector Length, it can be Figure 2 As shown on the left, four LANEs with a register width of 128 bits are set, namely LANE0-3. When the processor currently needs a VectorLength of 1024 bits, it can be as follows Figure 2 As shown on the right, eight LANEs with a register width of 128 bits are set, namely LANE0-7.

[0044] The instruction execution module 110 is used to execute the received instruction data.

[0045] In an optional scheme of this embodiment, after using the instruction allocation module to allocate different instruction data to the instruction execution module, the vector unit can use the instruction execution module to execute the corresponding instruction data, thereby obtaining the corresponding data execution results. After different instruction execution modules execute the received instruction data and output the corresponding data execution results, the vector unit can summarize the data execution results output by different instruction execution modules to obtain the execution results corresponding to different vector instructions.

[0046] In an embodiment of the present application, the instruction execution module includes: a data allocation unit, which is used to allocate the received instruction data to at least one issuance queue based on the data type of the received instruction data; an issuance queue, which is used to cache the instruction data; a data transmission network, which is connected to the issuance queue, and is used to transmit the instruction data to the data processing unit based on the data type of the instruction data stored in the issuance queue; and a data processing unit, which is used to process the received instruction data based on a preset processing logic to obtain a data processing result, wherein the preset processing logic corresponds to the data type.

[0047] In an optional scheme of the present embodiment, in order to improve the efficiency of processing instruction data, at least the above-mentioned data distribution unit Dispatch, issue queue Issue Queue, data transmission network Bypass Network and data processing unit can be configured in the instruction execution module, and the issue queue can be connected to the data distribution unit, the data transmission network can be connected to the issue queue, and the data processing unit can be connected to the data transmission network, wherein the data distribution unit can be used to parse the data type of the instruction data, and send the corresponding instruction data to different issue queues according to the parsed data type, different issue queues can be used to cache instruction data of different data types, the data transmission network can be used to send different instruction data to different data processing units according to the data type of the instruction data stored in the issue queue, and different data processing units can be used to process instruction data of different data types. Based on this, when using the instruction execution module to process instruction data, the data type of the received instruction data can be analyzed by the data allocation unit to determine the data types of different instruction data, and then the corresponding instruction data can be allocated to different issuance queues according to different data types, and the received instruction data can be cached in the issuance queue. Then, using the data transmission network, the instruction data stored in the issuance queue can be sent to the data processing unit according to different data types, so that the data processing unit can process the received instruction data according to the preset processing logic that matches the data type.

[0048] In an embodiment of the present application, the instruction execution module also includes: a vector register unit, connected to the data processing unit and the data transmission network, for storing data processing results and sending the data processing results to the data transmission network; a data transmission network, for transmitting the data processing results to the processing line cross-execution unit; a processing line cross-execution unit, connected to the data transmission network and the routing communication unit, for sending the first execution data of the instruction execution module to the routing communication unit, and receiving the second execution data sent by the routing communication unit, wherein the first execution data includes the data processing results, and the second execution data is used to represent the data sent by other instruction execution modules.

[0049] In an optional solution of the present embodiment, considering that there may be Reduction / Widen (data reduction / expansion) type instructions in the received vector instructions, multiple instruction execution modules may need to be used in the vector unit to collaboratively process such instructions. Correspondingly, data exchange is usually required between the instruction execution modules used to execute such instructions to ensure the accuracy of executing such vector instructions. Therefore, in order to ensure that data can be exchanged smoothly between different instruction execution modules, the above-mentioned vector register unit Virtual Register File and the processing line cross execution unit Cross Lane Execution can also be configured in the instruction execution module. Unit (abbreviated as XLANE or CLANE) and a routing communication unit Router, and connect the vector register unit with the data processing unit and the data transmission network, and connect the processing line cross execution unit with the data transmission network and the routing communication unit, wherein the vector register unit can be used to temporarily store the data processing result output by the data processing unit, the data transmission network can merge the data processing result stored in the vector register unit with the instruction data related to the above-mentioned data reduction / expansion class instructions in the instruction payload to obtain the first execution data, the processing line cross execution unit can be used to output the first execution data, and the routing communication unit can be used to exchange data between different instruction execution modules, such as exchanging the first execution data. Based on this, when the vector instruction is a data reduction / expansion type instruction, the vector unit can use the above-mentioned vector register unit in the instruction execution module to temporarily store the data processing results output by different data processing units, and send the data processing results to the data transmission network. The data transmission network integrates the data processing results and the above-mentioned instruction data related to the data reduction / expansion type instructions to obtain first execution data, and then sends the integrated first execution data to the processing line cross-execution unit. After receiving the first execution data, the processing line cross-execution unit can send the first execution data to the routing communication unit, which forwards it to the processing line cross-execution unit in other instruction execution modules. Correspondingly, the processing line cross-execution unit can also receive the second execution data sent by other instruction execution modules from the routing communication unit to realize data exchange between different instruction execution modules.

[0050] In an embodiment of the present application, the instruction execution module also includes: a renaming unit, connected to the data allocation unit, for adjusting the register name contained in the instruction data and sending the adjusted instruction data to the data allocation unit; the renaming unit is also connected to the vector register unit, for adjusting the register name of the vector register based on the register name of the physical register.

[0051] In an optional scheme of the present embodiment, considering that the operands in different vector instructions may point to different registers, when the names of different registers are the same, a reference register conflict may occur, resulting in affecting the efficiency of the instruction execution module in executing instruction data. Therefore, the above-mentioned renaming unit RENAME can also be configured in the instruction execution module, and the renaming unit can be connected to the data allocation unit and the vector register unit, so that the instruction execution module can use the renaming unit to adjust the register name contained in the instruction data, and send the adjusted instruction data to the data allocation unit for data allocation to avoid register name conflicts. At the same time, the renaming unit can also be used to adjust the name of the vector register based on the register name of the physical register to avoid conflicts between the register name of the vector register unit and the register name of the physical register unit.

[0052] To facilitate understanding of the above instruction execution module, Figure 3301 represents a renaming unit, 302 represents a data allocation unit, 303 represents an issue queue, 304 represents a data transmission network, 305 represents a data processing unit, 306 represents a processing line execution unit, 307 represents a vector register unit, and 308 represents a routing communication unit. The connection method of different units can be as shown above and will not be repeated here. It is worth noting that the issue queue can include at least four queues, namely LIQ, SIQ, VIQ and XLIQ, wherein LIQ refers to Load Issue Queue, i.e., a load queue, which can be used to cache data Load Data corresponding to data loading instructions, SIQ refers to Store Issue Queue, i.e., a storage queue, which can be used to cache data Store Data corresponding to data storage instructions, VIQ refers to Vector Issue Queue, i.e., a vector calculation queue, which can be used to cache data corresponding to calculation instructions in vector instructions, i.e., Vector Data, and XLIQ refers to XLANE Issue Queue, i.e., used to cache instruction data related to data reduction / expansion instructions. In the data processing unit, LSU stands for Load and Store Unit, which can be used to process data corresponding to data loading instructions and data storage instructions. VEC stands for vector calculation unit, which can be used to process data corresponding to calculation instructions in vector instructions. In the processing line execution unit, XR stands for receiving execution unit XLANE RECEIVE, which can be used to receive instruction data related to data reduction / expansion instructions, data processing results output by the data processing unit, and second execution data sent by other instruction execution modules forwarded by the communication unit ROUTER. XS stands for sending execution unit XLANE SEND, which can be used to send first execution data to the communication unit ROUTER.

[0053] Figure 4 This is a schematic diagram of a vector instruction splitting result shown in the present application, wherein Calculation corresponds to a calculation unit, which may have 8 execution units such as LANE0-7, and Destination corresponds to a destination unit, which may also have 8 execution units such as LANE0-7. Taking the vector instruction vwaddu.wv vd, vs2, vs1, vm as an example, the bit operation uop obtained by splitting the instruction may be:

[0054] 1st uop:gather tmp1,vs2 / / lane0-lane3

[0055] 2nd uop:addu tmp1,vs1,tmp1, / / lane0-lane3

[0056] 3rd uop:gather tmp1,vs2+1

[0057] 4th uop: addu tmp1,vs1,tmp1

[0058] 5th uop: scatter vd,tmp1

[0059] 6th uop: scatter vd+1,tmp1

[0060] Routing Protocol

[0061] like Figure 4 As shown, the execution units LANE0 and LANE1 in the computing unit can be made to correspond to the execution unit LANE0 in the target unit, the execution units LANE2 and LANE3 in the computing unit can be made to correspond to the execution unit LANE1 in the target unit, the execution units LANE4 and LANE5 in the computing unit can be made to correspond to the execution unit LANE2 in the target unit, and the execution units LANE6 and LANE7 in the computing unit can be made to correspond to the execution unit LANE3 in the target unit. Figure 5 It is a schematic diagram of a vector instruction execution process shown in the present application, wherein the gray part represents the units required to be used when executing the above-mentioned vector instructions. For example, in LANE0-6, the units required to be used are the renaming unit 301, the data allocation unit 302, the XLIQ in the issue queue 303, the data transmission network 304, the processing line execution unit 306, the vector register unit 307 and the routing communication unit 308. In LANE7, the receiving execution unit XLANE RECEIVE in the processing line execution unit 306 may no longer be used.

[0062] For ease of understanding, the English content and the corresponding Chinese interpretation of the routing communication protocol used in the routing communication unit can be shown in Table 1 below, and no further description is given here:

[0063] Table 1

[0064]

[0065]

[0066]

[0067] In an embodiment of the present application, the vector instructions include at least: data loading instructions and data storage instructions, and the instruction cache module includes: a first parsing unit, used to parse the instruction payload to obtain data loading instructions and data storage instructions; a second parsing unit, used to parse the instruction payload to obtain vector instructions.

[0068] In an optional scheme of the present embodiment, considering that vector instructions usually include calculation instructions that require calculation processing on data, as well as data loading instructions Load Instruction and data storage instructions Store Instruction for obtaining data, therefore, in order to ensure the efficiency of processing these calculation instructions, the vector unit can first obtain the data that needs to be processed through data loading instructions and data processing instructions before executing these calculation instructions. Based on this, the vector unit can separately extract the data loading instructions and data storage instructions contained in the instruction payload to quickly obtain the data currently needed to be used according to these two instructions. Correspondingly, the above-mentioned first parsing unit and the second parsing unit can be set in the instruction cache module for parsing the instruction payload, and the first parsing unit is used to parse the instruction payload to obtain the above-mentioned data loading instructions and data storage instructions, and the second parsing unit is used to parse the instruction payload to obtain the above-mentioned vector instructions.

[0069] In an embodiment of the present application, the instruction data includes at least: a load address and a storage address, and the instruction decoding module includes: a look-ahead decoder, which is used to decode and split data loading instructions and data storage instructions to obtain loading addresses and storage addresses, and send the loading addresses and storage addresses to the loading and storage units in the data processing unit; a standard decoder, which is used to decode and split vector instructions to obtain instruction data, and perform correlation detection on the vector instructions based on the instruction data to obtain correlation detection results, wherein the correlation detection results are used to characterize whether there is a conflict between registers corresponding to different vector instructions.

[0070] In an optional solution of the present embodiment, the instruction data may include at least two parts, a load address and a storage address. In order to quickly obtain the data required for different vector instructions, a look-ahead decoder Run-Ahead Decoder and a standard decoder Normal Decoder may be configured in the instruction decoding module. Correspondingly, the look-ahead decoder may be used to decode and split the above-mentioned parsed data loading instructions and data storage instructions to obtain the above-mentioned load address and storage address, and send the load address and storage address to the load and storage unit Load / Store Unit in the data processing unit to quickly obtain and store data. At the same time, the standard decoder may be used to decode and split the above-mentioned parsed vector instructions to obtain the above-mentioned instruction data. In addition, in order to avoid conflicts between registers corresponding to vector instructions and determine whether there is a dependency between different vector qualities, the above-mentioned standard decoder may be used to perform correlation detection on the parsed vector instructions to obtain the above-mentioned correlation detection result. The correlation detection result may also be applied to the above-mentioned renaming unit to rename the registers corresponding to different vector instructions to reduce conflicts when different registers are used.

[0071] In an embodiment of the present application, the data processing system also includes: a mask register, which is used to control the interrupt enable state of the data processing system, wherein the interrupt enable state is used to characterize whether the data processing system executes the interrupt request of the mask register; a reorder buffer, which is connected to the instruction allocation module, the instruction execution module and the mask register, and is used to obtain the instruction status of the vector instruction from the instruction allocation module and the instruction execution module, and update the interrupt ready state of the mask register based on the instruction status, wherein the interrupt ready state is used to characterize whether the interrupt request of the mask register can be read.

[0072] In an optional solution of the present embodiment, in order to facilitate the management of the processor's response to interrupts, the above-mentioned mask register MASK can also be configured in the vector unit, so as to use the mask register to control the data processing system in real time, that is, the interrupt enable state of the vector unit, so as to determine whether the vector unit can execute the interrupt request of the mask register, that is, to determine the interrupt request that the processor can currently accept. At the same time, the above-mentioned reorder buffer ROB (Reorder Buffer) can also be configured in the vector unit, and the reorder buffer is connected to the instruction allocation module, the instruction execution module and the mask register, so as to use the reorder buffer to obtain the instruction status of the vector instruction from the instruction allocation module and the instruction execution module, such as the execution status of the vector instruction, the correlation detection result and other information, and update the interrupt preparation state RDY of the mask register according to the obtained instruction status, so as to determine whether the interrupt request of the mask register can be read.

[0073] Figure 6 601 represents a mask register MASK, 602 represents a reorder buffer ROB, and Figure 6 As shown, the mask register can be connected to the reorder buffer, the instruction allocation module and the different instruction execution modules, and the reorder buffer can be connected to the different instruction execution modules. The vector unit can use the status of different vector instructions determined in the instruction allocation module to clear and update the interrupt preparation status and identification bit of the mask register, and read the interrupt status of the mask register in real time, so that the processor can execute the interrupt request in time. At the same time, the reorder buffer can be used to obtain the data processing results output by different instruction execution modules, and the interrupt preparation status of the mask register can be updated according to the obtained results, so that the processor can read the interrupt enable status of the mask register according to the interrupt preparation status, and receive executable interrupt requests according to the interrupt enable status.

[0074] In order to clearly show the system structure of the data processing system described above, Figure 7 701 represents an instruction payload, 702 represents a look-ahead decoder in an instruction decoding module, 703 represents a standard decoder in an instruction decoding module, 704 represents a load / store list, and 705 represents a memory network. Figure 7As shown, in the vector unit, the instruction cache module can cache the instruction payload sent by the scalar core, and parse the instruction payload to obtain data loading instructions, data storage instructions and all other vector instructions, and then decode and split the data loading instructions and data storage instructions through the look-ahead decoder to obtain the load address and the storage address, and decode and split all the vector instructions through the standard decoder to obtain the vector data of different vector instructions, and the data obtained by decoding and splitting can be sent to the instruction allocation module, and the instruction allocation module directly sends the load address and the storage address to the load / store list, and at the same time, different The instruction data is sent to the instruction execution module for execution, wherein the number of instruction execution modules and the register width can be determined by the computing power requirements of the processor. The instruction execution module can send the data processing results obtained by execution to the memory network, and summarize the data processing results output by different instruction execution modules through different buses and output them. In addition, in order to facilitate the processor to execute interrupt requests, the instruction allocation module can also be connected to the reordering buffer, and the reordering buffer can be connected to the mask register, so that the reordering buffer can obtain the instruction status of the vector instruction and update the interrupt preparation status of the mask register according to the obtained instruction status.

[0075] In the embodiment of the present application, the data processing system further includes: a state feedback module connected to the scalar core, for obtaining the instruction state of the vector instruction, and sending the instruction state to the scalar core.

[0076] In an optional scheme of the present embodiment, in order to ensure that the scalar core can send the instruction payload to the vector unit in a timely manner, and at the same time ensure that the scalar core can process other scalar instructions in a timely manner after sending the instruction payload, the above-mentioned state feedback module can also be set in the vector unit, and the state feedback module can be connected to the scalar core. The vector unit can use the state feedback module to obtain the instruction status of the vector instruction in real time, such as the execution status of the vector instruction, the number of vector instructions and other information, and send this information to the scalar core in a timely manner, so that the scalar core can determine the operation status of the vector unit in real time, and send the vector instructions and instruction data related to the vector instructions to the vector unit in a timely manner to assist the vector unit in executing different vector instructions.

[0077] Figure 8 801 represents a scalar core, 802 represents a vector unit, 803 represents a state feedback module in the vector unit, and 804 represents a communication channel. Figure 8As shown, the scalar core can send an instruction payload carrying the vector unit to the vector unit through the GIU, and continue to execute other scalar instructions after the sending is completed. The corresponding vector unit can cache and execute the vector instructions in the instruction payload. At the same time, the vector unit can obtain the instruction status of the vector instructions in real time through the GIU using the state feedback module, and transmit these instruction states to the scalar core through the communication channel. Alternatively, the scalar core can actively obtain the instruction status of the vector instructions currently executed by the vector unit through the communication channel by polling, traversal, etc., so that the scalar core can decide the next processing task according to the obtained instruction status, such as continuing to send vector instructions to the vector unit, or continuing to execute tasks such as scalar instructions.

[0078] According to an embodiment of the present application, a data processing method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0079] The method embodiment provided in Embodiment 1 of the present application can be executed in a RISC-V system, a RISC-V chip or a similar device. Fig. 9 1 is a hardware structure block diagram of a RISC-V system for implementing a data processing method according to the present application. Fig. 9 As shown, the RISC-V system 900 can be divided from the bottom layer to the upper layer into a reduced instruction set architecture 901 (including a basic instruction set 901-1 and an extended instruction set 901-2), a hardware layer 902 (including a processor 902-1, a peripheral hardware circuit 902-2, etc.), an interface layer 903, an operating system layer 904 (supporting multiple operating systems 904-1, 904-2, ..., 904-n, such as Linux, FreeSBD, RT-Tread, etc.), a middleware and library layer 905 (including a system library 905-1, an API 905-2 and a middleware service 905-3) and an application layer 906 (including multiple user programs and services 906-1, 906-2, ..., 906-n). The RISC-V system 900 also includes a tool chain 907 from the underlying hardware to the application layer. The tool chain may include a compiler and assembler 907-1, a linker 907-2, a debugger 907-3, a simulator and emulator 907-4, an integrated development environment 907-5, a hardware description language tool 907-6, a performance analysis tool 907-7, and a version control system 907-8, etc.

[0080] The instruction set architecture 901 defines the basic operations and instruction sets supported by the processor 902-1, including a basic instruction set and an extended instruction set, wherein the basic instruction set represents a basic integer instruction set, such as RV32I and RV64I, and the extended instruction set can be floating point, atomic operations, compressed instructions, etc.

[0081] The interface layer 903 includes the specific design of the processor, such as pipeline design, cache structure, execution unit, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0082] The operating system layer 904 is located at the hardware IQ and provides a hardware abstraction layer and management mechanism, so that applications can interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, etc.

[0083] The middleware and library layer 905 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while the middleware can provide complex services such as network communication and graphical user interfaces.

[0084] The application layer 906 uses the functions and services provided by the lower layer to implement specific application logic. These applications can be command line tools, graphical interface applications, server-side services, etc.

[0085] Tool chain 907 is a key component that connects the underlying hardware to the upper-level software. Various tools in tool chain 907 function at different levels to support the entire process from hardware design to software development, ensuring the consistency and effectiveness of the entire system design.

[0086] It should be noted that the layered design of the RISC-V architecture allows decoupling between different layers, so that each layer can be developed and optimized independently.

[0087] In an optional embodiment, Fig.10 Schematic diagram of a RISC-V architecture system on chip according to the present application. Fig.10As shown, the system on chip (SOC) includes at least one RISC-V core 1002 (only one is shown in the figure), and the RISC-V core 1002 is connected to peripheral devices through a bus 1004, including but not limited to ROM 1006, RAM 1008, timer 1010, UART (Universal Asynchronous Receiver / Transmitter) 1012, GPIO (General Purpose Input / Output) 1014, SPI (Serial Peripheral Interface Bus) 1016, etc.

[0088] Under the above operating environment, this application provides Fig.11 The data processing method shown. Fig.11 is a flow chart of a data processing method according to the present application, such as Fig.11 As shown, the method may include the following steps:

[0089] Step S1102, receiving the instruction payload sent by the scalar core.

[0090] In an optional scheme of this embodiment, in order to effectively process vector instructions, the vector unit can be connected to the scalar core, and the scalar core can send the instruction payload carrying the vector instructions to the vector unit for processing. Correspondingly, the vector unit can first receive the instruction payload sent by the scalar core.

[0091] Step S1104: decode and split at least one vector instruction included in the instruction payload to obtain at least one instruction data.

[0092] After receiving the instruction payload, the vector unit may decode and split at least one vector instruction included in the instruction payload to obtain instruction data of different vector instructions in the instruction payload.

[0093] Step S1106: allocating the instruction data to at least one instruction execution module based on the data characteristics of the instruction data.

[0094] Among them, the number of instruction execution modules and the register width of the instruction execution modules are determined by the computing power requirements of the processor.

[0095] After extracting the instruction data of different vector instructions, the vector unit can perform feature extraction on the obtained instruction data to obtain data features of different instruction data, and then distribute the different instruction data to the appropriate instruction execution module according to the extracted data features to ensure the efficiency of using the instruction execution module to process the received instruction data. Considering that the computing power requirements required by the processor are different when processing different vector instructions, in order to be able to match the appropriate instruction execution module for the vector instruction to improve the efficiency of processing the vector instruction and avoid wasting processing resources, the number and register width of the above instruction execution modules can be determined by the computing power requirements of the processor.

[0096] Step S1108, executing the instruction data based on the instruction execution module.

[0097] In an optional scheme of this embodiment, after different instruction data are assigned to instruction execution modules, the vector unit can use the instruction execution module to execute the corresponding instruction data, thereby obtaining the corresponding data execution results. Correspondingly, after different instruction execution modules execute the received instruction data and output the corresponding data execution results, the vector unit can summarize the data execution results output by different instruction execution modules to obtain the execution results corresponding to different vector instructions.

[0098] In an embodiment of the present application, vector instructions include: data loading instructions and data storage instructions. Before decoding and splitting at least one vector instruction contained in the instruction payload, the method also includes: using a first parsing unit to parse the instruction payload to obtain data loading instructions and data storage instructions; using a second parsing unit to parse the instruction payload to obtain vector instructions.

[0099] In an optional scheme of the present embodiment, considering that vector instructions usually include calculation instructions that require calculation processing on data, as well as data loading instructions and data storage instructions for obtaining data, therefore, in order to ensure the efficiency of processing these calculation instructions, the vector unit can first obtain the data that needs to be processed through data loading instructions and data processing instructions before executing these calculation instructions. Based on this, before decoding and splitting different vector instructions, the vector unit can separately extract the data loading instructions and data storage instructions contained in the instruction payload to quickly obtain the data currently needed based on these two instructions. Correspondingly, the vector unit can use the first parsing unit to parse the instruction payload to obtain the above-mentioned data loading instructions and data storage instructions, and use the second parsing unit to parse the instruction payload to obtain the above-mentioned vector instructions.

[0100] In an embodiment of the present application, at least one vector instruction included in an instruction payload is decoded and split to obtain at least one instruction data, including: decoding and splitting a data loading instruction and a data storage instruction based on a look-ahead decoder to obtain a loading address and a storage address, and sending the loading address and the storage address to a loading and storage unit; decoding and splitting the vector instruction based on a standard decoder to obtain instruction data, and performing a correlation check on the vector instruction based on the instruction data to obtain a correlation check result, wherein the correlation check result is used to characterize whether there is a conflict between registers corresponding to different vector instructions.

[0101] In an optional scheme of the present embodiment, the instruction data may include at least two parts: a load address and a storage address. In order to quickly obtain the data required for different vector instructions, the vector unit may use a forward decoder to decode and split the above-mentioned parsed data loading instructions and data storage instructions to obtain the above-mentioned loading address and storage address, and send the loading address and storage address to the loading and storage units in the data processing unit to quickly obtain and store data. At the same time, the standard decoder may be used to decode and split the above-mentioned parsed vector instructions to obtain the above-mentioned instruction data. In addition, in order to avoid conflicts between registers corresponding to vector instructions and determine whether there is a dependency between different vector qualities, the above-mentioned standard decoder may also be used to perform correlation detection on the parsed vector instructions to obtain the above-mentioned correlation detection results.

[0102] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0103] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0104] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0105] According to an embodiment of the present application, a data processing method is also provided. Fig.12 is a flow chart of another data processing method according to the present application, such as Fig.12 As shown, the method may include the following steps:

[0106] Step S1202: Receive the instruction payload sent by the scalar core by calling the first interface.

[0107] The first interface may be configured to receive a command payload.

[0108] In an optional solution of this embodiment, in order to effectively process the vector instruction, the vector unit may receive the instruction payload sent by the scalar core by calling the above-mentioned first interface.

[0109] Step S1204: decode and split at least one vector instruction included in the instruction payload to obtain at least one instruction data.

[0110] After receiving the instruction payload, the vector unit may decode and split at least one vector instruction included in the instruction payload to obtain instruction data of different vector instructions in the instruction payload.

[0111] Step S1206: Allocate the instruction data to at least one instruction execution module based on the data characteristics of the instruction data.

[0112] Among them, the number of instruction execution modules and the register width of the instruction execution modules are determined by the computing power requirements of the processor.

[0113] After extracting the instruction data of different vector instructions, the vector unit can perform feature extraction on the obtained instruction data to obtain data features of different instruction data, and then distribute the different instruction data to the appropriate instruction execution module according to the extracted data features to ensure the efficiency of using the instruction execution module to process the received instruction data. Considering that the computing power requirements required by the processor are different when processing different vector instructions, in order to be able to match the appropriate instruction execution module for the vector instruction to improve the efficiency of processing the vector instruction and avoid wasting processing resources, the number and register width of the above instruction execution modules can be determined by the computing power requirements of the processor.

[0114] Step S1208, executing the instruction data based on the instruction execution module.

[0115] In an optional scheme of this embodiment, after different instruction data are assigned to instruction execution modules, the vector unit can use the instruction execution module to execute the corresponding instruction data, thereby obtaining the corresponding data execution results. Correspondingly, after different instruction execution modules execute the received instruction data and output the corresponding data execution results, the vector unit can summarize the data execution results output by different instruction execution modules to obtain the execution results corresponding to different vector instructions.

[0116] Step S1210: output the execution result of the instruction data by calling the second interface.

[0117] The second interface may be an interface for outputting execution results of vector instructions.

[0118] In an optional solution of this embodiment, in order to facilitate the user to view the execution results of the vector instructions, the vector unit can also output the execution results corresponding to different instruction data in a preset operation interface by calling the above-mentioned second interface.

[0119] An embodiment of the present application also provides a processor, comprising any one of the above-mentioned data processing systems.

[0120] In the embodiment of the present application, the above-mentioned processor adopts a reduced instruction set architecture.

[0121] An embodiment of the present application also provides a system on chip, comprising any one of the above data processing systems.

[0122] The embodiment of the present application further provides a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store the program code executed by the method provided in the above embodiment.

[0123] Optionally, in this embodiment, the above storage medium may be located in any electronic device in a group of electronic devices in a computer network, or in any mobile terminal in a group of mobile terminals.

[0124] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for executing the following steps: receiving an instruction payload sent by a scalar core; decoding and splitting at least one vector instruction contained in the instruction payload to obtain at least one instruction data; based on data characteristics of the instruction data, allocating the instruction data to at least one instruction execution module, wherein the number of instruction execution modules and the register width of the instruction execution modules are determined by the computing power requirements of the processor; and executing the instruction data based on the instruction execution module.

[0125] The embodiment of the present application further provides a computer program product. Optionally, in this embodiment, the computer program product may include a computer program, and the computer program implements the method provided in the embodiment when executed by a processor.

[0126] The embodiments of the present application also provide a computer program product. Optionally, the computer program product may include a non-volatile computer-readable storage medium, which may be used to store a computer program, and when the computer program is executed by a processor, the method provided in the embodiments is implemented.

[0127] The embodiment of the present application further provides a computer program. Optionally, in this embodiment, when the computer program is executed by a processor, the method provided in the above embodiment is implemented.

[0128] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0129] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0130] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0131] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0132] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0133] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk, etc. Various media that can store program codes.

[0134] The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A data processing system, characterized in that: include: An instruction cache module, connected to the scalar core, for receiving and caching instruction payloads sent by the scalar core; an instruction decoding module, connected to the instruction cache module, for decoding and splitting at least one vector instruction included in the instruction payload to obtain instruction data of the at least one vector instruction; an instruction allocation module, connected to the instruction decoding module, and configured to allocate the instruction data to at least one instruction execution module based on data characteristics of the instruction data, wherein the number of the instruction execution modules and the register width of the instruction execution module are determined by the computing power requirement of the processor; The instruction execution module is used to execute the received instruction data.

2. The data processing system according to claim 1, characterized in that The instruction execution module comprises: a data allocating unit, configured to allocate the received instruction data to at least one issue queue based on a data type of the received instruction data; The issue queue is used to cache the instruction data; a data transmission network connected to the issue queue and used to transmit the instruction data to a data processing unit based on the data type of the instruction data stored in the issue queue; The data processing unit is used to process the received instruction data based on a preset processing logic to obtain a data processing result, wherein the preset processing logic corresponds to the data type.

3. The data processing system according to claim 2, characterized in that: The instruction execution module also includes: a vector register unit connected to the data processing unit and the data transmission network, and configured to store the data processing result and send the data processing result to the data transmission network; The data transmission network is used to transmit the data processing result to the processing line cross execution unit; The processing line cross-execution unit is connected to the data transmission network and the routing communication unit, and is used to send the first execution data of the instruction execution module to the routing communication unit, and receive the second execution data sent by the routing communication unit, wherein the first execution data includes the data processing result, and the second execution data is used to represent the data sent by other instruction execution modules.

4. The data processing system according to claim 3, characterized in that: The instruction execution module also includes: a renaming unit, connected to the data allocation unit, for adjusting the register name included in the instruction data, and sending the adjusted instruction data to the data allocation unit; The renaming unit is also connected to the vector register unit and is used to adjust the register name of the vector register based on the register name of the physical register.

5. The data processing system according to claim 1, characterized in that: The vector instructions at least include: data loading instructions and data storage instructions, and the instruction cache module includes: A first parsing unit, configured to parse the instruction payload to obtain the data loading instruction and the data storage instruction; The second parsing unit is used to parse the instruction payload to obtain the vector instruction.

6. The data processing system according to claim 5, characterized in that: The instruction data at least includes: a load address and a storage address, and the instruction decoding module includes: A look-ahead decoder, configured to decode and split the data loading instruction and the data storage instruction, obtain the loading address and the storage address, and send the loading address and the storage address to a loading and storage unit in a data processing unit; A standard decoder is used to decode and split the vector instructions to obtain the instruction data, and perform a correlation test on the vector instructions based on the instruction data to obtain a correlation test result, wherein the correlation test result is used to characterize whether there is a conflict between registers corresponding to different vector instructions.

7. The data processing system according to claim 1, characterized in that: The data processing system further comprises: An interrupt mask register, used to control an interrupt enable state of the data processing system, wherein the interrupt enable state is used to indicate whether the data processing system executes an interrupt request of the mask register; A reorder buffer is connected to the instruction allocation module, the instruction execution module and the mask register, and is used to obtain the instruction status of the vector instruction from the instruction allocation module and the instruction execution module, and update the interrupt preparation status of the mask register based on the instruction status, wherein the interrupt preparation status is used to indicate whether the interrupt request of the mask register can be read.

8. The data processing system according to claim 1, characterized in that: The data processing system further comprises: A state feedback module is connected to the scalar core and is used to obtain the instruction state of the vector instruction and send the instruction state to the scalar core.

9. A data processing method, characterized in that: include: receiving instruction payload sent by the scalar core; Decoding and splitting at least one vector instruction included in the instruction payload to obtain at least one instruction data; Based on data features of the instruction data, allocating the instruction data to at least one instruction execution module, wherein the number of the instruction execution modules and the register width of the instruction execution module are determined by the computing power requirement of the processor; The instruction data is executed based on the instruction execution module.

10. The method according to claim 9, characterized in that The vector instructions include: data loading instructions and data storage instructions. Before decoding and splitting at least one vector instruction included in the instruction payload, the method further includes: Parsing the instruction payload using a first parsing unit to obtain the data loading instruction and the data storage instruction; The instruction payload is parsed using a second parsing unit to obtain the vector instruction.

11. The method according to claim 10, characterized in that Decoding and splitting at least one vector instruction included in the instruction payload to obtain at least one instruction data, including: Decoding and splitting the data loading instruction and the data storage instruction based on a look-ahead decoder to obtain a loading address and a storage address, and sending the loading address and the storage address to a loading and storing unit; The vector instructions are decoded and split based on a standard decoder to obtain the instruction data, and a correlation test is performed on the vector instructions based on the instruction data to obtain a correlation test result, wherein the correlation test result is used to characterize whether there is a conflict between registers corresponding to different vector instructions.

12. A data processing method, characterized in that: include: receiving the instruction payload sent by the scalar core by calling the first interface; Decoding and splitting at least one vector instruction included in the instruction payload to obtain at least one instruction data; Based on data features of the instruction data, allocating the instruction data to at least one instruction execution module, wherein the number of the instruction execution modules and the register width of the instruction execution module are determined by the computing power requirement of the processor; Execute the instruction data based on the instruction execution module; The execution result of the instruction data is output by calling the second interface.

13. A processor, characterized in that: include: A data processing system as claimed in any one of claims 1 to 8.

14. The processor according to claim 13, characterized in that The processor adopts a reduced instruction set architecture.

15. A system on chip, characterized in that: include: A data processing system as claimed in any one of claims 1 to 8.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored executable program, wherein when the executable program is executed, the device where the storage medium is located is controlled to execute the method according to any one of claims 9 to 12.

17. A computer program product, characterized in that It comprises a computer program which, when executed by a processor, implements the method according to any one of claims 9 to 12.

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