Code evaluation and conversion method and system applied to heterogeneous multi-core chip, and medium

Abstract

The invention relates to the technical field of software code evaluation and conversion of heterogeneous multi-core chips, in particular to a code evaluation and conversion method and system applied to a heterogeneous multi-core chip and a medium. The method comprises the following steps: reading a configuration table to obtain hardware configuration information of equipment; constructing a simulation experiment environment in the corresponding configuration table; converting the software algorithm according to requirements; running a software algorithm in the simulation environment, enabling the algorithm to run on hardware with different hardware configurations through parameter setting, and obtaining technical indexes of algorithm running; analyzing and comparing performance indexes of the algorithm in different operation environments, and performing adjustment optimization and operation test on the algorithm; a software algorithm is deployed on specific hardware, and evaluation testing in an actual operation environment is carried out. According to the method, the performance of a software algorithm on a heterogeneous multi-core chip can be improved, the development cost is reduced, and the product development period is shortened.

Description

Technical Field

[0001] The present application relates to the technical field of software code evaluation and conversion for heterogeneous multi-core chips, and to a code evaluation and conversion method, system, and medium applied to heterogeneous multi-core chips. Background Art

[0002] Heterogeneous multi-core embedded chips are embedded system-on-chips (SoCs) that integrate multiple different types of processor cores. These cores may include, but are not limited to, general-purpose processor cores (such as RISC-V cores), digital signal processors (DSPs), neural network processors (NPUs), etc. With the rapid development of semiconductor technology, heterogeneous multi-core chips are gaining increasing attention because they can provide multiple processing capabilities on a single chip and optimize the performance of specific tasks.

[0003] In the software development process, code evaluation and conversion for heterogeneous multi-core chips are particularly important. Code evaluation aims to analyze and evaluate the quality of code through a series of technologies and tools to find potential problems and improve the readability, maintainability and testability of the code. This process helps ensure the stability and efficiency of the software in a complex multi-core environment.

[0004] On the other hand, code conversion is a key step to enable software to run across platforms or adapt to different processor architectures. It mainly involves converting code from one programming language or format to another programming language or format to meet specific development needs or optimize performance. On heterogeneous multi-core chips, since each processor core has a different instruction set architecture and computing power, the software algorithm needs to be converted and optimized accordingly according to the target core.

[0005] However, traditional approaches present many challenges in the algorithm deployment process on heterogeneous multi-core chips. In the past, programmers mainly relied on personal experience and intuition to decide where to deploy software algorithms on the chip, lacking clear technical indicators and automated tools to guide this process. This often leads to problems such as uneven algorithm performance, low resource utilization, and long development cycles.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The disclosed embodiments provide a code evaluation and conversion method, system, and medium for heterogeneous multi-core chips, which can improve the performance of software algorithms on heterogeneous multi-core chips, reduce development costs, and accelerate product development cycles.

[0009] In some embodiments, the method includes: reading a configuration table to obtain hardware configuration information of the device; Construct the simulation experiment environment in the corresponding configuration table to simulate the hardware environment of the software running process; Convert the software algorithm as required. If the software algorithm runs on the main core, no conversion is required. If the software algorithm runs in whole or in part on the acceleration core, the algorithm needs to be converted into a program of the instruction set architecture supported by the acceleration core. Run the software algorithm in the simulation environment, set parameters to enable the algorithm to run on hardware with different hardware configurations, and obtain technical indicators of the algorithm operation; Analyze and compare the performance indicators of algorithms in different operating environments, adjust and optimize the algorithms, and conduct operational tests; Deploy the software algorithm to specific hardware, conduct evaluation tests in the actual operating environment, and fine-tune the algorithm based on the test results until it meets the requirements.

[0010] Preferably, the hardware configuration information includes the overall information of the heterogeneous multi-core chip, the main frequency of the main core, the instruction set architecture, the memory and cache size, the main frequency of each acceleration core, the number of computing cores, the parallel computing capability, the memory capacity and bandwidth, and the port width information.

[0011] Preferably, the software algorithm conversion process includes reading source code, adding a startup code file, and compiling using an adapted compiler.

[0012] Preferably, the simulation environment includes a virtual machine, a simulator or a hardware accelerator.

[0013] Preferably, the technical indicators include time complexity, space complexity, correctness, and robustness.

[0014] Preferably, the performance indicators include algorithm execution time, memory usage, processing speed, stability and compatibility.

[0015] In some embodiments, the system comprises: A configuration table reading unit, used for reading the configuration table to obtain the hardware configuration information of the device; A simulation environment construction unit is used to construct a corresponding simulation experiment environment according to the configuration table information to simulate the hardware environment of the software running process; A program conversion unit is used to convert the software algorithm to be deployed in the acceleration core, including reading the source code of the software algorithm, adding the startup code file of the instruction set architecture corresponding to the acceleration core to form a new source code file, and calling the compiler component adapted by the acceleration core to compile the new source code file to generate a binary file that can be recognized by the acceleration core simulation experiment environment; The simulation operation unit is used to run the software algorithm in the simulation environment, and to set parameters so that the software algorithm can be run under different hardware configurations to obtain technical indicators of the algorithm operation; Performance evaluation unit, used to analyze and compare the performance indicators of algorithms in different operating environments, adjust and optimize the algorithms and perform running tests to obtain software algorithms that take into account overall performance indicators; The deployment test unit is used to deploy the optimized software algorithm to the actual hardware device for evaluation testing, and to perform fine-tuning and further testing until it meets the requirements.

[0016] Preferably, it also includes an auxiliary tool unit for recording logs and printing out performance evaluation data.

[0017] In some embodiments, the medium stores program instructions, and when the program instructions are run, the code evaluation and conversion method applied to heterogeneous multi-core chips is executed.

[0018] The code evaluation and conversion method, system, and medium for heterogeneous multi-core chips provided by the embodiments of the present disclosure can achieve the following technical effects: The present invention solves the difficulties encountered by heterogeneous multi-core chips in the algorithm deployment process. By building a simulation experiment environment, automatically converting algorithms, analyzing performance indicators and optimizing algorithms, the efficiency and accuracy of algorithm deployment are significantly improved, the portability and maintainability of the code are enhanced, and the performance and quality of the algorithm are optimized.

[0019] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein: Figure 1 It is a schematic flow chart of the method of the present invention. DETAILED DESCRIPTION

[0021] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0022] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0023] Combination Figure 1 , a code evaluation and conversion method applied to a heterogeneous multi-core chip includes: S1: Read the configuration table to obtain the hardware configuration information of the device; S2: Build the simulation experiment environment in the corresponding configuration table to simulate the hardware environment of the software running process; S3: Convert the software algorithm according to the requirements. If the software algorithm runs on the main core, no conversion is required. If the software algorithm runs in whole or in part on the acceleration core, the algorithm needs to be converted into a program of the instruction set architecture supported by the acceleration core. S4: Run the software algorithm in the simulation environment, set parameters to enable the algorithm to run on hardware with different hardware configurations, and obtain technical indicators of the algorithm operation; S5: Analyze and compare the performance indicators of the algorithm in different operating environments, adjust and optimize the algorithm and perform operation tests; S6: Deploy the software algorithm to specific hardware, conduct evaluation tests in the actual operating environment, and fine-tune the algorithm based on the test results until it meets the requirements.

[0024] As a refinement of the above embodiment, the hardware configuration information includes the overall information of the heterogeneous multi-core chip, the main frequency of the main core, the instruction set architecture, the memory and cache size, the main frequency of each acceleration core, the number of computing cores, the parallel computing capability, the memory capacity and bandwidth, and the port width information. By reading the configuration table to obtain the detailed hardware configuration information of the device, including the various performance indicators of the main core and the acceleration core, the algorithm deployment process has a basis to rely on, reducing the error and uncertainty of human judgment.

[0025] As a refinement of the above embodiment, the software algorithm conversion process includes reading source code, adding startup code files, and compiling using an adapted compiler. The specific startup code added during the conversion process and the call to the adapted compiler ensure the correct execution of the converted code on the acceleration core, reduce compatibility issues caused by environmental differences, and reduce maintenance costs.

[0026] As a refinement of the above embodiment, the simulation environment includes a virtual machine, a simulator or a hardware accelerator. By using the simulation experiment environment to simulate the operation of the software algorithm under different hardware conditions, the performance of the algorithm can be evaluated in advance, avoiding the risks and costs that may be caused by direct deployment on actual hardware.

[0027] As a refinement of the above embodiment, the technical indicators include time complexity, space complexity, correctness, and robustness. The algorithm is tested for performance in a simulation environment to obtain comprehensive technical indicators including time complexity, space complexity, correctness, and robustness, providing a scientific basis for further optimization of the algorithm.

[0028] As a refinement of the above embodiment, the performance indicators include algorithm execution time, memory usage, processing speed, stability and compatibility.

[0029] It should be noted that the present invention adjusts and optimizes the algorithm and performs operation tests on key technical indicators, and finally obtains a software algorithm that takes into account both overall performance indicators and highlights the optimization of key indicators, which significantly improves the performance and quality of the algorithm.

[0030] By evaluating and testing the algorithm before deployment on the actual hardware device, potential problems can be discovered and resolved in advance, avoiding possible failures and performance bottlenecks in the actual operating environment. By continuously fine-tuning and testing the algorithm until it meets the requirements, the stability and reliability of the algorithm in actual applications are ensured, reducing development costs and risks.

[0031] A code evaluation and conversion system for heterogeneous multi-core chips includes: A configuration table reading unit, used for reading the configuration table to obtain the hardware configuration information of the device; A simulation environment construction unit is used to construct a corresponding simulation experiment environment according to the configuration table information to simulate the hardware environment of the software running process; A program conversion unit is used to convert the software algorithm to be deployed in the acceleration core, including reading the source code of the software algorithm, adding the startup code file of the instruction set architecture corresponding to the acceleration core to form a new source code file, and calling the compiler component adapted by the acceleration core to compile the new source code file to generate a binary file that can be recognized by the acceleration core simulation experiment environment; The simulation operation unit is used to run the software algorithm in the simulation environment, and to set parameters so that the software algorithm can be run under different hardware configurations to obtain technical indicators of the algorithm operation; Performance evaluation unit, used to analyze and compare the performance indicators of algorithms in different operating environments, adjust and optimize the algorithms and perform running tests to obtain software algorithms that take into account overall performance indicators; The deployment test unit is used to deploy the optimized software algorithm to the actual hardware device for evaluation testing, and to perform fine-tuning and further testing until it meets the requirements.

[0032] As a refinement of the above embodiment, an auxiliary tool unit is further included for recording logs and printing out performance evaluation data.

[0033] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned code evaluation and conversion method applied to a heterogeneous multi-core chip.

[0034] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0035] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, and other media that can store program codes, or a transient storage medium.

[0036] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, method or device including the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0037] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians may clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0038] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0039] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A code evaluation and conversion method applied to heterogeneous multi-core chips, characterized in that: include: Read the configuration table to obtain the hardware configuration information of the device; Construct the simulation experiment environment in the corresponding configuration table to simulate the hardware environment of the software running process; Convert the software algorithm as required. If the software algorithm runs on the main core, no conversion is required. If the software algorithm runs in whole or in part on the acceleration core, the algorithm needs to be converted into a program of the instruction set architecture supported by the acceleration core. Run the software algorithm in the simulation environment, set parameters to enable the algorithm to run on hardware with different hardware configurations, and obtain technical indicators of the algorithm operation; Analyze and compare the performance indicators of algorithms in different operating environments, adjust and optimize the algorithms, and conduct operational tests; Deploy the software algorithm to specific hardware, conduct evaluation tests in the actual operating environment, and fine-tune the algorithm based on the test results until it meets the requirements.

2. The code evaluation and conversion method for heterogeneous multi-core chips according to claim 1, characterized in that: The hardware configuration information includes the overall information of the heterogeneous multi-core chip, the main frequency of the main core, the instruction set architecture, the memory and cache size, the main frequency of each acceleration core, the number of computing cores, the parallel computing capability, the memory capacity and bandwidth, and the port width information.

3. The code evaluation and conversion method applied to heterogeneous multi-core chips according to claim 1, characterized in that: The software algorithm conversion process includes reading source code, adding startup code files, and compiling with an adapted compiler.

4. The code evaluation and conversion method for heterogeneous multi-core chips according to claim 1, characterized in that: The simulation environment includes a virtual machine, a simulator or a hardware accelerator.

5. The code evaluation and conversion method applied to heterogeneous multi-core chips according to claim 1, characterized in that: The technical indicators include time complexity, space complexity, correctness, and robustness.

6. The code evaluation and conversion method for heterogeneous multi-core chips according to claim 1, characterized in that: The performance indicators include algorithm execution time, memory usage, processing speed, stability and compatibility.

7. A code evaluation and conversion system for heterogeneous multi-core chips for implementing any of the methods of claims 1-6, characterized in that: include: A configuration table reading unit, used for reading the configuration table to obtain the hardware configuration information of the device; A simulation environment construction unit is used to construct a corresponding simulation experiment environment according to the configuration table information to simulate the hardware environment of the software running process; A program conversion unit is used to convert the software algorithm to be deployed in the acceleration core, including reading the source code of the software algorithm, adding the startup code file of the instruction set architecture corresponding to the acceleration core to form a new source code file, and calling the compiler component adapted by the acceleration core to compile the new source code file to generate a binary file that can be recognized by the acceleration core simulation experiment environment; The simulation operation unit is used to run the software algorithm in the simulation environment, and to set parameters so that the software algorithm can be run under different hardware configurations to obtain technical indicators of the algorithm operation; Performance evaluation unit, used to analyze and compare the performance indicators of algorithms in different operating environments, adjust and optimize the algorithms and perform running tests to obtain software algorithms that take into account overall performance indicators; The deployment test unit is used to deploy the optimized software algorithm to the actual hardware device for evaluation testing, and to perform fine-tuning and further testing until it meets the requirements.

8. The code evaluation and conversion system for heterogeneous multi-core chips according to claim 7, characterized in that: Also included is an auxiliary tool unit for logging and printing out performance evaluation data.

9. A storage medium storing program instructions, characterized in that: When the program instructions are run, they execute the code evaluation and conversion method applied to a heterogeneous multi-core chip as described in any one of claims 1 to 6.

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