Debugging bus supporting high-frequency signals

Abstract

The invention discloses a debugging bus supporting high-frequency signals, and belongs to the field of communication. Based on a traditional chip debugging bus, the traditional chip debugging bus comprises a multiplexer, a chip pin and a plurality of modules. The plurality of modules are connected with the multiplexer, and the multiplexer is connected with the chip pins; the debugging bus supporting the high-frequency signals further comprises a global statistical module. The statistical module is positioned between the multiplexer and the chip pin; data in a chip and a clock to which the data belong are input into the statistical module together, and the statistical module detects high-frequency signals and meets statistical requirements of all modules. According to the invention, high-frequency signals can be supported, data statistics can be flexibly carried out on all modules, and meanwhile, fewer hardware resources are consumed.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a debugging bus supporting high-frequency signals. Background Art

[0002] The debug bus is a set of transmission lines dedicated to chip debugging. Its working principle is to use the I2C bus to configure the debug address, map the debug address to multiple sets of debug data (i.e., the key signals to be observed inside the chip), and then transmit the debug data to the test equipment through the debug interface. Finally, the test equipment is used to observe and analyze the debug data. The overall structure of the existing debug bus is as follows: Figure 1 shown.

[0003] The existing debug bus solution has the following two defects in actual use: 1. The debug interface is usually connected to the chip pins, and the maximum operating frequency of ordinary chip pins is usually low (about 10 MHz). As the chip operating rate continues to increase, the existing debug bus cannot observe and analyze the high-frequency signals in the chip, which may greatly increase the difficulty and complexity of chip testing; 2. If the existing debug bus wants to perform statistical results on the signals in the chip, it is necessary to preset the statistical function inside the module and then output the statistical value as debug data. As the chip functions become more complex, more and more modules need to observe statistical values ​​during testing, and it is difficult to predict the statistical content that needs to be observed for each module. Therefore, it is difficult to preset the corresponding statistical functions for all required modules during design, and presetting all statistical functions for all modules will consume a lot of hardware resources. Therefore, the statistical function of the existing debug bus is relatively complex in design and not flexible enough in use. Summary of the invention

[0004] The object of the present invention is to provide a debugging bus supporting high-frequency signals to solve the problems in the background technology.

[0005] In order to solve the above technical problems, the present invention provides a debugging bus supporting high-frequency signals, based on a traditional chip debugging bus, wherein the traditional chip debugging bus comprises a multiplexer, a chip pin, and several modules; the several modules are connected to the multiplexer, and the multiplexer is connected to the chip pin; The debugging bus supporting high-frequency signals also includes a global statistical module; the statistical module is located between the multiplexer and the chip pin; The internal data of the chip and the clock to which it belongs are input into the statistical module together, and the statistical module realizes the detection of high-frequency signals to meet the statistical requirements of all modules.

[0006] In one embodiment, the statistical module includes edge detection / level detection, a counter, a memory, a judgment module and an asynchronous FIFO; in the statistical module, the high-frequency clock and the high-frequency data of the same module are of the same source, and the high-frequency clock is used to perform edge detection or level detection on the high-frequency data, and the detection results are counted or the high-frequency data is stored according to the detection results. The low-frequency statistical value in a steady state is obtained through the judgment module, and the statistical value is switched to the clock domain where the chip pin is located using the asynchronous FIFO, and is output to the test equipment as the debugging data of the debug bus, thereby completing the observation and analysis of the high-frequency signal.

[0007] In one embodiment, the judgment module presets multiple judgment modes for flexible use in the test, including but not limited to the following six modes: (1) Event A has occurred N times, where N is an integer greater than 0; The application scenario is: detecting whether high-frequency data A has N pulses; The implementation method is: the high-frequency clock counts once each time it detects a rising edge or a falling edge of a pulse signal of the high-frequency data A, and sets the statistical value when the count value is greater than or equal to N, and remains unchanged when the count value is less than N; (2) Event A and event B occurred at the same time; The application scenario is: detecting whether high-frequency data A and high-frequency data B have pulses in the same clock cycle; The implementation method is: using a high-frequency clock to detect the rising edge or falling edge of high-frequency data A and high-frequency data B, when the pulse signals of high-frequency data A and high-frequency data B are detected at the same time in a certain clock cycle, the statistical value is set, and if the pulse signals are not detected at the same time, the statistical value remains unchanged; (3) After event A occurs, event B occurs N times; The application scenario is: detecting whether high-frequency data B has N pulses after high-frequency data A has pulsed; The implementation method is: use the high-frequency clock to detect the rising edge or falling edge of the high-frequency data A and the high-frequency data B, and count the pulse signal of the high-frequency data B only after the pulse of the high-frequency data A is detected. When the count value is greater than or equal to N, the statistical value is set. If the pulse of the high-frequency data A does not occur or the pulse count of the high-frequency data B is less than N, the statistical value remains unchanged. (4) How many times did event A occur before event B? The application scenario is: detecting how many times high-frequency data A has pulsed before high-frequency data B has pulsed; The implementation method is: use the high-frequency clock to detect the rising edge or falling edge of the high-frequency data A and the high-frequency data B, and keep counting the pulse signal of the high-frequency data A until the pulse of the high-frequency data B is detected and then stop counting. The count value is the statistical result. If the high-frequency data B does not have a pulse, the statistical value remains 0. (5) After event A occurs, observe the data of event B; The application scenario is: it is expected to observe a certain amount of high-frequency data B after a pulse occurs in high-frequency data A; The implementation method is: use the high-frequency clock to detect the rising edge or falling edge of the high-frequency data A and the high-frequency data B, and start storing the high-frequency data B when the pulse of the high-frequency data A is detected, and stop storing when the storage limit is reached. The stored data is the statistical result; (6) Observe the data of event A before event B occurs; The application scenario is: it is expected to observe high-frequency data A before the pulse of high-frequency data B occurs; The implementation method is: use a high-frequency clock to detect the rising edge or falling edge of high-frequency data A and high-frequency data B, and keep storing the pulse signal of high-frequency data A. When the storage limit is reached, the earliest stored data is discarded and the latest data is stored. When the pulse of high-frequency data B is detected, storage is stopped. The stored data is the statistical result.

[0008] The present invention provides a debugging bus supporting high-frequency signals, which can support high-frequency signals, can flexibly perform data statistics on all modules, and consume less hardware resources. On the basis of the existing chip debugging bus, a global statistical module is added, and the clock to which the data belongs is additionally input into the statistical module. In the statistical module, the high-frequency data is statistically analyzed in multiple judgment modes using the same high-frequency clock, and finally the low-frequency statistical results in a steady state can be transmitted to the test equipment as the debugging data of the debugging bus, thereby realizing the observation of the high-frequency signal in the chip by the debugging bus and the data statistics of all modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a diagram of the existing debug bus structure.

[0010] Figure 2 It is a debugging bus structure diagram of the present invention.

[0011] Figure 3 This is the structure diagram of the statistics module. DETAILED DESCRIPTION

[0012] The following is a further detailed description of a debug bus supporting high-frequency signals proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0013] The present invention provides a novel debugging bus, which supports high-frequency signals, can flexibly perform data statistics on all modules, consumes less hardware resources, and can be applicable to any high-speed chip design.

[0014] like Figure 2 As shown, the present invention adds a global statistical module based on the existing chip debugging bus, and inputs the internal data of the chip and its clock into the statistical module, so that it can not only realize the detection of high-frequency signals, but also meet the statistical requirements of all modules.

[0015] The statistical module includes edge detection / level detection, counter, memory, judgment module and asynchronous FIFO (first-in-first-out memory). Its structure is as follows: Figure 3 As shown. In the statistical module, because the high-frequency clock and high-frequency data of the same module are of the same source, the high-frequency clock can be used to perform edge detection or level detection on the high-frequency data, count the detection results or store the high-frequency data according to the detection results, and then obtain the low-frequency statistical value in a steady state through the judgment module, and finally use the asynchronous FIFO to switch the statistical value to the clock domain where the chip pin is located, and output it to the test equipment as the debugging data of the debug bus, so as to complete the observation and analysis of the high-frequency signal.

[0016] For the judgment module, because it is impossible to predict the specific needs of the chip during testing, multiple judgment modes are preset in the judgment module for flexible use in testing. The judgment modes may include but are not limited to the following six: 1. Event A has occurred N times (where N is an integer greater than 0). The application scenario is: detect whether high-frequency data A has N pulses. The implementation method is: the high-frequency clock counts once each time it detects a rising edge or falling edge of a pulse signal of high-frequency data A. When the count value is greater than or equal to N, the statistical value is set. When the count value is less than N, the statistical value remains unchanged. 2. Event A and event B occurred at the same time. The application scenario is: detect whether high-frequency data A and high-frequency data B have pulses in the same clock cycle. The implementation method is: use the high-frequency clock to detect the rising edge or falling edge of high-frequency data A and high-frequency data B. When the pulse signals of high-frequency data A and high-frequency data B are detected at the same time in a certain clock cycle, the statistical value is set. If the pulse signals are not detected at the same time, the statistical value remains unchanged; 3. After event A occurs, event B occurs N times. The application scenario is: detect whether high-frequency data B has N pulses after high-frequency data A has pulsed. The implementation method is: use a high-frequency clock to detect the rising or falling edge of high-frequency data A and high-frequency data B, and count the pulse signal of high-frequency data B only after the pulse of high-frequency data A is detected. When the count value is greater than or equal to N, the statistical value is set. If no pulse of high-frequency data A occurs or the pulse count of high-frequency data B is less than N, the statistical value remains unchanged; 4. How many times did event A occur before event B occurred? The application scenario is: detect how many times high-frequency data A has pulsed before high-frequency data B has pulsed. The implementation method is: use a high-frequency clock to detect the rising or falling edge of high-frequency data A and high-frequency data B, and keep counting the pulse signal of high-frequency data A until the pulse of high-frequency data B is detected, then stop counting. The count value is the statistical result. If no pulse occurs in high-frequency data B, the statistical value remains 0; 5. After event A occurs, observe the data of event B. The application scenario is: it is expected to observe a certain amount of high-frequency data B after a pulse occurs in high-frequency data A. The implementation method is: use a high-frequency clock to detect the rising or falling edge of high-frequency data A and high-frequency data B, and start storing high-frequency data B after detecting a pulse of high-frequency data A. Stop storing after reaching the upper limit of storage (the maximum storage capacity is limited by the memory size). The stored data is the statistical result; 6. Observe the data of event A before event B occurs. The application scenario is: it is expected to observe high-frequency data A before the pulse of high-frequency data B occurs. The implementation method is: use the high-frequency clock to detect the rising edge or falling edge of high-frequency data A and high-frequency data B, and store the pulse signal of high-frequency data A all the time. When the storage limit is reached, the earliest stored data is discarded and the latest data is stored. When the pulse of high-frequency data B is detected, the storage is stopped. The stored data is the statistical result.

[0017] When designing a chip debugging bus, the present invention adds a global statistical module based on the existing structure, and inputs the chip internal data and its clock into the statistical module to realize the detection of high-frequency signals and the data statistics of all modules. In the statistical module, the high-frequency clock is used to perform edge detection or level detection on the high-frequency data, the detection results are counted or the high-frequency data is stored according to the detection results, and then the steady-state, low-frequency statistical value is obtained through the judgment module, and finally the statistical value is switched to the clock domain where the chip pin is located and output using the asynchronous FIFO. By presetting multiple judgment modes in the judgment module, different judgment modes can be used according to specific test requirements, so that the statistical module can more flexibly perform statistics on high-frequency signals; the synchronized low-frequency statistical values ​​are transmitted to the test equipment as the debugging data of the debugging bus, and finally the debugging data is observed and analyzed using the test equipment.

[0018] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A debug bus that supports high-frequency signals, based on the traditional chip debug bus, The traditional chip debugging bus includes a multiplexer, a chip pin, and a plurality of modules; the plurality of modules are connected to the multiplexer, and the multiplexer is connected to the chip pin; It is characterized in that The debugging bus supporting high-frequency signals also includes a global statistical module; the statistical module is located between the multiplexer and the chip pin; The internal data of the chip and the clock to which it belongs are input into the statistical module together, and the statistical module realizes the detection of high-frequency signals to meet the statistical requirements of all modules.

2. The debug bus supporting high frequency signals as claimed in claim 1, characterized in that: The statistical module includes edge detection / level detection, a counter, a memory, a judgment module and an asynchronous FIFO; in the statistical module, the high-frequency clock and the high-frequency data of the same module are of the same source, the high-frequency clock is used to perform edge detection or level detection on the high-frequency data, the detection results are counted or the high-frequency data is stored according to the detection results, the low-frequency statistical value in a steady state is obtained through the judgment module, the statistical value is switched to the clock domain where the chip pin is located using the asynchronous FIFO, and is output to the test equipment as the debugging data of the debugging bus, thereby completing the observation and analysis of the high-frequency signal.

3. The debug bus supporting high frequency signals as claimed in claim 2, characterized in that: The judgment module presets multiple judgment modes for flexible use in the test, including but not limited to the following six modes: (1) Event A has occurred N times, where N is an integer greater than 0; The application scenario is: detecting whether high-frequency data A has N pulses; The implementation method is: the high-frequency clock counts once each time it detects a rising edge or a falling edge of a pulse signal of the high-frequency data A, and sets the statistical value when the count value is greater than or equal to N, and remains unchanged when the count value is less than N; (2) Event A and event B occurred at the same time; The application scenario is: detecting whether high-frequency data A and high-frequency data B have pulses in the same clock cycle; The implementation method is: using a high-frequency clock to detect the rising edge or falling edge of high-frequency data A and high-frequency data B, when the pulse signals of high-frequency data A and high-frequency data B are detected at the same time in a certain clock cycle, the statistical value is set, and if the pulse signals are not detected at the same time, the statistical value remains unchanged; (3) After event A occurs, event B occurs N times; The application scenario is: detecting whether high-frequency data B has N pulses after high-frequency data A has pulsed; The implementation method is: use the high-frequency clock to detect the rising edge or falling edge of the high-frequency data A and the high-frequency data B, and count the pulse signal of the high-frequency data B only after the pulse of the high-frequency data A is detected. When the count value is greater than or equal to N, the statistical value is set. If the pulse of the high-frequency data A does not occur or the pulse count of the high-frequency data B is less than N, the statistical value remains unchanged. (4) How many times did event A occur before event B? The application scenario is: detecting how many times high-frequency data A has pulsed before high-frequency data B has pulsed; The implementation method is: use the high-frequency clock to detect the rising edge or falling edge of the high-frequency data A and the high-frequency data B, and keep counting the pulse signal of the high-frequency data A until the pulse of the high-frequency data B is detected and then stop counting. The count value is the statistical result. If the high-frequency data B does not have a pulse, the statistical value remains 0. (5) After event A occurs, observe the data of event B; The application scenario is: it is expected to observe a certain amount of high-frequency data B after a pulse occurs in high-frequency data A; The implementation method is: use the high-frequency clock to detect the rising edge or falling edge of the high-frequency data A and the high-frequency data B, and start storing the high-frequency data B when the pulse of the high-frequency data A is detected, and stop storing when the storage limit is reached. The stored data is the statistical result; (6) Observe the data of event A before event B occurs; The application scenario is: it is expected to observe high-frequency data A before the pulse of high-frequency data B occurs; The implementation method is: use a high-frequency clock to detect the rising edge or falling edge of high-frequency data A and high-frequency data B, and keep storing the pulse signal of high-frequency data A. When the storage limit is reached, the earliest stored data is discarded and the latest data is stored. When the pulse of high-frequency data B is detected, storage is stopped. The stored data is the statistical result.

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