BMC (Baseboard Management Controller) bus data buffer device, BMC bus and baseboard management controller

Abstract

The invention provides a BMC bus data buffering device, a BMC bus and a baseboard management controller, the BMC bus data buffering device comprises a preprocessing module, an address register module and a plurality of chain type buffering structures, each chain type buffering structure comprises a plurality of chain type buffering modules, each chain type buffering module comprises a chain type buffering area and a buffering processing module, chained buffer areas of chained buffer modules in the chained buffer structure form a chained storage structure; the preprocessing module is used for distributing data packets to the chained buffer structure according to the occupation condition of the BMC bus; and the address register module is used for acquiring address storage information of the data packet address in the address storage space corresponding to the chained buffer module, so that the buffer processing module determines the cache position of the data packet in the chained buffer area and performs cache processing, and the data packets of the same data source are close to each other. According to the invention, the processing speed of the data packet is improved, the jamming phenomenon of the BMC system in operation is effectively reduced, the response capability and stability of the system are enhanced, and moreover, as each channel can be coordinated to process the data packet, the continuous high-frequency operation of the processor is avoided, and the power consumption of the processor is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of computer hardware, and in particular to a BMC bus data buffer device, a BMC bus and a baseboard management controller. Background Art

[0002] In the hardware structure, the Baseboard Management Controller (BMC) is an embedded management microcontroller, usually integrated on the server motherboard, used to monitor, manage and maintain the server hardware and system. BMC has its own processor, memory and storage, and can run independently of the server's main processor. The BMC bus allows the system to monitor various hardware states, including but not limited to key parameters such as temperature, voltage, current, fan speed, etc., through data transmission with different modules. At the same time, it provides high-performance network interconnection solutions to support high-speed data transmission in the system.

[0003] In the existing bus solution, a linear architecture is generally adopted. In this architecture, each data source is connected to the processor through the BMC bus module. The BMC bus module will allocate a data transmission channel for each data source. Each data transmission channel does not affect each other. Subsequently, the BMC bus module allocates a bus channel for the data to be input into the processor for data processing.

[0004] In this conventional processing, the BMC bus through which the data packets of each module are transmitted to the processor is pre-set. This method is simple, but the scalability is poor. Under this data transmission strategy, some channels may be occupied for a long time and in a busy state, which is prone to channel congestion. If some channels are blocked, data cannot be transmitted in time and there will be jams. In addition, the BMC chip requires the processor to run at a high frequency all the time, which consumes a lot of power. Summary of the invention

[0005] The present invention provides a BMC bus data buffer device, a BMC bus and a baseboard management controller, which are used to solve the defects of easy jamming and high processor power consumption in the prior art, thereby reducing jamming and lowering processor power consumption.

[0006] The present invention provides a BMC bus data buffer device, comprising: a preprocessing module, an address register module and a plurality of chain buffer structures, wherein the data output ends of the chain buffer structures are respectively connected to the data transmission channels of the BMC bus, the data input ends of the chain buffer structures are respectively connected to the data output ends of the preprocessing modules, the chain buffer structure comprises a plurality of chain buffer modules, the chain buffer modules comprise chain buffer zones and buffer processing modules, the chain buffer zones of the chain buffer modules in the chain buffer structure constitute a chain storage structure, and the buffer processing modules are respectively connected to the address register modules in communication; wherein: the preprocessing module is used to receive data packets from various data sources, and send the data packets of the same data source to the same address register module; Based on the data transmission channel, the data packet is allocated to the chain buffer structure according to the occupancy of the BMC bus; wherein the data information of the data packet includes the data packet address; the buffer processing module is used to receive the data packet and send the data packet address to the address storage module; the address storage module is used to obtain the address storage information of the data packet address in the address storage space corresponding to the chain buffer module, and send the address storage information to the buffer processing module; the buffer processing module is also used to determine the cache position of the data packet in the corresponding chain buffer according to the address storage information, and cache the data packet according to the cache position, so that the data packets of the same data source are close.

[0007] According to a BMC bus data buffer device provided by the present invention, the address storage information includes first information that the data packet address does not exist in the address storage space corresponding to the chain buffer module; the address register module is also used to: after obtaining the first information, store the data packet address in the address storage space, and change the count of the data packet address from 0 to 1; the buffer processing module is also used to: after receiving the first information, store the data packet at the end of the data packet queue in the corresponding chain buffer.

[0008] According to a BMC bus data buffer device provided by the present invention, the address storage information includes second information that the data packet address exists in the address storage space corresponding to the chain buffer module; the address register module is also used to: after obtaining the second information, add 1 to the count of the data packet address; the buffer processing module is also used to: after receiving the second information, compare the data packet address with the address of the data packet currently at the end of the data packet queue in the corresponding chain buffer; if the addresses of the two data packets are the same, store the currently received data packet at the end of the data packet queue in the chain buffer.

[0009] According to a BMC bus data buffer device provided by the present invention, the buffer processing module is further used for: if the addresses of the two data packets are different, storing the currently received data packet in front of the data packet currently at the end of the data packet queue.

[0010] According to a BMC bus data buffer device provided by the present invention, when the buffer processing module is used to store the currently received data packet in front of the data packet currently at the end of the data packet queue, it is specifically used to: move the data packet currently at the end of the data packet queue out of the data packet queue and store it into a preset temporary storage space; after storing the currently received data packet at the end of the data packet queue, the data packet in the temporary storage space is stored at the end of the data packet queue.

[0011] According to a BMC bus data buffer device provided by the present invention, the data packet queue follows the first-in-first-out principle.

[0012] According to a BMC bus data buffer device provided by the present invention, for a chain buffer module connected to the data output end, the buffer processing module in the chain buffer module is also used to: transmit the data packet at the head of the data packet queue in the chain buffer in the chain buffer module to the processor through the BMC bus, and move the other data packets in the data packet queue forward by one position; for other chain buffer modules other than the chain buffer module connected to the data output end, the buffer processing module in the chain buffer module is also used to: along the transmission direction of the data packet, after the data packet in the previous chain buffer module moves position, transmit the data packet at the head of the data packet queue in the chain buffer in the chain buffer module to the next chain buffer module, and move the other data packets in the data packet queue forward by one position; the address storage module is also used to: for the data packet moved out of the chain buffer, reduce the count of the address of the corresponding data packet in the address storage space of the corresponding chain buffer module by 1.

[0013] According to a BMC bus data buffer device provided by the present invention, the number of the chain buffer modules in the chain buffer structure corresponding to each BMC bus is the same.

[0014] The present invention also provides a BMC bus, comprising any one of the above-mentioned BMC bus data buffer devices.

[0015] The present invention also provides a baseboard management controller, comprising the above-mentioned BMC bus.

[0016] The BMC bus data buffer device, BMC bus and baseboard management controller provided by the present invention allocate data packets to a chain buffer structure according to bus occupancy by using a preprocessing module, thereby fully utilizing the bandwidth of the data bus and reducing the waiting time for data processing of different data sources. The chain storage module determines the cache position of the data packet in the corresponding chain buffer according to the data packet address storage information, and performs cache processing on the data packet according to the cache position, so that data packets of the same data source are close to each other, thereby improving the processing speed of the data packet, effectively reducing the jamming phenomenon of the BMC system during operation, enhancing the responsiveness and stability of the system, and because each channel can be coordinated to process the data packet, the continuous high-frequency operation of the processor is avoided, thereby reducing the power consumption of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a structural schematic diagram of a BMC bus data buffer device provided by the present invention.

[0019] Figure 2 The present invention provides a schematic diagram of data transmission of a BMC bus data buffer device.

[0020] Figure 3 The present invention is a schematic diagram of a processing flow when the BMC bus data buffer device provided by the present invention performs cache processing on a data packet.

[0021] Figure 4 It is a structural schematic diagram of a baseboard management controller provided by the present invention.

[0022] Figure 5 It is a data transmission schematic diagram of the baseboard management controller provided by the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] Figure 1 It is a structural schematic diagram of a BMC bus data buffer device provided by the present invention. Figure 2 Schematic diagram of data transmission of the BMC bus data buffer device provided by the present invention. Figure 1 , Figure 2 As shown, the BMC bus data buffer device provided by the present invention includes: a preprocessing module 1, an address storage module 2 and a plurality of chain buffer structures 3, the data output ends of the chain buffer structures 3 are respectively connected to the data transmission channels of the BMC bus, the data input ends of the chain buffer structures 3 are respectively connected to the data output ends of the preprocessing module 1, the chain buffer structure 3 includes a plurality of chain buffer modules 4, the chain buffer module 4 includes a chain buffer 5 and a buffer processing module 6, the chain buffer 5 of the chain buffer modules 4 in the chain buffer structure 3 constitutes a chain storage structure, and the buffer processing module 6 is respectively communicated with the address storage module 2; wherein: the preprocessing module 1 is used to receive data packets from various data sources, and in the data packets of the same data source On the basis of being sent to the same data transmission channel, the data packet is allocated to the chain buffer structure 3 according to the occupancy of the BMC bus; wherein the data information of the data packet includes the data packet address; the buffer processing module 6 is used to receive the data packet and send the data packet address to the address storage module 2; the address storage module 2 is used to obtain the address storage information of the data packet address in the address storage space corresponding to the chain buffer module 4, and send the address storage information to the buffer processing module 6; the buffer processing module 6 is also used to determine the cache position of the data packet in the corresponding chain buffer 5 according to the address storage information, and cache the data packet according to the cache position, so that the data packets of the same data source are close.

[0025] The BMC bus data buffer device provided by the present invention belongs to the functional module of the BMC bus. After the data packets of each data source are cached by the BMC bus data buffer device, they are sent to the data transmission channel of the BMC bus, and then sent to the processor for processing through the data transmission channel of the BMC bus. The BMC bus data buffer device is connected to the data channels of each data source, buffers the data packets sent from different modules, and sends them to the processor for interaction after processing.

[0026] The BMC bus data buffer device is connected to each data source through the preprocessing module 1, receives the data packets sent by each data source, and performs preprocessing. The output end of the preprocessing module 1 corresponds to the BMC bus data transmission channel one by one, and each BMC bus data transmission channel corresponds to a chain buffer structure 3. Data packets from different data sources enter the input buffer of the preprocessing module 1 and wait to be sent to the BMC bus. The preprocessing module 1 can send data packets from different input sources to the same data bus according to the load of the bus, but in order to ensure data consistency, data from the same input source will only be sent to the same bus. Through the scheduling of the preprocessing module 1, when a BMC bus data transmission channel is occupied, the waiting data packets can be sent to other channels instead of waiting for the previous group of data packets to be processed before processing. Through this preprocessing method, the data bus bandwidth can be utilized to the maximum extent and the waiting time of data from different data sources can be reduced.

[0027] After being processed by the preprocessing module 1, although the bandwidth of the data bus is fully utilized, the data packets entering the data bus may come from different input sources. The processor's processing of data is still affected by the different input sources transmitted by the bus, and the processing speed will be slower than that of transmitting data from another input source after a single input source is transmitted. Therefore, the present invention reduces the impact on the data packet processing rate caused by fully utilizing the bandwidth through the design of a chain buffer.

[0028] Each data transmission channel of the BMC bus corresponds to a chain buffer structure 3, and the chain buffer structure 3 includes multiple chain buffer modules 4. The chain buffer module 4 includes a chain buffer 5 and a buffer processing module 6. The chain buffer 5 of the chain buffer module 4 in the chain buffer structure 3 constitutes a chain storage structure. Since the data packet is transmitted from the chain buffer module 4 connected to the preprocessing module 1 to the BMC bus. Therefore, the data output end of the chain buffer 5 of the data transmission channel connected to the BMC bus is the data output end of the corresponding chain buffer structure 3. The data input end of the buffer processing module 6 connected to the preprocessing module 1 is the data input end of the corresponding chain buffer structure 3. For each chain buffer module 4, the buffer processing module 6 receives the data packet, determines the cache position of the data packet, and then stores the data packet in the corresponding chain buffer 5 for caching.

[0029] The data information of the data packet received by the buffer processing module 6 includes the data packet address. The buffer processing module 6 receives the data packet and sends the data packet address to the address storage module 2. The address storage module 2 obtains the address storage information of the data packet address in the address storage space corresponding to the corresponding chain buffer module 4 (that is, the chain buffer module 4 where the buffer processing module 6 that currently sends the data packet address is located), and sends the address storage information to the buffer processing module 6. The data packet address is related to the data source, and the data packet addresses of the same data source are the same. The buffer processing module 6 determines the cache position of the data packet in the corresponding chain buffer 5 based on the address storage information. The principle of determining the cache position is to make the storage positions of the data packets of the same data source closer, and cache the data packets according to the cache position.

[0030] Since the buffer processing device 6 in each chain buffer module 4 processes the storage locations of data packets from the same data source to be close to each other, after the data packets arrive at the processor, the probability and ratio of the same data source being close to each other will be greatly improved, which will significantly improve the processor's processing speed for the data packets and reduce the probability of jamming.

[0031] Among them, each module can be converted into a hardware circuit by writing Verilog code.

[0032] The BMC bus data buffer device provided by the present invention allocates data packets to a chain buffer structure according to bus occupancy by using a preprocessing module, thereby fully utilizing the bandwidth of the data bus and reducing the waiting time for data processing of different data sources. The chain storage module determines the cache position of the data packet in the corresponding chain buffer according to the data packet address storage information, and performs cache processing on the data packet according to the cache position, so that data packets of the same data source are close to each other, thereby improving the processing speed of the data packet, effectively reducing the jamming phenomenon of the BMC system during operation, enhancing the responsiveness and stability of the system, and because each channel can be coordinated to process the data packet, the continuous high-frequency operation of the processor is avoided, thereby reducing the power consumption of the processor.

[0033] According to a BMC bus data buffer device provided by the present invention, the address storage information includes first information that the data packet address does not exist in the address storage space corresponding to the chain buffer module 4; the address register module is also used to: after obtaining the first information, store the data packet address in the address storage space, and change the count of the data packet address from 0 to 1; the buffer processing module 6 is also used to: after receiving the first information, store the data packet at the end of the data packet queue in the corresponding chain buffer 5.

[0034] The address register module 2 is used to obtain the address storage information of the data packet address in the address storage space corresponding to the chain buffer module 4. The address storage information may be the first information that the data packet address does not exist in the address storage space corresponding to the chain buffer module 4. If the data packet address does not exist in the address storage space corresponding to the chain buffer module 4, it means that the data packet corresponding to the data packet address has been moved out of the chain buffer module 4, or the data packet corresponding to the data packet address has not entered the chain buffer module 4. The initial count value of the data packet address is 0. If the data packet address does not exist in the address storage space corresponding to the chain buffer module 4, the address register module 2 stores the data packet address in the address storage space and changes the count of the data packet address from 0 to 1.

[0035] Correspondingly, after the buffer processing module 6 receives the first information that the data packet address does not exist in the address storage space corresponding to the chain buffer module 4, it indicates that there is no data packet from the same data source in the corresponding chain storage area 5, and then the data packet is stored at the end of the data packet queue in the corresponding chain buffer 5.

[0036] The BMC bus data buffer device provided by the present invention stores the data packet address in the address storage space after acquiring the first information, changes the count of the data packet address from 0 to 1, and stores the data packet at the end of the data packet queue in the corresponding linked buffer, thereby realizing data packet cache processing when there is no data packet from the same data source in the linked buffer.

[0037] According to a BMC bus data buffer device provided by the present invention, the address storage information includes second information that the data packet address exists in the address storage space corresponding to the chain buffer module 4; the address register module is also used to: after obtaining the second information, add 1 to the count of the data packet address; the buffer processing module 6 is also used to: after receiving the second information, compare the data packet address with the address of the data packet currently at the end of the data packet queue in the corresponding chain buffer 5; if the addresses of the two data packets are the same, the currently received data packet is stored at the end of the data packet queue in the chain buffer 5.

[0038] The address register module 2 obtains the address storage information of the data packet address in the address storage space corresponding to the chain buffer module 4. The address storage information can also be the second information that the data packet address exists in the address storage space corresponding to the chain buffer module 4. If the data packet address exists in the address storage space corresponding to the chain buffer module 4, it means that the chain buffer 5 of the chain buffer module 4 stores a data packet from the same data source as the data packet. At this time, the address register module 2 adds 1 to the count of the data packet address. Correspondingly, after receiving the second information that the data packet address exists in the address storage space corresponding to the chain buffer module 4, the buffer processing module 6 needs to perform the operation of bringing the data packets of the same data source closer together. In order to reduce the processing of too many data packets and the consumption of processing resources, the buffer processing module 6 compares the data packet address with the address of the data packet currently at the end of the data packet queue in the corresponding chain buffer 5. If the addresses of the two data packets are the same, it means that the newly received data packet and the data packet currently at the end of the queue are data packets from the same data source. Then, directly storing the currently received data packet at the end of the data packet queue in the chain buffer achieves the close processing of the data packets of the same data source.

[0039] The BMC bus data buffer device provided by the present invention adds 1 to the count of the data packet address when the data packet address exists in the address storage space corresponding to the chain buffer module, compares the data packet address with the address of the data packet currently at the end of the data packet queue in the corresponding chain buffer, and if the addresses of the two data packets are the same, stores the currently received data packet at the end of the data packet queue in the chain buffer, thereby realizing close processing of data packets from the same data source.

[0040] According to a BMC bus data buffer device provided by the present invention, the buffer processing module 6 is further used for: if the addresses of the two data packets are different, storing the currently received data packet in front of the data packet currently at the end of the data packet queue.

[0041] The address register module 2 obtains the address storage information of the data packet address in the address storage space corresponding to the chain buffer module 4. The address storage information can also be the second information that the data packet address exists in the address storage space corresponding to the chain buffer module 4. If the data packet address exists in the address storage space corresponding to the chain buffer module 4, it means that the chain buffer 5 of the chain buffer module 4 stores a data packet from the same data source as the data packet. At this time, the address register module 2 adds 1 to the count of the data packet address. Correspondingly, after receiving the second information that the data packet address exists in the address storage space corresponding to the chain buffer module 4, the buffer processing module 6 needs to perform an operation of bringing the data packets of the same data source closer. The buffer processing module 6 compares the data packet address with the address of the data packet currently at the end of the data packet queue in the corresponding chain buffer 5. If the addresses of the two data packets are different, it means that the newly received data packet is not a data packet from the same data source as the data packet currently at the end of the queue, and the data packet from the same data source as the newly received data packet is stored in other locations. At this time, in order to avoid processing too many data packets and consuming processing resources, the buffer processing module 6 stores the currently received data packet in front of the data packet currently at the end of the data packet queue. Compared with the traditional method of storing the newly received data at the end of the queue, after the newly received data packet is stored, it actually exchanges its position with the data packet originally at the end of the queue, making the storage position of the newly received data packet closer to the data packet from the same data source.

[0042] Figure 3 1 is a schematic diagram of the processing flow of the BMC bus data buffer device provided by the present invention when caching data packets. Figure 3 As shown, after a single data packet is input into the chain buffer module 4, the data packet address is stored in the corresponding address storage space in the address register module 2. The address register module 2 determines whether the data packet address is the first appearance of the address. If it is the first appearance, the address register module allocates the address storage space, the counter changes from 0 to 1, and the data packet is normally stored at the end of the data packet queue. If the data packet address is not the first appearance, the data packet address has been stored in the address register, the counter of the corresponding space of the address register is increased by 1, and the data packet address of the newly received data packet is compared with the previous data packet address. If the two data packet addresses are the same, the newly received data packet is stored at the end of the queue. If the two data packet addresses are different, the data packet data is swapped front and back, and the end of the queue is skipped and stored in the second position.

[0043] The BMC bus data buffer device provided by the present invention stores the currently received data packet in front of the data packet currently at the end of the data packet queue when the address of the newly received data packet is different from that of the data packet at the end of the currently processed queue, thereby realizing close processing of data packets from the same data source.

[0044] According to a BMC bus data buffer device provided by the present invention, when the buffer processing module 6 is used to store the currently received data packet in front of the data packet currently at the end of the data packet queue, it is specifically used to: move the data packet currently at the end of the data packet queue out of the data packet queue and store it into a preset temporary storage space; after storing the currently received data packet at the end of the data packet queue, the data packet in the temporary storage space is stored at the end of the data packet queue.

[0045] When the buffer processing module 6 stores the currently received data packet in front of the data packet currently at the tail of the data packet queue, it first moves the data packet currently at the tail of the data packet queue out of the data packet queue and stores it in a preset temporary storage space, and then stores the currently received data packet at the tail of the data packet queue after the original tail data packet is moved out, so that the newly received data packet is currently at the tail of the queue, and then the data packet in the temporary storage space is stored in the tail of the new data packet queue, so that the data packet originally at the tail of the queue is still at the tail of the queue, and the newly received data packet is moved to the front of the data packet originally at the tail of the queue.

[0046] The BMC bus data buffer device provided by the present invention improves the processing efficiency of data packet switching by removing the data packet currently at the end of the data packet queue from the data packet queue and storing it in a preset temporary storage space, storing the currently received data packet at the end of the data packet queue, and then storing the data packet in the temporary storage space at the end of the data packet queue.

[0047] According to a BMC bus data buffer device provided by the present invention, the data packet queue follows the first-in-first-out principle.

[0048] The data packets in the chain buffer 5 follow the First Input First Output (FIFO) principle, so the data packets after the exchange of positions will be output to the next chain buffer module 4 more quickly for further close processing of data packets from the same data source.

[0049] The BMC bus data buffer device provided by the present invention reduces the complexity of close processing of data packets from the same data source by making the data packet queue follow the first-in first-out principle.

[0050] According to a BMC bus data buffer device provided by the present invention, for the chain buffer module 4 connected to the data output end, the buffer processing module 6 in the chain buffer module 4 is also used to: transmit the data packet at the head of the data packet queue in the chain buffer 5 in the chain buffer module 4 to the processor through the BMC bus, and move the other data packets in the data packet queue forward by one position; for other chain buffer modules 4 other than the chain buffer module 4 connected to the data output end, the buffer processing module 6 in the chain buffer module 4 is also used to: along the transmission direction of the data packet, after the data packet in the previous chain buffer module 4 moves position, transmit the data packet at the head of the data packet queue in the chain buffer 5 in the chain buffer module 4 to the next chain buffer module 4, and move the other data packets in the data packet queue forward by one position; the address storage module 2 is also used to: for the data packet moved out of the chain buffer 5, reduce the count of the address of the corresponding data packet in the address storage space of the corresponding chain buffer module 4 by 1.

[0051] For the chain buffer module 4 connected to the data output end, that is, for a chain storage structure 3, the last chain buffer module 4 along the data transmission direction, the data packets in the chain storage area 3 in the chain buffer module 4 will be moved into the processor through the BMC bus for processing. After the processor processes a data packet, a new data packet can enter the processor for processing, and other data packets move forward one position. Therefore, for the chain buffer module 4 connected to the data output end, the buffer processing module 6 in the chain buffer module 4 is also used to: transmit the data packet at the head of the data packet queue in the chain buffer 5 in the chain buffer module 4 to the processor through the BMC bus, and move other data packets in the data packet queue forward one position. Among them, after receiving the information that the data packet of the corresponding chain buffer structure 3 has been processed by the processor, the data packet at the head of the data packet queue in the chain buffer 5 in the chain buffer module 4 can be transmitted to the processor through the BMC bus.

[0052] For other chain buffer modules 4 other than the chain buffer module 4 connected to the data output end, there are other chain buffer modules 4 along the data transmission direction of these chain buffer modules 4. After the data packet of the chain buffer module 4 connected to the data output end moves forward, the data packets in the other chain buffer modules 4 also move forward. Therefore, for other chain buffer modules 4 other than the chain buffer module 4 connected to the data output end, the buffer processing module 6 in the chain buffer module 4 is also used to: along the transmission direction of the data packet, after the data packet in the previous chain buffer module 4 moves, transmit the data packet at the head of the data packet queue in the chain buffer 5 in the chain buffer module 4 to the next chain buffer module 4, and move the other data packets in the data packet queue forward by one position.

[0053] For a data packet moved out of the chain buffer 5, the address of the corresponding data packet in the address storage space corresponding to the chain buffer module 4 where the data packet is located should be reduced by 1. Therefore, the address register module 2 is also used for: for a data packet moved out of the chain buffer 5, reducing the count of the address of the corresponding data packet in the address storage space of the corresponding chain buffer module 4 by 1.

[0054] Assume that the chain buffer modules 4 in the chain storage structure 3 are X1, X2, ..., XN in the data transmission direction. When the first data packet enters the chain buffer 5 of X1, the address register 2 records the address of the first data packet. When the second data packet enters the chain buffer 5 of X1, the address register 2 continues to record the address. That is, whenever a new data packet enters the chain buffer 5, the address register 2 will record the address. At this time, the address of the new data packet is judged against the existing address in the address register 2. When the address comparison result is a new address, the data packet is directly stored normally and stored at the end of the queue. When the address of the new data packet is repeated with the previously recorded address, the corresponding address count of the address register is increased by one, and the new data packet is compared with the address of the previous data packet. If the address is the same as the previous data packet address, it means that the two data packets are associated data, and then they are stored normally. If the address is not the same as the previous data packet address, the two data packets are swapped. Since the chain buffer adopts the first-in-first-out principle, the data packets after swapping positions will be output to the next chain buffer module X2 faster.

[0055] When the data packet is output from the chain buffer 5 of X1 and input to the chain buffer 5 of X2, the corresponding address count in the address storage space of the address register 2 of X1 is reduced by 1. If the count is reduced to 0, it means that the address no longer exists in the chain buffer 5 of X1, and the space of the address register 2 can be used to write other addresses.

[0056] When a data packet passes through N chain buffers, it may go through a maximum of N position swaps. If there is a position swap, the data packet will definitely be closer to the data packet from the same input source. As the N setting increases, the data packet is likely to be adjacent to the data packet with the same address. For example, data packets a1, a2, and a3 from the same data source have an interval of 4 when entering the chain buffer. After passing through 8 chain buffers, these three data packets will be adjacent. The processor speeds up when processing data packets from the same input source. Therefore, under the premise of fully utilizing the bandwidth, the effect of continuous transmission of data packets from a single data source is achieved as much as possible.

[0057] The BMC bus data buffer device provided by the present invention ensures the reliability of buffer processing by sending a data packet to a processor for processing, and other data packets follow and move forward, and after the data packet is moved out of the chain buffer, the address count of the data packet in the corresponding address storage space is reduced by 1.

[0058] According to a BMC bus data buffer device provided by the present invention, the number of the chain buffer modules 4 in the chain buffer structure 3 corresponding to each BMC bus is the same.

[0059] When the number of chain buffer modules 4 in each chain buffer structure 3 is the same, the structure of each chain buffer structure 3 is the same, and the processing capacity of each chain buffer structure 3 is the same. When the preprocessing module 1 allocates data packets to the chain buffer structure 3, it only needs to consider the occupancy of the bus channel and the waiting situation of the data, which improves the ease of use. In addition, the same structure of each chain buffer structure 3 is also convenient for implementation. It can be understood that although the same number of chain buffer modules 4 in the chain buffer structure 3 corresponding to each BMC bus has an advantage, it is not necessarily required that the number of chain buffer modules 4 in the chain buffer structure 3 corresponding to each BMC bus must be the same, and there may also be a situation where the number of chain buffer modules 4 in the chain buffer structure 3 is different.

[0060] The BMC bus data buffer device provided by the present invention improves ease of use and convenience of implementation by ensuring that the number of chain buffer modules in the chain buffer structure corresponding to each BMC bus is the same.

[0061] The present invention also provides a BMC bus, which includes the BMC bus data buffer device described in any of the above embodiments. The present invention increases the transmission efficiency and reduces system jams by adding a chain buffer design to the BMC bus without increasing the operating frequency.

[0062] Figure 4 It is a structural schematic diagram of a baseboard management controller provided by the present invention. Figure 5 Schematic diagram of data transmission of the baseboard management controller provided by the present invention. Figure 4, Figure 5 As shown, the baseboard management controller provided by the present invention includes a BMC bus 10 and a processor 20, wherein the BMC bus 10 includes a BMC bus data buffer device 101. The BMC bus data buffer device 101 is any BMC bus data buffer device provided in the above embodiments. After the data of each data source is buffered by the BMC bus data buffer device 101, it is sent to the processor for processing through the data channel of the BMC bus 10.

[0063] Through the above technical implementation, the present invention can make full use of the bandwidth of the data bus at the same frequency, reduce the waiting time for data processing from different data sources, and reorder the data packets during transmission through the design of chain buffer to speed up the processing speed of data packets from the same data source. Thereby, the processor can execute more data within a certain period of time, effectively reducing the jamming phenomenon of the BMC system during operation. This not only improves the data processing speed, but also enhances the responsiveness and stability of the system.

[0064] This chain buffer design method is suitable for occasions that require high data throughput and low latency, such as large data centers, cloud computing platforms, high-performance computing clusters, etc. In these scenarios, fast processing and transmission of data is crucial to maintaining system performance.

[0065] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0066] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A BMC bus data buffer device, characterized in that: include: A preprocessing module, an address storage module and a plurality of chain buffer structures, wherein the data output ends of the chain buffer structures are respectively connected to the data transmission channels of the BMC bus, the data input ends of the chain buffer structures are respectively connected to the data output ends of the preprocessing modules, the chain buffer structure comprises a plurality of chain buffer modules, the chain buffer modules comprise chain buffer zones and buffer processing modules, the chain buffer zones of the chain buffer modules in the chain buffer structure constitute a chain storage structure, and the buffer processing modules are respectively connected in communication with the address storage modules; wherein: The preprocessing module is used to receive data packets from various data sources, and on the basis of sending data packets from the same data source to the same data transmission channel, allocate the data packets to the chain buffer structure according to the occupancy of the BMC bus; wherein the data information of the data packet includes the data packet address; The buffer processing module is used to receive the data packet and send the data packet address to the address storage module; The address storage module is used to obtain the address storage information of the data packet address in the address storage space corresponding to the chain buffer module, and send the address storage information to the buffer processing module; The buffer processing module is also used to determine the cache position of the data packet in the corresponding linked buffer according to the address storage information, and perform cache processing on the data packet according to the cache position so that the data packets from the same data source are close to each other.

2. The BMC bus data buffer device according to claim 1, characterized in that: The address storage information includes first information that the address of the data packet does not exist in the address storage space corresponding to the chain buffer module; The address register module is further used to: after acquiring the first information, store the data packet address in the address storage space, and change the count of the data packet address from 0 to 1; The buffer processing module is further configured to: after receiving the first information, store the data packet at the tail of the data packet queue in the corresponding linked buffer.

3. The BMC bus data buffer device according to claim 1, characterized in that: The address storage information includes second information that the address of the data packet exists in the address storage space corresponding to the chain buffer module; The address register module is further used to: after acquiring the second information, add 1 to the count of the data packet address; The buffer processing module is further used for: after receiving the second information, comparing the address of the data packet with the address of the data packet currently at the end of the data packet queue in the corresponding linked buffer; If the addresses of the two data packets are the same, the currently received data packet is stored at the end of the data packet queue in the chain buffer.

4. The BMC bus data buffer device according to claim 3, characterized in that: The buffer processing module is also used for: If the addresses of the two data packets are different, the currently received data packet is stored in front of the data packet currently at the end of the data packet queue.

5. The BMC bus data buffer device according to claim 4, characterized in that: When the buffer processing module is used to store the currently received data packet in front of the data packet currently at the end of the data packet queue, it is specifically used to: The data packet currently at the end of the data packet queue is removed from the data packet queue and stored in a preset temporary storage space; After the currently received data packet is stored at the end of the data packet queue, the data packet in the temporary storage space is stored at the end of the data packet queue.

6. The BMC bus data buffer device according to claim 2 or 3, characterized in that: The data packet queue follows the first-in-first-out principle.

7. The BMC bus data buffer device according to claim 6, characterized in that: For the chain buffer module connected to the data output end, the buffer processing module in the chain buffer module is further used to: transmit the data packet at the head of the data packet queue in the chain buffer in the chain buffer module to the processor through the BMC bus, and move other data packets in the data packet queue forward by one position; For other chain buffer modules other than the chain buffer module connected to the data output end, the buffer processing module in the chain buffer module is further used to: after the data packet in the previous chain buffer module moves its position along the transmission direction of the data packet, transmit the data packet at the head of the data packet queue in the chain buffer in the chain buffer module to the next chain buffer module, and move the other data packets in the data packet queue forward by one position; The address register module is further used for: for a data packet moved out of the chain buffer, reducing the count of the address of the data packet in the address storage space of the corresponding chain buffer module by 1.

8. The BMC bus data buffer device according to claim 1, characterized in that: The number of the chain buffer modules in the chain buffer structure corresponding to each BMC bus is the same.

9. A BMC bus, characterized in that: It comprises the BMC bus data buffer device as described in any one of claims 1 to 8.

10. A baseboard management controller, characterized in that: Including the BMC bus described in claim 9.

Images