PCIe equipment configuration method and device, electronic equipment and storage medium

Abstract

The invention provides a PCIe device configuration method and device, an electronic device and a storage medium, and is applied to the technical field of computers, the method provides a first preset device topology, at least one PCIe device link is recorded through the first preset device topology, any PCIe device in the PCIe device link supports an ARI function, and on the basis, when a PCIe bus system is subjected to device scanning, the ARI function is recorded through the first preset device topology, and the ARI function is recorded through the first preset device topology. After the PCIe device included in the current configuration period of the PCIe bus system is identified, the ARI function of the PCIe device in the PCIe bus system is enabled at least based on the first preset device topology, through the configuration method provided by the invention, the ARI function of the PCIe device can be automatically configured, the time required by a user for configuring the ARI function is saved, compared with manual configuration, the ARI function configuration efficiency is higher, and the user experience is improved. And the application requirement of efficient operation of a computer system is met.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a PCIe device configuration method, apparatus, electronic device and storage medium. Background Art

[0002] Based on PCIe (Peripheral Component Interconnect express) technology, each device in the PCIe bus system supports up to 8 functions, and each function corresponds to a unique function identifier. With the application of virtualization technology and the increase in device load, there are often insufficient function identifiers.

[0003] To solve this problem, PCIe technology provides the ARI (Alternative Routing-ID Interpretation) function. When the ARI function is enabled, the unused device identifiers in the PCIe bus system can be converted into functional identifiers for use, so that PCIe devices can support more device functions and meet actual application needs.

[0004] However, the inventors have found that in actual applications, users are required to manually configure the ARI function of each PCIe device in the PCIe bus system. Especially when the PCIe bus system includes multiple PCIe devices, not only is the configuration inefficient, but it also consumes a lot of user time and energy, making it difficult to meet the application requirements for efficient operation of the computer system. Summary of the invention

[0005] In view of this, the present application is committed to providing a PCIe device configuration method, apparatus, electronic device and readable storage medium to solve the problem in the prior art that the PCIe device configuration efficiency is low and it is difficult to meet the actual application needs.

[0006] In a first aspect, the present application provides a PCIe device configuration method, which is applied to a PCIe bus system, and the method comprises:

[0007] Performing device scanning on the PCIe bus system to identify PCIe devices included in the PCIe bus system in a current configuration cycle;

[0008] enabling an alternative routing ARI function of a PCIe device in the PCIe bus system based at least on a first preset device topology;

[0009] The first preset device topology records at least one PCIe device link, and any PCIe device in the PCIe device link supports the ARI function.

[0010] In an optional implementation, enabling an alternative routing ARI function of a PCIe device in the PCIe bus system based at least on a first preset device topology includes:

[0011] Determining whether a device update occurs in the PCIe bus system based on the PCIe devices included in the current configuration cycle of the PCIe bus system;

[0012] If no device update occurs in the PCIe bus system, enabling an ARI function of the PCIe device in the PCIe bus system according to the first preset device topology;

[0013] If a device update occurs in the PCIe bus system, an ARI function of the PCIe device in the PCIe bus system is enabled according to the device update status and the first preset device topology.

[0014] In an optional implementation, determining whether a device update occurs in the PCIe bus system based on a PCIe device currently included in the PCIe bus system includes:

[0015] Acquire a second preset device topology, where the second preset device topology records all PCIe devices included in the PCIe bus system in a previous configuration cycle;

[0016] If the PCIe devices included in the current configuration cycle of the PCIe bus system are consistent with the PCIe devices recorded in the second preset device topology, it is determined that no device update occurs in the PCIe bus system;

[0017] If the PCIe devices included in the current configuration cycle of the PCIe bus system are inconsistent with the PCIe devices recorded in the second preset device topology, it is determined that a device update occurs in the PCIe bus system.

[0018] In an optional implementation manner, enabling the ARI function of the PCIe device in the PCIe bus system according to the device update status and the first preset device topology includes:

[0019] If the PCIe bus system includes a newly added PCIe device, enabling the ARI function of each PCIe device in the first preset device topology, and configuring the ARI function of the newly added PCIe device according to the ARI function support status of the newly added PCIe device;

[0020] If the PCIe bus system uninstalls at least one target PCIe device, the ARI function of the PCIe device in the PCIe bus system is enabled according to the subordinate relationship between the target PCIe device and the first preset device topology and the first preset device topology.

[0021] In an optional implementation, enabling the ARI function of the PCIe device in the PCIe bus system according to the subordinate relationship between the target PCIe device and the first preset device topology and the first preset device topology includes:

[0022] If the target PCIe device is recorded in the first preset device topology, enabling ARI functions of other PCIe devices except the target PCIe device in the first preset device topology;

[0023] If the target PCIe device is not recorded in the first preset device topology, an ARI function of each PCIe device in the first preset device topology is enabled.

[0024] In an optional implementation, the PCIe device configuration method provided in the first aspect of the present application further includes:

[0025] The first preset device and the second preset device topology are updated according to the PCIe devices included in the current configuration cycle of the PCIe bus system.

[0026] In an optional implementation, the process of creating the first preset device topology includes:

[0027] Performing device scanning on the PCIe bus system in a target configuration cycle to identify PCIe devices included in the PCIe bus system in the target configuration cycle, wherein the target configuration cycle includes any configuration cycle before the current configuration cycle;

[0028] Determine at least one PCIe device link according to the communication connection relationship between the PCIe devices;

[0029] Each of the PCIe device links is recorded in a preset format to obtain the first preset device topology.

[0030] In an optional implementation, the PCIe devices included in the PCIe bus system include at least a root complex RC device and an endpoint EP device;

[0031] Determining at least one PCIe device link according to the communication connection relationship between the PCIe devices includes:

[0032] Determine a root port supporting the ARI function among the root ports of the RC device as a target root port;

[0033] Determine an EP device supporting the ARI function among the EP devices connected to each of the target root ports as the target EP device;

[0034] A PCIe device link is created according to the communication connection relationship between the target root port and the target EP device.

[0035] In an optional implementation, the PCIe bus system further includes a switching device;

[0036] Determining at least one PCIe device link according to the communication connection relationship between the PCIe devices includes:

[0037] Determine a root port supporting the ARI function among the root ports of the RC device as a target root port;

[0038] Determine a switching device supporting the ARI function among the switching devices connected to each of the target root ports as a target switching device;

[0039] Determine an EP device supporting the ARI function among the EP devices connected to each of the target root ports and each of the target switching devices as a target EP device;

[0040] A PCIe device link is created according to the communication connection relationship among the target root port, the target switching device and the target EP device.

[0041] In a second aspect, the present application provides a PCIe device configuration device, which is applied to a PCIe bus system, and the device includes:

[0042] A scanning unit, configured to perform device scanning on the PCIe bus system to identify PCIe devices included in the PCIe bus system in a current configuration cycle;

[0043] A configuration unit, configured to enable an alternative routing ARI function of a PCIe device in the PCIe bus system based at least on a first preset device topology;

[0044] The first preset device topology records at least one PCIe device link, and any PCIe device in the PCIe device link supports the ARI function.

[0045] In a third aspect, the present application provides an electronic device, including:

[0046] Memory and processor;

[0047] Wherein, the memory is used to store programs;

[0048] The processor is used to implement the PCIe device configuration method as described in any one of the first aspects of the present application by running the program in the memory.

[0049] In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the PCIe device configuration method as described in any one of the first aspects of the present application is implemented.

[0050] Based on the above content, the PCIe device configuration method provided by the present application provides a first preset device topology, records at least one PCIe device link through the first preset device topology, and any PCIe device in the PCIe device link supports the ARI function. Based on this, after performing a device scan on the PCIe bus system and identifying the PCIe devices included in the current configuration cycle of the PCIe bus system, the ARI function of the PCIe device in the PCIe bus system is enabled at least based on the first preset device topology. Through the configuration method provided by the present application, the ARI function of the PCIe device can be automatically configured, saving the time required for the user to configure the ARI function, and compared with manual configuration, the ARI function configuration efficiency is higher, meeting the application requirements of efficient operation of the computer system. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0052] Figure 1 It is a topological structure diagram of a PCIe bus system in the prior art.

[0053] Figure 2 This is a flow chart of a PCIe device configuration method provided by this application.

[0054] Figure 3 This is another topological structure diagram of a PCIe bus system in the prior art.

[0055] Figure 4 This is a flowchart of another PCIe device configuration method provided by this application.

[0056] Figure 5 This is a flowchart of a first preset device topology creation method provided in this application.

[0057] Figure 6 This is a structural block diagram of a PCIe device configuration device provided by this application.

[0058] Figure 7 This is a structural block diagram of another PCIe device configuration device provided by the present application.

[0059] Figure 8 It is a structural block diagram of an electronic device provided by this application. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0061] PCIe is a high-speed serial computer expansion bus standard, which is widely used for communication between processors and high-speed peripherals. In practical applications, the PCIe bus system consists of multiple point-to-point interconnected components. Figure 1 The topology diagram of the PCIe bus system shown in FIG. 1 shows a PCIe bus system that generally adopts a tree topology. The aforementioned interconnected components mainly include a CPU (processor or processor core) and PCIe devices, wherein PCIe devices include various types such as root complex (RC) devices, switch devices (Switch) and endpoint (EP) devices. In other implementations, PCIe devices may also include PCIe bridges. In addition, the PCIe bus system may also include memory.

[0062] In a typical CPU+accelerator heterogeneous computing system, the RC device is located between the CPU and the PCIe topology. It is connected to the CPU through a bus and has at least one root port. It communicates with each PCIe device in the PCIe tree topology through the root port. The main function of the RC device is to complete the address conversion from the memory domain to the PCIe bus domain. It is also the root of the PCIe bus system. The interfaces of the PCIe bus system and peripherals can be integrated into the RC device. It can lead to several root ports, and each root port can be connected to the PCIe node. The RC device can obtain the request information transmitted by the PCIe device to access the memory. Correspondingly, the RC device can also send the processor's request information to the EP device mounted on the system, thereby realizing the communication between the processor and the EP device. For any root port, it can support the Alternative Routing-ID Interpretation (ARI) function or not.

[0063] EP devices can be understood as devices that implement independent functions in the PCIe bus system. Different EP devices often support different functions, so that the PCIe bus system as a whole can support diverse application functions. In actual applications, the more typical EP devices include graphics cards, network cards, etc. At the same time, EP devices are similar to RC devices and can be used as the initiator or responder of PCIe transactions in actual applications.

[0064] As the middleware between RC devices and EP devices, the switching device is mainly responsible for transmitting data between RC devices and EP devices. It is generally not the initiator of the request or the final receiver. At the same time, the switching device can also be used to expand the PCIe link. Each data link of the PCIe bus only covers two devices, which cannot meet the data transmission requirements. Therefore, it can be expanded through the switching device.

[0065] Combination Figure 1 As shown, the switching device includes an upstream port and at least one downstream port ( Figure 1 The upstream port and downstream port of the switching device both support the PCIe bus standard. The RC device is connected to the upstream port of the switching device, and the downstream port of the switching device is connected to the corresponding EP device. Similar to the root port of the aforementioned RC device, the downstream port of the switching device may or may not support the ARI function.

[0066] It should be noted that Figure 1 This is only an example of the structure of a system on a chip. In other examples, the system on a chip may also include a switching device, or the switching device may also be set inside the system on a chip, which will not be described in detail here. Furthermore, in another possible implementation, the switching device may also be integrated with any EP device, and the PCIe device obtained by the integrated setting may be regarded as an EP device with the aforementioned switching device function.

[0067] In actual applications, there are often multiple PCIe devices mounted on the PCIe bus system. In order to effectively distinguish each PCIe device and ensure the accuracy of data transmission, the PCIe bus system assigns a unique device identification information, namely, the BDF identifier (Bus, Device, Function), to each function of each PCIe device mounted on the system.

[0068] As for the specific composition of the BDF identifier, the Bus field consists of 8 bits, the Device (Dev) field consists of 5 bits, and the Function (Function, Func) consists of 3 bits. Therefore, the PCIe protocol supports a total of 256 Buses, each Bus supports up to 32 Devs, and each Dev supports up to 8 Funcs. Through the BDF identifier, any PCIe function in the PCIe bus system topology can be distinguished and identified.

[0069] However, with the application of virtualization technology and the increase in device load in recent years, there are often insufficient function identifiers (Func). To solve this problem, PCIe technology provides the ARI function. When the ARI function is enabled, the unused device identifiers in the PCIe bus system can be converted into function identifiers, so that PCIe devices can support more device functions and meet actual application needs.

[0070] The inventors have found that in actual applications, users are required to manually configure the ARI function of each PCIe device in the PCIe bus system. Especially when the PCIe bus system includes multiple PCIe devices, not only is the configuration efficiency low, but it also consumes a lot of user time and energy, making it difficult to meet the application requirements for efficient operation of the computer system.

[0071] To solve the above problems, the present application provides a PCIe device configuration method, which records at least one PCIe device link through a first preset device topology, and any PCIe device in the PCIe device link supports the ARI function. After identifying the PCIe devices included in the PCIe bus system in the current configuration cycle, the ARI function of the PCIe device in the PCIe bus system is enabled at least based on the first preset device topology, and the ARI function of the PCIe device is automatically configured, saving the user's time required to configure the ARI function. Compared with manual configuration, the ARI function configuration efficiency is higher, which meets the application requirements of efficient operation of the computer system.

[0072] The PCIe device configuration method provided in the present application is applied to a processor, which may be integrated in a Figure 1 The processor in the system on chip shown may also be a processor that is independently set up with the PCIe bus system and exchanges information with the PCIe bus system. Furthermore, if the processor is further divided into a processor core and a PCIe controller, the method may also be specifically applied to the PCIe controller. In some cases, the PCIe device configuration method provided in the present application may also be applied to a server on the network side.

[0073] See also Figure 3As shown, the PCIe device configuration method provided in this application includes the following steps.

[0074] S100: Scan the PCIe bus system for devices to identify PCIe devices included in the PCIe bus system in a current configuration cycle.

[0075] Before data interaction with the PCIe bus system, the processor (or PCIe controller) needs to perform a device scan on the PCIe system to identify all PCIe devices included in the current configuration cycle of the PCIe bus system. It is understandable that the reason why all PCIe devices in the current configuration cycle are emphasized is that in actual applications, the PCIe devices mounted by the PCIe bus system may change, such as adding new PCIe devices or reducing PCIe devices. Therefore, it is necessary to perform the PCIe device configuration method provided by this application each time, that is, to identify the PCIe devices actually mounted by the PCIe bus system in each configuration cycle.

[0076] Further, based on the communication requirements between the processor and the PCIe bus system, after each power-on startup of the processor and the electronic device to which the PCIe bus system belongs, if the processor is provided with a processor core and a PCIe controller, the processor core will first initialize the PCIe controller, and after the PCIe controller completes the initialization operation, the PCIe device configuration method provided by the present application will be executed. Based on this, the aforementioned process of scanning the device of the PCIe bus system may also occur during the power-on startup process of the electronic device. In this case, the power-on startup process can be regarded as a configuration cycle. It is understandable that the length of the configuration cycle can be set according to the frequency of PCIe device changes in the PCIe bus system. If the PCIe device of the PCIe bus system changes frequently, the configuration cycle can be set shorter. On the contrary, if the PCIe device does not change frequently, the configuration cycle can be set longer.

[0077] In an optional implementation, a depth-first search algorithm (Breadth First Search, BFS) may be used to traverse the tree structure of the PCIe bus system. Figure 2The tree structure of the PCIe bus system shown in the figure, when scanning the PCIe system, first scan the devices on Bus 0; then scan RC0, and determine whether there is a device by reading the identity document (ID), such as the Vendor ID, etc. If it exists, then determine the type of this device by reading the specified register in the configuration space, that is, determine whether the current PCIe device is an EP device or an RC device. When it is determined to be an RC device, set the downstream bus number of the RC0 device to Bus 1; continue to scan downward, and then scan and find the EP0 device. Because the EP device is a terminal device, the enumeration scan of this branch ends, and it will return to the upper level bus (here is Bus 0) to continue scanning; repeat this process until all PCIe devices mounted on the PCIe bus system are found.

[0078] Of course, the PCIe bus system can also be scanned by other methods. As long as the method can identify all PCIe devices mounted on the PCIe bus system, it is optional and also falls within the scope of protection of this application without exceeding the core idea of ​​this application.

[0079] S110: Enable an alternative routing ARI function of a PCIe device in a PCIe bus system based at least on a first preset device topology.

[0080] The present application provides a first preset device topology, in which at least one PCIe device link is recorded, and any PCIe device in each PCIe device link supports the ARI function. After all PCIe devices in a PCIe bus system are identified, the ARI function of the corresponding PCIe device in the PCIe bus system is enabled at least according to the PCIe devices supporting the ARI function recorded in the first preset device topology.

[0081] It should be noted that the enabling of the ARI function also needs to consider other conditions, and the specific configuration process will be expanded in the subsequent content, which will not be described in detail here. Further, the specific creation process of the first preset device topology will also be expanded in the subsequent content, which will not be described in detail here.

[0082] To summarize, the PCIe device configuration method provided by the present application provides a first preset device topology, records at least one PCIe device link through the first preset device topology, and any PCIe device in the PCIe device link supports the ARI function. After identifying the PCIe devices included in the current configuration cycle of the PCIe bus system, the ARI function of the PCIe device in the PCIe bus system is enabled at least based on the first preset device topology, thereby automatically configuring the ARI function of the PCIe device, saving the user the time required to configure the ARI function, and compared with manual configuration, the ARI function configuration efficiency is higher, meeting the application requirements of efficient operation of the computer system.

[0083] Furthermore, at least one PCIe device link is recorded through the first preset device topology, and each PCIe device in the PCIe device link supports the ARI function. When configuring the ARI function, it is directly configured according to the information recorded in the first preset device topology, which can avoid traversing each PCIe device in the PCIe bus system again, and significantly improve the configuration efficiency of the ARI function.

[0084] Further, in Figure 2 Based on the embodiment shown, the present application provides another PCIe device configuration method, see Figure 4 As shown, the PCIe device configuration method provided in this embodiment includes the following steps.

[0085] S200: Scan the PCIe bus system for devices to identify PCIe devices included in the PCIe bus system in the current configuration cycle.

[0086] In an optional implementation, the specific implementation process of S200 can refer to Figure 2 The relevant contents of S100 in the illustrated embodiment will not be repeated here.

[0087] S210. Determine whether a device update occurs in the PCIe bus system based on the PCIe devices included in the current configuration cycle of the PCIe bus system. If not, execute S220. If yes, execute S230.

[0088] After identifying all PCIe devices included in the current configuration cycle of the PCIe bus system, in this step, it is further determined whether a device update occurs in the PCIe bus system. If no device update occurs, S220 is executed. On the contrary, if a device update occurs, S230 is executed.

[0089] In an optional implementation, the PCIe devices mounted in each configuration cycle of the PCIe bus system can be recorded. Based on this, after all PCIe devices mounted by the PCIe bus system in the current configuration cycle are determined, all PCIe devices mounted by the PCIe bus system in the current configuration cycle are compared with the recorded PCIe devices of the PCIe bus system in the previous configuration cycle, so as to determine whether a device update occurs in the PCIe bus system in the current configuration cycle.

[0090] In another optional embodiment, the present application also provides a second preset device topology, which records all PCIe devices included in the PCIe bus system in the previous configuration cycle. Based on this, the PCIe devices included in the PCIe bus system in the current configuration cycle are compared one by one with the PCIe devices recorded in the second preset device topology. If the PCIe devices included in the PCIe bus system in the current configuration cycle are consistent with the PCIe devices recorded in the second preset device topology, it is determined that no device update has occurred in the PCIe bus system. On the contrary, if the PCIe devices included in the PCIe bus system in the current configuration cycle are inconsistent with the PCIe devices recorded in the second preset device topology, it is determined that a device update has occurred in the PCIe bus system.

[0091] Furthermore, the present application provides a method for creating a second preset device topology. After executing the aforementioned S100 or S200, all PCIe devices mounted by the PCIe bus system in the current configuration cycle and the connection relationship between the PCIe devices can be obtained. Based on this, the aforementioned scanning results are recorded in a preset form, for example, an array or a linked list, and the second preset device topology can be obtained. In the next configuration cycle, the second preset device topology created in the current configuration cycle can be used to determine whether a device update has occurred. It is understandable that if the device update frequency of the PCIe bus system is extremely low, it is also feasible to complete the creation of the second preset device topology once and use it in multiple subsequent configuration cycles.

[0092] S220: Enable the ARI function of the PCIe device in the PCIe bus system according to the first preset device topology.

[0093] When it is determined that no device update occurs in the PCIe bus system, the ARI function of each PCIe device recorded in the first preset device topology can be enabled according to the record of the first preset device topology.

[0094] S230: Enable the ARI function of the PCIe device in the PCIe bus system according to the device update status and the first preset device topology.

[0095] It is understandable that the device update of the PCIe bus system can be divided into two situations, one is that the PCIe bus system adds a new PCIe device, and the other is that the PCIe system reduces the PCIe device.

[0096] Based on the above situation, when the PCIe bus system includes newly added PCIe devices, it is necessary to enable the ARI function of each PCIe device recorded in the first preset device topology. At the same time, it is necessary to further configure the ARI function of the newly added PCIe device according to the ARI function support of the newly added PCIe device.

[0097] For a newly added PCIe device in a PCIe bus system, the present application provides a method for configuring the ARI function of the device. Figure 1 As shown in the system architecture diagram, after determining that the PCIe bus system includes a newly added PCIe device, first determine the device type of the newly added PCIe device. If the newly added PCIe device is an RC device, determine whether each root port of the RC device supports the ARI function. If any root port supports the ARI function, enable the ARI function of the root port. Correspondingly, if any root port does not support the ARI function, the ARI function of the port cannot be enabled.

[0098] It should be noted that since the root port can be further connected to a switching device or an EP device, based on this, if any root port supports the ARI function, after enabling the ARI function of the root port, it will continue to determine whether other PCIe devices connected to the root port support the ARI function, and enable the ARI function of the PCIe devices that support the ARI function. Correspondingly, if the root port does not support the ARI function, even if other PCIe devices connected to it support the ARI function, it is not necessary to enable its ARI function.

[0099] If the newly added PCIe device is a switching device, determine whether each downstream port of the switching device supports the ARI function. If any downstream port supports the ARI function, enable the ARI function of the downstream port. Correspondingly, if any downstream port does not support the ARI function, the ARI function of the downstream port cannot be enabled.

[0100] It should be noted that, similar to the aforementioned RC device, the downstream port of the switching device can be further connected to the EP device. Based on this, if any downstream port of the switching device supports the ARI function, after enabling the ARI function of the downstream port, it will continue to determine whether other EP devices connected to the downstream port support the ARI function, and enable the ARI function of the EP devices that support the ARI function. Correspondingly, if the downstream port does not support the ARI function, even if other EP devices connected to it support the ARI function, it is not necessary to enable its ARI function.

[0101] If the newly added PCIe is an EP device, it is directly determined whether the EP device supports the ARI function. For EP devices that support the ARI function, the ARI function is enabled. Correspondingly, for EP devices that do not support the ARI function, the ARI function cannot be enabled, that is, no processing is performed on the EP device.

[0102] In an optional implementation, after the aforementioned steps, the specific situation of whether the newly added PCIe device supports the ARI function and the connection relationship between the newly added PCIe device and other PCIe devices in the PCIe bus system have been determined. Based on this, the first preset device topology and the second preset device topology can also be updated according to the PCIe devices (including original PCIe devices and newly added PCIe devices) included in the current configuration cycle of the PCIe bus system.

[0103] Furthermore, in view of the situation where a PCIe bus system reduces PCIe devices, the present application also provides a method for configuring the ARI function of the device.

[0104] Specifically, the PCIe device reduced in the PCIe bus system is defined as the target PCIe device. If the PCIe bus system uninstalls at least one target PCIe device, it is necessary to enable the ARI function of the PCIe device in the PCIe bus system according to the subordinate relationship between the target PCIe device and the first preset device topology and the first preset device topology. First, determine the subordinate relationship between the target PCIe device and the aforementioned first preset device topology, that is, determine whether the target PCIe device is recorded in the first preset device topology. If the target PCIe device is recorded in the first preset device topology, it means that the PCIe devices in the first preset device topology are reduced, and the ARI function of other PCIe devices other than the target PCIe device in the first preset device topology is enabled; correspondingly, if the target PCIe device is not recorded in the first preset device topology, it means that the reduction of the target PCIe device does not affect the first preset device topology. In this case, the ARI function of each PCIe device in the first preset device topology can be enabled according to the record of the first preset device topology.

[0105] In an optional embodiment, after the aforementioned steps, the subordinate relationship between the reduced target PCIe device and the first preset device topology has been determined. If the target PCIe device is not recorded in the first preset device topology, the reduction of the target PCIe device will not affect the first preset device topology. In this case, the first preset device topology is maintained unchanged. If the target PCIe device is recorded in the first preset device topology, the reduction of the target PCIe device will change the structure of the first preset device topology. In this case, it is necessary to update the first preset device topology and the second preset device topology according to the PCIe devices included in the current configuration cycle of the PCIe bus system (excluding the reduced target PCIe device).

[0106] In summary, the configuration method provided in this embodiment provides different configuration strategies according to the device update status of the PCIe bus system. When it is determined that no device update has occurred in the PCIe bus system, the ARI function of each PCIe device is directly configured based on the information recorded in the first preset device topology. When it is determined that a device update has occurred in the PCIe bus system, the ARI function of the PCIe device is further configured in combination with the device update status and the first preset device topology. The configuration strategy can be flexibly adjusted according to the actual situation of the PCIe bus system. Not only can the ARI function of the PCIe device be automatically configured, saving the user the time required to configure the ARI function, but also the configuration requirements of different scenarios can be met. The ARI function configuration efficiency is higher and meets the application requirements of efficient operation of the computer system.

[0107] The following is an introduction to the process of creating the first preset device topology described in the above embodiments. Figure 5 As shown, the process of creating the first preset device topology provided in this embodiment includes the following steps.

[0108] S300: Perform device scanning on the PCIe bus system in a target configuration period to identify PCIe devices included in the PCIe bus system in the target configuration period.

[0109] First of all, it should be noted that in this embodiment, the target configuration cycle refers to any configuration cycle before the current configuration cycle, that is, the first preset device topology can be used in multiple subsequent configuration cycles after a certain configuration cycle is created. Of course, the most preferred implementation is that each configuration cycle creates (including updating) the first preset device topology, so that it can be ensured that the first preset device topology closest to the current situation of the PCIe bus system can be used in the next configuration cycle. In this case, the target configuration cycle is the previous configuration cycle of the current configuration cycle. As for the specific selection of the target configuration cycle, it is necessary to consider the frequency of changes of PCIe devices in the PCIe bus system in actual applications. This application does not make specific restrictions on the specific selection of the target configuration cycle.

[0110] Based on the above content, the PCIe bus system is scanned for devices in the target configuration period to identify the PCIe devices included in the PCIe bus system in the target configuration period. As for the specific device scanning process, please refer to Figure 2 The implementation of the relevant contents of S100 in the illustrated embodiment will not be repeated here.

[0111] S310: Determine at least one PCIe device link according to the communication connection relationship between the PCIe devices.

[0112] The connection relationship between each PCIe device in the PCIe bus system can be seen in Figure 1 As shown, different communication links can be obtained according to the connection relationship and communication relationship between PCIe devices, and the PCIe device link mentioned in this application must be a communication link, but the communication link in the PCIe system is not necessarily the PCIe device link defined in this solution. From the foregoing content, it can be seen that the difference between the two is that each PCIe device in the PCIe device link supports the ARI function, while the PCIe device in the communication link may not support the ARI device.

[0113] See also Figure 1 As shown, a root port of the RC device is directly connected to the EP, and the two form a communication link. If the root port and the EP device connected to it both support the ARI function, the communication link is further used as a PCIe device link. On the contrary, if the root port or the EP device does not support the ARI function, the communication link cannot be used as a PCIe device link.

[0114] Based on the above, when the PCIe bus system includes RC devices, switching devices, and EP devices (see Figure 1 As shown), according to the connection relationship between each PCIe device in each communication link in the PCIe bus system, the root port supporting the ARI function among each root port of the RC device is determined as the target root port, the downstream port supporting the ARI function among each downstream port of each switching device is determined as the target downstream port, and the EP device supporting the ARI function among the EP devices connected to each target root port and each target downstream port is determined as the target EP device, and then according to the connection relationship between each PCIe device, the PCIe device link is determined accordingly.

[0115] In another optional implementation, the PCIe bus system is smaller in size and only includes RC devices and endpoint EP devices. In this case, the root ports of the RC devices that support the ARI function can be determined as target root ports, and the EP devices connected to the target root ports that support the ARI function can be determined as target EP devices. Furthermore, a PCIe device link is created based on the communication connection relationship between the target root port and the target EP device.

[0116] S320: Record each PCIe device link in a preset format to obtain a first preset device topology.

[0117] After traversing all the communication links in the PCIe bus system, the corresponding PCIe communication links can be obtained, and then each PCIe device link can be recorded in a preset form to obtain a first preset device topology. As mentioned above, the first preset device topology can be recorded in a variety of ways such as an array and a linked list, which also fall within the scope of protection of this application without exceeding the core idea of ​​this application.

[0118] It should be noted that the aforementioned second preset device topology can also be created by referring to the above method. The difference from the first preset device topology creation process is that when creating the second preset device topology, it is not necessary to distinguish whether each PCIe device supports the ARI function. It is only necessary to record the PCIe devices included in the PCIe system and the connection relationship between the PCIe devices.

[0119] It should also be noted that the PCIe device configuration method provided in any of the above embodiments can be used as a firmware program of the processor or as other forms of executable programs for the processor to call. As long as the implementation method can be reliably called by the processor when needed to improve memory performance, it is optional and also falls within the scope of protection of this application without exceeding the core idea of ​​this application.

[0120] The PCIe device configuration device provided by the present invention is introduced below. The PCIe device configuration device provided by the present invention belongs to the same application concept as the PCIe device configuration method provided by the embodiment of the present application, and can execute the PCIe device configuration method provided by any embodiment of the present application, and has the corresponding functional modules and beneficial effects of executing the PCIe device configuration method. For technical details not described in detail in this embodiment, please refer to the PCIe device configuration method provided by the embodiment of the present application, and will not be repeated here.

[0121] See also Figure 6 , Figure 6 : is a structural block diagram of a PCIe device configuration device provided in an embodiment of the present invention. The configuration device provided in this embodiment includes:

[0122] The scanning unit 10 is used to perform device scanning on the PCIe bus system to identify the PCIe devices included in the PCIe bus system in the current configuration cycle;

[0123] A configuration unit 20, configured to enable an alternative routing ARI function of a PCIe device in a PCIe bus system based at least on a first preset device topology;

[0124] The first preset device topology records at least one PCIe device link, and any PCIe device in the PCIe device link supports the ARI function.

[0125] Further, in Figure 6 Based on the embodiment shown, the present application also provides another PCIe device configuration device. Figure 6 The embodiment shown, see Figure 7 As shown, the configuration device provided in this embodiment also includes:

[0126] The updating unit 30 is used to update the first preset device topology and the second preset device topology according to the PCIe devices included in the current configuration cycle of the PCIe bus system.

[0127] Below, reference Figure 8 To describe the electronic device provided by the embodiment of the present invention, the electronic device provided by the embodiment may include: at least one processor 100, at least one communication interface 200, at least one memory 300 and at least one communication bus 400;

[0128] In the embodiment of the present invention, the number of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 is at least one, and the processor 100, the communication interface 200, and the memory 300 communicate with each other through the communication bus 400; obviously, Figure 8 The communication connections shown for the processor 100, the communication interface 200, the memory 300, and the communication bus 400 are merely optional;

[0129] Optionally, the communication interface 200 may be an interface of a communication module, such as an interface of a GSM module; the processor 100 may be a central processing unit CPU, or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0130] The memory 300 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0131] The processor 100 is specifically used to execute the application program in the memory to implement the steps of the PCIe device configuration method described above.

[0132] In some embodiments, this embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more instructions for implementing the above steps are stored, and when the one or more instructions are executed by one or more processors, the processors execute the PCIe device configuration method described above. For the relevant specific implementation, please refer to the above description, which will not be repeated here.

[0133] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the PCIe device configuration method according to various embodiments of the present application described in the above content of this specification.

[0134] The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0135] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0136] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0137] Flowcharts are used in this disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.

[0138] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any particular form of combination of hardware and software.

[0139] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0140] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A PCIe device configuration method, characterized in that: Applied to a PCIe bus system, the method comprises: Performing device scanning on the PCIe bus system to identify PCIe devices included in the PCIe bus system in a current configuration cycle; enabling an alternative routing ARI function of a PCIe device in the PCIe bus system based at least on a first preset device topology; The first preset device topology records at least one PCIe device link, and any PCIe device in the PCIe device link supports the ARI function.

2. The PCIe device configuration method according to claim 1, characterized in that: The enabling of an alternative routing ARI function of a PCIe device in the PCIe bus system based at least on a first preset device topology includes: Determining whether a device update occurs in the PCIe bus system based on the PCIe devices included in the current configuration cycle of the PCIe bus system; If no device update occurs in the PCIe bus system, enabling an ARI function of the PCIe device in the PCIe bus system according to the first preset device topology; If a device update occurs in the PCIe bus system, an ARI function of the PCIe device in the PCIe bus system is enabled according to the device update status and the first preset device topology.

3. The PCIe device configuration method according to claim 2, characterized in that: Determining whether a device update occurs in the PCIe bus system based on the PCIe devices currently included in the PCIe bus system includes: Acquire a second preset device topology, where the second preset device topology records all PCIe devices included in the PCIe bus system in a previous configuration cycle; If the PCIe devices included in the current configuration cycle of the PCIe bus system are consistent with the PCIe devices recorded in the second preset device topology, it is determined that no device update occurs in the PCIe bus system; If the PCIe devices included in the current configuration cycle of the PCIe bus system are inconsistent with the PCIe devices recorded in the second preset device topology, it is determined that a device update occurs in the PCIe bus system.

4. The PCIe device configuration method according to claim 2, characterized in that: The enabling of the ARI function of the PCIe device in the PCIe bus system according to the device update status and the first preset device topology includes: If the PCIe bus system includes a newly added PCIe device, enabling the ARI function of each PCIe device in the first preset device topology, and configuring the ARI function of the newly added PCIe device according to the ARI function support status of the newly added PCIe device; If the PCIe bus system uninstalls at least one target PCIe device, the ARI function of the PCIe device in the PCIe bus system is enabled according to the subordinate relationship between the target PCIe device and the first preset device topology and the first preset device topology.

5. The PCIe device configuration method according to claim 4, characterized in that: Enabling the ARI function of the PCIe device in the PCIe bus system according to the subordinate relationship between the target PCIe device and the first preset device topology and the first preset device topology includes: If the target PCIe device is recorded in the first preset device topology, enabling ARI functions of other PCIe devices except the target PCIe device in the first preset device topology; If the target PCIe device is not recorded in the first preset device topology, an ARI function of each PCIe device in the first preset device topology is enabled.

6. The PCIe device configuration method according to claim 3, characterized in that: Also includes: The first preset device topology and the second preset device topology are updated according to the PCIe devices included in the current configuration cycle of the PCIe bus system.

7. The PCIe device configuration method according to any one of claims 1 to 6, characterized in that: The process of creating the first preset device topology includes: Performing device scanning on the PCIe bus system in a target configuration cycle to identify PCIe devices included in the PCIe bus system in the target configuration cycle, wherein the target configuration cycle includes any configuration cycle before the current configuration cycle; Determine at least one PCIe device link according to the communication connection relationship between the PCIe devices; Each of the PCIe device links is recorded in a preset format to obtain the first preset device topology.

8. The PCIe device configuration method according to claim 7, characterized in that: The PCIe devices included in the PCIe bus system at least include a root complex RC device and an endpoint EP device; Determining at least one PCIe device link according to the communication connection relationship between the PCIe devices includes: Determine a root port supporting the ARI function among the root ports of the RC device as a target root port; Determine an EP device supporting the ARI function among the EP devices connected to each of the target root ports as the target EP device; A PCIe device link is determined according to a communication connection relationship between the target root port and the target EP device.

9. The PCIe device configuration method according to claim 8, characterized in that: The PCIe bus system also includes a switching device; Determining at least one PCIe device link according to the communication connection relationship between the PCIe devices includes: Determine a root port supporting the ARI function among the root ports of the RC device as a target root port; Determine a downstream port that supports the ARI function among the downstream ports of the switching device as a target downstream port; Determine an EP device supporting the ARI function among the EP devices connected to each of the target root ports and each of the target downstream ports as a target EP device; A PCIe device link is determined according to a communication connection relationship among the target root port, the target downstream port, and the target EP device.

10. A PCIe device configuration device, characterized in that: Applied to a PCIe bus system, the device comprises: A scanning unit, configured to perform device scanning on the PCIe bus system to identify PCIe devices included in the PCIe bus system in a current configuration cycle; A configuration unit, configured to enable an alternative routing ARI function of a PCIe device in the PCIe bus system based at least on a first preset device topology; The first preset device topology records at least one PCIe device link, and any PCIe device in the PCIe device link supports the ARI function.

11. An electronic device, characterized in that: include: Memory and processor; Wherein, the memory is used to store programs; The processor is used to implement the PCIe device configuration method as described in any one of claims 1 to 9 by running the program in the memory.

12. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the PCIe device configuration method according to any one of claims 1 to 9 is implemented.

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