Semiconductor devices and calibration methods in calculation of their electrical characteristics

Abstract

The present invention provides a semiconductor device and a calibration method for calculating its electrical characteristics. The calibration method comprises the following steps: a step of determining whether the difference between a first electrical characteristic measurement value and a first electrical characteristic calculation value of an adjustment semiconductor device (2) including an adjustment main body portion (20) having a structure substantially the same as that of an object main body portion (10) and an adjustment wiring portion (21) having a higher heat dissipation than an object wiring portion (11) is within a specified tolerance range; and a step of adjusting a specified physical constant including a carrier mobility used in a second simulation for calculating an electrical characteristic value of an object semiconductor device (1) using the carrier mobility of the adjustment semiconductor device (2) when the determination result in the step is within the tolerance range.

Description

Technical Field

[0001] The present invention particularly relates to semiconductor devices and calibration methods in calculation of electrical characteristics thereof. Background Art

[0002] Conventionally, as part of circuit design of a semiconductor device, there is a case where a device structure of the semiconductor device is optimized by performing TCAD (Technology Computer Aided Design) on the semiconductor device as a target of circuit design.

[0003] In TCAD, electrical characteristics such as current-voltage characteristics are calculated. In addition, for the prototype of the semiconductor device that is the object of circuit design, electrical characteristics such as current-voltage characteristics are measured. Then, the calculated value of the electrical characteristics is compared with the measured value of the electrical characteristics, and if the difference is not within the allowable range, correction is performed. In the correction, for example, physical constants such as carrier mobility (sometimes also called "electron mobility") are adjusted. Summary of the invention

[0004] Problem that the invention aims to solve

[0005] When measuring electrical characteristics such as current-voltage characteristics, the semiconductor device of the prototype generates self-heating, which sometimes causes a decrease in current due to the temperature dependency of carrier mobility. Therefore, it is difficult to accurately perform calibration in the calculation of the electrical characteristics of the semiconductor device. In addition, for the semiconductor device itself, the drain current decreases due to self-heating, and the circuit performance such as switching speed is reduced.

[0006] The present invention is achieved in view of the above situation. That is, to address the above problem, a calibration method for calculating the electrical characteristics of a semiconductor device that can improve the calculation accuracy of the electrical characteristics of the semiconductor device, an adjustment semiconductor device for calibration, and a semiconductor device that can suppress the reduction of circuit performance are provided.

[0007] Means used to solve problems

[0008] In order to achieve the above-mentioned object, a calibration method in calculation of electrical characteristics of a semiconductor device, an adjustment semiconductor device used for calibration, and a semiconductor device according to one embodiment of the present invention have the following features.

[0009] In order to achieve the above-mentioned object, in a first aspect, some embodiments of the present disclosure provide a calibration method in calculating the electrical characteristics of a semiconductor device, wherein the target semiconductor device comprises: a target main body portion, comprising a semiconductor element; and a target wiring portion, stacked on the target main body portion, for energizing the semiconductor element,

[0010] The calibration method in the electrical characteristic calculation of the semiconductor device comprises the following steps:

[0011] The first step is to measure a first measurement value related to an electrical characteristic of a semiconductor device including an adjustment body portion and an adjustment wiring portion, namely, an adjustment semiconductor device, wherein the adjustment body portion is formed of the same structure as the target body portion, and the adjustment wiring portion has a higher heat dissipation property than the target wiring portion;

[0012] A second step is to adjust a predetermined physical constant including a carrier mobility used in a first simulation, wherein the first simulation calculates a value related to an electrical characteristic of the adjustment semiconductor device;

[0013] A third step is to calculate a first calculated value related to the electrical characteristics of the adjustment semiconductor device through the first simulation;

[0014] A fourth step of determining whether a difference between the first measured value of the electrical characteristic obtained in the first step and the first calculated value of the electrical characteristic obtained in the third step is within a prescribed tolerance range;

[0015] A fifth step of measuring a second measurement value related to the electrical characteristics of the target semiconductor device when the result of the determination in the fourth step is within the range of the predetermined tolerance;

[0016] A sixth step of adjusting a predetermined physical constant including the carrier mobility used in a second simulation using the carrier mobility of the adjustment semiconductor device in the second step, wherein the second simulation calculates a value related to the electrical characteristics of the target semiconductor device;

[0017] A seventh step is to calculate a second calculated value related to the electrical characteristics of the target semiconductor device through the second simulation; and

[0018] In an eighth step, it is determined whether a difference between the second measured value of the electrical characteristic obtained in the fifth step and the second calculated value of the electrical characteristic obtained in the seventh step is within a predetermined tolerance range.

[0019] According to the calibration method in the calculation of the electrical characteristics of the semiconductor device described in the above-mentioned embodiment, first, a calibration process (first step to second step) as a first stage is performed on a semiconductor device including an adjustment body portion and an adjustment wiring portion, that is, an adjustment semiconductor device, where the adjustment body portion is composed of the same structure as the target body portion of the target semiconductor device, and the heat dissipation of the adjustment wiring portion is higher than that of the target wiring portion, thereby improving the accuracy of the physical constant having a temperature coefficient such as carrier mobility. Then, a calibration process (third step to fifth step) as a second stage is performed, thereby improving the accuracy of the second simulation for the target semiconductor device that is more susceptible to self-heating than the adjustment semiconductor device, and improving the accuracy of the calculation of the electrical characteristic value of the final target semiconductor device 1.

[0020] In a second aspect, some embodiments of the present disclosure provide a semiconductor device for adjustment, which is used in a calibration method for calculating electrical characteristics of the semiconductor device, wherein:

[0021] The semiconductor element of the adjustment body portion includes a gate electrode, an active region, and an element isolation film.

[0022] The active region and the element separation film are formed in a state of being opposed to each other and bonded in a horizontal direction.

[0023] The gate electrode is formed across the active region and the element separation film at a boundary between the active region and the element separation film.

[0024] forming the adjustment wiring portion on the upper surface of the gate electrode,

[0025] The adjustment wiring portion includes a metal columnar plug.

[0026] The number of plugs included in the adjustment wiring portion is greater than the number of metal columnar plugs included in the target wiring portion.

[0027] The plurality of plugs are formed on the upper surface of the gate electrode within the range of the active region and the element isolation film in a plan view.

[0028] According to the adjustment semiconductor device described in the above-mentioned embodiment, since the number of plugs included in the adjustment wiring portion is greater than the number of metal columnar plugs included in the target wiring portion, when observed from above, the plurality of plugs are formed not only in the range of the element separation film on the upper surface of the gate electrode but also in the range of the active region, thereby enabling the heat dissipation of the adjustment semiconductor device to be higher than that of the target semiconductor device.

[0029] In some embodiments of the present disclosure, the adjustment semiconductor device includes a plurality of adjustment wiring portions, and the plurality of adjustment wiring portions are sequentially stacked on the adjustment body portion.

[0030] In some embodiments of the present disclosure, the first adjustment wiring portion joined to the adjustment main body portion includes a plurality of gate plugs formed on the upper surface of the gate electrode, the plurality of gate plugs formed on the upper surface of the element separation film or the upper surface of the drift layer or the upper surface of the P-type diffusion layer, and a plurality of drain plugs formed on the upper surface of the drain, and a plurality of source plugs spanning the upper surface of the N-type source and the upper surface of the P-type source.

[0031] In some embodiments of the present disclosure, one or more adjustment wiring portions formed above the first adjustment wiring portion include a plurality of gate plugs, and the plurality of gate plugs are formed above the plurality of gate plugs of the first adjustment wiring portion.

[0032] In some embodiments of the present disclosure, all the plugs included in the adjustment wiring portion are connected to wiring at their upper ends, and metal columnar plugs are formed on the wiring. In this way, the adjustment semiconductor device can further improve the heat dissipation of the adjustment semiconductor device.

[0033] In some embodiments of the present disclosure, the formation position of a part of the plugs included in the adjustment wiring portion in a plan view is the same as the formation position of all the plugs included in the target wiring portion in a plan view. In this way, the adjustment semiconductor device can further improve the heat dissipation of the adjustment semiconductor device, and improve the structural identity between the target semiconductor device 1 and the adjustment semiconductor device, thereby improving the accuracy of the calculation of the electrical characteristic value of the final target semiconductor device 1.

[0034] In a third aspect, some embodiments of the present disclosure provide a semiconductor device, comprising: a semiconductor element; and a wiring layer stacked on the semiconductor element and used to energize the semiconductor element.

[0035] The semiconductor element includes a gate electrode, an active region, and an element separation film.

[0036] The active region and the element separation film are formed in a state of being opposed to each other and bonded in a horizontal direction.

[0037] The gate electrode is formed across the active region and the element separation film at a boundary between the active region and the element separation film.

[0038] The wiring layer includes a plurality of metal columnar plugs.

[0039] The plurality of plugs are formed on the upper surface of the gate electrode within the range of the active region and the element isolation film in a plan view.

[0040] According to the semiconductor device described in the above embodiment, since the plurality of plugs are formed not only in the region of the element separation film on the upper surface of the gate electrode but also in the region of the active region, the heat dissipation of the semiconductor device can be improved. As a result, the reduction in drain current due to self-heating can be suppressed, and the reduction in circuit performance such as switching speed can be suppressed.

[0041] In some embodiments of the present disclosure, the multiple plugs include multiple gate plugs formed on the upper surface of the gate electrode and formed on the upper surface of the element separation film, multiple drain plugs formed on the upper surface of the drain, and multiple source plugs spanning the upper surface of the N-type source and the upper surface of the P-type source.

[0042] In some embodiments of the present disclosure, a plurality of the plugs are arranged in parallel and separated from each other along the front-to-back direction.

[0043] The unexpected effects that the present invention can produce are:

[0044] According to the calibration method in calculating the electrical characteristics of the semiconductor device and the adjustment semiconductor device used for calibration, the accuracy of calculating the electrical characteristics of the semiconductor device can be improved. In addition, the semiconductor device according to the present invention can suppress the reduction of circuit performance such as switching speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 The present invention is a flowchart of a calibration method for calculating electrical characteristics of a semiconductor device involved in some embodiments of the present disclosure.

[0047] Figure 2A is a top view of a semiconductor device involved in some embodiments of the present disclosure.

[0048] Figure 2B Yes means Figure 2A AA section schematic diagram.

[0049] Figure 2C Yes means Figure 2B The BB cross-sectional view of FIG. 1 is a view schematically showing a structure in which the wiring interlayer film is removed.

[0050] Figure 3A is a top view of a semiconductor device for adjustment involved in some embodiments of the present disclosure.

[0051] Figure 3B Yes means Figure 3A A diagram showing the schematic structure of the OO cross section.

[0052] Figure 3C Yes means Figure 3B The PP cross-sectional view of FIG. 1 is a diagram schematically showing a structure in which the first wiring interlayer film is removed.

[0053] Figure 3D Yes means Figure 3B The QQ cross-sectional view of FIG. 1 is a diagram schematically showing a structure in which the first wiring interlayer film and the second wiring interlayer film are removed.

[0054] Description of reference numerals:

[0055] 1…Target semiconductor device, 2…Adjustment semiconductor device,

[0056] 10 ... object main body, 11 ... object wiring part,

[0057] 20 ... main body for adjustment, 21 ... first wiring portion for adjustment, 22 ... second wiring portion for adjustment, 23 ... third wiring portion for adjustment,

[0058] 101 ... a first supporting substrate, 102 ... a first SOI substrate insulating film, 103 ... a first drift layer, 104 ... a first P-type diffusion layer, 105 ... a first element isolation film, 106 ... a first drain electrode, 107 ... a first source electrode, 108 ... a first gate electrode, 109 ... a first gate insulating film,

[0059] 111 ... plug, 111A ... gate plug, 111B ... drain plug, 111C ... source plug, 112A ... gate wiring, 112B ... drain wiring, 112C ... source wiring, 113 ... wiring interlayer film,

[0060] 201 ... second supporting substrate, 202 ... second SOI substrate insulating film, 203 ... second drift layer, 204 ... second P-type diffusion layer, 205 ... second element isolation film, 206 ... second drain electrode, 207 ... second source electrode, 208 ... second gate electrode, 209 ... second gate insulating film

[0061] 211 ... a first plug, 211A ... a first gate plug, 211B ... a first drain plug, 211C ... a first source plug,

[0062] 212 ... first wiring, 212A ... first gate wiring, 212B ... first drain wiring, 212C ... first source wiring, 213 ... first wiring interlayer film

[0063] 221 ... second plug, 221A ... second gate plug, 222A ... second gate wiring, 222 ... second wiring, 223 ... second wiring interlayer film

[0064] 231…third plug, 231A…third gate plug, 232A…third gate wiring, 232A…third wiring, 233…third wiring interlayer film. DETAILED DESCRIPTION

[0065] (First embodiment)

[0066] Hereinafter, a calibration method in calculation of electrical characteristics of a semiconductor device according to a first embodiment of the present invention and an adjustment semiconductor device used for calibration will be described with reference to the drawings.

[0067] first, Figure 1 FIG. 1 is a flowchart of a calibration method for calculating electrical characteristics of a semiconductor device according to the first embodiment of the present invention. Figure 1 As shown, the calibration method is roughly divided into a first-stage calibration process (step S1) and a second-stage calibration process (step S2).

[0068] The first stage calibration process is performed on the adjustment semiconductor device 2 described later. On the other hand, the second stage calibration process is performed on the target semiconductor device 1 described later. The adjustment semiconductor device 2 is formed by adding a heat dissipation structure to the basic structure of the target semiconductor device 1. That is, the adjustment semiconductor device 2 is based on the target semiconductor device 1, and has higher heat dissipation than the target semiconductor device 1. The target semiconductor device 1 and the adjustment semiconductor device 2 are manufactured under the same conditions. The target semiconductor device 1 and the adjustment semiconductor device 2 will be described later.

[0069] First, a first-stage calibration process (step S1) is performed on the adjustment semiconductor device 2 at a preset room temperature to determine the carrier mobility at room temperature, which is a physical constant. Next, a second-stage calibration process (step S2) is performed on the target semiconductor device 1 at room temperature in the first-stage calibration process (step S1) using the carrier mobility determined in the first-stage calibration process (step S1) to determine physical constants including the carrier mobility.

[0070] The first-stage calibration process includes a first electrical characteristic value measuring process (step S11), a first physical constant adjusting process (step S12), a first electrical characteristic value calculating process (step S13), and a first electrical characteristic value comparing process (step S14). The second-stage calibration process includes a second electrical characteristic value measuring process (step S21), a second physical constant adjusting process (step S22), a second electrical characteristic value calculating process (step S23), and a second electrical characteristic value comparing process (step S24).

[0071] In the first electrical characteristic value measuring step (step S11 ), predetermined values ​​related to electrical characteristics (electrical characteristic values) such as a threshold value and a drain current of the adjustment semiconductor device 2 are measured at a predetermined room temperature.

[0072] In the first physical constant adjustment step (step S12), predetermined physical constants such as carrier mobility, gate capacitance, wiring resistivity, diffusion constant of impurities during manufacturing, and relative dielectric constant of oxide film of the adjustment semiconductor device 2 used in the next first electrical characteristic value calculation step (step S13) are adjusted and temporarily determined. However, in the first first physical constant adjustment step (step S12) in the first stage calibration step, the physical constants are not adjusted and the default values ​​are used.

[0073] In the first electrical characteristic value calculation step (step S13), the electrical characteristic value of the adjustment semiconductor device 2 is calculated by performing TCAD on the adjustment semiconductor device 2. In addition, before the first electrical characteristic value calculation step (step S13) is performed, the gate length of the LDMOS (Laterally Diffused MOS: lateral diffused metal oxide) constituting the adjustment body 20 included in the adjustment semiconductor device 2 described later, the gate oxide film thickness and other structural conditions, the dielectric constant of the silicon oxide film, etc., the amount of ion implantation to the source and drain, the energy, the annealing temperature, the time and other process conditions are given.

[0074] In the first electrical characteristic value comparison process (step S14), the various electrical characteristic values ​​(first electrical characteristic measurement values) measured in the first electrical characteristic value measurement process (step S11) are compared with the various electrical characteristic values ​​(first electrical characteristic calculation values) calculated in the first electrical characteristic value calculation process (step S13), and it is determined whether the difference (first electrical specific difference) between the various first electrical characteristic measurement values ​​and the first electrical characteristic calculation values ​​is within the tolerance range predetermined for each type of electrical characteristic.

[0075] In the first electrical characteristic value comparison step (step S14 ), when it is determined that the first electrical characteristic differences of all types are within the tolerance range, the first stage calibration step (step S1 ) is terminated and the second stage calibration step (step S2 ) is entered.

[0076] On the other hand, in the first electrical characteristic value comparison process (step S14), when it is determined that any type of first electrical specific difference is not within the tolerance range, the process returns to the first physical constant adjustment process (step S12). That is, in the first electrical characteristic value comparison process (step S14), the first physical constant adjustment process (step S12) to the first electrical characteristic value comparison process (step S14) are repeatedly performed until it is determined that all types of first electrical specific differences are within the tolerance range.

[0077] In the first physical constant adjustment process (step S12 ) from the second time onwards, the first electrical specific difference that has just been performed is added, and a part or all of the physical constants are adjusted and temporarily determined.

[0078] Furthermore, in the first electrical characteristic value comparison step (step S14), when it is determined that the first electrical characteristic difference values ​​of all types are within the tolerance range, the various physical constants tentatively determined in the most recent first physical constant adjustment step (step S12) are determined as the various physical constants of the adjustment semiconductor device 2. In particular, regarding the carrier mobility, as described later, considering that the adjustment semiconductor device 2 has higher heat dissipation than the target semiconductor device 1 and the influence of self-heating is extremely small, the room temperature at this time is fixed to the temperature of the carrier mobility.

[0079] In the second electrical characteristic value measurement step (step S21 ), the electrical characteristic value of the target semiconductor device 1 is measured at the same room temperature as the room temperature in the first electrical characteristic value measurement step (step S11 ).

[0080] In the second physical constant adjustment step (step S22), predetermined physical constants such as gate capacitance, wiring resistivity, diffusion constant of impurities during manufacturing, and relative dielectric constant of oxide film of the target semiconductor device 1 (in simulation) used in the next second electrical characteristic value calculation step (step S23) are adjusted and temporarily determined. However, in the first second physical constant adjustment step (step S22) in the second stage calibration step, the physical constants are not adjusted, and various physical constants determined in the first stage calibration step are used.

[0081] In the second electrical characteristic value calculation step (step S23), the electrical characteristic value of the target semiconductor device 1 is calculated by performing TCAD on the target semiconductor device 1. In addition, before the second electrical characteristic value calculation step (step S23) is performed, the gate length of the LDMOS constituting the target body 10 included in the target semiconductor device 1 described later, the gate oxide film thickness and other structural conditions, the dielectric constant of the silicon oxide film, etc., the amount of ion implantation to the source and drain, the energy, the annealing temperature, the time and other process conditions are given. In addition, the structural conditions such as the gate length, gate oxide film thickness, etc. of the LDMOS of the target main body 10 included in the target semiconductor device 1, as well as the process conditions such as the dielectric constant of the silicon oxide film, etc., the amount of ion implantation to the source and drain, the energy, the annealing temperature, and the time are the same as the structural conditions such as the gate length, gate oxide film thickness, etc. of the LDMOS of the adjustment main body 20 included in the adjustment semiconductor device 2, as well as the dielectric constant of the silicon oxide film, etc., the amount of ion implantation to the source and drain, the energy, the annealing temperature, and the time.

[0082] In the second electrical characteristic value comparison process (step S24), the electrical characteristic value (second electrical characteristic measurement value) measured in the second electrical characteristic value measurement process (step S21) is compared with the electrical characteristic value (second electrical characteristic calculation value) calculated in the second electrical characteristic value calculation process (step S23) to determine whether the difference (second electrical specific difference) between various second electrical characteristic measurement values ​​and the second electrical characteristic calculation value is within the tolerance range predetermined for each type of electrical characteristic.

[0083] In the second electrical characteristic value comparison step (step S24 ), when it is determined that the second electrical characteristic difference values ​​of all types are within the tolerance range, the second stage calibration step (step S2 ) is terminated, and the calibration method is terminated.

[0084] On the other hand, in the second electrical characteristic value comparison process (step S24), when it is determined that any type of second electrical specific difference is not within the tolerance range, the process returns to the second physical constant adjustment process (step S22). That is, in the second electrical characteristic value comparison process (step S24), the second physical constant adjustment process (step S22) to the second electrical characteristic value comparison process (step S24) are repeatedly performed until it is determined that all types of second electrical specific differences are within the tolerance range.

[0085] In the second physical constant adjustment process (step S22) from the second time onwards, the second electrical specific difference just performed is added to adjust and provisionally determine a part or all of the physical constants. However, regarding the carrier mobility, the value provisionally determined in the first physical constant adjustment process (step S12) performed last time in the first stage calibration process (step S1) is not changed.

[0086] In addition, in the second electrical characteristic value comparison process (step S24), when it is determined that the second electrical characteristic differences of all types are within the tolerance range, the various physical constant parameters temporarily determined in the most recent second physical constant adjustment process (step S22) are determined as the various physical constant parameters of the target semiconductor device 1.

[0087] Next, the target semiconductor device 1 and the adjustment semiconductor device 2 are described. First, the target semiconductor device 1 is described. Figure 2A is a top view of the target semiconductor device 1, Figure 2B Yes means Figure 2A The schematic structure of the AA section is shown in FIG. Figure 2C BB is a diagram showing a cross section, and is a diagram showing a schematic structure without a wiring interlayer film described later. Figure 2A , Figure 2B , Figure 2C The “front”, “right” and “up” described in the specification define the front-to-rear direction, the left-to-right direction and the up-to-down direction, but the relationship between these directions and the orientation of the target semiconductor device 1 is not limited to the embodiment described below.

[0088] The target semiconductor device 1 includes a target main body portion 10 and a target wiring portion 11. Specifically, the target semiconductor device 1 has a two-layer structure in which the target main body portion 10 and the target wiring portion 11 are formed on the upper surface thereof.

[0089] The object body 10 is composed of an N-channel power MOSFET (Metal-Oxide-Semiconductor Field-EffectTransistor). The object body 10 includes a first support substrate 101, a first SOI substrate insulating film 102, a first drift layer 103, a first P-type diffusion layer 104, a first element isolation film 105, a first drain 106, a first source 107, a first gate electrode 108, and a first gate insulating film 109. In addition, Figure 2B In the figure, the first gate electrode 108 and the first gate insulating film 109 appear to be included in the target wiring portion 11 in terms of configuration, but this is only for convenience, and the first gate electrode 108 and the first gate insulating film 109 are included in the target body portion 10 .

[0090] The first support substrate 101 is formed across both left and right ends at the lowest layer of the target body 10. A first SOI substrate insulating film 102 is stacked on the first support substrate 101. The first SOI substrate insulating film 102 is also formed across both left and right ends of the target body 10. A first drift layer 103 and a first P-type diffusion layer 104 are stacked on the first SOI substrate insulating film 102.

[0091] In contrast, the first drift layer 103 is disposed on the right side, and the first P-type diffusion layer 104 is disposed on the left side. Furthermore, the first drift layer 103 and the first P-type diffusion layer 104 are formed in a state of being bonded to each other in the left-right direction on the opposite side to the first element isolation film 105 described later. In addition, the left-right length of the first drift layer 103 is longer than the left-right length of the first P-type diffusion layer 104.

[0092] The first element separation film 105 is formed on the upper surface of the first drift layer 103 at the substantially center in the left-right direction. That is, the first element separation film 105 is formed so as to be embedded in the upper side of the first drift layer 103 so that the cross-sectional shape of the first drift layer 103 becomes a substantially horizontally long U-shape. That is, the first drift layer 103 as an active region and the first element separation film 105 are formed in a state of being bonded to each other in the left-right direction.

[0093] The first drain electrode 106 is formed on the upper surface of the right end portion of the first drift layer 103. That is, the first drift layer 103 is joined to the first drain electrode 106 at the upper surface of the right end portion.

[0094] The upper surface of the first drain electrode 106 is coplanar with the upper surface of the first element isolation film 105. The first element isolation film 105 is bonded to the first drain electrode 106 and the first drift layer 103 on the right side.

[0095] The upper surface of the left end portion of the first drift layer 103 is coplanar with the upper surface of the first element isolation film 105. The first element isolation film 105 is bonded to the first drift layer 103 at the left side surface.

[0096] A first source 107 is formed on the upper surface of approximately half of the left side of the first P-type diffusion layer 104. The first source 107 is composed of a first N-type source 107A and a first P-type source 107B. Relatively, the first N-type source 107A is arranged on the right side, and the first P-type source 107B is arranged on the left side. The first N-type source 107A and the first P-type source 107B are bonded to each other. In addition, the first N-type source 107A and the first P-type source 107B are bonded to the first P-type diffusion layer 104 at the bottom surface. In addition, the left-right length of the first N-type source 107A is approximately the same as the left-right length of the first P-type source 107B. In addition, the thickness of the first N-type source 107A is approximately the same as the thickness of the first P-type source 107B.

[0097] The upper surfaces of the first N-type source 107A, the first P-type source 107B, and the first P-type diffusion layer 104 are coplanar. Therefore, the first N-type source 107A is bonded to the first P-type diffusion layer 104 on the right side.

[0098] The first gate electrode 108 is stacked on the upper surfaces of the first P-type diffusion layer 104, the first drift layer 103, and the first element separation film 105 via the first gate insulating film 109. In other words, the first gate electrode 108 is formed on the boundary (on the bonding surface) between the first element separation film 105 and the first drift layer 103 as the active region, spanning the first element separation film 105 and the first drift layer 103. In detail, the first gate electrode 108 stacked on the first gate insulating film 109 is formed to span the left half of the upper surface of the first element separation film 105 and the entire upper surface of the left side of the first P-type diffusion layer 104 in the left-right direction, and further to the right half of the upper surface of the first P-type diffusion layer 104.

[0099] In the first embodiment, the first support substrate 101 is composed of P-type silicon, the first drain 106 is composed of an N-type semiconductor, the first N-type source 107A is composed of an N-type semiconductor, the first P-type source 107B is composed of a P-type semiconductor, and the first gate electrode 108 is composed of polysilicon. The first drift layer 103 is a so-called "N-well region" and is composed of an N-type semiconductor. The first P-type diffusion layer 104 is a so-called "P-body region" and is composed of a P-type semiconductor. The first SOI substrate insulating film 102, the first element separation film 105, and the first gate insulating film 109 are composed of a silicon oxide film (SiO2).

[0100] In addition, as an example, the thickness of the first P-type diffusion layer 104 is 0.3-3 μm, such as 0.3 μm, 1 μm, 2 μm or 3 μm; the charge density of the first P-type diffusion layer 104 during ion implantation is 5E15-3E16 / cm 2 , such as 5E15 / cm 2, 1E16 / cm 2 , 2E16 / cm 2 or 3E16 / cm 2 Similarly, the thickness of the first drift layer 103 is 0.3-3 μm, such as 0.3 μm, 1 μm, 2 μm or 3 μm; the charge density on the surface of the first drift layer 103 is 5E15-3E16 / cm 2 , such as 5E15 / cm 2 , 1E16 / cm 2 , 2E16 / cm 2 or 3E16 / cm 2 In addition, the surface charge density of the first drain 106 and the first N-type source 107A is 5E19-5E20 / cm 2 , such as 5E19 / cm 2 , 1E20 / cm 2 、3E20 / cm 2 or 5E20 / cm 2 In addition, the charge density on the surface of the first P-type source 107B is 5E19-5E20 / cm 2 , such as 5E19 / cm 2 , 1E20 / cm 2 、3E20 / cm 2 or 5E20 / cm 2 Therefore, the first P-type diffusion layer 104 and the first P-type source 107B are fixed to the same potential, forming a so-called “butting contact”.

[0101] In addition, the thickness of the first element separation film 105 is 0.3-1 μm, such as 0.3 μm, 0.5 μm, 0.8 μm or 1 μm; the thickness of the first gate insulating film 109 is 0.1-0.5 μm, such as 0.1 μm, 0.3 μm, 0.5 μm; In addition, the first SOI substrate insulating film 102 is composed of a buffer oxide film with a thickness of 100 nm-500 nm and an N-type silicon layer with a thickness of 0.3 μm-3 μm formed on the surface thereof, wherein the thickness of the buffer oxide film can be 100 nm, 200 nm, 300 nm or 500 nm, and the thickness of the N-type silicon layer can be 0.3 μm, 1 μm, 2 μm or 3 μm.

[0102] The target wiring portion 11 is a normal wiring structure. Specifically, the target wiring portion 11 includes a plug 111 , a wiring 112 , and a wiring interlayer film 113 .

[0103] The plugs 111 are formed in a columnar shape extending in the vertical direction and include a plurality of (three in the first embodiment) gate plugs 111A, a plurality of (five in the first embodiment) drain plugs 111B, and a plurality of (five in the first embodiment) source plugs 111C.

[0104] A plurality of (three in the first embodiment) gate plugs 111A are formed on the upper surface of the right end of the first gate electrode 108, in other words, are formed on the upper surface of the first element isolation film 105 via the first gate insulating film 109 and the first gate electrode 108, and are arranged in parallel and separated from each other in the front-to-back direction. A plurality of (five in the first embodiment) drain plugs 111B are formed on the upper surface of the first drain 106, and are arranged in parallel and separated from each other in the front-to-back direction. A plurality of (five in the first embodiment) source plugs 111C are formed across the upper surface of the first N-type source 107A and the upper surface of the first P-type source 107B, and are arranged in parallel and separated from each other in the front-to-back direction.

[0105] As the wiring 112, there are a gate wiring 112A, a drain wiring 112B, and a source wiring 112C. The gate wiring 112A is connected to the upper ends of all the gate plugs 111A. The drain wiring 112B is connected to the upper ends of all the drain plugs 111B. The source wiring 112C is connected to the upper ends of all the source plugs 111C.

[0106] However, the top-view shapes of the gate wiring 112A, the drain wiring 112B, and the source wiring 112C are appropriately set within a range that does not short-circuit the gate wiring 112A, the drain wiring 112B, and the source wiring 112C individually and does not short-circuit the gate wiring 112A, the drain wiring 112B, and the source wiring 112C with each other. Figure 2B and Figure 2C The solid lines and imaginary lines (one-dot chain lines) regarding the gate wiring 112A, the drain wiring 112B, and the source wiring 112C described in FIG. 1 indicate the ranges in which the wirings are formed.

[0107] The wiring interlayer film 113 is deposited to a position higher than the upper surface of the wiring 112. Furthermore, the wiring interlayer film 113 substantially fills the upper side of the target body portion 10 except for the plug 111 and the wiring 112. That is, the wiring interlayer film 113 insulates between the gate plug 111A, the drain plug 111B and the source plug 111C, between the gate wiring 112A, the drain wiring 112B and the source wiring 112C, and between the plug 111 and the wiring 112.

[0108] In the first embodiment, the gate plug 111A, the drain plug 111B, and the source plug 111C may be made of tungsten. Furthermore, a barrier metal made of titanium nitride or the like is formed at a predetermined film thickness at the bottom of the gate plug 111A, the drain plug 111B, and the source plug 111C. The gate wiring 112A, the drain wiring 112B, and the source wiring 112C may be made of aluminum. The wiring interlayer film 113 may be made of a silicon oxide film.

[0109] Next, the adjustment semiconductor device 2 will be described. Figure 3A is a top view of the adjustment semiconductor device 2, Figure 3B Yes means Figure 3A The schematic structure of the OO section is shown in FIG. Figure 3C Yes means Figure 3B PP cross-sectional view is a diagram showing a schematic structure in which the first wiring interlayer film 213 described later is removed. Figure 3D Yes means Figure 3B The QQ cross-sectional view of FIG. 1 is a diagram showing a schematic structure in which the first wiring interlayer film 213 and the second wiring interlayer film 223 described later are removed. Figure 3A , Figure 3B , Figure 3C , Figure 3D The words “front”, “right” and “up” are used to define the front-to-back direction, the left-to-right direction and the up-to-down direction, but the relationship between these directions and the orientation of the adjustment semiconductor device 2 is not limited to the embodiment described below.

[0110] The adjustment semiconductor device 2 includes an adjustment body portion 20, a first adjustment wiring portion 21, a second adjustment wiring portion 22, and a third adjustment wiring portion 23. Specifically, the adjustment semiconductor device 2 has a four-layer structure in which the first adjustment wiring portion 21, the second adjustment wiring portion 22, and the third adjustment wiring portion 23 are sequentially stacked on the adjustment body portion 20.

[0111] The adjustment body 20 is composed of an N-channel power MOSFET and has the same structure as the target body 10. Therefore, the adjustment body 20 includes a second support substrate 201, a second SOI substrate insulating film 202, a second drift layer 203, a second P-type diffusion layer 204, a second element separation film 205, a second drain 206, a second source 207, a second gate electrode 208, and a second gate insulating film 209, which are configured in the same manner as the first support substrate 101, the first SOI substrate insulating film 102, the first drift layer 103, the first P-type diffusion layer 104, the first element separation film 105, the first drain 106, the first source 107, the first gate electrode 108, and the first gate insulating film 109 of the target body 10 in terms of shape, size, and material.

[0112] In addition, the second drift layer 203 and the second element separation film 205 as the active region are formed in a state of being bonded to each other in the horizontal direction. In addition, the second drift layer 203 and the second P-type diffusion layer 204 are formed in a state of being bonded to each other in the left-right direction on the opposite side of the second element separation film 205 described later. In addition, the second gate electrode 208 is formed on the boundary (bonding surface) between the second element separation film 205 and the second drift layer 203 as the active region, across the second element separation film 205 and the second drift layer 203 device and further to the second P-type diffusion layer 204. The second source 207 is composed of a second N-type source 207A and a second P-type source 207B, and the second N-type source 207A and the second P-type source 207B are bonded to each other.

[0113] The first adjustment wiring portion 21 is a well-known general wiring structure. Specifically, the first adjustment wiring portion 21 includes a first plug 211 , a first wiring 212 , and a first wiring interlayer film 213 .

[0114] The first plug 211 is formed in a columnar shape extending in the vertical direction and includes a plurality of (49 in the first embodiment) first gate plugs 211A, a plurality of (5 in the first embodiment) first drain plugs 211B, and a plurality of (5 in the first embodiment) first source plugs 211C.

[0115] A plurality of (49 in the first embodiment) first gate plugs 211A are formed in a planar manner on the entire upper surface of the second gate electrode 208, and are dispersed in a grid pattern consisting of 7 substantially equally spaced in the left-right direction and 7 substantially equally spaced in the front-back direction. That is, a plurality of first gate plugs 211A are formed on the upper surfaces of the second drift layer 203, the second P-type diffusion layer 204, and the second element isolation film 205, respectively, with the second gate electrode 208 and the second gate insulating film 209 interposed therebetween.

[0116] Among the plurality of (49 in the first embodiment) first gate plugs 211A, the positions of the first gate plugs 211A (three in the center in the front-rear direction at the right end) are the same as the positions where the gate plugs 111A are formed on the upper surface of the first gate electrode 108 related to the target wiring portion 11. And each of the first gate plugs 211A is formed to have the same structure as the gate plug 111A of the target wiring portion 11. Therefore, in the first adjustment wiring portion 21, the first gate plugs 211A are formed at the positions of the gate plugs 111A related to the target wiring portion 11 and other positions on the upper surface of the second gate electrode 208.

[0117] A plurality of (five in the first embodiment) first drain plugs 211B are formed on the upper surface of the second drain 206, and are arranged in parallel and spaced apart from each other in the front-rear direction. The positions where the first drain plugs 211B are formed on the upper surface of the second drain 206 are the same as the positions where the drain plugs 111B are formed on the upper surface of the first drain 106 associated with the target wiring portion 11. Each of the first drain plugs 211B is formed to have the same structure as the drain plugs 111B of the target wiring portion 11.

[0118] A plurality of (five in the first embodiment) first source plugs 211C are formed across the upper surface of the second N-type source 207A and the upper surface of the second P-type source 207B, and are arranged in parallel and spaced apart from each other in the front-rear direction. The positions where the first source plugs 211C are formed on the upper surface of the second source 207 are the same as the positions where the source plugs 111C are formed on the upper surface of the first source 107 associated with the target wiring portion 11. Each of the first source plugs 211C is formed to have the same structure as the source plugs 111C of the target wiring portion 11.

[0119] The first wiring 212 includes a first gate wiring 212A, a first drain wiring 212B, and a first source wiring 212C. The first gate wiring 212A is connected to the upper ends of all the first gate plugs 211A. The first drain wiring 212B is connected to the upper ends of all the first drain plugs 211B. The first source wiring 212C is connected to the upper ends of all the first source plugs 211C.

[0120] In addition, the top-view shapes of the first gate wiring 212A, the first drain wiring 212B, and the first source wiring 212C are appropriately set within a range that does not short-circuit the first gate wiring 212A, the first drain wiring 212B, and the first source wiring 212C individually and does not short-circuit the first gate wiring 212A, the first drain wiring 212B, and the first source wiring 212C with each other. Figure 3B and Figure 3C The solid lines and imaginary lines (one-dot chain lines) regarding the first gate wiring 212A, the first drain wiring 212B, and the first source wiring 212C described in FIG. 2 indicate the ranges in which the wirings are formed.

[0121] In addition, the left-right length of the range where the first gate wiring 212A is formed is longer than the left-right length of the second gate electrode 208, and the front-back length of the range where the first gate wiring 212A is formed is longer than the front-back length of the second gate electrode 208. In addition, in the first embodiment, the left end of the range where the first gate wiring 212A is formed is located at substantially the same position as the left end of the second gate electrode 208. On the other hand, the right end of the range where the first gate wiring 212A is formed is located further to the right than the right end of the second gate electrode 208. In addition, the front end of the range where the first gate wiring 212A is formed is located further forward than the front end of the second gate electrode 208, and the rear end of the range where the first gate wiring 212A is formed is located further rearward than the rear end of the second gate electrode 208.

[0122] The first wiring interlayer film 213 is deposited in the vertical direction to a position substantially the same as the lower surface of the first wiring 212. Furthermore, the first wiring interlayer film 213 substantially fills the upper side of the adjustment body 20 except for the first plug 211 and the first wiring 212. That is, the first wiring interlayer film 213 insulates the first gate plug 211A, the first drain plug 211B, and the first source plug 211C, and the first plug 211 and the first wiring 212.

[0123] In the first embodiment, the first gate plug 211A, the first drain plug 211B, and the first source plug 211C are so-called "tungsten plugs" and are mainly made of tungsten. However, a barrier metal made of titanium nitride or the like is formed at a predetermined film thickness at the bottom of the first gate plug 211A, the first drain plug 211B, and the first source plug 211C. The first gate wiring 212A, the first drain wiring 212B, and the first source wiring 212C are made of aluminum. The first wiring interlayer film 213 is made of a silicon oxide film.

[0124] The second adjustment wiring portion 22 has a known general wiring structure and specifically includes a second plug 221 , a second wiring 222 , and a second wiring interlayer film 223 .

[0125] The second plug 221 is formed in a columnar shape extending in the vertical direction. A plurality of (72 in the first embodiment) second gate plugs 221A are included as the second plug 221. The second adjustment wiring portion 22 does not include components corresponding to the first drain plug 211B and the first source plug 211C in the first adjustment wiring portion 21.

[0126] A plurality of (72 in the first embodiment) second gate plugs 221A are formed in a planar manner on the entire upper surface of the first gate wiring 212A, and are dispersed in a grid pattern consisting of 8 equally spaced in the left-right direction and 9 equally spaced in the front-back direction. Among them, the positions of the 49 second gate plugs 221A, which are 7 columns except the right end column in the left-right direction and 7 columns except the front end column and the rear end column in the front-back direction, are the same as the positions where the first gate plugs 211A are formed on the upper surface of the second gate electrode 208 associated with the first wiring portion 21 for adjustment. Therefore, in the second wiring portion 22 for adjustment, the second gate plugs 221A are formed on the upper surface of the first gate plugs 211A, at the positions of the first gate plugs 211A associated with the first wiring portion 21 for adjustment, and at other locations. In addition, the shape of each second gate plug 221A is substantially the same as the shape of each first gate plug 211A of the first wiring portion 21 for adjustment.

[0127] The second wiring 222 includes a second gate wiring 222A. The second gate wiring 222A is connected to the upper ends of all the second gate plugs 221A. In the second adjustment wiring portion 22, there is no portion corresponding to the first drain plug 211B and the first source plug 211C in the first adjustment wiring portion 21, and therefore, there is no portion corresponding to the first drain wiring 212B and the first source wiring 212C in the first adjustment wiring portion 21.

[0128] In addition, the planar shape of the second gate wiring 222A is formed into a shape appropriately set within a range in which the second gate wiring 222A is not short-circuited. Figure 3B and Figure 3C The solid line related to the second gate wiring 222A described in FIG. 1 indicates a range in which the wiring is formed.

[0129] The second wiring interlayer film 223 is deposited in the vertical direction to a position substantially the same as the lower surface of the second wiring 222. Furthermore, the second wiring interlayer film 223 is substantially filled in the first wiring 212 and the second plug 221 except for the lower surface of the first wiring 212 associated with the first adjustment wiring portion 21 and the lower surface of the second wiring 222 associated with the second adjustment wiring portion 22. That is, the second wiring interlayer film 223 insulates the first wirings 212, the second gate plugs 221A, the second plug 221 and the first wiring 212, and the second plug 221 and the second wiring 222.

[0130] In the first embodiment, the second gate plug 221A may be made of tungsten. The second gate wiring 222A may be made of aluminum. The second wiring interlayer film 223 may be made of a silicon oxide film.

[0131] The third wiring portion 23 for adjustment has a normal wiring structure and specifically includes a third plug 231 , a third wiring 232 , and a third wiring interlayer film 233 .

[0132] The third plug 231 is formed to have the same structure as the second plug 221 related to the second wiring portion 22 for adjustment. That is, as the third plug 231, a plurality of (72 in the first embodiment) third gate plugs 231A are included. And the plurality of (72 in the first embodiment) third gate plugs 231A are formed in a plane on the entire upper surface of the second gate wiring 222A, and are dispersed in a grid shape consisting of 8 equally spaced in the left-right direction and 9 equally spaced in the front-back direction. In a plan view, the positions where the plurality of (72 in the first embodiment) third gate plugs 231A are formed are substantially the same as the positions where the plurality of (72 in the first embodiment) second gate plugs 221A are formed.

[0133] The third wiring 232 is formed to have a structure substantially the same as that of the second wiring 222 associated with the second wiring portion 22 for adjustment. That is, the third wiring 232 includes a third gate wiring 232A. The shape of the third wiring 232 when viewed from above is substantially the same as that of the second wiring 222 associated with the second wiring portion 22 for adjustment when viewed from above. Figure 3B The solid line related to the third gate wiring 232A described in shows the range where the wiring is formed.

[0134] The third wiring interlayer film 233 is deposited to a position higher than the upper surface of the third wiring 232. The third wiring interlayer film 233 is substantially filled in the second wiring 222, the third plug 231, and the third wiring 232, which are located above the lower surface of the second wiring 222 related to the second wiring portion 22 for adjustment. That is, the third wiring interlayer film 233 insulates the second wirings 222, the third gate plugs 231A, the third wirings 232, the third plug 231 and the second wiring 222, and the third plug 231 and the third wiring 232.

[0135] In addition, Figure 3B It is recorded that the first wiring interlayer film 213 is accumulated to a height substantially the same as the lower surface of the first wiring 212, the second wiring interlayer film 223 is accumulated to a height substantially the same as the lower surface of the second wiring 222, and the third wiring interlayer film 233 is accumulated to a position higher than the upper surface of the third wiring 232. However, it is also possible to treat the first wiring interlayer film 213, the second wiring interlayer film 223, and the third wiring interlayer film 233 as a whole without clearly distinguishing the first wiring interlayer film 213, the second wiring interlayer film 223, and the third wiring interlayer film 233 in structure.

[0136] Next, the heat dissipation of the target semiconductor device 1 and the adjustment semiconductor device 2 is described. When a voltage is applied to the first gate electrode 108 and the second gate electrode 208, a current flows between the first SOI substrate insulating film 102 and the second SOI substrate insulating film 202 of the first drift layer 103 and the second drift layer 203 and the first element isolation film 105 and the second element isolation film 205, and the first drift layer 103 and the second drift layer 203 generate self-heating.

[0137] Furthermore, the thermal conductivity of the silicon oxide film, i.e., SiO2, constituting the first SOI substrate insulating film 102, the second SOI substrate insulating film 202, the first element separation film 105, the second element separation film 205, the first gate insulating film 109, the second gate insulating film 209, the wiring interlayer film 113, the first wiring interlayer film 213, the second wiring interlayer film 223, and the third wiring interlayer film 233 is 1.38 W / m·k, and the thermal conductivity of silicon constituting the majority of the first drift layer 103, the second drift layer 203, and the first gate electrode 108, the second gate electrode 208 is 160 W / m·k. That is, the thermal conductivity of the first element separation film 105, the second element separation film 205, etc. is very low both relatively and absolutely compared with the thermal conductivity of the first drift layer 103, the second drift layer 203, etc. Therefore, if only the target body portion 10 in the target semiconductor device 1 and the adjustment body portion 20 in the adjustment semiconductor device 2 are considered, since the first drift layer 103 and the second drift layer 203 are sandwiched by the silicon oxide film above and below, it is difficult to dissipate heat from the first drift layer 103 and the second drift layer 203. Therefore, when the first drift layer 103 and the second drift layer 203 generate self-heating, the internal temperature of the first drift layer 103 and the second drift layer 203 rises.

[0138] On the other hand, the thermal conductivity of tungsten contained in the plug 111 and the first plug 211 is 198 W / m·k, and the thermal conductivity of aluminum constituting the second plug 221, the third plug 231, and the wiring 112, the first wiring 212, the second wiring 222, and the third wiring 232 is 236 W / m·k. That is, the thermal conductivity of the plug 111, the first plug 211, etc. and the thermal conductivity of the wiring 112, the first wiring 212, etc. are relatively and absolutely very high compared with the thermal conductivity of the first element separation film 105, the second element separation film 205, etc. Therefore, the heat generated by the self-heating in the first drift layer 103 and the second drift layer 203 is dissipated through the first gate electrode 108, the second gate electrode 208, the first drain 106, the second drain 206, and the first source 107, the second source 207.

[0139] Here, when comparing the target semiconductor device 1 and the adjustment semiconductor device 2, the structure of the drain plug 111B is the same as the structure of the first drain plug 211B, the number of the drain plugs 111B is the same as the number of the first drain plugs 211B, and the structure of the source plug 111C is the same as the structure of the first source plug 211C, and the number of the source plugs 111C is the same as the number of the first source plugs 211C. Therefore, the heat dissipation of the drain plug 111B and the source plug 111C related to the target wiring portion 11 is the same as the heat dissipation of the first drain plug 211B and the first source plug 211C related to the adjustment first wiring portion 21.

[0140] However, although the structure of the gate plug 111A is the same as that of the first gate plug 211A, the number of the first gate plugs 211A is about 16 times the number of the gate plugs 111A, and the first gate plugs 211A are also formed on the second drift layer 203 as the active region and the upper surface of the second P-type diffusion layer 204. Therefore, the heat dissipation of the portion of the first gate plug 211A related to the adjustment first wiring portion 21 is much higher than the heat dissipation of the portion of the gate plug 111A related to the target wiring portion 11. Furthermore, although the target semiconductor device 1 does not have a structure for improving the heat dissipation on the target wiring portion 11, the adjustment semiconductor device 2 has the adjustment second wiring portion 22 and the adjustment third wiring portion 23 formed on the adjustment first wiring portion 21, and the adjustment second wiring portion 22 and the adjustment third wiring portion 23 have the second gate plugs 221A and the third gate plugs 231A formed thereon, which are larger in number than the first gate plug 211A and have higher thermal conductivity than the first gate plug 211A. Therefore, the heat dissipation of the adjustment semiconductor device 2 becomes much higher than that of the target semiconductor device 1 with respect to the self-heating in the first drift layer 103 and the second drift layer 203.

[0141] As described above, according to the calibration method in the electrical characteristic calculation of the target semiconductor device 1 involved in the first embodiment, the target semiconductor device 1 includes: a target body portion 10 including an LDMOS (semiconductor element); and a target wiring portion 11 stacked on the target body portion 10 and used to energize the LDMOS (semiconductor element), including the following steps: a first electrical characteristic value measuring step (first step), in which the electrical characteristic value of the semiconductor device for adjustment 2, which includes an adjustment body portion 20 and an adjustment first wiring portion 21, is measured, wherein the adjustment body portion 20 is composed of a structure substantially the same as the target body portion 10, and the heat dissipation of the adjustment wiring portion is higher than that of the target wiring portion 11; a first physical constant adjusting step (second step), in which a predetermined physical constant including a carrier mobility used in a first simulation, in which the electrical characteristic value of the adjustment semiconductor device 2 is calculated, is adjusted; a first electrical characteristic value calculating step (third step), in which the electrical characteristic value of the adjustment semiconductor device 2 is calculated by the first simulation; and a first electrical characteristic value comparing step (fourth step), in which it is determined whether the electrical characteristic value of the semiconductor device 2 for adjustment is compared with the first electrical characteristic value measuring step (first step). a second electrical characteristic value measuring step (fifth step), in which, when the determination result in the first electrical characteristic value comparing step (fourth step) is within the tolerance range, the electrical characteristic value of the target semiconductor device 1 is measured; a second physical constant adjusting step (sixth step), in which, using the carrier mobility of the adjustment semiconductor device 2 in the first physical constant adjusting step (second step) just performed, a predetermined physical constant including the carrier mobility used in the second simulation is adjusted, and the electrical characteristic value of the target semiconductor device 1 is calculated in the second simulation; a second electrical characteristic value calculating step (seventh step), in which the electrical characteristic value of the target semiconductor device 1 is calculated by the second simulation; and a second electrical characteristic value comparing step (eighth step), in which, it is determined whether the difference between the second electrical characteristic measurement value obtained in the second electrical characteristic value measuring step (fifth step) and the second electrical characteristic calculation value obtained in the second electrical characteristic value calculating step (seventh step) is within the tolerance range. First, a first-stage calibration process (step S1: first electrical characteristic value measurement process to first electrical characteristic value comparison process) is performed on a semiconductor device including an adjustment main body portion 20 and an adjustment first wiring portion 21, namely, an adjustment semiconductor device 2, so as to improve the accuracy of physical constants having temperature coefficients such as carrier mobility, wherein the adjustment main body portion 20 is composed of a structure roughly the same as that of the target main body portion 10 of the target semiconductor device 1, and the heat dissipation of the adjustment first wiring portion 21 is higher than that of the target wiring portion 11.Then, the second stage calibration process (step S2: second electrical characteristic value measurement process to second electrical characteristic value measurement process) is performed using the physical constants obtained in the first stage calibration process (step S1: first electrical characteristic value measurement process to first electrical characteristic value comparison process), thereby improving the accuracy of the second simulation of the target semiconductor device 1 that is more susceptible to self-heating than the adjustment semiconductor device 2, and improving the accuracy of the final electrical characteristic value calculation of the target semiconductor device 1.

[0142] In addition, the LDMOS (semiconductor element) constituting the adjustment body 20 of the adjustment semiconductor device 2 includes a second gate electrode 208, a second drift layer 203 as an active region, a second P-type diffusion layer 204, and a second element separation film 205. The second drift layer 203 and the second element separation film 205 are formed in a state of being bonded to each other in a horizontal direction, and the second gate electrode 208 straddles the second drift layer 203 and the second element separation film 205 at a boundary between the second drift layer 203 and the second element separation film 205. 5, an adjustment first wiring portion 21 is formed on the upper surface of the second gate electrode 208, the adjustment first wiring portion 21 includes a first gate plug 211A made of metal and in a columnar shape, the number of the first gate plugs 211A included in the adjustment first wiring portion 21 is greater than the number of the first gate plugs 111A made of metal and in a columnar shape included in the target wiring portion 11, and a plurality of first gate plugs 211A are formed in the upper surface of the second gate electrode 208 in the range of the second drift layer 203 and the second element isolation film 205 in a plan view. Therefore, the heat dissipation of the adjustment semiconductor device 2 can be made higher than that of the target semiconductor device 1.

[0143] Furthermore, the first gate wiring 212A is connected to the upper ends of all the first gate plugs 211A included in the first adjustment wiring portion 21, and a second gate plug 221A made of metal and in a columnar shape is formed on the first gate wiring 212A. Therefore, the heat dissipation of the adjustment semiconductor device 2 can be further improved. In addition, the formation position of a part of the first gate plug 211A included in the first adjustment wiring portion 21 is substantially the same as the formation position of all the gate plugs 111A included in the target wiring portion 11 when viewed from above. Therefore, the heat dissipation of the adjustment semiconductor device 2 can be further improved, and the structural identity between the target semiconductor device 1 and the adjustment semiconductor device 2 is improved, thereby improving the accuracy of the calculation of the electrical characteristic value of the final target semiconductor device 1.

[0144] In addition, when the adjustment semiconductor device 2 is used as a semiconductor device that is generally used (assembled in a product), the second drift layer 203 and the second element separation film 205 are formed in a state of being bonded to each other in a horizontal direction, the second gate electrode 208 is formed across the second drift layer 203 and the second element separation film 205 at the boundary between the second drift layer 203 and the second element separation film 205, and the adjustment first wiring portion 21 includes a plurality of first gate plugs 211A made of metal and having a columnar shape, and the plurality of first gate plugs 211A are formed in the range of the second drift layer 203 and the second element separation film 205 in a plan view from the upper surface of the second gate electrode 208. Therefore, it is possible to suppress a decrease in drain current due to self-heating, and to suppress a decrease in circuit performance such as switching speed.

[0145] (Variation)

[0146] The present invention has been described above based on the embodiments. It will be understood by those skilled in the art that the embodiments are merely illustrative and that various modifications are possible in the combination of the above-described components, and these modifications are also within the scope of the present invention.

[0147] For example, in the first embodiment, the object body 10 includes a first supporting substrate 101, a first SOI substrate insulating film 102, a first drift layer 103, a first P-type diffusion layer 104, a first element separation film 105, a first drain 106, a first source 107, a first gate electrode 108 and a first gate insulating film 109, but its structure and layout are not limited to the first embodiment and can be appropriately deformed.

[0148] In addition, the object of calibration is the object semiconductor device 1 including the object main body 10 composed of an N-channel power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), but the semiconductor element constituting the object main body 10 is not limited to the N-channel power MOSFET. For example, other types of transistors such as P-channel power MOSFET and bipolar transistors can be formed as the object main body 10 and used as the object of calibration, and can also be formed as the adjustment main body 20 of the adjustment semiconductor device 2. Alternatively, a power MOS transistor using a surface layer of a semiconductor such as a drain extended MOS or an IGBT (Insulated Gate Bipolar Transistor) can be formed as the object main body 10 and used as the object of calibration, and can also be formed as the adjustment main body 20 of the adjustment semiconductor device 2. In addition, the object of calibration can also be applied to a P-channel LDMOS (Laterally Double Diffused MOS).

[0149] In the first embodiment, the number of the first drain plugs 211B and the first source plugs 211C is the same as the number of the drain plugs 111B and the source plugs 111C. However, the number of one or both of the first drain plugs 211B and the first source plugs 211C may be greater than the number of the drain plugs 111B and the source plugs 111C.

[0150] In the first embodiment, the formation positions of the first gate plugs 211A completely include the formation positions of the gate plugs 111A. However, as long as the number of first gate plugs 211A is greater than the number of gate plugs 111A, the formation positions of the first gate plugs 211A may be partially included or not included at all.

[0151] The adjustment semiconductor device 2 includes three wiring layers, namely, the first adjustment wiring portion 21 to the third adjustment wiring portion 23 . The number of wiring layers may be any number as long as the heat dissipation of the portion other than the adjustment main body portion 20 is higher than that of the target wiring portion 11 .

[0152] In addition, the target body portion 10 includes the first SOI substrate insulating film 102 , but may include a bulk silicon substrate instead of the first SOI substrate insulating film 102 . The same applies to the second SOI substrate insulating film 202 of the adjustment body portion 20 .

[0153] In the first embodiment, each wiring is made of aluminum, but it may be made of copper. The thermal conductivity of copper is 398 W / m·k, so copper will have a better effect from the perspective of reducing the influence of self-heating. However, from the perspective of manufacturing cost, aluminum is advantageous.

[0154] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0155] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A calibration method for calculating electrical characteristics of a semiconductor device, characterized in that: The target semiconductor device comprises: a target main body portion including a semiconductor element; and a target wiring portion stacked on the target main body portion and used to energize the semiconductor element. The calibration method in the electrical characteristic calculation of the semiconductor device comprises the following steps: The first step is to measure a first measurement value related to an electrical characteristic of an adjustment semiconductor device including an adjustment body portion and an adjustment wiring portion, wherein the adjustment body portion is formed of the same structure as the target body portion, and the adjustment wiring portion has a higher heat dissipation property than the target wiring portion; A second step is to adjust a predetermined physical constant including a carrier mobility used in a first simulation, wherein the first simulation calculates a value related to an electrical characteristic of the adjustment semiconductor device; A third step is to calculate a first calculated value related to the electrical characteristics of the adjustment semiconductor device through the first simulation; A fourth step of determining whether a difference between the first measured value of the electrical characteristic obtained in the first step and the first calculated value of the electrical characteristic obtained in the third step is within a prescribed tolerance range; A fifth step of measuring a second measurement value related to the electrical characteristics of the target semiconductor device when the result of the determination in the fourth step is within the range of the predetermined tolerance; A sixth step of adjusting a predetermined physical constant including the carrier mobility used in a second simulation using the carrier mobility of the adjustment semiconductor device in the second step, wherein the second simulation calculates a value related to the electrical characteristics of the target semiconductor device; A seventh step is to calculate a second calculated value related to the electrical characteristics of the target semiconductor device through the second simulation; and In an eighth step, it is determined whether a difference between the second measured value of the electrical characteristic obtained in the fifth step and the second calculated value of the electrical characteristic obtained in the seventh step is within a predetermined tolerance range.

2. A semiconductor device for adjustment, used in a calibration method for calculating electrical characteristics of the semiconductor device according to claim 1, characterized in that: The semiconductor element of the adjustment body of the adjustment semiconductor device includes a gate electrode, an active region, and an element isolation film. The active region and the element separation film are formed in a state of being bonded to each other in a horizontal direction. The gate electrode is formed across the active region and the element separation film at a boundary between the active region and the element separation film. forming the adjustment wiring portion on the upper surface of the gate electrode, The adjustment wiring portion includes a metal columnar plug. The number of plugs included in the adjustment wiring portion is greater than the number of metal columnar plugs included in the target wiring portion. The plurality of plugs are formed on the upper surface of the gate electrode within the range of the active region and the element isolation film in a plan view.

3. The semiconductor device for adjustment according to claim 2, wherein: The adjustment body includes a plurality of adjustment wiring portions, and the plurality of adjustment wiring portions are sequentially stacked on the adjustment body portion.

4. The semiconductor device for adjustment according to claim 3, wherein: The first adjustment wiring portion joined to the adjustment main body portion includes a plurality of gate plugs formed on the upper surface of the gate electrode, the plurality of gate plugs formed on the upper surface of the element separation film or the upper surface of the drift layer or the upper surface of the P-type diffusion layer, a plurality of drain plugs formed on the upper surface of the drain, and a plurality of source plugs spanning the upper surface of the N-type source and the upper surface of the P-type source.

5. The semiconductor device for adjustment according to claim 4, characterized in that One or more adjustment wiring portions formed above the first adjustment wiring portion include a plurality of gate plugs, and the plurality of gate plugs are formed above the plurality of gate plugs of the first adjustment wiring portion.

6. The semiconductor device for adjustment according to claim 2, wherein: Wiring is connected to the upper ends of all the plugs included in the adjustment wiring portion, and a metal columnar plug is formed on the wiring.

7. The semiconductor device for adjustment according to claim 2, wherein: A portion of the plugs included in the adjustment wiring portion are formed at positions in a plan view that are identical to positions in which all of the plugs included in the target wiring portion are formed in a plan view.

8. A semiconductor device used in the calibration method for calculating electrical characteristics of the semiconductor device according to claim 1, characterized in that: include: Semiconductor components; and a wiring layer stacked on the semiconductor element for energizing the semiconductor element, The semiconductor element includes a gate electrode, an active region, and an element separation film. The active region and the element separation film are formed in a state of being bonded to each other in a horizontal direction. The gate electrode is formed across the active region and the element separation film at a boundary between the active region and the element separation film. The wiring layer includes a plurality of metal columnar plugs. The plurality of plugs are formed on the upper surface of the gate electrode within the range of the active region and the element isolation film in a plan view.

9. The semiconductor device according to claim 8, characterized in that The plurality of plugs include a plurality of gate plugs formed on the upper surface of the gate electrode and formed on the upper surface of the element separation film, a plurality of drain plugs formed on the upper surface of the drain, and a plurality of source plugs spanning the upper surface of the N-type source and the upper surface of the P-type source.

10. The semiconductor device according to claim 9, characterized in that The plurality of plugs are arranged in parallel and separated from each other in the front-rear direction.

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