Field programmable gate array (FPGA) development method and system based on visual graphic design platform

Abstract

The invention provides an FPGA development method and system based on a visual graphic design platform, and relates to the technical field of visual graphics, and the method comprises the steps: building a visual graphic module according to a module definition in a Verilog language, and providing a circuit module library comprising a logic gate module, a combinational logic module and a sequential logic module in a design interface; adding a required visual graphic module into the circuit view from the circuit module library in a dragging manner; all module information is obtained, a module linear lookup table with module IDs as indexes is generated, and module parameters, ports, internal behavior level statements and data flow statements are converted into codes; corresponding Verilog codes are generated, wherein the Verilog codes comprise a parameter declaration code, a port declaration code, a connection line code and a module code; recursively executing the Verilog code generation step on the sub-modules until code conversion of all the modules is completed; and integrating all the generated Verilog codes to form a complete FPGA (Field Programmable Gate Array) design code.

Description

Technical Field

[0001] The present invention relates to a visual graphics technology, and in particular to an FPGA development method and system based on a visual graphics design platform. Background Art

[0002] During the FPGA development process, designers need to write Verilog code to describe the specific functions of the circuit at the structural and behavioral levels, thereby providing a basis for the subsequent design process. This design process requires designers to learn the syntax specifications of the Verilog hardware description language and have strong coding skills, which has a high threshold for beginners. There are also some integrated development environments (IDEs) on the market that try to simplify the FPGA development process, such as Xilinx's Vivado and Intel's Quartus Prime. However, most of these tools are designed for professional engineers, with powerful functions but complex interfaces and steep learning curves. In addition, the high cost of these tools also makes small and medium-sized enterprises and individual developers discouraged.

[0003] Problems and shortcomings of the background technology:

[0004] High learning threshold: Existing FPGA development tools require users to master complex hardware description languages ​​and command line operations. For beginners and non-professional users, the learning curve is steep and difficult to get started. Especially when writing Verilog code, designers need to be familiar with its syntax specifications and have strong coding skills, which is a big challenge for novices.

[0005] Complex interface: The existing integrated development environment (IDE) is powerful but has a complex interface, which makes it difficult for non-professional users and beginners to operate. Many users feel confused and overwhelmed when faced with complex tool interfaces, which affects design efficiency.

[0006] High cost: Professional FPGA development tools are usually expensive, which is a considerable expense for small and medium-sized enterprises and individual developers, thus limiting the use and promotion of FPGA technology by these groups. Summary of the invention

[0007] The embodiments of the present invention provide an FPGA development method and system based on a visual graphic design platform, which can solve the problems in the prior art.

[0008] According to a first aspect of the embodiments of the present invention,

[0009] Provides FPGA development methods based on a visual graphic design platform, including:

[0010] A visual graphic module is established according to the module definition in the Verilog language, wherein the visual graphic module includes a square icon, a module name, an input port, an output port, parameters, and an internal editable area, wherein the input port is located on the left side of the square icon, and the output port is located on the right side of the square icon; a circuit module library including a logic gate module, a combinational logic module, and a sequential logic module is provided in a design interface; a desired visual graphic module is added from the circuit module library to a circuit view by dragging and dropping; and the input port and the output port of each visual graphic module are connected by mouse operation in the circuit view to form a complete circuit design;

[0011] Configure behavioral statements in the internal editable area of ​​each visualization graphic module to implement the specific functions of the module; obtain the parameter module, input port and output port information of the current top-level view, and save them as the top-level parameter array, top-level input array and top-level output array respectively; obtain all connection information, create a connection relationship table containing the connection start module and connection target module data; obtain all module information, generate a module linear lookup table indexed by module ID, and convert module parameters, ports, internal behavioral statements and data flow statements into code;

[0012] According to the top-level parameter array, top-level input array, top-level output array, connection relationship table and module linear lookup table, corresponding Verilog codes are generated, including parameter declaration codes, port declaration codes, connection codes and module codes; the above Verilog code generation steps are recursively performed on the sub-modules until the code conversion of all modules is completed; all the generated Verilog codes are integrated to form a complete FPGA design code.

[0013] In an optional embodiment,

[0014] A visual graphic module is established according to the module definition in the Verilog language, wherein the visual graphic module includes a square icon, a module name, an input port, an output port, parameters and an internal editable area, wherein the input port is located on the left side of the square icon and the output port is located on the right side of the square icon; a circuit module library including a logic gate module, a combinational logic module and a sequential logic module is provided in a design interface; a required visual graphic module is added from the circuit module library to a circuit view by dragging and dropping; and the input port and the output port of each visual graphic module are connected by mouse operation in the circuit view to form a complete circuit design including:

[0015] Parse the Verilog module definition, extract the module name, input port, output port and parameter information; create a rectangular body as a visualization graphic module based on the extracted information, draw the module name in the center of the top of the rectangular body, draw the input ports evenly distributed on the left side of the rectangular body, draw the output ports evenly distributed on the right side of the rectangular body, list the parameter names and default values ​​at the bottom of the rectangular body, and reserve an editable area in the center of the rectangular body;

[0016] Add a mouse hover effect to each port of the visualization graphic module to display the port name and data type; add an editing function to the parameters; add a double-click event to the editable area to open the Verilog code editor; build a circuit module library, classify the modules into logic gate modules, combinational logic modules and sequential logic modules, and predefine common modules under each category; implement a split view circuit design main interface, with the module library displayed on the left and the circuit design area on the right; add a drag event listener to each module item in the module library to implement the function of dragging the module from the module library to the circuit design area; add a mouse event listener to the input and output ports of each module in the circuit design area to implement the function of connecting modules;

[0017] Implements a path planning algorithm for connections, automatically generates a broken line path that avoids other modules; provides module position adjustment, rotation, mirroring, and deletion functions, and automatically deletes all connected connections when a module is deleted; implements real-time Verilog syntax checking, and performs syntax verification when the user edits module parameters or internal logic; performs circuit integrity checking, detects unconnected input ports and output ports, and potential logic loops; traverses all modules and connections in the circuit design, and generates corresponding Verilog module code and connection code based on module type, parameter settings, internal logic, and connection information; integrates all generated codes to form a complete Verilog design file.

[0018] In an optional embodiment,

[0019] Configure behavioral statements in the internal editable area of ​​each visualization graphic module to implement the specific functions of the module; obtain the parameter module, input port and output port information of the current top-level view, and save them as the top-level parameter array, top-level input array and top-level output array respectively; obtain all connection information, create a connection relationship table containing the connection start module and connection target module data; obtain all module information, generate a module linear lookup table with module ID as the index, and convert module parameters, ports, internal behavioral statements and data flow statements into code including:

[0020] Traverse all module graphs in the top-level view, extract basic information such as module ID, module name and module type of each module, and parse the internal structure of the module to obtain module parameters, module ports, module internal behavior-level statements and module data flow statements;

[0021] Using the module ID as an index, create a module linear lookup table, each entry of the module linear lookup table includes a module ID, a module name, a module type, a module parameter list, a module port list, a module internal behavior level statement list, and a module data flow statement list;

[0022] For each module in the module linear lookup table, the module parameter list is converted into Verilog parameter declaration code, the module port list is converted into Verilog port declaration code, the module internal behavioral level statements are converted into Verilog process block code, the module data flow statements are converted into Verilog continuous assignment statements, and the converted codes are stored in the corresponding fields of the module linear lookup table.

[0023] In an optional embodiment,

[0024] The method further comprises:

[0025] Traverse the top-level parameter array, generate Verilog parameter declaration statements, and integrate them to form a parameter declaration code block;

[0026] Traverse the top-level input array and the top-level output array, generate Verilog port declaration statements, and integrate them to form a port declaration code block;

[0027] Traverse the connection relationship table, generate Verilogwire declaration statements and assign continuous assignment statements, and integrate them to form a wiring code block;

[0028] Traversing the module linear lookup table, extracting the converted code of each module, encapsulating it in a Verilogmodule structure, and integrating all module codes to form a module code block;

[0029] According to the Verilog syntax specification, the parameter declaration code block, port declaration code block, connection code block and module code block are integrated, necessary comments and document descriptions are added, and a complete FPGA design Verilog code file is generated.

[0030] In an optional embodiment,

[0031] According to the top-level parameter array, the top-level input array, the top-level output array, the connection relationship table and the module linear lookup table, the corresponding Verilog code is generated, including parameter declaration code, port declaration code, wiring code and module code, including:

[0032] Receive the top-level parameter array, the top-level input array, the top-level output array, the connection relationship table and the module linear lookup table;

[0033] Traversing the top-level parameter array, extracting the parameter name, data type and default value of each parameter, generating a Verilog parameter declaration statement, and integrating all parameter declaration statements to form a parameter declaration code block;

[0034] The top-level input array and the top-level output array are traversed respectively, the port name, bit width and direction of each port are extracted, a Verilog port declaration statement is generated, and all the port declaration statements are integrated to form a port declaration code block.

[0035] In an optional embodiment,

[0036] The method further comprises:

[0037] Traversing the connection relationship table, extracting the signal name, bit width and connection information of each connection item, generating Verilogwire declaration statements and assign continuous assignment statements, and integrating all wire declaration statements and assign statements to form a connection code block;

[0038] Traversing the module linear lookup table, extracting the module name, parameter list, port list, internal behavior level statement and data flow statement of each module item, generating Verilog module structure code, and integrating all module codes into a module code block;

[0039] Combining the parameter declaration code block, the port declaration code block, the connection code block and the module code block in the order of the Verilog syntax specification;

[0040] Generates a header comment containing the design name, author, and date information and adds it before the assembled code.

[0041] According to a second aspect of the embodiments of the present invention,

[0042] Provides an FPGA development system based on a visual graphic design platform, including:

[0043] The first unit is used to establish a visual graphic module according to the module definition in the Verilog language, wherein the visual graphic module includes a square icon, a module name, an input port, an output port, parameters and an internal editable area, wherein the input port is located on the left side of the square icon and the output port is located on the right side of the square icon; a circuit module library including a logic gate module, a combinational logic module and a sequential logic module is provided in a design interface; a required visual graphic module is added from the circuit module library to a circuit view by dragging and dropping; and an input port and an output port of each visual graphic module are connected by mouse operation in the circuit view to form a complete circuit design;

[0044] The second unit is used to configure the behavior-level statements in the internal editable area of ​​each visualization graphic module to realize the specific functions of the module; obtain the parameter module, input port and output port information of the current top-level view, and save them as the top-level parameter array, top-level input array and top-level output array respectively; obtain all the connection information, create a connection relationship table containing the connection start module and the connection target module data; obtain all the module information, generate a module linear lookup table with the module ID as the index, and convert the module parameters, ports, internal behavior-level statements and data flow statements into code;

[0045] The third unit is used to generate corresponding Verilog codes, including parameter declaration codes, port declaration codes, wiring codes and module codes, according to the top-level parameter array, top-level input array, top-level output array, connection relationship table and module linear lookup table; recursively execute the above Verilog code generation steps on the sub-modules until the code conversion of all modules is completed; and integrate all the generated Verilog codes to form a complete FPGA design code.

[0046] According to a third aspect of the embodiments of the present invention,

[0047] An electronic device is provided, comprising:

[0048] processor;

[0049] a memory for storing processor-executable instructions;

[0050] The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0051] According to a fourth aspect of the embodiments of the present invention,

[0052] A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented.

[0053] In order to lower the threshold of FPGA design and improve development efficiency, this application designs a visual graphic design platform. This platform uses a schematic view to display all circuit function modules on the interface and provides a complete circuit module library. Users only need to drag the required circuit modules and use the mouse to connect components to complete a circuit, and convert it into Verilog code through algorithms. It has the characteristics of low entry threshold, simple and fast operation, and intuitiveness.

[0054] The visual graphic design platform designed by this application displays circuit function modules through a schematic view and provides a complete circuit module library. Users only need to drag and drop modules and connect components to complete circuit design and automatically convert it into Verilog code. The platform lowers the learning threshold, is easy and fast to operate, and has intuitive features. It solves the problems and shortcomings of the existing technology and greatly improves the ease of use and efficiency of FPGA development. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A flowchart of an FPGA development method based on a visual graphic design platform according to an embodiment of the present invention;

[0056] Figure 2 A schematic diagram of a Verilog module definition according to an embodiment of the present invention;

[0057] Figure 3 A schematic diagram of a circuit diagram of an embodiment of the present invention;

[0058] Figure 4 It is a schematic diagram of the structure of an FPGA development system based on a visual graphic design platform according to an embodiment of the present invention. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0060] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0061] Figure 1 This is a flow chart of the FPGA development method based on the visual graphic design platform according to an embodiment of the present invention, with reference to Figure 2 and Figure 3 , the method comprising:

[0062] S101. Establish a visual graphic module according to the module definition in the Verilog language, wherein the visual graphic module includes a square icon, a module name, an input port, an output port, parameters, and an internal editable area, wherein the input port is located on the left side of the square icon, and the output port is located on the right side of the square icon; provide a circuit module library including a logic gate module, a combinational logic module, and a sequential logic module in the design interface; add the required visual graphic module from the circuit module library to the circuit view by dragging and dropping; connect the input port and the output port of each visual graphic module in the circuit view by mouse operation to form a complete circuit design;

[0063] S102. Configure behavioral statements in the internal editable area of ​​each visualization graphic module to implement the specific functions of the module; obtain the parameter module, input port and output port information of the current top-level view, and save them as the top-level parameter array, top-level input array and top-level output array respectively; obtain all connection information, create a connection relationship table containing the connection start module and the connection target module data; obtain all module information, generate a module linear lookup table with the module ID as the index, and convert the module parameters, ports, internal behavioral statements and data flow statements into code;

[0064] S103. Generate corresponding Verilog codes, including parameter declaration codes, port declaration codes, wiring codes and module codes, according to the top-level parameter array, top-level input array, top-level output array, connection relationship table and module linear lookup table; recursively execute the above Verilog code generation steps on the sub-modules until the code conversion of all modules is completed; integrate all the generated Verilog codes to form a complete FPGA design code.

[0065] In an optional embodiment,

[0066] A visual graphic module is established according to the module definition in the Verilog language, wherein the visual graphic module includes a square icon, a module name, an input port, an output port, parameters and an internal editable area, wherein the input port is located on the left side of the square icon and the output port is located on the right side of the square icon; a circuit module library including a logic gate module, a combinational logic module and a sequential logic module is provided in a design interface; a required visual graphic module is added from the circuit module library to a circuit view by dragging and dropping; and the input port and the output port of each visual graphic module are connected by mouse operation in the circuit view to form a complete circuit design including:

[0067] Parse the Verilog module definition, extract the module name, input port, output port and parameter information; create a rectangular body as a visualization graphic module based on the extracted information, draw the module name in the center of the top of the rectangular body, draw the input ports evenly distributed on the left side of the rectangular body, draw the output ports evenly distributed on the right side of the rectangular body, list the parameter names and default values ​​at the bottom of the rectangular body, and reserve an editable area in the center of the rectangular body;

[0068] Add a mouse hover effect to each port of the visualization graphic module to display the port name and data type; add an editing function to the parameters; add a double-click event to the editable area to open the Verilog code editor; build a circuit module library, classify the modules into logic gate modules, combinational logic modules and sequential logic modules, and predefine common modules under each category; implement a split view circuit design main interface, with the module library displayed on the left and the circuit design area on the right; add a drag event listener to each module item in the module library to implement the function of dragging the module from the module library to the circuit design area; add a mouse event listener to the input and output ports of each module in the circuit design area to implement the function of connecting modules;

[0069] Implements a path planning algorithm for connections, automatically generates a broken line path that avoids other modules; provides module position adjustment, rotation, mirroring, and deletion functions, and automatically deletes all connected connections when a module is deleted; implements real-time Verilog syntax checking, and performs syntax verification when the user edits module parameters or internal logic; performs circuit integrity checking, detects unconnected input ports and output ports, and potential logic loops; traverses all modules and connections in the circuit design, and generates corresponding Verilog module code and connection code based on module type, parameter settings, internal logic, and connection information; integrates all generated codes to form a complete Verilog design file.

[0070] Exemplarily, a regular expression or a specialized Verilog parser is used to extract module name, input port, output port and parameter information; the behavior description inside the module is parsed to identify editable areas.

[0071] Create a rectangle as the main body of the module. Its size is dynamically adjusted according to the number of ports and parameters. Draw the module name in the center of the top of the rectangle. Draw the input ports evenly distributed on the left side of the rectangle, each represented by a small circle. Draw the output ports evenly distributed on the right side of the rectangle, each represented by a small circle. List the parameter names and default values ​​at the bottom of the rectangle. Reserve an editable area in the center of the rectangle for displaying and editing internal logic.

[0072] Add mouse hover effect to each port to display the port name and data type; add editing function to parameters to allow users to modify default values; add double-click event to internal editable area to open Verilog code editor; build circuit module library.

[0073] Create three main categories: logic gate modules, combinational logic modules, and sequential logic modules; further subdivide each category into subcategories such as basic logic gates, multiplexers, flip-flops, etc.

[0074] A series of commonly used modules are predefined for each category, such as AND gate, OR gate, D flip-flop, etc.; a visual graphical representation is created for each predefined module.

[0075] Design a tree-structured module library interface to display all categories and subcategories; display all available modules in each category under that category; provide a thumbnail preview and a brief description of the circuit design interface implementation for each module.

[0076] Create a split view with the module library on the left and the circuit design area on the right; add a menu bar and toolbar at the top to provide file operation, editing, view control and other functions; add a status bar at the bottom to display the current operation status and prompt information.

[0077] Add a drag event listener to each module item in the module library; when dragging starts, create a semi-transparent module graphic as a drag preview; implement collision detection during dragging to ensure that modules can only be placed in the valid area; when dragging ends, create a complete visual graphic module instance at the placement location.

[0078] Add mouse event listeners to the input and output ports of each module; when the user clicks a port, start drawing a temporary connection; track mouse movement and update the endpoint position of the temporary connection in real time; when the user clicks another compatible port, create a permanent connection object; implement the connection path planning algorithm to automatically generate a broken line path that avoids other modules.

[0079] Allows users to adjust the module position by dragging; provides rotation and mirroring operations to flexibly adjust the module direction; implements the module deletion function and automatically deletes all the lines connected to it; allows users to adjust the line path and provides the function of manually editing the line breakpoints.

[0080] Verilog syntax checking is performed in real time when users edit module parameters or internal logic; syntax error information is displayed in the status bar or floating prompt.

[0081] Implemented algorithms to detect unconnected input and output ports; check if there are logic loops and alert the user to potential problems.

[0082] Traverse all modules and connections in the circuit design; generate corresponding Verilog module code according to the module type, parameter settings and internal logic; generate connection code between modules according to the connection information; integrate all generated codes to form a complete Verilog design file.

[0083] Through the above detailed steps, we have realized a fully functional visual circuit design system. This system not only allows users to design digital circuits intuitively, but also automatically generates corresponding Verilog codes, greatly improving the efficiency and accuracy of digital circuit design. This method combines traditional textual Verilog programming with modern graphical interface design, providing FPGA developers with a powerful and easy-to-use tool.

[0084] In an optional embodiment,

[0085] Configure behavioral statements in the internal editable area of ​​each visualization graphic module to implement the specific functions of the module; obtain the parameter module, input port and output port information of the current top-level view, and save them as the top-level parameter array, top-level input array and top-level output array respectively; obtain all connection information, create a connection relationship table containing the connection start module and connection target module data; obtain all module information, generate a module linear lookup table with module ID as the index, and convert module parameters, ports, internal behavioral statements and data flow statements into code including:

[0086] Traverse all module graphs in the top-level view, extract basic information such as module ID, module name and module type of each module, and parse the internal structure of the module to obtain module parameters, module ports, module internal behavior-level statements and module data flow statements;

[0087] Using the module ID as an index, create a module linear lookup table, each entry of the module linear lookup table includes a module ID, a module name, a module type, a module parameter list, a module port list, a module internal behavior level statement list, and a module data flow statement list;

[0088] For each module in the module linear lookup table, the module parameter list is converted into Verilog parameter declaration code, the module port list is converted into Verilog port declaration code, the module internal behavioral level statements are converted into Verilog process block code, the module data flow statements are converted into Verilog continuous assignment statements, and the converted codes are stored in the corresponding fields of the module linear lookup table.

[0089] For example, top-level view information collection:

[0090] Traverse all graphic elements in the top-level view; identify and extract parameter module graphics; parse the properties of the parameter module, including parameter name, type and default value; store the extracted parameter information in the top-level parameter array, where each element contains the parameter name, type and default value.

[0091] Traverse the left border of the top-level view; identify and extract the input port graph; parse the attributes of the input port, including the port name, bit width, and data type; store the extracted input port information into the top-level input array, where each element contains the port name, bit width, and data type.

[0092] Traverse the right border of the top-level view; identify and extract the output port graph; parse the output port attributes, including port name, bit width, and data type; store the extracted output port information into the top-level output array, where each element contains the port name, bit width, and data type.

[0093] Traverse all the connection graphs in the top-level view; for each connection, identify its starting module and target module; extract the properties of the connection, including signal name, bit width, etc.

[0094] Initialize an empty connection relationship table; create a table entry for each extracted connection information; the table entry contains the following fields: connection ID, starting module ID, starting port name, target module ID, target port name, signal name, bit width; add the created table entry to the connection relationship table.

[0095] Traverse all module graphs in the top-level view; for each module, extract its basic information such as ID, name, type, etc.; parse the internal structure of the module, including parameters, ports, internal behavioral level statements, and data flow statements.

[0096] Initialize an empty module linear lookup table; create lookup table entries with module ID as index; each table entry contains: module ID, module name, module type, parameter list, port list, internal behavior-level statement list, and data flow statement list.

[0097] For each module in the module linear lookup table:

[0098] a. Convert the parameter list into Verilog parameter declaration code;

[0099] b. Convert the port list into Verilog port declaration code;

[0100] c. Convert internal behavioral level statements into Verilog procedural block codes;

[0101] d. Convert data flow statements into Verilog continuous assignment statements;

[0102] The converted codes are stored in the corresponding fields of the module linear lookup table.

[0103] Traverse the top-level parameter array; for each parameter, generate the corresponding Verilog parameter declaration statement; integrate all parameter declaration statements to form a complete parameter declaration code block.

[0104] Traverse the top-level input array and the top-level output array; for each port, generate the corresponding Verilog port declaration statement; integrate all port declaration statements to form a complete port declaration code block.

[0105] Traverse the connection relationship table; for each connection, generate the corresponding Verilog wire declaration statement; generate the necessary assign continuous assignment statements to ensure correct signal transmission; integrate all wire declarations and assign statements to form a complete wiring code block.

[0106] Traverse the module linear lookup table; for each module, extract its converted code; encapsulate the code in a Verilogmodule structure; integrate all module codes to form a complete module code block.

[0107] According to the Verilog syntax specification, the generated parameter declaration code, port declaration code, connection code and module code are integrated; necessary comments and document descriptions are added; and a complete FPGA design Verilog code file is generated.

[0108] Through the above detailed steps, accurate conversion from visual graphic design platform to Verilog code can be achieved. This method not only ensures the correctness and integrity of the code, but also improves the efficiency and maintainability of FPGA development.

[0109] In an optional embodiment,

[0110] The method further comprises:

[0111] Traverse the top-level parameter array, generate Verilog parameter declaration statements, and integrate them to form a parameter declaration code block;

[0112] Traverse the top-level input array and the top-level output array, generate Verilog port declaration statements, and integrate them to form a port declaration code block;

[0113] Traverse the connection relationship table, generate Verilog wire declaration statements and assign continuous assignment statements, and integrate them to form a connection code block;

[0114] Traversing the module linear lookup table, extracting the converted code of each module, encapsulating it in a Verilogmodule structure, and integrating all module codes to form a module code block;

[0115] According to the Verilog syntax specification, the parameter declaration code block, port declaration code block, connection code block and module code block are integrated, necessary comments and document descriptions are added, and a complete FPGA design Verilog code file is generated.

[0116] In an optional embodiment,

[0117] According to the top-level parameter array, the top-level input array, the top-level output array, the connection relationship table and the module linear lookup table, the corresponding Verilog code is generated, including parameter declaration code, port declaration code, wiring code and module code, including:

[0118] Receive the top-level parameter array, the top-level input array, the top-level output array, the connection relationship table and the module linear lookup table;

[0119] Traversing the top-level parameter array, extracting the parameter name, data type and default value of each parameter, generating a Verilog parameter declaration statement, and integrating all parameter declaration statements to form a parameter declaration code block;

[0120] The top-level input array and the top-level output array are traversed respectively, the port name, bit width and direction of each port are extracted, a Verilog port declaration statement is generated, and all the port declaration statements are integrated to form a port declaration code block.

[0121] In an optional embodiment,

[0122] The method further comprises:

[0123] Traversing the connection relationship table, extracting the signal name, bit width and connection information of each connection item, generating Verilogwire declaration statements and assign continuous assignment statements, and integrating all wire declaration statements and assign statements to form a connection code block;

[0124] Traversing the module linear lookup table, extracting the module name, parameter list, port list, internal behavior level statement and data flow statement of each module item, generating Verilog module structure code, and integrating all module codes into a module code block;

[0125] Combining the parameter declaration code block, the port declaration code block, the connection code block and the module code block in the order of the Verilog syntax specification;

[0126] Generates a header comment containing the design name, author, and date information and adds it before the assembled code.

[0127] Another embodiment of the present application is as follows:

[0128] Circuit design method using visual graphics module:

[0129] Module definition: According to the module definition in the Verilog language, the corresponding visual graphic module is established. Port list->graphic module input on the left and output on the right; parameter declaration->parameter graphic module; behavioral level statement, data flow statement->editable area inside the graphic module; variable declaration, port declaration, module name, module statement end are provided by the following conversion algorithm.

[0130] Graphical representation: Each circuit module is represented by a square icon with the module name attached. The input port and output port of the module are represented by the straight lines on the left and right respectively. Internal structure: Each module stores behavioral level statements to ensure the functional and logical correctness of the module. Circuit view: A circuit view consists of input ports, output ports and multiple graphic modules. FPGA developers can complete the circuit design by dragging the required visual graphic modules into the view and connecting the lines between the modules.

[0131] Module definition and creation: Create corresponding visual graphic modules according to the definition in the Verilog language. Each module is represented by a square icon, the straight line on the left represents the input port, and the straight line on the right represents the output port.

[0132] Module dragging and connection: FPGA developers drag the required visual graphical modules into the circuit view in the design interface.

[0133] By dragging the straight lines of the input and output ports, different modules are connected to form a complete circuit design (such as Figure 3 shown).

[0134] Behavioral statement configuration: Configure corresponding behavioral statements within each module to implement the specific functions of the module.

[0135] Ensure that the connections between modules are correct, the behavior logic is consistent, and the expected functions of the circuit are achieved.

[0136] Circuit design completed: After the connection is completed, the circuit design is verified and tested through the graphical interface to ensure the logical correctness and functional realization of the designed circuit.

[0137] Visualization of graphic modules and circuit design language Verilog conversion algorithm:

[0138] Get the top view parameter module: Get the parameter module of the current top view and save it as the top parameter array. Get the input and output ports: Get the input and output ports of the current top view and save them as the top input array and output array respectively. Create a connection relationship table: Get all the wires and create a connection relationship table, which contains data such as the wire start module and the wire target module. Generate module linear lookup table: Get all modules, generate a linear lookup table with the module ID as the index, and convert the module parameters, ports, module internal behavior-level statements and data flow statements into code. Generate Verilog parameter declaration code: Traverse the top parameter array and convert it into Verilog parameter declaration code. Generate Verilog port declaration code: Traverse the top input array and the top output array and convert them into Verilog port declaration code. Generate Verilog wire code: Traverse the connection relationship table and convert it into Verilog wire declaration code and assign continuous assignment code. Encapsulate module code: Traverse the module linear lookup table and encapsulate the code into Verilog module code. Recursively process submodules: After the top-level view is completed, enter the submodule and continue the above process to ensure that all modules are correctly converted to Verilog code.

[0139] Module library for common circuit functions:

[0140] The platform has pre-built-in modules required for various commonly used circuit designs, including the following categories: Logic gate module: including basic logic operation units such as AND gate, OR gate, NOT gate, XOR gate, etc. Combinatorial logic module: covers various adders (such as half adders, full adders), comparators, decoders, decoders, selectors, voters, etc. Sequential logic module: includes counters, triggers (such as D triggers, JK triggers), latches, shift registers, etc. All elements in these module libraries can be directly retrieved through the platform and used and combined by dragging and dropping. Users only need to select the corresponding module from the library according to the design requirements, drag and connect, and they can quickly build the required circuit. This modular design greatly improves the efficiency and flexibility of circuit design, simplifies the design process, and is suitable for various circuit design application scenarios.

[0141] Figure 4 FIG. 1 is a schematic diagram of the structure of an FPGA development system based on a visual graphic design platform according to an embodiment of the present invention. Figure 4 As shown, the system comprises:

[0142] The first unit is used to establish a visual graphic module according to the module definition in the Verilog language, wherein the visual graphic module includes a square icon, a module name, an input port, an output port, parameters and an internal editable area, wherein the input port is located on the left side of the square icon and the output port is located on the right side of the square icon; a circuit module library including a logic gate module, a combinational logic module and a sequential logic module is provided in a design interface; a required visual graphic module is added from the circuit module library to a circuit view by dragging and dropping; and an input port and an output port of each visual graphic module are connected by mouse operation in the circuit view to form a complete circuit design;

[0143] The second unit is used to configure the behavior-level statements in the internal editable area of ​​each visualization graphic module to realize the specific functions of the module; obtain the parameter module, input port and output port information of the current top-level view, and save them as the top-level parameter array, top-level input array and top-level output array respectively; obtain all the connection information, create a connection relationship table containing the connection start module and the connection target module data; obtain all the module information, generate a module linear lookup table with the module ID as the index, and convert the module parameters, ports, internal behavior-level statements and data flow statements into code;

[0144] The third unit is used to generate corresponding Verilog codes, including parameter declaration codes, port declaration codes, wiring codes and module codes, according to the top-level parameter array, top-level input array, top-level output array, connection relationship table and module linear lookup table; recursively execute the above Verilog code generation steps on the sub-modules until the code conversion of all modules is completed; and integrate all the generated Verilog codes to form a complete FPGA design code.

[0145] According to a third aspect of the embodiments of the present invention,

[0146] An electronic device is provided, comprising:

[0147] processor;

[0148] a memory for storing processor-executable instructions;

[0149] The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0150] According to a fourth aspect of the embodiments of the present invention,

[0151] A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented.

[0152] The present invention may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for executing various aspects of the present invention.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. The FPGA development method based on the visual graphic design platform is characterized by: include: Establishing a visual graphic module according to the module definition in the Verilog language, wherein the visual graphic module includes a square icon, a module name, an input port, an output port, a parameter, and an internal editable area, wherein the input port is located on the left side of the square icon, and the output port is located on the right side of the square icon; providing a circuit module library including a logic gate module, a combinational logic module, and a sequential logic module in a design interface; adding a desired visual graphic module from the circuit module library to a circuit view by dragging and dropping; Connecting the input ports and output ports of each visualization graphic module by mouse operation in the circuit view to form a complete circuit design; Configure behavioral statements in the internal editable area of ​​each visualization graphic module to implement the specific functions of the module; obtain the parameter module, input port and output port information of the current top-level view, and save them as the top-level parameter array, top-level input array and top-level output array respectively; obtain all connection information, create a connection relationship table containing the connection start module and connection target module data; obtain all module information, generate a module linear lookup table indexed by module ID, and convert module parameters, ports, internal behavioral statements and data flow statements into code; According to the top-level parameter array, top-level input array, top-level output array, connection relationship table and module linear lookup table, corresponding Verilog codes are generated, including parameter declaration codes, port declaration codes, connection codes and module codes; the above Verilog code generation steps are recursively performed on the sub-modules until the code conversion of all modules is completed; all the generated Verilog codes are integrated to form a complete FPGA design code.

2. The method according to claim 1, characterized in that Establishing a visual graphic module according to the module definition in the Verilog language, wherein the visual graphic module includes a square icon, a module name, an input port, an output port, a parameter, and an internal editable area, wherein the input port is located on the left side of the square icon, and the output port is located on the right side of the square icon; providing a circuit module library including a logic gate module, a combinational logic module, and a sequential logic module in a design interface; adding a desired visual graphic module from the circuit module library to a circuit view by dragging and dropping; In the circuit view, the input ports and output ports of each visualization graphic module are connected by mouse operation to form a complete circuit design including: Parse the Verilog module definition, extract the module name, input port, output port and parameter information; create a rectangular body as a visualization graphic module based on the extracted information, draw the module name in the center of the top of the rectangular body, draw the input ports evenly distributed on the left side of the rectangular body, draw the output ports evenly distributed on the right side of the rectangular body, list the parameter names and default values ​​at the bottom of the rectangular body, and reserve an editable area in the center of the rectangular body; Add a mouse hover effect to each port of the visualization graphic module to display the port name and data type; add an editing function to the parameters; add a double-click event to the editable area to open the Verilog code editor; build a circuit module library, classify the modules into logic gate modules, combinational logic modules and sequential logic modules, and predefine common modules under each category; implement a split view circuit design main interface, with the module library displayed on the left and the circuit design area on the right; add a drag event listener to each module item in the module library to implement the function of dragging the module from the module library to the circuit design area; add a mouse event listener to the input and output ports of each module in the circuit design area to implement the function of connecting modules; Implements a path planning algorithm for connections, automatically generates a broken line path that avoids other modules; provides module position adjustment, rotation, mirroring, and deletion functions, and automatically deletes all connected connections when a module is deleted; implements real-time Verilog syntax checking, and performs syntax verification when the user edits module parameters or internal logic; performs circuit integrity checking, detects unconnected input ports and output ports, and potential logic loops; traverses all modules and connections in the circuit design, and generates corresponding Verilog module code and connection code based on module type, parameter settings, internal logic, and connection information; integrates all generated codes to form a complete Verilog design file.

3. The method according to claim 1, characterized in that Configure behavioral statements in the internal editable area of ​​each visualization graphic module to implement the specific functions of the module; obtain the parameter module, input port and output port information of the current top-level view, and save them as the top-level parameter array, top-level input array and top-level output array respectively; obtain all connection information, create a connection relationship table containing the connection start module and connection target module data; obtain all module information, generate a module linear lookup table with module ID as the index, and convert module parameters, ports, internal behavioral statements and data flow statements into code including: Traverse all module graphs in the top-level view, extract basic information such as module ID, module name and module type of each module, and parse the internal structure of the module to obtain module parameters, module ports, module internal behavior-level statements and module data flow statements; Using the module ID as an index, create a module linear lookup table, each entry of the module linear lookup table includes a module ID, a module name, a module type, a module parameter list, a module port list, a module internal behavior level statement list, and a module data flow statement list; For each module in the module linear lookup table, the module parameter list is converted into Verilog parameter declaration code, the module port list is converted into Verilog port declaration code, the module internal behavior level statement is converted into Verilog process block code, the module data flow statement is converted into Verilog continuous assignment statement, and the converted code is stored in the corresponding field of the module linear lookup table.

4. The method according to claim 3, characterized in that: The method further comprises: Traverse the top-level parameter array, generate Verilog parameter declaration statements, and integrate them to form a parameter declaration code block; Traverse the top-level input array and the top-level output array, generate Verilog port declaration statements, and integrate them to form a port declaration code block; Traverse the connection relationship table, generate Verilog wire declaration statements and assign continuous assignment statements, and integrate them to form a connection code block; Traversing the module linear lookup table, extracting the converted code of each module, encapsulating it in a Verilog module structure, and integrating all module codes to form a module code block; According to the Verilog syntax specification, the parameter declaration code block, port declaration code block, connection code block and module code block are integrated, necessary comments and document descriptions are added, and a complete FPGA design Verilog code file is generated.

5. The method according to claim 1, characterized in that According to the top-level parameter array, the top-level input array, the top-level output array, the connection relationship table and the module linear lookup table, the corresponding Verilog code is generated, including parameter declaration code, port declaration code, wiring code and module code, including: Receive the top-level parameter array, the top-level input array, the top-level output array, the connection relationship table and the module linear lookup table; Traversing the top-level parameter array, extracting the parameter name, data type and default value of each parameter, generating a Verilog parameter declaration statement, and integrating all parameter declaration statements to form a parameter declaration code block; The top-level input array and the top-level output array are traversed respectively, the port name, bit width and direction of each port are extracted, a Verilog port declaration statement is generated, and all the port declaration statements are integrated to form a port declaration code block.

6. The method according to claim 5, characterized in that The method further comprises: Traversing the connection relationship table, extracting the signal name, bit width and connection information of each connection item, generating Verilogwire declaration statements and assign continuous assignment statements, and integrating all wire declaration statements and assign statements to form a connection code block; Traversing the module linear lookup table, extracting the module name, parameter list, port list, internal behavior level statement and data flow statement of each module item, generating Verilog module structure code, and integrating all module codes into a module code block; Combining the parameter declaration code block, the port declaration code block, the connection code block and the module code block in the order of the Verilog syntax specification; Generates a header comment containing the design name, author, and date information and adds it before the assembled code.

7. An FPGA development system based on a visual graphic design platform, used to implement the method according to any one of claims 1 to 6, characterized in that: include: The first unit is used to establish a visual graphic module according to the module definition in the Verilog language, wherein the visual graphic module includes a square icon, a module name, an input port, an output port, parameters and an internal editable area, wherein the input port is located on the left side of the square icon and the output port is located on the right side of the square icon; a circuit module library including a logic gate module, a combinational logic module and a sequential logic module is provided in the design interface; and a required visual graphic module is added from the circuit module library to a circuit view by dragging and dropping; Connecting the input ports and output ports of each visualization graphic module by mouse operation in the circuit view to form a complete circuit design; The second unit is used to configure the behavior-level statements in the internal editable area of ​​each visualization graphic module to realize the specific functions of the module; obtain the parameter module, input port and output port information of the current top-level view, and save them as the top-level parameter array, top-level input array and top-level output array respectively; obtain all the connection information, create a connection relationship table containing the connection start module and the connection target module data; obtain all the module information, generate a module linear lookup table with the module ID as the index, and convert the module parameters, ports, internal behavior-level statements and data flow statements into code; The third unit is used to generate corresponding Verilog codes, including parameter declaration codes, port declaration codes, wiring codes and module codes, according to the top-level parameter array, top-level input array, top-level output array, connection relationship table and module linear lookup table; recursively execute the above Verilog code generation steps on the sub-modules until the code conversion of all modules is completed; and integrate all the generated Verilog codes to form a complete FPGA design code.

8. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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