Design method, computer-readable medium, and computer-implemented system

Abstract

The invention provides a design method of an integrated circuit combined with simulation of an ECO process. An example method includes receiving an initial design and performing an automatic marking process. The automatic marking process includes performing a first automatic marking process to surround a first plurality of active cells of the design with a first computer-aided design (CAD) layer corresponding to a first plurality of engineering change command (ECO) cells; performing an enhanced automatic marking process to cover the irregular shape of the design with a second CAD layer corresponding to a second plurality of ECO cells; and performing a second automatic marking process to fill empty areas of the design with a third CAD layer corresponding to a third plurality of ECO cells. The method further includes populating the design with the first plurality of ECO cells, the second plurality of ECO cells, and the third plurality of ECO cells.

Description

Technical Field

[0001] The present invention relates to a design method, a computer readable medium and a computer implemented system. Background Art

[0002] In integrated circuit (IC) design, the engineering change order (ECO) process is often used to modify the layout in the late stages of design or after tapeout. By implementing ECO, designers can incorporate changes to correct errors or optimize performance without a comprehensive and costly redesign. Summary of the invention

[0003] An embodiment of the present invention provides a method for designing an integrated circuit. The method for designing an integrated circuit includes: receiving an initial design; performing an automatic marking process, including: performing a first automatic marking process to surround a first plurality of valid cells of the initial design using a first computer-aided design layer corresponding to a first plurality of engineering change order cells; performing an enhanced automatic marking process to cover irregular shapes of the initial design using a second computer-aided design layer corresponding to a second plurality of engineering change order cells; and performing a second automatic marking process to fill empty areas of the initial design using a third computer-aided design layer corresponding to a third plurality of engineering change order cells; and filling the initial design using the first plurality of engineering change order cells, the second plurality of engineering change order cells, and the third plurality of engineering change order cells.

[0004] An embodiment of the present invention provides a non-transitory computer-readable medium. The non-transitory computer-readable medium is encoded with a memory storing instructions for making an integrated circuit, and when the instructions are executed, operations including the following steps are performed: initializing an automatic marking process to fill an initial circuit design with a plurality of engineering change order cells to form an updated design; inserting a dummy pattern, wherein the dummy pattern is configured to prevent dents during fabrication; performing a final design rule check; performing rule check extraction and post-layout simulation; and causing the integrated circuit to be fabricated according to the updated design.

[0005] An embodiment of the present invention provides a computer-implemented system for making design changes to an integrated circuit. The computer-implemented system for making design changes to an integrated circuit includes: one or more processors; and a computer-readable memory that communicates with the one or more processors and is encoded with instructions for commanding the one or more processors to perform the following steps: receiving an input design including a plurality of valid cells; inserting an engineering change order cell into the input design through a simulated engineering change order process to form an updated design; fabricating the integrated circuit based on the updated design; implementing the engineering change order by routing at least one engineering change order cell of the updated design to at least one valid cell of the updated design, thereby creating a revised design; and fabricating a revised integrated circuit based on the revised design. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a flow chart illustrating a design method according to an embodiment.

[0007] Figure 2 FIG. 5 is a flow chart illustrating a method of designing an integrated circuit according to an embodiment.

[0008] Figure 3 1 is a flowchart and a figure illustrating an automatic labeling process according to an embodiment.

[0009] Figure 4 is a schematic diagram illustrating an automatic labeling process according to an embodiment.

[0010] Figure 5 FIG. 4 is a schematic diagram illustrating an ECO cell region formed by an automatic marking process according to an embodiment.

[0011] Figure 6 is a schematic flow chart illustrating an automatic labeling process according to an embodiment.

[0012] Figure 7 1 is a flowchart and a figure illustrating an automatic labeling process according to an embodiment.

[0013] Figure 8 is a schematic diagram illustrating an automatic labeling process according to an embodiment.

[0014] Fig. 9 FIG. 4 is a flowchart illustrating a corner inspection process according to an embodiment.

[0015] Fig.10 is a schematic diagram illustrating various stages of a corner inspection process according to an embodiment.

[0016] Fig.11 1 is a flowchart and a diagram illustrating a DRC pre-checker according to an embodiment.

[0017] Fig.12 A schematic diagram is shown depicting the layout of a design after a simulated ECO process according to an embodiment.

[0018] Fig.13A , Fig. 13B and Fig. 13C is a block diagram illustrating an exemplary system for implementing the method described herein for designing an integrated circuit.

[0019] Fig.14 FIG. 1 is a flow chart illustrating a method for implementing a design change to an integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than itself representing the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0022] Some embodiments of the present disclosure are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the stages described may be replaced or deleted for different embodiments. Additional features may be added to the circuit. Some of the features described below may be replaced or deleted for different embodiments. Although some embodiments are discussed using operations performed in a particular order, the operations may be performed in another logical order.

[0023] As described above, the ECO process can be incorporated into the IC design process to enable efficient implementation of design changes and modifications. Nevertheless, introducing design changes can be a long and expensive process. The increasing complexity of circuit design and manufacturing processes (especially in circuits using analog cells) has led to a longer time period between design tape-out and wafer completion. Additionally, implementing some design changes may include changing the mask used during the process, which further increases production time and cost. Therefore, the time and cost of a particular design from the initial stage, through testing, and into production can be very large.

[0024] To facilitate ECO and accelerate design changes, ECO cells can be inserted into the design floor plan. These cells may include a predetermined architecture that is selected to provide specific functions based on design needs. ECO cells can be strategically placed throughout the design to replace failed functional cells or enable layout changes without a complete redesign.

[0025] The present subject matter introduces ECO cells into analog design and provides an analog ECO flow to enable efficient ECO of circuits using analog cells. The analog ECO flow can support early oxygen diffusion and polysilicon (ODPO) tape-out, thereby reducing turn-around time (TAT) when implementing changes. In addition, the flow can reduce design time-to-market and improve process costs by facilitating back-end-of-line (BEOL) mask updates.

[0026] The embodiments described herein may provide an auto-marker process that can populate ECO computer-aided-design (CAD) with higher efficiency. Additionally, the embodiments described herein may provide pre-check and corner check solutions that avoid erroneous design rule check (DRC) errors caused by the implementation of ECOs. The introduction of ECO cells and the use of analog ECO processes may improve productivity between initial IC design and final product. In some embodiments, ECO cells may be populated into a design with an efficiency exceeding 70%.

[0027] Figure 1is a flow chart depicting a design method according to an embodiment. An exemplary analog ECO process may start at 101 with a new tape-out of an initial design. In an embodiment, the new tape-out may be optimized for improvement metrics such as power, performance, and area (PPA). In general, increasing PPA during production has a negative impact on TAT. The embodiments described herein may provide products with strong PPA characteristics without compromising TAT. As part of the tape-out process 101, a front-end-of-line (FEOL) mask may be manufactured. The FEOL mask may be used to transfer the pattern of the active components of the integrated circuit to the silicon wafer. The FEOL mask may be time-consuming and expensive to manufacture. An advantage of the embodiments described herein may be that design changes may be implemented without returning to this step and manufacturing a new FEOL mask.

[0028] The flow may then proceed to post-layout simulation and analysis at 103. During this stage, the tape-out design may be evaluated to see if it complies with the design constraints. For example, at this stage, rule checks such as design rule checking may be performed, parasitic extraction may be performed, and other analyses such as timing analysis and noise analysis may be performed.

[0029] Next, the design may undergo performance retuning and trimming at 105. Here, based on the results of simulation and analysis, the design may be retuned and optimized, and components of the design may be trimmed, such as by laser trimming, to obtain desired electrical characteristics.

[0030] After retuning and trimming, the flow may proceed to layout customization at 107. During layout customization, the designer may modify or optimize the physical layout of the components of the design to improve performance and meet constraints. As non-limiting examples, the designer may modify the layout for the purpose of area optimization or performance optimization.

[0031] After layout customization, the flow may proceed to silicon metrology at 109 where the customized design on actual silicon wafers may be tested and verified to confirm functionality. Once silicon metrology is complete, the final product may be ready to enter the market, as indicated at 113. However, in other cases, design changes may be required, in which case the flow may return to a previous stage, as indicated by 111.

[0032] In an embodiment, the ECO cell and simulation ECO flow may enable design changes to be implemented by returning to the post-layout simulation and analysis stage 103. This may eliminate the need to generate a new FEOL mask, which is an expensive and time consuming process.

[0033] After the design change, the flow may proceed in the same manner as described above. However, by using ECO cells according to embodiments of the present subject matter, the process may be simplified. After the analysis, re-tuning, and trimming are completed, the flow may be about enabling the ECO cells in the design, as shown at 115. The desired design changes may be implemented by enabling and strategically using these ECO cells, without requiring a new mask as described above. After the ECO cells are enabled, the flow may proceed to the final product 113 through layout customization 107 and silicon metrology 109.

[0034] Figure 2 is a flow chart illustrating a method for designing an integrated circuit according to an embodiment. The method of design may be combined with an analog ECO flow configured to insert ECO cells into the design. The method may begin at 201 by generating or receiving an initial design. A designer may generate an initial design and the initial design may be received and used as input by a software design tool such as an EDA or CAD tool. The initial design may be a completed valid design (including a schematic diagram and layout of the circuit design). In an embodiment, the initial design may include an intellectual property (IP) design, in which the designer integrates customizable, reusable IP blocks including pre-designed circuits and functions into the layout.

[0035] Next, the method may proceed to 203, where the design may undergo a pre-check process that evaluates the design for any DRC issues before inserting ECO cells. Figure 3 and Fig.11 A pre-checker according to the present subject matter is described in more detail. If the design does not pass the pre-check process, the flow may return to 201, where the floor plan may be modified to avoid DRC issues. If the pre-check does not identify any issues, the flow may enter the simulation ECO process 250. The simulation ECO process 250 may include a series of processes that ultimately insert ECO cells into the design data.

[0036] At 205, an ECO automatic marking process may be used to draw the ECO CAD layer. The automatic marking process may insert design layers corresponding to ECO cells and other types of cells to populate the ECO CAD layer. The ECO CAD layers may each include a specific layer level of an IC build-up having multiple layers. The automatic marking process may be automatic and may be initiated by the designer after generating an initial design and performing a DRC pre-check. The automatic marking process may be performed in a series of stages and may further include a corner checking process. Figures 3 to 10 Elaborate on the automatic tagging process in more detail.

[0037] After the ECO CAD layers are drafted, they may be reviewed and revised by the designer at 207. In an embodiment, the review and revision process is performed manually. The ECO CAD layer design may be reviewed for consistency with a plurality of predefined layer designs. The designer may modify the layers created by the automatic marking process to ensure that the layers track one of the predefined layer types.

[0038] Next, the method may proceed to 209 and a decoupling capacitor layer corresponding to a decoupling capacitor (Decap) cell may be added to the design. In an embodiment, the decoupling capacitor cell may include an ECO decoupling capacitor cell that provides a decoupling capacitor function while also enabling the ECO in the event of a design change. For example, the need for a design change may change the power characteristics of the design. By strategically placing the ECO decoupling capacitor cells into the design, the ECO implemented to make the required design changes can use these ECO decoupling capacitor cells to achieve the desired characteristics. This can save time and cost associated with inserting new decoupling capacitor cells and ECOs, and can ensure that the design will not be less than optimal due to the lack of properly placed decoupling capacitor cells. In an embodiment, the ECO decoupling capacitor cell can be manually placed by an instruction or command from the designer. The design tool being used can receive this instruction or command from the designer and place the ECO decoupling capacitor cell in the corresponding position in the design.

[0039] After placing the ECO decoupling capacitor layer to define the ECO decoupling capacitor cell, another pre-check may be performed at 211 to ensure that the ECO CAD layer including the ECO decoupling capacitor layer does not trigger any DRC violations. If any rules are violated, the method may return to 207 and the ECO CAD layer may be revised again to eliminate any violations. If no rules are violated, the method may proceed to the next stage.

[0040] At 213, the ECO cells and ECO decoupling capacitor cells are populated into the design from the ECO CAD layer. In an embodiment, the populating process may be automated or performed by a software tool. For example, an electronic design automation (EDA) tool may populate the design with ECO cells and ECO decoupling capacitor cells at locations verified by the pre-check in 211. Once the cells are populated, the design may proceed to final check and processing before final tape-out.

[0041] In an embodiment, the method then proceeds to 215, where the schematic may be back-annotated to update the decoupling capacitor cell location. Back-annotation may enable the designer to keep the design in sync with the layout. By back-annotating the design with the decoupling capacitors, the designer may be able to implement design changes and ECOs more efficiently if desired.

[0042] After back annotation, the method may proceed to 217 where simulations are performed to confirm whether the leakage level is acceptable. If the leakage level is unacceptable, the designer may tie-off one or more of the decoupling capacitor cells. If the leakage is deemed acceptable, the method may proceed to the next stage.

[0043] At 219, dummy patterns may be inserted into the design. These patterns may enable the physical design to form a more uniform pattern and reduce the occurrence of sag and other anomalies that lead to poor performance. In an embodiment, the dummy patterns may be inserted by a dummy utility system.

[0044] Next, a final DRC check may be performed at 221. The final DRC check may consider all components of the design, including newly added dummy features. Including the final DRC check 221 may ensure that all spacing is appropriate and may mitigate the possibility of device failure after fabrication.

[0045] After the final DRC check 221, RC extraction and additional post-layout simulations may be performed at 223 to prepare the design for final sign-off. RC extraction may determine the parasitic resistance and capacitance in the design by analyzing the layout. The determined parasitic resistance and capacitance values ​​may then be used in post-layout simulations to accurately simulate the performance of devices fabricated according to the design.

[0046] After performing RC extraction and post-layout simulation, the method may proceed to tape-out at 225. In an embodiment, tape-out may include processing the design and fabricating an integrated circuit according to the design. For example, a designer may consider the results of a simulation and determine that the design is ready for fabrication, and then an integrated circuit may be fabricated according to the design. This is generally the final stage of integrated circuit design; however, in some cases, the design may need to be changed in the future. By incorporating ECO cells throughout the design, the analog ECO flow according to the embodiments described herein may facilitate efficient ECO in the event of future design changes.

[0047] Figure 31 is a flow chart and figures illustrating an automatic marking process according to an embodiment. In an embodiment, the automatic marking process can be performed in a series of stages. The first automatic marking stage can be used to surround the valid simulation cells of the design, and the second automatic marking stage can fill the empty areas of the design.

[0048] The automatic marking process may begin at 301 where an initial design is received. Figure 2 The process described, the initial design may be a completed valid design. In an embodiment, the valid design may include a plurality of valid cells. The valid cell may include a predetermined standard architecture selected to provide a specific function. In an embodiment, the valid cell may include an analog cell. These cells may be designed to include a specific internal arrangement of transistors, capacitors, or other components sufficient to provide their specified functions. For example, the analog cell may include an amplifier, a regulator, a comparator, a filter, or any other type of analog cell required for a specific design. The architecture of the analog cell may be stored in an analog cell library, and the architecture of the analog cell may be called from the analog cell library, thereby enabling the designer of the initial design to create complex and densely packaged integrated circuits with reduced time and effort.

[0049] After receiving the initial design, the first automatic marking process begins at 303. In this stage, the automatic marking process uses the first ECO cell 330 to surround the effective cell 320 of the design. The first ECO cell 330 may also include a predetermined standard architecture configured to provide a specific function. In an embodiment, the first ECO cell 330 may include the same cell type as the effective cell 320 surrounded by the first ECO cell 330. If the effective cell 320 does not pass, this can be conducive to efficient ECO, in which case one of the surrounding ECO cells can be routed into the design to replace the effective cell 320. However, unlike the effective cell 320, the first ECO cell 330 is not initially routed with other components of the design. This can keep the first ECO cell 330 as a placeholder, which can be integrated into the design during the ECO process to implement design changes.

[0050] After the ECO cells are inserted into the surrounding simulation cells, an enhanced automatic marking process may be applied at 305 to cover areas where some parts of the design have irregular shapes. For example, the second effective cell 322 may be very close to other cells of the design 335. The presence of other cells 335 inhibits the ability of the automatic marking process to completely insert the ECO cells into all empty spaces. Therefore, the enhanced automatic marking process may be used to insert the second ECO cell 324 into these areas so as to fill as much as possible without overwriting pre-existing design data or violating any design rules. In an embodiment, the second ECO cell 324 may include the same cell type as the second effective cell 322.

[0051] Once the analog cells of the design have been surrounded by the ECO cells of the first auto-marking process, a second auto-marking process may be started at 307. In an embodiment, the second auto-marking process may fill the "true empty" regions 350 of the design with the third ECO cells 332. For example, the design may incorporate multiple components including a diode 345, a bipolar junction transistor (BJT) 355, and other components 340. These components may include any type of cell or IC element as desired by the designer.

[0052] In the design, these locations of these components may form empty spaces in the design indicated by dashed lines 350. To maximize efficiency, the automatic marking process aims to fill as much of this empty space as possible with the third ECO cell 332. In an embodiment, the third ECO cell filled in the vacuum region may include a complementary metal oxide semiconductor (CMOS) analog cell. This maintains flexibility for future functions of the ECO cell in response to design changes.

[0053] After the second automatic marking process, at 309, the ECO cells may be overlaid with ECO decoupling capacitor cells 360. In an embodiment, this may be a manual process in which the designer overlays the ECO cells with ECO decoupling capacitor cells based on the desired functional and electrical characteristics. Next, at 310, a DRC pre-check may be performed on all ECO CAD layers (including the layers with manually entered ECO decoupling capacitor cells). This DRC pre-check may include the above referenced Figure 2 The DRC pre-check process 211 is discussed. If no rule violations are found, the cell can be inserted into the design at 311.

[0054] Figure 4 is a schematic diagram illustrating a first automatic labeling process 303 according to an embodiment. In an embodiment, the first automatic labeling process 303 may begin at 401 by an initial design including a plurality of active cells 420. The active cells 420 may include the active cells 420 as described above with reference to FIG. Figure 3 Next, at 403, the auto-marking process may create a first ECO box 422 extending in a first direction from all valid cells in the auto-marking area. These ECO boxes 422 represent areas into which ECO cells may be placed in a later stage of the design process.

[0055] For example, the first direction may be the x-direction and the first ECO frame 422 may extend from the top edge to the bottom edge of each active cell. The first ECO frame 422 in the first direction may extend in a series of steps, wherein each step includes an extension of a predefined minimum width. For example, 403 shows each active cell 420 having a first extension of minimum width. This extension continues until a conflict between adjacent extensions is detected.

[0056] When a conflict occurs, the auto-marker designates the location of the conflict as the boundary of each extension in the conflict, as shown in 405. For example, as shown in 405, two ECO boxes of adjacent valid cells may conflict, thereby forming a boundary 423. This boundary 423 depicts the outer edge of the ECO cells that may be formed in this area. This process can continue at 407, where, when the conflicting extension stops extending, the first ECO box 422 without conflict continues to extend to the boundary of the area undergoing the auto-marking process.

[0057] Next, under the condition that the boundaries of the ECO cell are set in the first direction, the process can be performed at 409, and a second ECO frame 424 can be created in the second direction. For example, the second direction can be the y direction. In an embodiment, the length of each second ECO frame 424 in the first direction or the x direction can be equal to the span of each active cell in this direction plus the span of the ECO frame 422 on each side of the active cell. Similar to the first ECO frame 422, the second ECO frame 424 can be extended in a series of steps, where each step includes an extension of a predefined minimum width.

[0058] As shown in 411, the second ECO box 424 can extend until adjacent ECO boxes touch each other. For example, the second ECO box 424 from the first valid cell may collide with the second ECO box 424 of the second valid cell at the boundary 425. This boundary can delineate the edge where the ECO cell can be placed in the second direction. Thus, the first automatic marking process can identify the empty area into which the ECO cell can be placed.

[0059] Figure 5 is a schematic diagram illustrating the resulting ECO cell region from the first automatic marking process according to an embodiment. For example, Figure 5 This may correspond to the design at 411 as described above. In this example, the first automatic marking process may be performed on 12 rectangular areas (in Figure 5 Each ECO cell region has an edge defined by the periphery of the auto-marked region or by the border between the extensions of adjacent active cells.

[0060] Figure 6 3 is a schematic flow chart illustrating an enhanced automatic marking process 305 according to an embodiment. The design may include an effective simulation cell 620 and a plurality of other cells 630. The presence of these other cells may make it more difficult to form the ECO box of the first automatic marking process. Therefore, an enhanced automatic marking process may be introduced to fill the irregular shape. At 601, the design may include the following steps: Figure 4 The first ECO frame 622 and the second ECO frame 624 are formed by the described process.

[0061] At 603, third ECO frames 641 may be created to delineate empty spaces into which ECO cells may be filled. In an embodiment, these ECO frames may be created to align with the top edge of the active cells 620 and may extend to the border of the auto-marking area. For example, the third extension 641 may first grow in the x-direction toward the perimeter of the auto-marking area before extending in the y-direction to fill the empty spaces.

[0062] At 605, the third ECO box may then extend in the second direction (y direction) until a conflict is detected. For example, as shown at 607, the third ECO box 641 may conflict with one of the other cells 630, causing the automatic marking process to set a boundary for this area. Another third ECO box 641 may reach the bottom boundary of the second ECO box 624. Therefore, the automatic marking process may set this as the boundary of this particular third ECO box. However, in other embodiments, the rules of the process may be set so that this third ECO box extends completely to the peripheral edge of the automatic marking area.

[0063] Next, at 609, a fourth ECO frame 643 may be created to fill as much of the remaining empty space as possible. The fourth ECO frame 643 may first grow in the y direction toward the periphery of the automatic marking area. As shown at 611, once the fourth ECO frame 643 extends the maximum distance in the y direction, the fourth ECO frame 643 may be extended in the x direction until it conflicts with the existing structure. By combining this enhanced automatic marking process, a high ECO cell coverage ratio may be obtained even for design areas with irregular shapes.

[0064] Figure 7 3 is a flow chart and figure illustrating a second automatic labeling process 307 according to an embodiment. The second automatic labeling process may be employed to fill the empty space with ECO cells. In an embodiment, the second automatic labeling process may begin at 701 by determining the existence of an empty region. Next, at 703, all vertices of the empty region may be determined and a sequence of vertices may be determined.

[0065] For example, an empty area 725 can be determined. To do this, the designer can use a software tool such as an EDA tool or a CAD tool to identify all areas within the design boundary that are not occupied by the CAD layer. From this empty area, it can then be determined that there are a total of eight vertices. The order of the vertices can then be determined so that the ECO cell can be created. In an embodiment, the sequence may first proceed in the x direction and then in the y direction. Thus, the first vertex will be the vertex with the lowest x position and y position. The next vertex will be any vertex at the same y position as the first vertex (if a first vertex exists) and at the next lowest x position. Once all vertices along this x extension are numbered, the vertices along the next y level can be assigned. This hierarchical structure can produce something like Figure 7 The vertex sequence for the empty region 725 is shown in .

[0066] Next, at 705, a box may be extended to cover the empty area starting from the first vertex. In an embodiment, the first box may extend from the first vertex in the x-direction, and the second box may extend from the first vertex in the y-direction. The areas of the two boxes are compared to each other, and the box with the largest area is selected to form an ECO extension from the first vertex. Next, at 707, this ECO extension may be converted to an ECO mark 735, which indicates that this area is designated for an ECO cell in the design.

[0067] The second automatic labeling process then proceeds to 709, where it is determined whether there are more vertices from which an ECO extension can be formed. If so, the second automatic labeling process proceeds to 710 and stages 705 to 709 are repeated until there is an ECO mark extending from each vertex. In an embodiment, although this process can be repeated for each vertex, a smaller number of ECO marks may be required to fully cover the empty area compared to the total number of vertices. For example, the empty area 725 may include eight vertices, but the area may be filled with only three ECO marks: an ECO mark 735 created by extending from the first vertex; an ECO mark 745 created by extending from the second vertex; and an ECO mark 755 created by extending from the third vertex. Once all vertices have been analyzed and there is no more space to be covered, the second automatic labeling process ends at 711. The second automatic labeling process can be used to fill empty areas of different complexity.

[0068] Figure 8 8 is a schematic diagram illustrating a second automatic marking process according to an embodiment. Here, the empty area 825 may include a more complex shape including a total of twenty vertices. The second automatic marking process may generate a fill design 835 including multiple ECO marks.

[0069] In an embodiment, the twenty vertex voids may be substantially filled with six ECO marks. Figure 8Each ECO mark is depicted and the vertex from which the ECO mark extends is shown in large font. Thus, the first ECO mark may extend from the first vertex, the second ECO mark may extend from the third vertex, the third ECO mark may extend from the fifth vertex, the fourth ECO mark may extend from the eighth vertex, the fifth ECO mark may extend from the thirteenth vertex, and the sixth ECO mark may extend from the fourteenth vertex.

[0070] Due to the complexity of the shape of the empty region 825, the entire region may not be filled by the ECO marking. This may be the result of a design rule indicating that an ECO cell may not fit in the unoccupied silver strip. However, the designer may attempt to resolve this issue during the manual review and revision phase when realizing that the silver strip is still unoccupied, as long as marking this area for an ECO cell does not violate any design rules.

[0071] Fig. 9 is a flow chart depicting stages of a corner check flow according to an embodiment. A corner check flow may be provided to ensure that the auto-marking process does not create an ECO CAD layer that would violate a design rule. In an embodiment, the corner check flow may begin at 901 by receiving an ECO box created during the auto-marking process. The corner check flow may have a predetermined priority sequence that determines which box to check first and how to proceed after the first box.

[0072] Next, at 903, a virtual frame extending in three directions from each corner of the designed first ECO frame may be created. Fig.10 The virtual box according to an embodiment is explained in more detail. In an embodiment, based on the predetermined priority sequence described above, a virtual box is first created around the first ECO box. After evaluating the virtual box extending from the first ECO box, the process may continue to the next ECO box in the sequence.

[0073] After the virtual boxes are created, the boxes may be checked at 905 to determine whether all layers within each virtual box belong to the same layer. For example, the virtual boxes are evaluated to see if the virtual box is completely within a specific ECO CAD layer. If all layers within each virtual box belong to the same ECO CAD layer, the flow may proceed to 909 and this process may be repeated for each ECO box.

[0074] However, if the check performed at 905 indicates that a conflict exists and one or more virtual boxes include layers belonging to multiple ECOCAD layers, then the ECO boxes can be shifted at 907 to avoid such an outcome. In an embodiment, such shifting can occur according to predetermined blocking conditions designed to avoid rule violations while preserving as much fill area as possible. After repeating this process for each ECO box at 909, the corner check process can end at 911.

[0075] Fig.10 1 is a schematic diagram illustrating various stages of a corner inspection process according to an embodiment. The corner inspection process may begin at 1001 with a design to be inspected. In an embodiment, the design may include a plurality of first valid cells 1012, a plurality of second valid cells 1014, and a plurality of ECO boxes 1010. For example, the automatic marking process may define four ECO boxes, and the four ECO boxes may be numbered one to four according to a predetermined priority sequence.

[0076] Next, at 1003, a virtual box extending from the first ECO box may be created. A virtual box 1016 extending from each corner of the first ECO box in the priority sequence may be created. In an embodiment, three virtual boxes may be created for each corner of each ECO box, each virtual box extending in a different direction. For example, a first virtual box may extend diagonally from each corner, a second virtual box may start at the corner and include an extension in the x-direction, and a third virtual box may start at the corner and include an extension in the y-direction.

[0077] Based on specific design considerations, these virtual frames may include predetermined sizes and extensions in the x-direction and the y-direction. For example, a first virtual frame with a diagonal extension may extend 0.336 microns in the x-direction and 0.336 microns in the y-direction. A second virtual frame with an x-direction extension may extend 0.336 microns in the x-direction and 0.26 microns in the y-direction. A third virtual frame with a y-direction extension may extend 0.26 microns in the x-direction and 0.336 microns in the y-direction. These dimensions may form the pattern of virtual frame 1016 shown in 1003.

[0078] After the virtual boxes are created, a check is performed to determine whether all layers within each virtual box belong to the same layer of the device. In an embodiment, this check may include comparing the boundary area of ​​each virtual box with the boundary area of ​​each valid cell and the boundary area of ​​each ECO box to determine whether there is a conflict. For example, consider the virtual boxes labeled 1016A, 1016B, and 1016C, as seen at 1003. Checking virtual box 1016A may indicate that all layers within 1016A belong to ECO box 2. Therefore, all layers within the virtual boxes belong to the same ECO CAD layer and no conflict is detected.

[0079] In contrast, an inspection of 1016B may indicate that a portion of the virtual box is within ECO box 2 and another portion is within ECO box 3. Therefore, a conflict between the boundaries of ECO box 2 and ECO box 3 may be detected, and the inspection may determine that the layers within virtual box 1016B do not belong to the same layer. Due to this conflict, the ECO boxes may be shifted to avoid any rule violations.

[0080] Similarly, an inspection of 1016C may indicate that part of the virtual box is within ECO box 3, but other parts are outside of this box. Here, this may also indicate that not all layers within virtual box 1016C belong to the same layer, and the ECO box may be shifted to avoid any rule violations.

[0081] The shifting of the ECO frame can be performed according to a predetermined blocking condition. In an embodiment, the amount by which the frame is shifted can be determined by the amount of overlap between the conflicting virtual frame and the ECO frame. For example, ECO frame 1 can be shifted a sufficient distance so that the virtual frame 1016 formed around ECO frame 1 does not intersect with ECO frames 2 to 4, and the virtual frame extending from ECO frame 2 to ECO frame 4 does not intersect with ECO frame 1.

[0082] Such a shift is depicted at 1005. As shown, the x-direction extension of ECO box 1 can be shifted so that it does not extend to intersect ECO box 1018 created around ECO box 2. Similarly, as shown at 1007, after the shift, the virtual box 1018 surrounding ECO box 3 and the virtual box 1020 surrounding ECO box 4 do not intersect ECO box 1. By shifting the ECO boxes in this manner, potential design rule violations caused by spacing violations between ECO box 1 and adjacent structures can be avoided. Therefore, the corner check process can be configured to reduce DRC errors. 1009 depicts the final size of each ECO box after employing the corner check process according to an embodiment.

[0083] Fig.11 1 is a flowchart and a diagram illustrating a DRC pre-checker according to an embodiment. Fig.11 The flowchart and schematic diagram shown in the above Figure 2 The same as described above. In an embodiment, the DRC pre-checker 1110 can be used at any stage before the cell is inserted into the design. Therefore, the designer can know whether the design rules may be violated at any time during the creation of the ECO cell. Compared with the DRC pre-check being used only as the last measure before inserting the ECO cell, this can alert the designer to the problem earlier, thereby saving time and forming a more efficient design process. The DRC pre-checker 1110 can check at least 187 specific design rules maintained by the pre-checker. By adopting this DRC pre-check process, the designer can ensure that failures related to various design rule violations can be avoided.

[0084] Fig.12A schematic diagram of the layout of the design after the simulation ECO process according to the embodiment is shown. The diagram illustrates the efficiency of the filling process of the simulation ECO process described herein. Layout 1201 illustrates the first layout before the simulation ECO process. Layout 1203 illustrates the same layout after the simulation ECO process according to the embodiment described herein, wherein the empty space is filled by the ECO cell. The percentage of the empty space filled by the ECO cell after the simulation ECO process can be considered as the ECO filling efficiency of the process. The ECO filling efficiency of the embodiment described herein can be greater than 70%. In some embodiments, the ECO filling efficiency can even be greater than 80%.

[0085] Table 1205 describes the efficiency of this process. In an embodiment, layout 1201 may include empty spaces that occupy 24.2% of the total area. After ECO fill, the ECO cells may fill 20.1% of the entire area, which indicates an ECO fill efficiency of 82.3%.

[0086] Layout 1207 depicts a second layout before the analog ECO process. Layout 1209 depicts the same layout after the analog ECO process is applied and the empty spaces are filled with ECO. In an embodiment, the layout may include diodes and BJTs. To avoid DRC violations caused by placing cells and / or metal layers too close to these components, larger spacing areas may surround these components.

[0087] Table 1211 describes the efficiency of this process. Layout 1207 may include empty spaces that occupy 81.9% of the total area. After ECO fill, the ECO cells may fill up to 64.5% of the total area, which indicates an ECO fill efficiency of 78.7%. By achieving a high level of ECO fill efficiency, the simulated ECO flow described herein may facilitate efficient ECO in response to design changes.

[0088] Fig.13A , Fig. 13B and Fig. 13C An exemplary system for implementing the methods described herein for designing an integrated circuit is depicted. For example, Fig.13AAn exemplary system 1300 is depicted that includes a stand-alone computer architecture in which a processing system 1302 (e.g., one or more computer processors located in a given computer or in multiple computers that are separate and distinct from each other) includes a computer-implemented electronic circuit design engine 1304 executed on the processing system 1302. The processing system 1302 may also access a computer-readable memory 1307 in addition to one or more data stores 1308. The one or more processors of the processing system 1302 may communicate with the computer-readable memory 1307, which may store instructions that, when executed, command the one or more processors to perform the operations of the methods described herein. The one or more data stores 1308 may include a cell library database 1310 and a circuit design database 1312. In an embodiment, the cell library database 1310 may include a simulation cell library. The processing system 1302 may be a distributed parallel computing environment that can be used to process very large data sets.

[0089] Fig. 13B A system 1320 is depicted that includes a client-server architecture. One or more user personal computers (PCs) 1322 access one or more servers 1324 running an electronic circuit design engine 1337 on a processing system 1327 via one or more networks 1328. The one or more servers 1324 may access a computer readable memory 1330 and one or more data stores 1332. The one or more data stores 1332 may include a cell library database 1334 and a circuit design database 1338.

[0090] Fig. 13C A separate computer architecture 1350 (eg Fig.13A1350 , which may be used to include and / or implement program instructions for system embodiments of the present disclosure. Bus 1352 may be used as an information highway to interconnect other illustrated components of the hardware. Processing system 1354, labeled as a central processing unit (CPU) (e.g., one or more computer processors at a given computer or multiple computers), may perform the computational and logical operations required to execute the program. Non-transitory processor-readable storage media (e.g., read only memory (ROM) 1358 and random access memory (RAM) 1359) may communicate with processing system 1354 and may include one or more programming instructions for implementing the method of designing an integrated circuit. Program instructions may be stored on a non-transitory computer-readable storage medium (e.g., a magnetic disk, an optical disk, a recordable memory device, a flash memory, or other physical storage medium).

[0091] exist Fig.13A , Fig. 13B and Fig. 13C 1307, 1330, 1358, 1359 or data storage 1308, 1332, 1383, 1384, 1388 may include one or more data structures for storing and associating various data used in the exemplary system for designing integrated circuits. For example, the data structure stored in any of the aforementioned locations can be used to store data from XML files, initial parameters, and / or data for other variables described herein. Disk controller 1390 interfaces one or more optional disk drives to system bus 1352. The disk drives may be an external or internal floppy disk drive such as 1383, an external or internal CD-ROM drive such as 1384, a CD-R, CD-RW, or DVD drive, or an external or internal hard drive 1385. In addition to physical devices, the system bus 1352 may communicate with cloud-based virtual devices. As previously described, the various disk drives and disk controllers are optional.

[0092] Each of the element manager, real-time data buffer, transport, file input processor, database index shared access memory loader, reference data buffer, and data manager may include a software application stored in one or more of the disk drives connected to the disk controller 1390, ROM 1358, and / or RAM 1359. The processor 1354 may access one or more components as needed. The display interface 1387 may enable information from the bus 1352 to be displayed on the display 1380 in an audio, graphical, or alphanumeric format. Communications with external devices may occur using various communication ports 1382 as appropriate. In addition to these computer-type components, the hardware may also include a data input device (e.g., keyboard 1379) or other input devices 1381, such as a microphone, remote control, pointer, mouse, and / or joystick.

[0093] Additionally, the methods and systems described herein may be implemented on many different types of processing devices by program code including program instructions executable by a device processing subsystem. The software program instructions may include source code, object code, machine code, or any other stored data that may be operated on to cause a processing system to perform the methods and operations described herein and may be provided in any suitable language, such as, for example, C, C++, Java, or any other suitable programming language. However, other implementations may also be used, such as firmware or even appropriately designed hardware configured to perform the methods and systems described herein.

[0094] The data of the systems and methods (e.g., associations, mappings, data inputs, data outputs, intermediate data results, final data results, etc.) may be stored in and implemented in one or more different types of computer-implemented data stores (e.g., different types of storage devices and programming constructs (e.g., RAM, ROM, flash memory, flat files, databases, programming data structures, programming variables, conditional (IF-THEN) (or similar type) statement constructs, etc.). It should be noted that the data structure describes the format for organizing and storing data in a database, program, memory, or other computer-readable medium used by a computer program.

[0095] The computer components, software modules, functions, data storage devices and data structures described herein may be connected to each other directly or indirectly so as to achieve the data flow required for their operation. It should also be noted that modules or processors include, but are not limited to, code units that implement software operations, and may be implemented as, for example, subroutine code units, or software function code units, or objects (such as in an object-oriented paradigm), or applets, or computer scripting languages, or another type of computer code. Software components and / or functions may be located on a single computer or distributed across multiple computers depending on the circumstances at hand.

[0096] Fig.14 is a flow chart illustrating a method for implementing a design change on an integrated circuit according to an embodiment. Figure 2 As described above, the method of designing an integrated circuit combined with the analog ECO flow can proceed to tape-out without implementing design changes through the ECO. However, after tape-out, new information may appear, indicating to the designer that the ECO implementing the design change may improve the performance of the device.

[0097] The method of implementing such a change may begin at 1401, where an input design may be received. The input design may include a plurality of active cells interconnected and organized to implement a desired function. In an embodiment, one or more active cells may include analog cells.

[0098] Next, at 1403, the ECO cells may be inserted into the design via a simulated ECO flow. The simulated ECO flow may be the same as described above for Figure 2 The simulated ECO flow 250 is illustrated. This process may include an automatic marking flow around valid cells using an ECO CAD layer (the ECO CAD layer may then be inserted into the design as an ECO cell).

[0099] After inserting the ECO cells, simulations may be run to determine the performance of the design and the simulations may be analyzed to ensure proper operation. If the analysis reveals any problems, the designer may change the design accordingly. If the design passes all tests, the method may proceed to tape-out at 1407. During tape-out, the design may be processed and manufactured. However, the method may continue to 1409 where it may be determined whether the ECO will improve the design.

[0100] ECOs may be needed for a variety of reasons, including as a response to errors or failures detected in a device fabricated according to the design, to implement new features in the design or to improve performance. If it is determined that the ECO will not improve the design, the process ends at 1415. Conversely, if it is determined at 1409 that the ECO may be beneficial, the ECO may be implemented at 1411.

[0101] Implementing an ECO may include using ECO cells of the design to achieve the change. These cells are not initially routed with any active components of the design. However, in order to implement the ECO, at least one ECO may be routed to connect to at least one active cell of the design. The presence of these ECO cells dispersed throughout the design enables such an ECO to be implemented without requiring a large amount of redesign. After implementing the ECO, the revised design is tape-out at 1413, and the method ends at 1415.

[0102] Methods, computer-readable media, and systems are described herein. In an exemplary design method for an integrated circuit, an initial design is received. An automatic marking process is performed, the automatic marking process including a first automatic marking process, an enhanced automatic marking process, and a second automatic marking process. The first automatic marking process uses a first CAD layer corresponding to a first plurality of ECO cells to surround a first plurality of valid cells of the design. The enhanced automatic marking process uses a second CAD layer corresponding to a second plurality of ECO cells to cover an irregular shape of the design. And the second automatic marking process uses a third CAD layer corresponding to a third plurality of ECO cells to fill an empty area of ​​the design. The method further includes using a first plurality of ECO cells, a second plurality of ECO cells, and a third plurality of ECO cells to fill the design.

[0103] In a related embodiment, the integrated circuit design method further includes: receiving multiple revisions to one of the first computer-aided design layer, the second computer-aided design layer and the third computer-aided design layer from a user; and modifying the initial design in response to the multiple revisions.

[0104] In a related embodiment, the integrated circuit design method further includes: receiving multiple instructions from the user for adding a decoupling capacitor layer corresponding to an engineering change order decoupling capacitor cell to the initial design; and modifying the initial design in response to the multiple instructions.

[0105] In a related embodiment, the method of designing an integrated circuit further includes: performing a design rule check pre-check on the initial design after modifying the initial design in response to the multiple instructions; and receiving a second set of revisions from the user in response to failing the design rule check pre-check.

[0106] In a related embodiment, the integrated circuit design method further includes: performing a design rule check pre-check on the initial design before performing the automatic marking process; and modifying the initial design in response to failure to pass the design rule check pre-check.

[0107] In a related embodiment, the first automatic marking process includes: generating a plurality of first engineering change command boxes extending in a first direction from each of the first plurality of valid cells; extending the plurality of first engineering change command boxes in the first direction until a conflict is detected; generating a plurality of second engineering change command boxes extending in a second direction from each of the plurality of valid cells; and extending the plurality of second engineering change command boxes in the second direction until a conflict is detected.

[0108] In a related embodiment, the second automatic marking process includes: (a) determining the existence of an empty area; (b) detecting all vertices of the empty area and determining the sequence of the vertices; (c) extending a first engineering change command box from a first vertex in a first direction, and extending a second engineering change command box from the first vertex in a second direction; (d) comparing an area of ​​the first engineering change command box with an area of ​​the second engineering change command box; (e) converting the box with a larger area between the first engineering change command box and the second engineering change command box into an engineering change command mark; and (f) repeating steps (c) to (e) for each of the vertices.

[0109] In a related embodiment, the integrated circuit design method further includes: after using the first plurality of engineering change order cells, the second plurality of engineering change order cells and the third plurality of engineering change order cells to fill the initial design, performing rule check extraction and post-layout simulation on the initial design.

[0110] In a related embodiment, the integrated circuit design method further includes: after using the first plurality of engineering change order cells, the second plurality of engineering change order cells and the third plurality of engineering change order cells to fill the initial design, performing rule check extraction and post-layout simulation on the initial design.

[0111] In a related embodiment, the first plurality of active cells are simulation cells.

[0112] In another example, a non-transitory computer-readable medium is provided, the non-transitory computer-readable medium being encoded with a memory storing instructions for making an integrated circuit. The instructions, when executed, cause the following operations to be performed: initializing an automatic marking process to populate an initial circuit design with a plurality of ECO cells, thereby forming an updated design. Inserting a dummy pattern into the updated design, the dummy pattern being configured to prevent dents during fabrication. Performing a final DRC check, RC extraction, and post-layout simulation. The executed instructions cause an integrated circuit to be fabricated based on the updated design.

[0113] In a related embodiment, the initial circuit design includes a plurality of simulation cells.

[0114] In a related embodiment, the automatic marking process surrounds the plurality of simulation cells with the plurality of engineering change order cells.

[0115] In a related embodiment, the operations further include initializing a corner check flow configured to reduce design rule checking errors.

[0116] In a related embodiment, the updated design includes an engineering change order fill efficiency greater than 70%.

[0117] In a related embodiment, the operations further include adding at least one engineering change order decoupling capacitor layer to the initial circuit design.

[0118] In a related embodiment, populating the initial circuit design further includes populating the at least one ECO decoupling capacitor layer to form at least one ECO decoupling capacitor cell in the updated design.

[0119] In a related embodiment, the updated design further includes a plurality of valid cells; and the plurality of engineering change order cells are not routed to connect to any of the plurality of valid cells in the updated design.

[0120] In an exemplary system for making design changes to an integrated circuit, an input design including a plurality of active cells is received. ECO cells are inserted into the input design via a simulated ECO flow to form an updated design. An integrated circuit is fabricated based on the updated design. ECOs are implemented by routing at least one ECO cell of the updated design to at least one active cell of the updated design, thereby creating a revised design. A revised integrated circuit is fabricated based on the revised design.

[0121] In a related embodiment, at least one active cell of the plurality of active cells comprises a simulation cell.

[0122] In a related embodiment, the simulating the engineering change order flow includes: performing an automatic marking process to surround the plurality of valid cells with a plurality of engineering change order cells, wherein the automatic marking process includes: generating a plurality of first engineering change order boxes extending in a first direction from each of the plurality of valid cells; extending the plurality of first engineering change order boxes in the first direction until a conflict is detected; generating a plurality of second engineering change order boxes extending in a second direction from each of the plurality of valid cells; and extending the plurality of second engineering change order boxes in the second direction until a conflict is detected.

[0123] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for designing an integrated circuit, characterized in that: include: Receive initial design; Implement an automated tagging process, including: performing a first automated marking process to surround a first plurality of valid cells of the initial design with a first computer-aided design layer corresponding to a first plurality of engineering change order cells; performing an enhanced automatic marking process to cover the irregular shape of the initial design with a second computer-aided design layer corresponding to a second plurality of engineering change order cells; and performing a second automatic marking process to fill empty areas of the initial design with a third computer-aided design layer corresponding to a third plurality of engineering change order cells; and The initial design is populated with the first plurality of engineering change order cells, the second plurality of engineering change order cells, and the third plurality of engineering change order cells.

2. The integrated circuit design method according to claim 1, characterized in that: Also includes: receiving a plurality of revisions to one of the first CAD layer, the second CAD layer, and the third CAD layer from a user; and The initial design is modified in response to the plurality of revisions.

3. The integrated circuit design method according to claim 2, characterized in that: Also includes: receiving a plurality of instructions from the user for adding a decoupling capacitor layer corresponding to an engineering change order decoupling capacitor cell to the initial design; as well as The initial design is modified in response to the plurality of instructions.

4. The integrated circuit design method according to claim 3, characterized in that: Also includes: After modifying the initial design in response to the plurality of instructions, performing a design rule check pre-check on the initial design; and A second set of revisions is received from the user in response to failing the design rule check pre-check.

5. The integrated circuit design method according to claim 1, characterized in that: Also includes: performing a design rule check pre-check on the initial design before performing the automatic marking process; as well as In response to failing the design rule check pre-check, the initial design is modified.

6. The integrated circuit design method according to claim 1, characterized in that: The first automatic marking process includes: generating a plurality of first engineering change order boxes extending in a first direction from each of the first plurality of valid cells; Extending the plurality of first engineering change command boxes in the first direction until a conflict is detected; generating a plurality of second engineering change order boxes extending in a second direction from each of the plurality of valid cells; and The plurality of second engineering change order frames are extended in the second direction until a conflict is detected.

7. The integrated circuit design method according to claim 1, characterized in that: The second automatic marking process comprises: (a) Determine the existence of a void area; (b) detecting all vertices of the empty region and determining the sequence of the vertices; (c) extending a first engineering change command frame from a first vertex in a first direction, and extending a second engineering change command frame from the first vertex in a second direction; (d) comparing the area of ​​the first engineering change order box with the area of ​​the second engineering change order box; (e) converting the box with a larger area between the first engineering change order box and the second engineering change order box into an engineering change order mark; and (f) Repeat steps (c) to (e) for each of the vertices.

8. The integrated circuit design method according to claim 1, characterized in that: Also includes: After the initial design is populated with the first plurality of engineering change order cells, the second plurality of engineering change order cells, and the third plurality of engineering change order cells, rule check extraction and post-layout simulation are performed on the initial design.

9. A non-transitory computer readable medium encoded with a memory storing instructions for fabricating an integrated circuit, characterized in that: When executed, the instructions cause operations including the following steps to be performed: Initializing an automatic marking process to populate the initial circuit design with a plurality of engineering change order cells to form an updated design; inserting a dummy pattern, wherein the dummy pattern is configured to prevent depression during fabrication; Conduct final design rule checks; Perform rule check extraction and post-layout simulation; as well as The integrated circuit is caused to be fabricated according to the updated design.

10. A computer-implemented system for making design changes to an integrated circuit, characterized in that: include: one or more processors; as well as A computer readable memory in communication with the one or more processors and encoded with instructions for instructing the one or more processors to perform steps comprising: receiving an input design including a plurality of valid cells; inserting an engineering change order cell into the input design to form an updated design via a simulated engineering change order flow; fabricating the integrated circuit based on the updated design; implementing an engineering change order by routing at least one engineering change order cell of the updated design to at least one valid cell of the updated design, thereby creating a revised design; as well as A revised integrated circuit is fabricated based on the revised design.

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