Chip design pattern verification method and system, intelligent terminal, and storage medium

Abstract

The present application discloses a verification method and system for chip design patterns, an intelligent terminal, and a storage medium. The method includes: identifying each figure of the chip design pattern; obtaining the minimum distance between the vertex of the figure and the points of other boundaries of the figure in the first direction to obtain each first self-spacing, obtaining the minimum distance between the vertex of each figure and other figures in the first direction to obtain each first adjacent spacing; obtaining the minimum distance between the vertex of each figure and the points on other boundaries of the figure in the second direction to obtain each second self-spacing, obtaining the minimum distance between the vertex of each figure and other figures in the second direction to obtain each second adjacent spacing; calculating each self-minimum size according to each first self-spacing and second self-spacing; calculating the minimum spacing between each figure and other figures according to each first adjacent spacing and second adjacent spacing; verifying each figure according to each self-minimum size and the minimum spacing between figures. The present application can quickly verify chip patterns.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a chip design pattern verification method and system, an intelligent terminal, and a storage medium. Background Art

[0002] Integrated circuits are the foundation of the electronic information industry. With the reduction of key dimensions of high-end chips and the increase in chip layout complexity, how to quickly verify chip design patterns to ensure the feasibility, reliability and yield of process processing has become one of the key links in the chip manufacturing process.

[0003] After the chip pattern designed according to the needs is exposed, developed, etched and other links, the photomask pattern is transferred to the wafer surface to obtain a chip that realizes a specific function. As the key size of the chip is reduced, the diffraction effect of the light source of the lithography machine is enhanced, and the ambiguity of the imaging pattern on the wafer surface becomes larger, and the mask pattern cannot be transferred correctly, causing distortion and affecting the chip function. Therefore, it is necessary to detect the chip pattern on the photomask after optical proximity correction (OPC) to ensure that the minimum distance between different patterns meets the preset threshold and ensure the resolution of the exposure pattern on the wafer surface.

[0004] Currently, for photomasks of complex chips, contour magnification, cross pattern extraction, polygon minimum distance acquisition and other links are used to check the minimum adjacent distance of each pattern. If there is no cross pattern, it means that the pattern meets the process requirements. Otherwise, it is judged whether the minimum distance between the cross pattern and the current pattern meets the requirements. The above process needs to traverse all patterns to check all patterns on the photomask. As the complexity of high-end integrated circuits increases, the key of patterns gradually decreases, and the relative positions between different patterns become more complicated. The traditional method of sequentially checking each chip pattern is very time-consuming and cannot meet engineering needs.

[0005] For non-Manhattan patterns (Manhattan: each side of the pattern is parallel to the coordinate axis), the pattern outline is difficult to define, and the pattern cross calculation based on the outline magnification is inaccurate, resulting in verification failure and affecting the yield. If the fast verification of the photomask pattern is achieved quickly and accurately to ensure the effectiveness of the mask pattern, it is crucial to improve the yield of high-end chips.

[0006] By grouping the edge tables that form the mask pattern (in different directions), calculating the minimum distance of the edges of different groups, the minimum distance of the pattern itself is obtained, and the current pattern is inspected for small sizes. By grouping the edge tables of different cross patterns, the minimum distance between different patterns is calculated, and the minimum distance between different patterns is inspected. The calculation complexity can be reduced by recording the mutual distance between different patterns.

[0007] As the key dimensions of high-end chips decrease and their complexity increases, the coupling information between different patterns on the mask has a greater impact on the exposure image. The verification method based on the adjacent information of the pattern has a high computational complexity and can no longer meet the needs of engineering applications. Especially with the development of advanced technologies such as inverse lithography technology (ILT), the mask pattern is more complex, and the calculation of the relative distance between the chip pattern size and the sizes of different patterns is more complex. The calculation method based on edge grouping is inefficient and cannot meet the needs of industrial applications. Summary of the invention

[0008] In view of this, the present application provides a chip design pattern verification method and system, a smart terminal, and a storage medium to improve the chip design pattern verification efficiency.

[0009] The present application provides a chip design pattern verification method, comprising the following steps:

[0010] Identify each graphic on the chip design pattern, each of the graphics includes one pattern or multiple connected patterns;

[0011] Obtain the minimum distance between the vertex of each of the graphics and points on other boundaries of the graphics in the first direction to obtain the first self-spacing of each of the graphics, and obtain the minimum distance between the vertex of each of the graphics and other graphics in the first direction to obtain the first adjacent spacing of each of the graphics;

[0012] Obtain the minimum distance between the vertex of each of the figures and points on other boundaries of the figure in the second direction to obtain the second self-spacing corresponding to each of the figures, and obtain the minimum distance between the vertex of each of the figures and other figures in the second direction to obtain the second adjacent spacing corresponding to each of the figures;

[0013] Calculate the minimum size of each of the graphics according to the first spacing between the graphics and the second spacing between the graphics;

[0014] Calculate the minimum inter-figure distance between each of the figures and other figures according to the first adjacent distance and the second adjacent distance of each of the figures;

[0015] Each graphic is checked according to its own minimum size and the minimum spacing between graphics.

[0016] Optionally, the method of obtaining the minimum distance between each vertex of the graphics and points on other boundaries of the graphics in the first direction to obtain the first self-spacing of each graphics, and obtaining the minimum distance between each vertex of the graphics and other graphics in the first direction to obtain the first adjacent spacing of each graphics includes: determining a first scan line that passes through each vertex of the graphics and extends along the first direction; identifying the first intersection of each of the first scan lines with each of the graphics; obtaining the first intra-graph spacing between each vertex and the first intersection on the corresponding first scan line and located on the graphics where the vertex is located; taking the first inter-graph spacing between each vertex and the first intersection on the corresponding first scan line and located on other graphics; determining the first self-spacing of each graphics according to the minimum value of the first intra-graph spacings corresponding to each graphics; determining the first adjacent spacing of each graphics according to the minimum value of the first inter-graph spacings corresponding to each graphics.

[0017] Optionally, the method of obtaining the minimum distance between each vertex of the graphics and points on other boundaries of the graphics in the second direction to obtain the second self-spacing corresponding to each graphics, and obtaining the minimum distance between each vertex of the graphics and other graphics in the second direction to obtain the second adjacent spacing corresponding to each graphics, includes: determining a second scan line that passes through each vertex of the graphics and extends along the second direction; identifying a second intersection point between each second scan line and each graphics; obtaining the second intra-graphic spacing between each vertex and a second intersection point on the corresponding second scan line and located on the graphics where the vertex is located; obtaining the second inter-graphic spacing between each vertex and a second intersection point on the corresponding second scan line and located on other graphics; determining the second self-spacing of each graphics according to the minimum value of the second intra-graphic spacings corresponding to each graphics; and determining the second adjacent spacing of each graphics according to the minimum value of the second inter-graphic spacings corresponding to each graphics.

[0018] Optionally, the calculating the minimum self-size of each of the graphics based on the first self-spacing and the second self-spacing of each of the graphics includes: using the first self-spacing of each of the graphics as the minimum distance within the graphics in the first direction; using the second self-spacing of each of the graphics as the minimum distance within the graphics in the second direction; substituting the minimum distance within the graphics in the first direction and the minimum distance within the graphics in the second direction into a preset distance transfer function to calculate the minimum self-size of each of the graphics; the distance transfer function is used to calculate the minimum distance between points that meet preset conditions.

[0019] Optionally, the method of calculating the minimum inter-figure spacing between each of the graphics and other graphics based on the first adjacent spacing and the second adjacent spacing of each of the graphics includes: using the first adjacent spacing of each of the graphics as the minimum inter-figure distance between each of the graphics and other graphics in the first direction; using the second adjacent spacing of each of the graphics as the minimum inter-figure distance between each of the graphics and other graphics in the second direction; substituting the minimum inter-figure distance between each of the graphics and other graphics in the first direction and the minimum inter-figure distance between each of the graphics and other graphics in the second direction into a preset distance transfer function to calculate the minimum inter-figure spacing between each of the graphics; the distance transfer function is used to calculate the minimum distance between points that meet preset conditions.

[0020] Optionally, the distance transfer function includes:

[0021] ,

[0022] ,

[0023] in, Indicates the minimum distance between points that meet the preset conditions. is the generalized coordinate position of each figure, Indicates the distance in the first direction between two points that meet the preset conditions. Indicates the distance in the second direction between two points that meet the preset conditions. Indicates taking The minimum value of Indicates taking The minimum value of Indicates taking The minimum value of .

[0024] Optionally, checking each graphic according to its own minimum size and the minimum spacing between graphics includes: if in a graphic, the own minimum size is greater than or equal to a first resolution threshold, and the minimum spacing between graphics is greater than or equal to the first resolution threshold, then determining that the corresponding graphic has passed the check.

[0025] The present application also provides a chip design pattern verification system, including:

[0026] An identification module, used to identify each graphic on the chip design pattern, each of which includes one pattern or multiple connected patterns;

[0027] A first acquisition module is used to acquire the minimum distance between the vertex of each of the graphics and other points on the boundary of the graphics in the first direction to obtain the first self-spacing of each of the graphics, and acquire the minimum distance between the vertex of each of the graphics and other graphics in the first direction to obtain the first adjacent spacing of each of the graphics;

[0028] A second acquisition module is used to obtain the minimum distance between the vertex of each of the graphics and points on other boundaries of the graphics in the second direction, to obtain the second self-spacing corresponding to each of the graphics, and to obtain the minimum distance between the vertex of each of the graphics and other graphics in the second direction, to obtain the second adjacent spacing corresponding to each of the graphics;

[0029] A first calculation module, used for calculating the minimum size of each of the graphics according to the first self-spacing and the second self-spacing of each of the graphics;

[0030] A second calculation module is used to calculate the minimum inter-figure distance between each of the figures and other figures according to the first adjacent distance and the second adjacent distance of each of the figures;

[0031] The verification module is used to verify each graphic according to its own minimum size and the minimum spacing between graphics.

[0032] The present application also provides an intelligent terminal, comprising: a memory and a processor, wherein the memory stores a verification program for a chip design pattern, and when the verification program for the chip design pattern is executed by the processor, the steps of any of the above chip design pattern verification methods are implemented.

[0033] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above chip design pattern verification methods are implemented.

[0034] The verification method and system, intelligent terminal, and storage medium of the above-mentioned chip design pattern of the present application obtain the first self-spacing, first adjacent spacing, second self-spacing, and second adjacent spacing corresponding to each graphic, calculate the minimum self-size of each graphic according to the first self-spacing and second self-spacing of each graphic, calculate the minimum inter-graphic spacing between each graphic and other graphics according to the first adjacent spacing and second adjacent spacing of each graphic, and then verify whether each graphic meets the exposure and other process requirements in the process of generating the corresponding chip according to the minimum self-size of each graphic and the minimum inter-graphic spacing, so as to realize rapid verification of the chip pattern.

[0035] Furthermore, by scanning each vertex with the first scan line and the second scan line, the first self-spacing, the first adjacent spacing, the second self-spacing and the second adjacent spacing corresponding to each figure can be quickly obtained; the minimum size of each figure and the minimum spacing between different images can be obtained through the distance transfer function; the linear search in two directions can be used to replace the double search, which can reduce the computational complexity and greatly improve the computational efficiency. It can be seen that the present application can improve the verification efficiency of chip patterns in many aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 It is a schematic flow chart of a chip design pattern verification method according to an embodiment of the present application;

[0038] Figure 2 It is a schematic diagram of a chip design pattern according to an embodiment of the present application;

[0039] Figure 3 is a graphical schematic diagram of an embodiment of the present application;

[0040] Figure 4 It is a schematic diagram of the structure of a chip design pattern verification system according to an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0042] In a first aspect, the present application provides a chip design pattern verification method, which can be executed by an intelligent terminal for verifying chip patterns in a chip design drawing. Figure 1 As shown, the chip design pattern verification method includes the following steps S110 to S160.

[0043] S110, identifying each graphic on the chip design pattern, each of the graphics including one pattern or a plurality of connected patterns.

[0044] The chip design pattern includes multiple patterns on the chip, such as reference Figure 2 As shown, each graphic may have an intersection (or overlapping area) between the various patterns, or may not have an intersection. Here, multiple patterns with intersections are merged into one graphic, that is, each graphic includes one pattern or multiple patterns that are connected (or have intersections). For example, Figure 3 As shown, if pattern A1, pattern A2 and pattern A3 are connected or have an intersection, then pattern A1, pattern A2 and pattern A3 are one figure.

[0045] S120, obtaining the minimum distance between each vertex of the figure and points on other boundaries of the figure (i.e., boundaries that do not pass through corresponding vertices) in the first direction to obtain a first self-spacing of each figure, and obtaining the minimum distance between each vertex of the figure and other figures in the first direction to obtain a first adjacent spacing of each figure.

[0046] S130, obtaining the minimum distance between each vertex of the figure and points on other boundaries of the figure in the second direction, obtaining the second self-spacing corresponding to each figure, and obtaining the minimum distance between each vertex of the figure and other figures in the second direction, obtaining the second adjacent spacing corresponding to each figure.

[0047] The vertices of the above-mentioned figure may include the intersections of the boundaries on the figure. The first direction may be the horizontal direction or the x-axis direction of the coordinate system where the figure is located, and the second direction may be the vertical direction or the y-axis direction of the coordinate system where the figure is located, so as to simplify the subsequent related calculation process.

[0048] Optionally, the above steps may construct a vertex sequence including vertices of each graph, so as to obtain each required distance parameter for each point in the vertex sequence.

[0049] Specifically, in this embodiment, a digital simulation model can be extracted according to the mask pattern to construct a two-dimensional vertex sequence as shown in the following formula (1) to represent each graphic:

[0050] (1)

[0051] ,

[0052] In the formula, Indicates the graphic number. represents the nth graph, represents the i-th vertex in the n-th graph, m represents the total number of vertices in the n-th graph, express The coordinates of .

[0053] S140, calculating the minimum size of each of the graphics according to the first self-spacing and the second self-spacing of each of the graphics.

[0054] S150, calculating the minimum inter-graphics distance between each of the graphics and other graphics according to the first adjacent spacing and the second adjacent spacing of each of the graphics.

[0055] S160, checking each graphic according to its own minimum size and the minimum distance between graphics.

[0056] The above-mentioned minimum size of the graphics and the minimum spacing between graphics can be used to determine whether the corresponding graphics meet the process requirements such as exposure for generating the corresponding chip. For example, if the minimum size of the graphics and the minimum spacing between graphics both meet the corresponding resolution threshold requirements, it means that the corresponding graphics can be exposed normally. Otherwise, it means that the corresponding graphics cannot be exposed (or the exposure step is prone to errors, etc.). The chip design pattern can be quickly verified based on the minimum size of the graphics and the minimum spacing between graphics.

[0057] The above-mentioned verification method of the chip design pattern identifies each figure on the chip design pattern, obtains the minimum distance between the vertex of each figure and the points on other boundaries of the figure in the first direction, thereby obtaining the first self-spacing of each figure, obtains the minimum distance between the vertex of each figure and other figures in the first direction, thereby obtaining the first adjacent spacing of each figure, obtains the minimum distance between the vertex of each figure and the points on other boundaries of the figure in the second direction, thereby obtaining the second self-spacing corresponding to each figure, and obtains the minimum distance between the vertex of each figure and other figures in the second direction, thereby obtaining the second adjacent spacing corresponding to each figure, thereby calculating the self-minimum size of each of the figures according to the first self-spacing and the second self-spacing of each figure, calculating the minimum spacing between each figure and other figures according to the first adjacent spacing and the second adjacent spacing of each figure, and then verifying whether each figure meets the process requirements such as exposure in the process of generating the corresponding chip according to the self-minimum size of each figure and the minimum spacing between figures, thereby realizing rapid verification of chip patterns.

[0058] In some embodiments, the method of obtaining the minimum distance between each vertex of the graphic and points on other boundaries of the graphic in the first direction to obtain the first self-spacing of each graphic, and obtaining the minimum distance between each vertex of the graphic and other graphics in the first direction to obtain the first adjacent spacing of each graphic, includes: determining a first scan line that passes through each vertex of the graphic and extends along the first direction; identifying the first intersection of each of the first scan lines with each graphic (or the boundary of the graphic); obtaining the first intra-graphic spacing between each vertex and the first intersection on the corresponding first scan line and located on the graphic where the vertex is located; obtaining the first inter-graphic spacing between each vertex and the first intersection on the corresponding first scan line and located on other graphics; determining the first self-spacing of each graphic according to the minimum value of the first intra-graphic spacings corresponding to each graphic; and determining the first adjacent spacing of each graphic according to the minimum value of the first inter-graphic spacings corresponding to each graphic.

[0059] If the first direction is the x-axis direction, the first scan line may also be referred to as a horizontal scan line. Each horizontal scan line may form a horizontal scan line set. The horizontal scan line set is recorded as ,in For all vertices, The number of coordinates, that is, the number of horizontal scan lines or strips, is the jth horizontal scan line, 1≤j≤N, and the horizontal scan lines in the horizontal scan line set are ordered, for example, The coordinates change from large to small or from small to large.

[0060] Compute horizontal scan line set The intersection of each horizontal scan line and each figure (or figure boundary) in the image is identified, that is, each first intersection is identified. If a vertex and the first intersection on the horizontal scan line passing through the vertex belong to the same figure, the distance between the first intersection and the corresponding vertex is calculated after pairing, and recorded as the current pattern's own horizontal spacing (i.e., the first intra-figure spacing); if a vertex and the first intersection on the horizontal scan line passing through the vertex do not belong to the same figure, it is recorded as the adjacent horizontal spacing of different patterns (i.e., the first inter-figure spacing); after all horizontal scan lines have completed scanning, for the same figure, the minimum value of the self-horizontal spacing is taken as the first self-spacing of the corresponding figure. , take the minimum value of the adjacent horizontal spacing as the first adjacent spacing of the corresponding figure .

[0061] In this embodiment, the first scanning line is used to scan each vertex, so as to quickly obtain the first self-distance and the first adjacent distance corresponding to each figure.

[0062] In some embodiments, the method of obtaining the minimum distance between the vertex of each of the graphics and points on other boundaries of the graphics in the second direction to obtain the second self-spacing corresponding to each of the graphics, and obtaining the minimum distance between the vertex of each of the graphics and other graphics in the second direction to obtain the second adjacent spacing corresponding to each of the graphics, includes: determining a second scan line that passes through the vertex of each of the graphics and extends along the second direction; identifying the second intersection of each second scan line with each of the graphics (or the graphics boundary); obtaining the second intra-graphic spacing between each vertex and the second intersection on the corresponding second scan line and located on the graphics where the vertex is located; obtaining the second inter-graphic spacing between each vertex and the second intersection on the corresponding second scan line and located on other graphics; determining the second self-spacing of each of the graphics according to the minimum value of the second intra-graphic spacings corresponding to each of the graphics; and determining the second adjacent spacing of each of the graphics according to the minimum value of the second inter-graphic spacings corresponding to each of the graphics.

[0063] If the second direction is the y-axis direction, the second scan line can also be called a vertical scan line. Each vertical scan line can form a vertical scan line set. The vertical scan line set is recorded as ,in For all vertices, The number of coordinates, that is, the number of vertical scan lines, is the kth vertical scan line, 1≤k≤M, and each vertical scan line in the vertical scan line set is ordered, for example, The coordinates change from large to small or from small to large.

[0064] Compute vertical scan line sets The intersection of each vertical scan line and each figure in the image is to identify each second intersection. If a vertex and the second intersection on the vertical scan line passing through the vertex belong to the same figure, the distance between the second intersection and the corresponding vertex is calculated after pairing, and recorded as the self-vertical spacing of the current pattern (i.e., the spacing within the second figure); if a vertex and the second intersection on the vertical scan line passing through the vertex do not belong to the same figure, it is recorded as the adjacent vertical spacing of different patterns (i.e., the spacing between the second figures); after all vertical scan lines have completed scanning, for the same figure, the minimum value of the self-vertical spacing is taken as the second self-spacing of the corresponding figure. , take the minimum value of the adjacent vertical spacing as the second adjacent spacing of the corresponding figure .

[0065] In this embodiment, the second scanning line is used to scan each vertex to quickly obtain the second self-spacing and the second adjacent spacing corresponding to each figure.

[0066] In some embodiments, the calculation of the minimum size of each graphic according to the first spacing and the second spacing of each graphic includes: using the first spacing of each graphic as the minimum distance within the graphic in the first direction; using the second spacing of each graphic as the minimum distance within the graphic in the second direction; substituting the minimum distance within the graphic in the first direction and the minimum distance within the graphic in the second direction into a preset distance transfer function to calculate the minimum size of each graphic; the distance transfer function is used to calculate the minimum distance between points that meet preset conditions. Optionally, the preset conditions may include conditions such as the points involved in the calculation are located on the boundaries of each graphic.

[0067] In some embodiments, the calculation of the minimum inter-figure spacing between each of the graphics and other graphics based on the first adjacent spacing and the second adjacent spacing of each of the graphics includes: using the first adjacent spacing of each of the graphics as the minimum inter-figure distance between each of the graphics and other graphics in the first direction; using the second adjacent spacing of each of the graphics as the minimum inter-figure distance between each of the graphics and other graphics in the second direction; substituting the minimum inter-figure distance between each of the graphics and other graphics in the first direction and the minimum inter-figure distance between each of the graphics and other graphics in the second direction into a preset distance transfer function to calculate the minimum inter-figure spacing of each of the graphics; the distance transfer function is used to calculate the minimum distance between points that meet preset conditions. Optionally, the preset conditions may include conditions such as the points involved in the calculation are located on the boundaries of each of the graphics.

[0068] Specifically, the distance transfer function includes:

[0069] (2)

[0070] ,

[0071] in, Indicates the minimum distance between points that meet the preset conditions. is the generalized coordinate position of each figure, for example Including the coordinate position set that represents each figure, for example It can represent the set of points on the boundaries of each figure. Indicates the distance in the first direction between two points that meet the preset conditions. Indicates the distance in the second direction between two points that meet the preset conditions. Indicates taking The minimum value of Indicates taking The minimum value of Indicates taking The minimum value of .

[0072] In some examples, the process of determining the distance transfer function includes:

[0073] Treat each graphic as a pixel and define the distance transfer function:

[0074] ,

[0075] ,

[0076] in, is the generalized distance between two pixels; is the generalized coordinate position of the spatial image distribution; decomposing the above formula (2) into horizontal and vertical directions, we get:

[0077] (3)

[0078] At this time, the calculation of the minimum distance is converted into a distribution calculation in two directions; that is, the calculation is performed separately The minimum and The minimum value in the direction; thereby reducing the computational complexity by one dimension to improve computational efficiency.

[0079] When calculating the minimum size of a graphic itself, the first self-spacing is used to directly replace the , directly replace the second self-spacing in formula (3) , get the current minimum spacing of the corresponding graphics (i.e., its own minimum size). When calculating the minimum spacing between graphs, the first adjacent spacing is used to directly replace the , directly replace the second adjacent spacing in formula (3) , get the current minimum spacing of the corresponding graphics (i.e. the minimum spacing between images).

[0080] This example replaces the double search with linear search in two directions, which can reduce the computational complexity and thus improve the verification efficiency.

[0081] In some embodiments, the checking of each graphic according to its own minimum size and the minimum spacing between graphics includes: if in a graphic, the own minimum size is greater than or equal to the first resolution threshold, and the minimum spacing between graphics is greater than or equal to the first resolution threshold, it means that the corresponding graphic can be exposed normally, and the corresponding graphic is judged to have passed the check; if in a graphic, the own minimum size is less than the first resolution threshold, or the minimum spacing between graphics is less than the first resolution threshold, it means that the corresponding graphic cannot be exposed or the related process is prone to errors, and the corresponding graphic is judged to have failed the check. Optionally, the above-mentioned first resolution threshold and second resolution threshold can be set according to factors such as the performance characteristics of the corresponding semiconductor process equipment.

[0082] The verification method of the above chip design pattern obtains the first self-spacing, first adjacent spacing, second self-spacing and second adjacent spacing corresponding to each graphic, calculates the self-minimum size of each graphic according to the first self-spacing and second self-spacing of each graphic, calculates the minimum spacing between each graphic and other graphics according to the first adjacent spacing and second adjacent spacing of each graphic, and then verifies whether each graphic meets the exposure and other process requirements in the process of generating the corresponding chip according to the self-minimum size of each graphic and the minimum spacing between graphics, so as to realize the rapid verification of the chip pattern. Among them, the first self-spacing, first adjacent spacing, second self-spacing and second adjacent spacing corresponding to each graphic can be quickly obtained by scanning each vertex with the first scanning line and the second scanning line; the self-minimum size of each graphic and the minimum spacing between different images can be obtained by the distance transfer function; the replacement of the double search by linear search in two directions can reduce the calculation complexity and greatly improve the calculation efficiency; it can be seen that the present application can improve the verification efficiency from many aspects.

[0083] The second aspect of the present application provides a chip design pattern verification system, which can be provided in an intelligent terminal for verifying chip design patterns. Figure 4 As shown, the verification system of the above chip design pattern includes:

[0084] The recognition module 110 is used to recognize each graphic on the chip design pattern, each of which includes one pattern or multiple connected patterns;

[0085] A first acquisition module 120 is used to acquire the minimum distance between the vertex of each of the graphics and other points on the boundary of the graphics in the first direction to obtain a first self-spacing of each of the graphics, and to acquire the minimum distance between the vertex of each of the graphics and other graphics in the first direction to obtain a first adjacent spacing of each of the graphics;

[0086] A second acquisition module 130 is used to acquire the minimum distance between the vertex of each of the graphics and points on other boundaries of the graphics in the second direction, to obtain a second self-spacing corresponding to each of the graphics, and to acquire the minimum distance between the vertex of each of the graphics and other graphics in the second direction, to obtain a second adjacent spacing corresponding to each of the graphics;

[0087] A first calculation module 140, configured to calculate the minimum size of each of the graphics according to the first spacing between the graphics and the second spacing between the graphics;

[0088] A second calculation module 150 is used to calculate the minimum inter-graph distance between each of the graphs and other graphs according to the first adjacent distance and the second adjacent distance of each of the graphs;

[0089] The verification module 160 is used to verify each graphic according to its own minimum size and the minimum distance between graphics.

[0090] For the specific definition of the verification system of the chip design pattern, please refer to the definition of the verification method of the chip design pattern in the above text, which will not be repeated here. Each module in the verification system of the above chip design pattern can be implemented in whole or in part by software, hardware and a combination thereof. The above modules can be embedded in or independent of the operation module in the relevant computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the operation module can call and execute the operations corresponding to the above units.

[0091] The present application also provides an intelligent terminal, which may include: a memory and a processor, wherein the memory stores a verification program for a chip design pattern, and when the verification program for the chip design pattern is executed by the processor, the steps of the verification method for the chip design pattern described in any of the above embodiments are implemented.

[0092] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the chip design pattern verification method described in any of the above embodiments are implemented.

[0093] Although the present application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on reading and understanding this specification and the accompanying drawings. The present application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components, the terms used to describe such components are intended to correspond to any component (unless otherwise indicated) that performs the specified function of the component (e.g., it is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementation of the present specification shown herein.

[0094] That is, the above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

[0095] In addition, in the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0096] In this application, the word "exemplary" is used to mean "used as an example, illustration or description". Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or more advantageous than other embodiments. In order to enable any technician in the field to implement and use the present application, the present application provides the above description. In the above description, various details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the present application obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.

Claims

1. A chip design pattern verification method, characterized in that: The chip design pattern verification method comprises: Identify each graphic on the chip design pattern, each of the graphics includes one pattern or multiple connected patterns; Obtain the minimum distance between the vertex of each of the graphics and points on other boundaries of the graphics in the first direction to obtain the first self-spacing of each of the graphics, and obtain the minimum distance between the vertex of each of the graphics and other graphics in the first direction to obtain the first adjacent spacing of each of the graphics; Obtain the minimum distance between the vertex of each of the figures and points on other boundaries of the figure in the second direction to obtain the second self-spacing corresponding to each of the figures, and obtain the minimum distance between the vertex of each of the figures and other figures in the second direction to obtain the second adjacent spacing corresponding to each of the figures; Calculate the minimum size of each of the graphics according to the first spacing between the graphics and the second spacing between the graphics; Calculate the minimum inter-figure distance between each of the figures and other figures according to the first adjacent distance and the second adjacent distance of each of the figures; Each graphic is checked according to its own minimum size and the minimum spacing between graphics.

2. The chip design pattern verification method according to claim 1, characterized in that: The step of obtaining the minimum distance between the vertex of each of the graphics and points on other boundaries of the graphics in the first direction to obtain the first self-spacing of each of the graphics, and obtaining the minimum distance between the vertex of each of the graphics and other graphics in the first direction to obtain the first adjacent spacing of each of the graphics includes: Determine a first scan line passing through each vertex of the graph and extending along a first direction; identifying a first intersection point between each of the first scanning lines and each of the graphics; Obtaining a first intra-graph distance between each of the vertices and a first intersection point corresponding to the first scan line and located on the graph where the vertex is located; Obtaining a first inter-graph distance between each of the vertices and a first intersection point corresponding to the first scan line and located on other graphs; Determine the first self-spacing of each of the graphics according to the minimum value of the first intra-graphic spacing corresponding to each of the graphics; The first adjacent spacing of each of the graphics is determined according to the minimum value of the first inter-graphic spacing corresponding to each of the graphics.

3. The chip design pattern verification method according to claim 1, characterized in that: The step of obtaining the minimum distance between the vertex of each of the graphics and points on other boundaries of the graphics in the second direction to obtain the second self-spacing corresponding to each of the graphics, and obtaining the minimum distance between the vertex of each of the graphics and other graphics in the second direction to obtain the second adjacent spacing corresponding to each of the graphics includes: Determine a second scan line passing through each vertex of the graph and extending along a second direction; identifying a second intersection point between each of the second scanning lines and each of the graphics; Obtain a second intra-graph distance between each of the vertices and a second intersection point corresponding to the second scan line and located on the graph where the vertex is located; Obtaining a second inter-graph distance between each of the vertices and a second intersection point corresponding to the second scan line and located on other graphs; Determine the second internal spacing of each of the graphics according to the minimum value of the second internal spacing corresponding to each of the graphics; The second adjacent spacing of each of the graphics is determined according to the minimum value of the second inter-graphic spacing corresponding to each of the graphics.

4. The chip design pattern verification method according to claim 1, characterized in that: The calculating the minimum size of each graphic according to the first self-spacing and the second self-spacing of each graphic comprises: Taking the first self-spacing of each of the graphics as the minimum distance within the graphics in the first direction; The second self-spacing of each of the graphics is used as the minimum distance within the graphics in the second direction; Substituting the minimum distance within the figure in the first direction and the minimum distance within the figure in the second direction of each of the graphics into a preset distance transfer function to calculate the minimum size of each of the graphics; the distance transfer function is used to calculate the minimum distance between points that meet preset conditions.

5. The chip design pattern verification method according to claim 1, characterized in that: The step of calculating the minimum inter-graph distance between each of the graphs and other graphs according to the first adjacent distance and the second adjacent distance of each of the graphs comprises: The first adjacent spacing of each of the graphics is used as the minimum distance between each of the graphics and other graphics in the first direction; The second adjacent spacing of each of the graphics is used as the minimum distance between each of the graphics and other graphics in the second direction; The minimum inter-image distance between each of the graphics and other graphics in the first direction and the minimum inter-image distance between each of the graphics and other graphics in the second direction are substituted into a preset distance transfer function to calculate the minimum inter-image spacing of each of the graphics; the distance transfer function is used to calculate the minimum distance between points that meet preset conditions.

6. The chip design pattern verification method according to claim 4 or 5, characterized in that: The distance transfer function includes: ， ， in, Indicates the minimum distance between points that meet the preset conditions. is the generalized coordinate position of each figure, Indicates the distance in the first direction between two points that meet the preset conditions. Indicates the distance in the second direction between two points that meet the preset conditions. Indicates taking The minimum value of Indicates taking The minimum value of Indicates taking The minimum value of .

7. The chip design pattern verification method according to claim 1, characterized in that: The step of checking each graphic according to its own minimum size and the minimum spacing between graphics comprises: If, in a graphic, the minimum size thereof is greater than or equal to the first resolution threshold, and the minimum spacing between graphics is greater than or equal to the first resolution threshold, then it is determined that the corresponding graphic has passed the verification.

8. A chip design pattern verification system, characterized in that: include: An identification module, used to identify each graphic on the chip design pattern, each of which includes one pattern or multiple connected patterns; A first acquisition module is used to acquire the minimum distance between the vertex of each of the graphics and other points on the boundary of the graphics in the first direction to obtain the first self-spacing of each of the graphics, and acquire the minimum distance between the vertex of each of the graphics and other graphics in the first direction to obtain the first adjacent spacing of each of the graphics; A second acquisition module is used to obtain the minimum distance between the vertex of each of the graphics and points on other boundaries of the graphics in the second direction, to obtain the second self-spacing corresponding to each of the graphics, and to obtain the minimum distance between the vertex of each of the graphics and other graphics in the second direction, to obtain the second adjacent spacing corresponding to each of the graphics; A first calculation module, used for calculating the minimum size of each of the graphics according to the first self-spacing and the second self-spacing of each of the graphics; A second calculation module is used to calculate the minimum inter-figure distance between each of the figures and other figures according to the first adjacent distance and the second adjacent distance of each of the figures; The verification module is used to verify each graphic according to its own minimum size and the minimum spacing between graphics.

9. An intelligent terminal, characterized in that: The intelligent terminal includes: a memory and a processor, wherein the memory stores a verification program for a chip design pattern, and when the verification program for the chip design pattern is executed by the processor, the steps of the verification method for the chip design pattern according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip design pattern verification method according to any one of claims 1 to 7 are implemented.

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