Semiconductor structure and forming method thereof
By forming capacitor openings on the semiconductor substrate and filling flush electrode layers, and forming conductive plugs in the dielectric layer, the problem of insufficient performance stability of deep trench capacitors is solved, and the stability and signal-to-noise of capacitors are achieved Improved.
Patent Information
- Application Number
- CN202310816091.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-04
- Publication Date
- 2025-01-07
AI Technical Summary
The performance stability of existing deep trench capacitors needs to be improved, especially when the capacitor is enlarged, the stability of the capacitor is difficult to ensure.
By forming capacitance openings on the semiconductor substrate, filling the electrode layers stacked along the normal direction of the capacitance opening, and forming conductive plugs in the dielectric layer to ensure that the contact surfaces of the electrode layers of each layer are flush and the depth of the conductive plugs are the same , avoid unevenness of the dielectric layer during planarization and reduce the formation of silicon bridges.
The number of electrode layers and capacitance is improved, and the performance stability of the semiconductor structure is improved, the formation of silicon bridges caused by different dielectric layers is avoided, and the signal-to-noise ratio and storage capacitance of the capacitor are enhanced.
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Figure CN119275203A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a semiconductor manufacturing process, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] The semiconductor integrated circuit industry has experienced exponential growth in recent years. Technological advances in integrated circuit (IC) materials and design have enabled each generation of integrated circuits to have smaller and more complex circuits than the previous generation. Deep trench capacitors (DTC) form three-dimensional vertical capacitors by etching deep trenches (DT) into the silicon substrate, allowing the capacitor to have larger capacitance while reducing its size. High-density deep trench capacitors can filter noise and improve the signal-to-noise ratio. There are two main ways to improve deep trench capacitors: one is to increase the depth of the deep trench capacitor, and the other is to increase the number of layers of the deep trench capacitor.
[0003] However, in the existing technology, the performance stability of deep trench capacitors needs to be improved. Summary of the invention
[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can increase the capacitance of the capacitor and improve the performance stability of the capacitor.
[0005] In order to solve the above technical problems, the technical solution of the present invention proposes a semiconductor structure and a method for forming the same, wherein the forming method comprises: providing a substrate; forming a capacitor opening in the substrate, the capacitor opening comprising a first region and a second region located on the first region, the size of the second region along a direction parallel to the substrate surface is larger than the size of the first region along a direction parallel to the substrate surface; forming a capacitor structure filling the capacitor opening in the capacitor opening, the capacitor structure comprising a plurality of electrode layers stacked along a normal direction of the capacitor opening, each of the electrode layers having a mutually flush contact surface; forming a dielectric layer on the capacitor structure and the substrate; forming a plurality of conductive plugs in the dielectric layer, each of the conductive plugs being respectively connected to each of the contact surfaces.
[0006] Optionally, the electrode layer further includes: an end region higher than the contact surface and exposing the contact surface; the height range of the end region is: less than or equal to
[0007] Optionally, the bottom dimension of the second zone is smaller than the top dimension, and the dimension of the first zone along the direction parallel to the substrate surface is twice the depth of the second zone; the sidewall morphology of the second zone includes: a stepped surface, a concave curved surface or a plane perpendicular to the substrate surface.
[0008] Optionally, when the sidewall morphology of the second region is a stepped surface, the number of step layers is the same as the number of electrode layers.
[0009] Optionally, the number of the electrode layers is greater than or equal to 4, and the thickness of each electrode layer is equal.
[0010] Optionally, when the sidewall morphology of the second region is a step surface, the method for forming the second region includes: forming a first mask layer on the surface of the substrate, the first mask layer having a mask opening that exposes a portion of the substrate surface; performing several etching processes on the substrate and the first mask layer until the second region of the capacitor opening is formed, each etching process includes: using the first mask layer as a mask to etch the exposed substrate surface; after etching the exposed substrate surface, performing side etching on the sidewall of the mask opening to expose a portion of the substrate surface, and the etching direction of the side etching is parallel to the substrate surface.
[0011] Optionally, the method for forming the capacitor structure includes: forming an initial capacitor structure in the capacitor opening, the initial capacitor structure including several layers of initial electrode layers stacked along the normal direction of the capacitor opening, the top surface of each layer of the initial electrode layers having an area to be etched; forming a second mask layer on the surface of the initial capacitor structure, the second mask layer exposing the surface of the area to be etched; etching the initial capacitor structure using the second mask layer as a mask to form the capacitor structure, the surface of the area to be etched after being etched forms the contact surface.
[0012] Optionally, it also includes: a barrier layer located on the surface of the capacitor structure and the surface of the substrate, wherein the barrier layer exposes the surface of the contact surface.
[0013] Optionally, it further includes: an electric contact layer located on the surface of the contact surface; the conductive plug is located on the surface of the electric contact layer; and the material of the electric contact layer includes metal silicide.
[0014] Optionally, after forming the conductive plug, the method further includes: forming a metal layer on the dielectric layer, wherein the conductive plug connects the capacitor structure and the metal layer.
[0015] Optionally, the method for forming the dielectric layer includes: forming an initial dielectric layer on the capacitor structure and the substrate; and performing a planarization process on the initial dielectric layer until a dielectric layer with a flat surface is obtained.
[0016] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, comprising: a substrate; a capacitor opening located in the substrate, the capacitor opening comprising a first region and a second region located on the first region, the size of the second region along a direction parallel to the substrate surface is larger than the size of the first region along a direction parallel to the substrate surface; a capacitor structure located in the capacitor opening, the capacitor structure comprising a plurality of electrode layers stacked along a normal direction of the capacitor opening, each of the electrode layers having a mutually flush contact surface; a dielectric layer located on the capacitor structure and the substrate; a plurality of conductive plugs located in the dielectric layer, each of the conductive plugs being respectively connected to each of the contact surfaces.
[0017] Optionally, a dimension of the first region of the capacitor opening along a direction parallel to the substrate surface is twice a depth of the second region of the capacitor opening.
[0018] Optionally, it also includes: a linear oxide layer located between the capacitor opening and the capacitor structure.
[0019] Optionally, the capacitor structure further includes: a capacitor dielectric layer located between adjacent electrode layers; the electrode layer material includes polysilicon; and the capacitor dielectric layer material includes silicon nitride.
[0020] Optionally, the thickness of the electrode layer is greater than
[0021] Optionally, the electrode layer further includes: an end region higher than the contact surface and exposing the contact surface; the height range of the end region is: less than or equal to
[0022] Optionally, it also includes: side walls located at the side walls of the end regions of each electrode layer.
[0023] Optionally, a bottom dimension of the second region is smaller than a top dimension, and a sidewall morphology of the second region includes: a stepped surface, a concave curved surface, or a plane perpendicular to the substrate surface.
[0024] Optionally, it also includes: a barrier layer located on the surface of the capacitor structure and the surface of the substrate, and the barrier layer exposes the surface of the contact surface.
[0025] Optionally, it further includes: an electric contact layer located on the surface of each of the contact surfaces; the conductive plug is located on the surface of the electric contact layer; and the material of the electric contact layer includes metal silicide.
[0026] Optionally, it also includes: a metal layer located on the dielectric layer and connected to the conductive plug.
[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0028] In the semiconductor structure provided by the technical solution of the present invention, each electrode layer has a mutually flush contact surface, so that while the number of electrode layers is increased to increase the capacitance, the depth of the conductive plugs connecting the electrode layers is the same and maintained within a preset range, thereby improving the uniformity of etching and being conducive to increasing the number of electrode layers and increasing capacitance.
[0029] Furthermore, the semiconductor structure further includes: a metal layer located on the dielectric layer and connected to the conductive plug. Since the contact surfaces of the electrode layers of each layer are flush and the height of each end region is small, when the dielectric layer is formed between the capacitor structure and the substrate surface, the height difference of the contact surfaces of the electrode layers of each layer is too large, resulting in different removal rates of the initial dielectric layer at different locations during the flattening process of the initial dielectric layer, which causes different heights of the dielectric layer at different locations. This prevents the formation of a silicon bridge between the contact surface of the electrode layer and the metal layer, thereby improving the performance stability of the semiconductor structure.
[0030] In the method for forming a semiconductor structure provided by the technical solution of the present invention, each electrode layer has a mutually flush contact surface, so that while the number of electrode layers is increased to increase the capacitance, the depth of the conductive plugs connecting the electrode layers is the same and maintained within a preset range, thereby improving the uniformity of etching and being conducive to increasing the number of electrode layers and increasing capacitance.
[0031] Furthermore, after forming the conductive plug, it also includes: forming a metal layer on the dielectric layer, and the conductive plug connects the capacitor structure and the metal layer. Since the contact surfaces of the electrode layers of each layer are flush, and the height of each end area is small, when the dielectric layer is formed between the capacitor structure and the substrate surface, the height difference of the contact surfaces of the electrode layers is too large, resulting in different removal rates at different locations of the initial dielectric layer during the flattening process of the initial dielectric layer, causing different heights of the dielectric layer at different locations. This prevents the formation of a silicon bridge between the contact surface of the electrode layer and the metal layer, thereby improving the performance stability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 It is a schematic diagram of a cross-sectional structure of a semiconductor structure;
[0033] Figures 2 to 15 It is a structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION
[0034] As described in the background art, in the existing process, the performance stability of deep trench capacitors needs to be improved.
[0035] Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor structure.
[0036] Please refer to Figure 1, providing a substrate 100; forming a capacitor opening (not marked) in the substrate 100; forming a capacitor structure 101 filling the capacitor opening in the capacitor opening (not marked), the capacitor structure 101 including a plurality of electrode layers 102 stacked along a normal direction of the capacitor opening; forming a dielectric layer 103 on the surfaces of the capacitor structure 101 and the substrate 100; forming a plurality of through holes (not marked) in the dielectric layer 103, the through holes (not marked) exposing a portion of the surface of each electrode layer 102; forming a conductive layer 104 in the through holes (not marked); forming a metal layer 105 on the dielectric layer 103, the conductive layer 104 connecting the metal layer 105 and the capacitor structure 101.
[0037] The thickness of each electrode layer 102 is greater than
[0038] The method for forming the dielectric layer 103 includes: forming an initial dielectric layer on the surface of the capacitor structure 101 and the substrate 100 , and performing a planarization process on the initial dielectric layer to form the dielectric layer 103 .
[0039] On the one hand, the capacitor structure 101 includes a plurality of electrode layers 102, each of which has a thickness greater than Therefore, when the number of electrode layers 102 is increased to increase the capacitance, the distance between the top surface of the capacitor structure 101 and the substrate 100 is too large, exceeding the etching limit of the through hole (not marked); on the other hand, in the process of planarizing the initial dielectric layer, since the upper surface heights of the electrode layers 102 of the capacitor structure 101 are different, the thickness of the initial dielectric layer at each position on the upper surface of the capacitor structure 101 is different, and the consumption rate of each position of the initial dielectric layer during the planarization process to form the dielectric layer 103 is different, a silicon bridge will be generated between the capacitor structure 101 and the metal layer 105, thereby reducing the performance stability of the semiconductor structure.
[0040] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, which increases the capacitance of the capacitor and improves the performance stability of the capacitor.
[0041] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0042] Figures 2 to 15 It is a structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention.
[0043] Please refer to Figure 2 , providing a substrate 200.
[0044] In this embodiment, the material of the substrate 200 includes silicon.
[0045] In other embodiments, the material of the substrate includes: silicon carbide, silicon germanium, gallium arsenide, silicon on insulator (SOI), or germanium on insulator (GOI).
[0046] Please refer to Figure 3 A first capacitor opening 201 is formed in the substrate 200, wherein the first capacitor opening 201 includes a first region and a second region located on the first region, wherein a size of the second region along a direction parallel to the surface of the substrate 200 is larger than a size of the first region along a direction parallel to the surface of the substrate 200.
[0047] Specifically, in this embodiment, the depth of the second zone is
[0048] The bottom dimension of the second region is smaller than the top dimension, and the dimension of the first region in a direction parallel to the surface of the substrate 200 is twice the depth of the second region; the sidewall morphology of the second region includes: a step surface, a concave curved surface or a plane perpendicular to the surface of the substrate. The effect of the dimension of the second region in a direction parallel to the surface of the substrate 200 being larger than the dimension of the first region in a direction parallel to the surface of the substrate 200 is that: when the capacitor structure 210 is subsequently formed in the first capacitor opening 201, the dimension of the second region in a direction parallel to the surface of the substrate 200 is larger, which can increase the surface area of the capacitor structure 210 and increase the storage capacitance of the capacitor structure 210 while reducing the occupied area of the capacitor structure 210 as much as possible.
[0049] The dimension of the first region along the direction parallel to the surface of the substrate 200 is twice the depth of the second region, so as to ensure that the capacitor structure 210 formed subsequently fills the entire first capacitor opening 201 .
[0050] Specifically, in this embodiment, please refer to Figure 3 The sidewall morphology of the second region of the first capacitor opening 201 is a stepped surface.
[0051] The advantage of the sidewall morphology of the second area of the first capacitor opening 201 being a stepped surface is that when the sidewall morphology of the second area of the first capacitor opening 201 is a stepped surface, the surface area of each electrode layer 212 of the capacitor structure 210 can be increased to increase the storage capacitance of the capacitor structure 210 while minimizing the occupied area of the capacitor structure 210.
[0052] Specifically, in this embodiment, when the sidewall morphology of the second region is a step surface, the method for forming the second region includes: forming a first mask layer (not marked) on the surface of the substrate 200, the first mask layer (not marked) having a mask opening that exposes a portion of the surface of the substrate 200; performing several etching processes on the substrate 200 and the first mask layer (not marked) until the second region of the first capacitor opening 201 is formed, each etching process includes: using the first mask layer (not marked) as a mask to etch the exposed surface of the substrate 200; after etching the exposed surface of the substrate 200, performing side etching on the sidewall of the mask opening to expose a portion of the surface of the substrate 200, and the etching direction of the side etching is parallel to the surface of the substrate 200.
[0053] The etching process of the etching treatment includes: dry etching.
[0054] In another embodiment, please refer to Figure 4 The sidewall morphology of the second region of the second capacitor opening 202 is perpendicular to the plane of the substrate 200 surface.
[0055] When the sidewall morphology of the second region of the second capacitor opening 202 is a plane perpendicular to the surface of the substrate 200, the method for forming the second region includes: forming a third mask layer (not labeled) on the surface of the substrate 200, the third mask layer (not labeled) exposing a portion of the surface of the substrate 200; using the third mask layer (not labeled) as a mask, etching the substrate 200 to form the second region of the second capacitor opening 202.
[0056] The etching process of the etching treatment includes: dry etching.
[0057] In another embodiment, please refer to Figure 5 The sidewall morphology of the second region of the third capacitor opening 203 is a concave curved surface.
[0058] When the sidewall morphology of the second zone of the third capacitor opening 203 is a concave curved surface, the method for forming the second zone includes: forming a fourth mask layer (not labeled) on the surface of the substrate 200, the fourth mask layer (not labeled) having a mask opening exposing a portion of the surface of the substrate 200; etching the exposed surface of the substrate 200 using the fourth mask layer (not labeled) as a mask; after etching the exposed surface of the substrate 200, laterally etching the sidewall of the mask opening to expose a portion of the surface of the substrate 200 to form the second zone of the third capacitor opening 203.
[0059] The etching process of the etching treatment includes: dry etching.
[0060] Specifically, in this embodiment, when forming the first capacitor opening 201 (such as Figure 3After the first capacitor opening 201 (as shown) Figure 3 A linear oxide layer (not marked) is formed on the surface.
[0061] The linear oxide layer (not labeled) serves to isolate the substrate 200 from the capacitor structure 210 formed subsequently, thereby preventing the substrate 200 from directly contacting the capacitor structure 210 formed subsequently.
[0062] In this embodiment, in the first capacitor opening 201 (such as Figure 3 After a linear oxide layer (not labeled) is formed on the surface of the first capacitor opening 201 (as shown), Figure 3 The capacitor structure 210 is formed to fill the first capacitor opening 201. The method for forming the capacitor structure 210 is shown in Figures 6 to 9 .
[0063] Please Figure 3 Based on reference Figure 6 , in the first capacitor opening 201 (such as Figure 3 An initial first capacitor structure 204 is formed in the first capacitor opening 201, and the initial first capacitor structure 204 includes a plurality of initial first electrode layers 205 stacked along the normal direction of the first capacitor opening 201.
[0064] The initial first capacitor structure 204 further includes: an initial first capacitor dielectric layer (not labeled) located between adjacent initial first electrode layers 205 .
[0065] The initial first capacitor structure 204 is formed by deposition. Specifically, in this embodiment, the deposition method is furnace tube high temperature deposition.
[0066] In this embodiment, the material of the initial first electrode layer 205 includes polysilicon.
[0067] The material of the initial first capacitor dielectric layer (not labeled) is a non-conductive insulator. Specifically, in this embodiment, the material of the initial first capacitor dielectric layer (not labeled) includes silicon nitride.
[0068] Specifically, in this embodiment, the number of layers of the initial first electrode layer 205 is greater than or equal to 4 layers.
[0069] When the number of the initial first electrode layer 205 is large, the volume of the initial first capacitor structure 204 is large, which can improve the storage capacitance of the subsequently formed capacitor structure 210, improve the signal-to-noise ratio of the capacitor structure 210, and improve the performance of the capacitor structure 210.
[0070] The thickness of the initial first electrode layer 205 is greater than
[0071] Specifically, in this embodiment, the thickness of each layer of the initial first electrode layer 205 is equal.
[0072] In other embodiments, the thicknesses of the initial first electrode layers may be unequal.
[0073] Please refer to Figure 7 , for the initial first capacitor structure 204 (such as Figure 6 The surface of the first capacitor 201 is planarized to form an initial second capacitor structure 206, wherein the initial second capacitor structure 206 includes a plurality of initial second electrode layers 207 stacked along the normal direction of the first capacitor opening 201, and the top surface of each initial second electrode layer 207 has an area 208 to be etched.
[0074] The planarization treatment method includes: mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization treatment method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing method, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the shortcomings of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nano level.
[0075] The purpose of flattening the surface of the initial first capacitor structure 204 is to obtain an initial second capacitor structure 206 with a smaller surface height difference, which is beneficial to improving the etching uniformity in the process of etching the initial second capacitor structure 206 to obtain the capacitor structure 210 .
[0076] The initial second capacitor structure 206 further includes an initial second capacitor dielectric layer (not labeled) located between adjacent initial second electrode layers 207 .
[0077] In this embodiment, the material of the initial second electrode layer 207 includes polysilicon.
[0078] The material of the initial second capacitor dielectric layer (not labeled) is a non-conductive insulator. Specifically, in this embodiment, the material of the initial second capacitor dielectric layer (not labeled) includes silicon nitride.
[0079] Specifically, in this embodiment, the number of layers of the initial second electrode layer 207 is greater than or equal to 4 layers.
[0080] When the number of the initial second electrode layer 207 is large, the volume of the initial second capacitor structure 206 is large, which can improve the storage capacitance of the subsequently formed capacitor structure 210 , improve the signal-to-noise ratio of the capacitor structure 210 , and improve the performance of the capacitor structure 210 .
[0081] The thickness of each initial second electrode layer 207 is greater than
[0082] Specifically, in this embodiment, the thickness of each layer of the initial second electrode layer 207 is equal.
[0083] In other embodiments, the thicknesses of the initial second electrode layers may be unequal.
[0084] Please refer to Figure 8 A second mask layer 209 is formed on the surface of the initial second capacitor structure 206 , and the second mask layer 209 exposes the surface of the to-be-etched area 208 .
[0085] The method for forming the second mask layer 209 includes: forming a second mask material layer (unlabeled) on the surface of the initial second capacitor structure 206; forming a photoresist layer (unlabeled) on the surface of the second mask material layer (unlabeled); using the photoresist layer (unlabeled) as a mask, etching the second mask material layer (unlabeled) to form the second mask layer 209.
[0086] Please refer to Fig. 9 , with the second mask layer 209 (such as Figure 8 ) is a mask, and the initial second capacitor structure 206 (as shown) is etched Figure 8 As shown), the capacitor structure 210 is formed, and the capacitor structure 210 includes a plurality of electrode layers 212 stacked along the normal direction of the first capacitor opening 201, each electrode layer 212 has a mutually flush contact surface 211, and the electrode layer 212 also includes: an end region 213 higher than the contact surface 211 and exposing the contact surface 211.
[0087] The etching process includes: dry etching. Dry etching is an etching technology with strong anisotropy and high selectivity. Dry etching methods include: physical etching, chemical etching, and physical and chemical etching.
[0088] The initial second capacitor structure 206 is etched (eg Figure 8The function of the method is to obtain a capacitor structure 210 in which the contact surfaces 211 of each electrode layer 212 are flush with each other. On the one hand, a dielectric layer 217 is subsequently formed on the surface of the capacitor structure 210, and a conductive plug 218 is formed in the dielectric layer 217, so that the depth of the conductive plug 218 connecting each electrode layer 212 is the same and maintained within a preset range, thereby improving the uniformity of etching; on the other hand, since the contact surfaces 211 of each electrode layer 212 are flush, when the dielectric layer 217 is formed on the surface of the capacitor structure 210 and the substrate 200, a silicon bridge will not be formed between the contact surface 211 of the electrode layer 212 and the metal layer 219 due to the different heights of the surface of the dielectric layer 217, thereby improving the performance stability of the semiconductor structure.
[0089] The capacitor structure 210 includes a plurality of electrode layers 212 stacked along a normal direction of the first capacitor opening 201 , and each of the electrode layers 212 has a contact surface 211 flush with each other.
[0090] The contact surfaces 211 of the electrode layers 212 are flush. On the one hand, while the number of electrode layers 212 is increased to increase the capacitance, the depths of the conductive plugs 218 connecting the electrode layers 212 are the same and maintained within a preset range, thereby reducing the difficulty of etching and facilitating increasing the number of electrode layers 212 and increasing the capacitance. On the other hand, the contact surfaces 211 of the electrode layers 212 are flush, so that when the dielectric layer 217 is formed on the surface of the capacitor structure 210 and the substrate 200, a silicon bridge will not be formed between the contact surface 211 of the electrode layer 212 and the subsequently formed metal layer 219 due to the different surface heights of the dielectric layer 217, thereby improving the performance stability of the capacitor.
[0091] The electrode layer 212 further includes an end region 213 that is higher than the contact surface 211 and exposes the contact surface 211; the height range of the end region 213 is less than or equal to:
[0092] In this embodiment, the material of the electrode layer 212 includes polysilicon.
[0093] The capacitor structure 210 further includes a capacitor dielectric layer (not labeled) located between adjacent electrode layers 212 .
[0094] The material of the capacitor dielectric layer (not marked) is a non-conductive insulator. Specifically, in this embodiment, the material of the capacitor dielectric layer (not marked) includes silicon nitride.
[0095] Specifically, in this embodiment, the number of the electrode layer 212 is greater than or equal to 4 layers, and the thickness of the material of each layer of the electrode layer 212 is greater than
[0096] When the thickness of the electrode layer 212 is too small, the resistance will be too large, thereby reducing the performance of the semiconductor device.
[0097] When the number of the electrode layers 212 is large, the volume of the capacitor structure 210 is large, which can improve the signal-to-noise ratio of the capacitor structure 210 and enhance the performance of the capacitor structure 210. In this embodiment, the volume range of the capacitor structure 210 is: 400nf / mm 2 ~500nf / mm 2 .
[0098] Specifically, in this embodiment, the thickness of each electrode layer 212 is equal.
[0099] In other embodiments, the thicknesses of the electrode layers may be unequal.
[0100] Specifically, in this embodiment, when the sidewall morphology of the second region is a stepped surface, the number of step layers is the same as the number of layers of the electrode layer 212 .
[0101] Please refer to Fig.10 A sidewall 214 is formed on the sidewall surface of the end region 213 of each electrode layer 212 .
[0102] The function of the sidewall spacer 214 is to serve as a protection layer for the gate when the conductive plug 218 is subsequently etched to form the conductive plug 218 .
[0103] The material of the sidewall spacer 214 includes silicon oxide or silicon nitride.
[0104] In this embodiment, the thickness of the side wall 214 is
[0105] Please refer to Fig.11 An electrical contact layer 215 is formed on the surface of the capacitor structure 210 and the surface of the substrate 200 .
[0106] The material of the electrical contact layer 215 includes metal silicide, and the conductivity of metal silicide is between that of metal and silicon.
[0107] In this embodiment, the thickness of the electrical contact layer 215 is:
[0108] The function of the electrical contact layer 215 is to achieve the connection between the capacitor structure 210 and the subsequently formed conductive plug 218 . The subsequently formed conductive plug 218 is located on the surface of the electrical contact layer 215 .
[0109] Please refer to Fig.12 After the electrical contact layer 215 is formed, a barrier layer 216 is formed on the surface of the electrical contact layer 215 .
[0110] The thickness range of the barrier layer 216 is:
[0111] The function of the barrier layer 216 is to provide an etching barrier layer for the subsequent etching process of forming the conductive plug 218 .
[0112] Please refer to Fig.13 , when forming the barrier layer 216 (such as Fig.12 After that, in the capacitor structure 210 (as shown Fig.12 A dielectric layer 217 is formed on the substrate 200 as shown in FIG.
[0113] The method for forming the dielectric layer 217 includes: forming a dielectric layer 217 on the capacitor structure 210 (such as Fig.12 An initial dielectric layer (not labeled) is formed on the substrate 200 as shown; the initial dielectric layer (not labeled) is planarized to form the dielectric layer 217.
[0114] The method for forming the initial dielectric layer includes deposition. Specifically, in this embodiment, the deposition method is chemical vapor deposition.
[0115] The planarization treatment method includes: mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization treatment method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing method, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the shortcomings of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nano level.
[0116] The thickness range of the dielectric layer 217 is:
[0117] The thickness of the dielectric layer 217 determines the depth of the conductive plug 218 subsequently formed in the dielectric layer.
[0118] Since the contact surfaces 211 of the electrode layers 212 of each layer are flush and the height of each end region 213 is small, when the dielectric layer 217 is formed on the surface of the capacitor structure 210 and the substrate 200, the height difference of the contact surfaces 211 of each layer of the electrode layers 212 is not too large, resulting in different removal rates of the initial dielectric layer (not marked) at different locations during the planarization process of the initial dielectric layer (not marked) and causing different heights of the dielectric layer 217 at different locations. This prevents the formation of a silicon bridge between the contact surface 211 of the electrode layer 212 and the metal layer 219, thereby improving the performance stability of the semiconductor structure.
[0119] Please refer to Fig.14, a plurality of conductive plugs 218 are formed in the dielectric layer 217 , and each of the conductive plugs 218 is respectively connected to each of the contact surfaces 211 .
[0120] The method for forming the conductive plug 218 includes: forming a fifth mask layer (not labeled) on the surface of the dielectric layer 217, wherein the fifth mask layer (not labeled) exposes a portion of the surface of the dielectric layer 217; using the fifth mask layer as a mask, etching the dielectric layer 217 to form a plurality of openings (not labeled) exposing the capacitor structure 210; and forming conductive plugs 218 in the plurality of openings.
[0121] The depth range of the conductive plug 218 is:
[0122] The material of the conductive plug 218 includes tungsten.
[0123] Please refer to Fig.15 After forming the conductive plug 218 , a metal layer 219 is formed on the dielectric layer 217 , and the conductive plug 218 connects the capacitor structure 210 and the metal layer 219 .
[0124] The material of the metal layer 219 includes copper.
[0125] The metal layer 219 is connected to the capacitor structure 210 through a conductive plug 218. Since the contact surfaces 211 of the electrode layers 207 of each layer are flush and the height of each end area 213 is small, the dielectric layer 217 formed on the surface of the capacitor structure 210 and the substrate 200 has an equal removal rate at all locations on the surface during the planarization process. The thickness of the dielectric layer 217 is uniform, and the different heights of the surface of the dielectric layer 217 will not cause a silicon bridge to be formed between the contact surface 211 of the electrode layer 212 and the metal layer 219, thereby improving the performance stability of the semiconductor structure.
[0126] Accordingly, the present invention also provides a semiconductor structure, please continue to refer to Fig.15 , comprising: a substrate 200; a first capacitor opening 201 (such as Figure 3 As shown), the first capacitor opening 201 (as shown Figure 3 ) includes a first region and a second region located on the first region, wherein the size of the second region along a direction parallel to the surface of the substrate 200 is larger than the size of the first region along a direction parallel to the surface of the substrate 200; the first capacitor opening 201 (as shown Figure 3 The capacitor structure 210 includes a plurality of layers along the first capacitor opening 201 (as shown in FIG. Figure 3 The electrode layers 212 are stacked in the normal direction, and each of the electrode layers 212 has a contact surface 211 flush with each other (as shown in FIG. Fig. 9 ); a dielectric layer 217 located on the capacitor structure 210 and the substrate 200; a plurality of conductive plugs 218 located in the dielectric layer 217, each of the conductive plugs 218 being respectively connected to each of the contact surfaces 211 (as shown); Fig. 9 shown) are connected.
[0127] The semiconductor structure includes a substrate 200 .
[0128] In this embodiment, the material of the substrate 200 is silicon.
[0129] In other embodiments, the material of the substrate includes: silicon carbide, silicon germanium, gallium arsenide, silicon on insulator (SOI), or germanium on insulator (GOI).
[0130] The semiconductor structure includes: a first capacitor opening 201 (eg, Figure 3 As shown), the first capacitor opening 201 (as shown Figure 3 ) includes a first region and a second region located on the first region, wherein the size of the second region along a direction parallel to the surface of the substrate 200 is larger than the size of the first region along the direction parallel to the surface of the substrate 200.
[0131] In this embodiment, the depth of the second zone is
[0132] The bottom size of the second region is smaller than the top size, and the sidewall morphology of the second region includes: a stepped surface, a concave curved surface or a plane vertical to the substrate surface.
[0133] Specifically, in this embodiment, the morphology of the sidewall of the second region is a step surface. When the morphology of the sidewall of the second region is a step surface, the number of step layers is the same as the number of layers of the electrode layer 212 .
[0134] In another embodiment, the morphology of the sidewall of the second region is a plane perpendicular to the substrate surface. Figure 4 .
[0135] In another embodiment, the morphology of the sidewall of the second region is a concave curved surface. Figure 5 .
[0136] The dimension of the first region of the first capacitor opening 201 along a direction parallel to the surface of the substrate 200 is twice the depth of the second region of the first capacitor opening 201 .
[0137] The semiconductor structure includes: a first capacitor opening 201 (such as Figure 3 The capacitor structure 210 includes a plurality of layers along the first capacitor opening 201 (as shown in FIG. Figure 3The electrode layers 212 are stacked in a normal direction (as shown), and each of the electrode layers 212 has a contact surface 211 that is flush with each other.
[0138] The material of the electrode layer 212 includes polysilicon.
[0139] The thickness of the electrode layer 212 is greater than
[0140] In this embodiment, the number of the electrode layers 212 is greater than or equal to 4, and the thickness of each electrode layer 212 is equal.
[0141] In other embodiments, the thicknesses of the electrode layers may be unequal.
[0142] The electrode layer 212 further includes an end region 213 that is higher than the contact surface 211 and exposes the contact surface 211; the height range of the end region 213 is less than or equal to:
[0143] The capacitor structure 210 further includes a capacitor dielectric layer located between adjacent electrode layers 212 .
[0144] The material of the capacitor dielectric layer includes silicon nitride.
[0145] The volume range of the capacitor structure 210 is: 400nf / mm 2 ~500nf / mm 2 .
[0146] The semiconductor structure includes: a linear oxide layer located between the first capacitor opening 201 and the capacitor structure 210 .
[0147] The semiconductor structure includes a spacer 214 located on the sidewall surface of the end region 213 of each electrode layer 212 .
[0148] The material of the sidewall spacer 214 includes silicon oxide or silicon nitride.
[0149] In this embodiment, the thickness of the side wall 214 is:
[0150] The semiconductor structure includes an electrical contact layer 215 located on the surface of the capacitor structure 210 and the surface of the substrate 200 .
[0151] The material of the electrical contact layer 215 includes metal silicide, and the conductivity of metal silicide is between that of metal and silicon.
[0152] In this embodiment, the thickness of the electrical contact layer 215 is:
[0153] The semiconductor structure includes a barrier layer 216 located on the surface of the electrical contact layer 215 .
[0154] The semiconductor structure includes: a dielectric layer 217 located on the barrier layer 216 , the capacitor structure 210 , and the substrate 200 .
[0155] The thickness range of the dielectric layer 217 is:
[0156] The semiconductor structure includes: a plurality of conductive plugs 218 located in the dielectric layer 217 , each of the conductive plugs 218 is connected to each of the contact surfaces 211 .
[0157] The depth range of the conductive plug 218 is:
[0158] The material of the conductive plug 218 includes tungsten.
[0159] The semiconductor structure includes a metal layer 219 located on the dielectric layer 217 and connected to the conductive plug 218 .
[0160] The material of the metal layer 219 includes copper.
[0161] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: substrate; A capacitor opening located in the substrate, the capacitor opening comprising a first region and a second region located on the first region, wherein a dimension of the second region along a direction parallel to a substrate surface is larger than a dimension of the first region along a direction parallel to the substrate surface; A capacitor structure located in the capacitor opening, the capacitor structure comprising a plurality of electrode layers stacked along a normal direction of the capacitor opening, each of the electrode layers having a mutually flush contact surface; a dielectric layer located on the capacitor structure and the substrate; A plurality of conductive plugs are located in the dielectric layer, and each of the conductive plugs is respectively connected to each of the contact surfaces.
2. The semiconductor structure according to claim 1, wherein: The dimension of the first region of the capacitor opening in a direction parallel to the substrate surface is twice the depth of the second region of the capacitor opening.
3. The semiconductor structure according to claim 1, wherein: Also includes: A linear oxide layer is located between the capacitor opening and the capacitor structure.
4. The semiconductor structure according to claim 1, wherein: The capacitor structure further includes: a capacitor dielectric layer located between adjacent electrode layers; the electrode layer material includes polysilicon; and the capacitor dielectric layer material includes silicon nitride.
5. The semiconductor structure according to claim 4, characterized in that The thickness of the electrode layer is greater than 6. The semiconductor structure according to claim 1, wherein: The electrode layer further comprises: an end region higher than the contact surface and exposing the contact surface; the height range of the end region is: less than or equal to 7. The semiconductor structure according to claim 6, wherein: Also includes: The side walls are located at the side walls of the end regions of each electrode layer.
8. The semiconductor structure according to claim 1, wherein: The bottom size of the second region is smaller than the top size, and the sidewall morphology of the second region includes: a stepped surface, a concave curved surface or a plane vertical to the substrate surface.
9. The semiconductor structure according to claim 6, wherein: Also includes: A barrier layer is located on the surface of the capacitor structure and the surface of the substrate, and the barrier layer exposes the contact surface.
10. The semiconductor structure according to claim 9, wherein: Also includes: An electric contact layer is located on the surface of each of the contact surfaces; the conductive plug is located on the surface of the electric contact layer; and the material of the electric contact layer includes metal silicide.
11. The semiconductor structure according to claim 9, wherein: Also includes: A metal layer is located on the dielectric layer and connected to the conductive plug.
12. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a capacitor opening in the substrate, the capacitor opening comprising a first region and a second region located on the first region, wherein a size of the second region along a direction parallel to a substrate surface is larger than a size of the first region along a direction parallel to the substrate surface; A capacitor structure is formed in the capacitor opening to fill the capacitor opening, wherein the capacitor structure includes a plurality of electrode layers stacked along a normal direction of the capacitor opening, and each of the electrode layers has a contact surface flush with each other; forming a dielectric layer on the capacitor structure and the substrate; A plurality of conductive plugs are formed in the dielectric layer, and each of the conductive plugs is respectively connected to each of the contact surfaces.
13. The method for forming a semiconductor structure according to claim 12, wherein: The electrode layer further comprises: an end region higher than the contact surface and exposing the contact surface; the height range of the end region is: less than or equal to 14. The method for forming a semiconductor structure according to claim 12, wherein: The bottom size of the second region is smaller than the top size, and the size of the first region in a direction parallel to the substrate surface is twice the depth of the second region; The sidewall morphology of the second region includes: a stepped surface, a concave curved surface or a plane perpendicular to the substrate surface.
15. The method for forming a semiconductor structure according to claim 14, wherein: When the sidewall morphology of the second region is a stepped surface, the number of step layers is the same as the number of electrode layers.
16. The method for forming a semiconductor structure according to claim 15, wherein: The number of the electrode layers is greater than or equal to 4, and the thickness of each electrode layer is equal.
17. The method for forming a semiconductor structure according to claim 14, wherein: When the sidewall morphology of the second region is a step surface, the method for forming the second region includes: forming a first mask layer on the surface of the substrate, the first mask layer having a mask opening that exposes a portion of the substrate surface; performing several etching processes on the substrate and the first mask layer until the second region of the capacitor opening is formed, each etching process includes: using the first mask layer as a mask to etch the exposed substrate surface; after etching the exposed substrate surface, performing side etching on the sidewall of the mask opening to expose a portion of the substrate surface, and the etching direction of the side etching is parallel to the substrate surface.
18. The method for forming a semiconductor structure according to claim 17, wherein: The method for forming the capacitor structure comprises: forming an initial capacitor structure in the capacitor opening, the initial capacitor structure comprising a plurality of initial electrode layers stacked along the normal direction of the capacitor opening, the top surface of each initial electrode layer having an area to be etched; forming a second mask layer on the surface of the initial capacitor structure, the second mask layer exposing the surface of the area to be etched; etching the initial capacitor structure using the second mask layer as a mask to form the capacitor structure, the surface of the area to be etched after being etched forms the contact surface.
19. The method for forming a semiconductor structure according to claim 12, wherein: Also includes: A barrier layer is located on the surface of the capacitor structure and the surface of the substrate, and the barrier layer exposes the surface of the contact surface.
20. The method for forming a semiconductor structure according to claim 12, wherein: Also includes: An electrical contact layer located on the surface of the contact surface; the conductive plug is located on the surface of the electrical contact layer; The material of the electrical contact layer includes metal silicide.
21. The method for forming a semiconductor structure according to claim 12, wherein: After forming the conductive plug, the method further includes: forming a metal layer on the dielectric layer, wherein the conductive plug connects the capacitor structure with the metal layer.
22. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the dielectric layer comprises: forming an initial dielectric layer on the capacitor structure and the substrate; and performing a planarization process on the initial dielectric layer until a dielectric layer with a flat surface is obtained.