Electronic device and method of manufacturing electronic device

Abstract

An electronic device and a method of manufacturing the electronic device. In one example, an electronic device may include: a first substrate; an electronic component disposed over one side of the first substrate; and a vertical interconnect coupled to the side of the first substrate. The vertical interconnect may include: a first metal core ball proximate to the first substrate; a second metal core ball disposed over the first metal core ball and away from the first substrate; and a fusible material coupling the first metal core ball with the second metal core ball. The fusible material may be coupled to the first substrate. A second substrate may be disposed over the electronic component and the vertical interconnect. The fusible material of the vertical interconnect may be coupled to the second substrate. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly to electronic devices and methods of making electronic devices. Background Art

[0002] Previous electronic packages and methods of forming electronic packages are inadequate, for example resulting in excessive cost, reduced reliability, relatively low performance, or excessive package size. Other limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with the present disclosure and referring to the drawings. Summary of the invention

[0003] One aspect of the present invention is an electronic device, comprising: a first substrate; an electronic component disposed above one side of the first substrate; a vertical interconnect coupled to the side of the first substrate, the vertical interconnect comprising: a first metal core ball close to the first substrate; a second metal core ball disposed above the first metal core ball and away from the first substrate; and a fusible material coupling the first metal core ball with the second metal core ball, wherein the fusible material is coupled to the first substrate; and a second substrate disposed above the electronic component and the vertical interconnect, wherein the fusible material of the vertical interconnect is coupled to the second substrate.

[0004] In the electronic device according to an aspect of the present invention, the diameter of the first metal core ball is greater than the diameter of the second metal core ball.

[0005] In the electronic device according to aspects of the present invention, the sidewall of the vertical interconnect includes a substantially convex geometry in a region surrounding a point between the first metal core ball and the second metal core ball.

[0006] In the electronic device according to an aspect of the present invention, a height of the electronic component measured from the side of the first substrate is greater than a diameter of the first metal core ball.

[0007] In the electronic device according to an aspect of the present invention, the first substrate includes: an internal terminal; and a dielectric structure defining an opening above the internal terminal, wherein the fusible material extends through the opening to the internal terminal.

[0008] In the electronic device according to an aspect of the present invention, the fusible material extends from the opening to a portion of the dielectric structure adjacent to the opening.

[0009] In the electronic device according to an aspect of the present invention, the first metal core ball contacts the second metal core ball.

[0010] The electronic device according to aspects of the present invention further includes a second vertical interconnect coupled to the first substrate and disposed laterally to the electronic component, wherein the second vertical interconnect includes a third metal core ball close to the first substrate and a fourth metal core ball away from the first substrate.

[0011] Another aspect of the present invention is an electronic device, comprising: a first internal terminal; a fusible material coupled to the first internal terminal; a first metal core ball close to the first internal terminal and coupled to the fusible material; a second metal core ball far away from the first internal terminal and coupled to the fusible material; and a second internal terminal coupled to the fusible material and close to the second metal core ball.

[0012] In the electronic device according to another aspect of the present invention, the sidewall of the fusible material includes a substantially convex geometry in a region surrounding a point between the first metal core ball and the second metal core ball.

[0013] According to another aspect of the present invention, the electronic device further includes an electronic component adjacent to the first metal core ball, wherein a height of the electronic component is greater than a height of the first metal core ball.

[0014] According to another aspect of the present invention, the electronic device further comprises a dielectric structure defining an opening above the first internal terminal, wherein the fusible material extends through the opening to the first internal terminal.

[0015] In the electronic device according to another aspect of the present invention, the fusible material extends from the opening to a portion of the dielectric structure adjacent to the opening.

[0016] In an electronic device according to another aspect of the present invention, the first metal core ball contacts the second metal core ball.

[0017] Another aspect of the present invention is a method for manufacturing an electronic device, comprising: setting a first substrate; setting a first metal core ball on the first substrate; setting a second substrate; setting a second metal core ball on one side of the second substrate; setting an electronic component on the side of the second substrate; and coupling the first metal core ball to the second metal core ball with a fusible material.

[0018] In a method according to yet another aspect of the present invention, the fusible material includes a substantially convex geometry in a region surrounding a point between the first metal core ball and the second metal core ball.

[0019] In the method according to another aspect of the present invention, the diameter of the first metal core ball is greater than the diameter of the second metal core ball.

[0020] According to another aspect of the present invention, the method further includes disposing an encapsulant between the first substrate and the second substrate.

[0021] In the method according to yet another aspect of the invention, coupling the first metal core ball to the second metal core ball further comprises applying a temperature greater than about 220° C. for a period greater than about 15 seconds.

[0022] In the method according to yet another aspect of the invention, coupling the first metal core ball to the second metal core ball further includes applying a temperature of about 255°C. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A cross-sectional view of an example electronic device is shown.

[0024] FIG. 2A to FIG. 2I An example method for manufacturing an electronic device is shown. Figure 2EA exhibit Figure 2E Segment A of . Figure 2GA Shows the metal core ball after coupling to the metal core ball Figure 2G Area A. Figure 2GB Shows the metal core ball after coupling to the metal core ball Figure 2G Area B. Figure 2GC Shows the metal core ball after coupling to the metal core ball Figure 2G Area C. Figure 2GD Shows the metal core ball after coupling to the metal core ball Figure 2G area D.

[0025] Figure 3 and Figure 3A A cross-sectional view of an example electronic device is shown.

[0026] The following discussion provides various examples of electronic devices and methods of making electronic devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. The detailed description herein is presented for illustrative purposes only and not for limiting purposes. For example, the steps recited in any of the method or process descriptions may be performed in any order and are not necessarily limited to the order presented. In the following discussion, the terms "example" and "for example" are non-limiting.

[0027] The figures illustrate general constructions, and descriptions and details of well-known features and techniques may be omitted so as not to unnecessarily obscure the present disclosure. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be enlarged relative to other elements to help improve the understanding of the examples discussed in the present disclosure. The same reference numerals in different figures represent the same elements.

[0028] The term "or" means any one or more of the items in the list connected by "or". As an example, "x or y" means any one of the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any one of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0029] The terms “comprises,” “comprising,” “includes,” and “including” are “open” terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features.

[0030] The terms "first", "second", etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, the first element discussed in the present disclosure may be referred to as the second element without departing from the teachings of the present disclosure.

[0031] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly coupled through one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B or indirectly coupled to element B through an intervening element C. Similarly, the terms "above" or "on" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly coupled by one or more other elements. As used herein, the term coupled may refer to electrical coupling or mechanical coupling. DETAILED DESCRIPTION

[0032] An example electronic device may include: a first substrate; an electronic component disposed over a side of the first substrate; and a vertical interconnect coupled to the side of the first substrate. The vertical interconnect may include: a first metal core ball proximate to the first substrate; a second metal core ball disposed over the first metal core ball and away from the first substrate; and a fusible material coupling the first metal core ball with the second metal core ball. The fusible material may be coupled to the first substrate. The second substrate may be disposed over the electronic component and the vertical interconnect. The fusible material of the vertical interconnect may be coupled to the second substrate.

[0033] Another example electronic device may include: a first internal terminal; a fusible material coupled to the first internal terminal; and a first metal core ball proximate to the first internal terminal and coupled to the fusible material. A second metal core ball may be distal to the first internal terminal and coupled to the fusible material. A second internal terminal may be coupled to the fusible material and proximate to the second metal core ball.

[0034] An example method of manufacturing an electronic device may include the following steps: providing a first substrate; providing a first metal core ball on the first substrate; and providing a second substrate. The second metal core ball may be provided on one side of the second substrate. The electronic device may be provided on the side of the second substrate. The first metal core ball may be coupled to the second metal core ball with a fusible material.

[0035] Other examples are included in the present disclosure. Such examples can be found in the drawings, claims or specification of the present disclosure.

[0036] Various example devices and methods incorporate a vertical interconnect structure having multiple metal core balls (e.g., copper core balls) that are vertically stacked and coupled together by a fusible material. The use of multiple metal core balls in a single vertical interconnect structure can enable the use of thicker die in an electronic device, which tends to improve thermal performance. Multiple stacked metal core balls per vertical interconnect can simplify thermal compression bonding (TCB), for example, by forming a vertical interconnect with sufficient joint height before performing a pullback step to artificially stretch the vertical interconnect. The joint height and fusible volume of the vertical interconnect structure can also be controlled by selecting the diameters of the top and bottom metal core balls used to form the vertical interconnect.

[0037] Reference Figure 1 , shows a cross-sectional view of an example electronic device 100. Figure 1In an example of the present invention, the electronic device 100 may include an electronic component 102, one or more vertical interconnects 107, a redistribution structure 104, and a redistribution structure 114. In some examples, the electronic device 100 may further include an external interconnect 116, an electronic component 118, an electronic component 120, or an encapsulation 122. According to various examples, the electronic component 102 may be coupled to the redistribution structure 114. The vertical interconnect 107 may include an upper metal core ball 106 and a lower metal core ball 108. The upper metal core ball 106 may be vertically stacked on the lower metal core ball 108. The upper metal core ball 106 and the lower metal core ball 108 may be coupled together by a fusible material 109. The vertical interconnect 107 may be coupled to the redistribution structure 114 and the redistribution structure 104 by the fusible material 109. The upper metal core ball 106 may be close to the redistribution structure 104 and away from the redistribution structure 114. The lower metal core ball 108 may be proximate to the redistribution structure 114 and distal to the redistribution structure 104. The encapsulant 122 may be disposed between the redistribution structure 104 and the redistribution structure 114, on the electronic component 102, and on the vertical interconnect 107. The external interconnect 116, electronic component 118, or electronic component 120, or other passive devices, electronic components, or interconnects may be coupled to the redistribution structure 114 on the outside of the electronic device 100 (e.g., on a side of the redistribution structure 114 opposite to the electronic component 102 and the encapsulant 122). In some examples, the electronic component 118 may include a pad side capacitor 118 (LSC). In some examples, the electronic component 120 may include a deep trench capacitor 120 (DTC).

[0038] FIG. 2A to FIG. 2I An example method for manufacturing electronic device 100 using cross-sectional views is shown. Figure 2A The electronic device 100 is shown in an early stage of manufacture. Figure 2A , the substrate 200 may be disposed on a surface of a carrier 201. In some examples, the substrate 200 may include a plurality of redistribution structures 104 that are integrally formed with each other and arranged in rows, columns, arrays, or any other arrangement. The redistribution structure 104 may be used as an upper redistribution structure in subsequent steps described below. The substrate 200 may include a dielectric structure 204 and a conductive structure 202. The conductive structure 202 may include an internal terminal 206 and an external terminal 207. An internal dielectric layer 208 of the dielectric structure 204 may be adjacent and partially cover the internal terminal 206 of the conductive structure 202 on the inner side of the substrate 200. The external terminal 207 of the conductive structure 202 may be disposed on the outer side of the substrate 200 opposite to the internal terminal 206 (e.g., on a side of the substrate 200 that faces the carrier 201).

[0039] In some examples, the external terminal 207 or the internal terminal 206 may include a pattern on the surface of the carrier 201. The external terminal 207 or the internal terminal 206 may include or be referred to as a conductor, a conductive material, a pad, a pad, or an under-bump metal (UBM). In some examples, the external terminal 207 or the internal terminal 206 may include copper, gold, silver, or nickel. In some examples, the external terminal 207 or the internal terminal 206 may be provided by plating. For example, the external terminal 207 or the internal terminal 206 may be provided by plating using a seed layer. After a metal seed layer is provided above the upper surface of the carrier 201, a mask pattern is provided above the upper surface of the seed layer. For example, the mask pattern may include a photoresist material. The external terminal 207 or the internal terminal 206 is then plated on the portion of the seed layer exposed from the mask pattern. After the external terminal 207 or the internal terminal 206 is formed, the mask pattern and the portion of the seed layer located below the mask pattern may be removed. In some examples, the thickness of the external terminal 207 or the internal terminal can be in the range of about 3 micrometers (μm) to 20 μm. As used herein with reference to measurements of length, about can mean + / -5%, + / -10%, + / -15%, + / -20%, or + / -25%.

[0040] In some examples, carrier 201 may be a substantially planar plate. Carrier 201 may include or be referred to as a plate, a single plate, a wafer, a panel, or a strip. For example, carrier 201 may be made of steel, stainless steel, aluminum, copper, ceramic, glass, or a wafer containing a semiconductor material. In some examples, the thickness of carrier 201 may be in the range of about 300 μm to 2000 μm, and the width of carrier 201 may be in the range of about 100 millimeters (mm) to 300 mm. Carrier 201 is used to support and enable handling of components during the process of setting substrate 200.

[0041] In some examples, the carrier 201 may include a temporary bonding layer disposed on the surface of the carrier 201. External terminals 207 may be provided on the surface of the temporary bonding layer of the carrier 201. The temporary bonding layer may be formed by performing a coating process (e.g., spin coating, blade coating, casting, brushing, spraying, slit-type extrusion coating, curtain coating, inclined plate coating or blade coating) on ​​the surface of the carrier 201, a printing process (e.g., screen printing, pad printing, gravure printing, elastic printing, or lithography), an inkjet printing process, an intermediate technology between coating and printing, or by direct attachment of an adhesive film or adhesive tape. In some examples, the temporary bonding layer may include or be referred to as a temporary adhesive film, a temporary adhesive tape or a temporary adhesive coating. For example, the temporary bonding layer may be a thermal release tape (film) film or an optical release tape (film), and the bonding strength may be weakened or removed by heat or light, respectively. In some examples, the temporary bonding layer may have a bonding strength weakened or removed by a physical or chemical external force. The temporary bonding layer may allow the carrier 201 to be separated from the substrate 200 .

[0042] In some examples, a dielectric structure 204 may be provided on the upper side of the external terminal 207 and the carrier 201. After the dielectric structure 204 is provided to cover the external terminal 207 and the carrier 201, an opening exposing the external terminal 207 may be provided in the dielectric structure 204. For example, the opening may be formed by forming a mask pattern on the upper side of the dielectric structure 204 and then removing the exposed dielectric structure 204 by etching. In some examples, the opening may be referred to as or include an orifice or a hole. In some examples, the dielectric structure 204 may include or be referred to as a dielectric layer, a coreless layer or a fillerless layer. For example, the dielectric structure 204 may include an electrically insulating material such as polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), a resin or an ajinomoto deposited film (ABF). In some examples, the dielectric structure 204 may be formed by spin coating, spray coating, dip coating or rod coating. In some examples, the thickness of individual layers of the dielectric structure 204 may be in a range of approximately 5 μm to 30 μm.

[0043] In some examples, the conductive structure 202 may be disposed above and interlaced with the layers of the dielectric structure 204. The conductive structure 202 may include one or more conductive layers and form a conductive path that passes horizontally and vertically through the dielectric structure 204. The conductive structure 202 may be configured to have a plurality of patterns, and the respective patterns may be electrically connected to the external terminals 207 and the internal terminals 206 of the conductive structure 202. In some examples, the conductive structure 202 may include or be referred to as a conductive layer, a trace, a pad, a via, a redistribution layer (RDL), a wiring pattern, or a circuit pattern. In some examples, the conductive structure 202 may include copper, gold, silver, or nickel. In some examples, the conductive structure 202 may include elements, features, materials, or manufacturing methods similar to or the same as those previously described for the external terminal 207. The external terminal 207 may be part of the conductive structure 202. In some examples, the overall thickness of the individual layers of the conductive structure 202 may be in the range of about 3 μm to 20 μm. The conductive structure 202 may include a conductive layer positioned inside the dielectric structure 204 (eg, Figure 2A An internal terminal 206 at the upper side of the body.

[0044] In some examples, the internal dielectric layer 208 of the dielectric structure 204 may be disposed on the upper side of the internal terminal 206. After the internal dielectric layer 208 is disposed to cover the internal terminal 206, an opening exposing the internal terminal 206 may be disposed in the internal dielectric layer 208. For example, the opening may be formed by forming a mask pattern on the upper side of the internal dielectric layer 208 and then removing the exposed portion of the internal dielectric layer 208 by etching. In some examples, the opening may be referred to as or include an orifice or a hole. The internal dielectric layer 208 may be formed by spin coating, spray coating, dip coating, or rod coating. In some examples, the thickness of the internal dielectric layer 208 may be in the range of about 5 μm to 30 μm. In some examples, the internal dielectric layer 208 may include a solder resist.

[0045] It is contemplated and understood that one or more layers or elements of the conductive structure 202 may be interleaved with the dielectric structure 204, and the dielectric structure 204 and the conductive structure 202 may each include any number of layers in the substrate 200. The internal terminals 206 and the external terminals 207 may be disposed spaced apart from each other in a row or column direction on opposite sides of the substrate 200. In some examples, the overall thickness of the substrate 200 may be in a range of approximately 5 μm to 200 μm. In some examples, the substrate 200 may include a laminate substrate.

[0046] In some examples, substrate 200 may be a redistribution layer ("RDL") substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers, and the RDL substrate may include a plurality of units of a redistribution structure 104 suitable for singulation during formation of the electronic device 100. The RDL substrate may be formed layer by layer over an electronic component to be coupled to the RDL substrate. The RDL substrate may be formed layer by layer over a carrier and may be fully or partially removed after the electronic component is coupled to the RDL substrate. The RDL substrate may be manufactured layer by layer as a wafer-level substrate on a circular wafer with a wafer-level process, or may be manufactured layer by layer as a panel-level substrate on a rectangular or square panel carrier with a panel-level process.

[0047] The RDL substrate may be formed in an additive buildup process and may include one or more dielectric layers stacked alternately with one or more conductive layers and defining respective conductive redistribution patterns or traces configured to collectively fan electrical traces out of or into the footprint of an electronic component. The conductive pattern may be formed using a plating process such as an electroplating process or an electroless plating process. The conductive pattern may include a conductive material such as copper or other plateable metal. The location of the conductive pattern may be made using a photopatterning process such as a photolithography process and a photoresist material used to form a photolithography mask.

[0048] The dielectric layer of the RDL substrate may be patterned with a photopatterning process and may include a photolithographic mask through which light is exposed to desired features of the photopattern, such as vias in the dielectric layer. The dielectric layer may be made of a photo-definable organic dielectric material such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). Such dielectric materials may be spin-coated or otherwise applied in liquid form rather than attached in the form of a preformed film. In order to permit the desired photo-defined features to be properly formed, such photo-definable dielectric materials may omit structural reinforcements, or may be filler-free, without strands, woven fabrics, or other particles that may interfere with light from the photopatterning process. In some instances, such filler-free properties of filler-free dielectric materials may permit a reduction in the thickness of the resulting dielectric layer. Although the photo-definable dielectric material described above may be an organic material, in some instances, the dielectric material of the RDL substrate may include one or more inorganic dielectric layers. Some examples of inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON). The inorganic dielectric layer may be formed by growing the inorganic dielectric layer using an oxidation or nitridation process rather than using a photo-defined organic dielectric material. Such inorganic dielectric layers may be filler-free without strands, woven fabrics, or other different inorganic particles. In some examples, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates may include or be referred to as coreless substrates.

[0049] In some examples, substrate 200 can be a preformed substrate. The preformed substrate can be manufactured before being attached to the electronic component (or before being placed above carrier 201), and can include a dielectric layer between corresponding conductive layers. The conductive layer can include copper and can be formed using an electroplating process. The dielectric layer can be a relatively thick non-photodefinable layer, which can be attached in a preformed film form rather than in a liquid form, and can include a resin with fillers such as strands, woven fabrics and / or other inorganic particles for rigid or structural support. Since the dielectric layer is non-photodefinable, features such as through holes or openings can be formed by using drilling or lasers. In some examples, the dielectric layer can include prepreg materials or Ajinomoto stacked film (ABF). The preformed substrate can include a permanent core structure or carrier, such as a dielectric material including BT or FR4, and the dielectric layer and the conductive layer can be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate and the permanent core structure is omitted, and the dielectric layer and the conductive layer may be formed on a sacrificial carrier that is removed after the dielectric layer and the conductive layer are formed and before being attached to the electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminate substrate. This preformed substrate may be formed by a semi-additive process or a modified semi-additive process. The substrate in the present disclosure may include a preformed substrate or an RDL substrate.

[0050] Figure 2B A cross-sectional view of the electronic device 100 is shown in a post-manufacturing stage. Figure 2B , the metal core ball 106 may be disposed above the substrate 200. The metal core ball 106 may be coupled to the internal terminal 206 of the conductive structure 202. The metal core ball 106 may be provided with a fusible coating 205 surrounding or substantially surrounding the metal core of the metal core ball 106. The metal core ball 106 may be made of a conductive material having a higher melting point than the surrounding fusible coating 205, such as copper, gold, silver, palladium, or nickel. The metal core ball 106 may be referred to as a solder-coated metal core ball. In some examples, the height of the metal core ball 106 may be in the range of about 3 μm to 200 μm. The metal core balls 106 may be spaced apart from each other in rows, columns, arrays, or other patterns.

[0051] Figure 2C A cross-sectional view of the electronic device 100 is shown in a post-manufacturing stage. Figure 2C, the substrate 210 may be disposed on a surface of a carrier 211. In some examples, the substrate 210 may include a plurality of redistribution structures 114 that are integrally formed with each other and arranged in rows, columns, arrays, or any other arrangement. The redistribution structure 114 may be used as a lower redistribution structure in subsequent steps described below. The substrate 210 may include a dielectric structure 214 and a conductive structure 212. The conductive structure 212 may include an internal terminal 216 and an external terminal 217. An internal dielectric layer 218 of the dielectric structure 214 may be on the inner side of the substrate 210. The internal dielectric layer 218 may be adjacent to and partially cover the internal terminal 216. The external terminal 217 of the conductive structure 212 may be disposed on the outer side of the substrate 210 opposite to the internal terminal 216 (e.g., on a side of the substrate 210 that faces the carrier 211). The substrate 210 may include structures or processing steps that are similar or identical to those described for the substrate 200. Conductive structure 212 may include structures or processing steps similar to or the same as those described for conductive structure 202. Dielectric structure 214 may include structures or processing steps similar to or the same as those described for dielectric structure 204. Internal terminal 216 may include structures or processing steps similar to or the same as those described for internal terminal 206. External terminal 217 may include structures or processing steps similar to or the same as those described for external terminal 207. Internal dielectric layer 218 may include structures or processing steps similar to or the same as those described for internal dielectric layer 208.

[0052] Figure 2D A cross-sectional view of the electronic device 100 is shown in a post-manufacturing stage. Figure 2D , a metal core ball 108 may be disposed over a substrate 210. The metal core ball 108 may be coupled to an internal terminal 216. The metal core ball 108 may be provided with a fusible coating 215 that surrounds or substantially surrounds a metal core of the metal core ball 106. The metal core ball 108 may include structures or processing steps similar to or the same as those described for the metal core ball 106. The fusible coating 215 may include structures or processing steps similar to or the same as those described herein for the fusible coating 205.

[0053] Figure 2E and Figure 2EA A cross-sectional view of the electronic device 100 is shown in a post-manufacturing stage. Figure 2EA Show in more detail Figure 2E The electronic component 102 may be disposed above the substrate 210. Figure 2E and Figure 2EAIn an example of the present invention, the electronic component 102 may be disposed between the metal core balls 108 above the redistribution structure 114. The electronic component 102 may be coupled to the internal terminals 216 of the redistribution structure 114. In some examples, the lower side of the electronic component 102 (e.g., the side oriented toward the redistribution structure 114) may include or be referred to as the active side, and the upper side of the electronic component 102 (e.g., the side oriented away from the redistribution structure 114) may include or be referred to as the inactive side or back side. The electronic component 102 may include component interconnects 220 on the lower side. The component interconnects 220 may be disposed on the lower side of the electronic component 102 and may be spaced apart from each other in rows, columns, arrays, or other patterns. The component interconnects 220 may include or be referred to as bumps, pads, or pillars. The component interconnects 220 may be input / output terminals of the electronic component 102. In some examples, component interconnects 220 may be disposed on the underside of electronic component 102 by electrolytic plating, electroless plating, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). For example, after disposing a photoresist pattern that exposes the bonding pads of electronic component 102, component interconnects 220 may be disposed and coupled to the exposed bonding pads. In some examples, the thickness (or height) of component interconnects 220 may be in the range of about 10 μm to 100 μm, and the pitch may be in the range of about 20 μm to 300 μm.

[0054] In some examples, a pick-and-place device may pick up the electronic component 102 and place it on the redistribution structure 114. The component interconnects 220 of the electronic component 102 may be located on the upper side of the internal terminals 216 of the redistribution structure 114. Subsequently, the component interconnects 220 of the electronic component 102 may be bonded to the internal terminals 216 by a reflow or thermocompression bonding process. In some examples, the electronic component 102 may include or be referred to as a die, a chip, or a package.

[0055] In some examples, the underfill 222 may be positioned between the electronic component 102 and the redistribution structure 114. The underfill 222 may be coupled to the underside of the electronic component 102 and the inner side of the redistribution structure 114. The underfill 222 may be coupled to the component interconnect 220 of the electronic component 102. The underfill 222 may include or be referred to as a dielectric layer or a non-conductive paste. The underfill 222 may be free of inorganic fillers. In some examples, the underfill 222 may include or be referred to as a capillary underfill (CUF), a non-conductive paste (NCP), a non-conductive film (NCF), an anisotropic conductive film (ACF), or an anisotropic conductive paste (ACP). In some examples, the underfill 222 may be a molded underfill (MUF), and the underfill 222 may be considered to be part of the encapsulant 122 ( Figure 2F ). In some examples, the bottom filler 222 may be cured after being positioned between the electronic component 102 and the redistribution structure 114. In some examples, after the bottom filler 222 is disposed to cover the inner side of the redistribution structure 114, the component interconnect 220 of the electronic component 102 may pass through the bottom filler 222 and be coupled to the internal terminal 216. The bottom filler 222 may prevent or reduce the occurrence of separation of the electronic component 102 from the redistribution structure 114 due to physical impact or chemical process.

[0056] Figure 2F A cross-sectional view of the electronic device 100 is shown in a post-manufacturing stage. Figure 2F , substrate 200 may be released from carrier 201 and positioned over substrate 210. Individual cells of upper redistribution structure 104 may be vertically aligned with individual cells of lower redistribution structure 114. Upper metal core balls 106 may be vertically aligned with lower metal core balls 108. In some examples, alignment may be performed on a hot press device for coupling metal core balls 106 and 108 in a subsequent processing step.

[0057] Figure 2G A cross-sectional view of the electronic device 100 is shown in a post-manufacturing stage. Figure 2G In some examples, metal core ball 106 is coupled to metal core ball 108. In some examples, hot pressing can be used to couple the metal core balls. The temperature and pressure applied during hot pressing can be selected to cause the fusible coating 205, 215 ( Figure 2F ) is maintained aligned as it flows into the fusible material 109 to couple the upper metal core ball 106 to the vertically aligned lower metal core ball 108. In some examples, the metal core balls 106, 108 can be spherical. In some examples, one or more metal core balls can be ovalized or flattened against an adjacent internal terminal or metal core ball to resist lateral displacement.

[0058] In some examples, thermocompression bonding can couple the metal core ball 106 and the metal core ball 108 with the fusible material 109. The temperature can be maintained above a temperature threshold for a predetermined duration. Examples of suitable temperature thresholds may include about 200°C, about 210°C, about 220°C, about 240°C, or about 250°C. As used herein with reference to temperature, about may mean + / -5°C, + / -10°C, + / -15°C, + / -20°C, or + / -25°C. Examples of suitable durations may include a period greater than about 10 seconds (sec), about 15sec, about 20sec, or about 25sec. As used herein with reference to a period, about may mean + / -1sec, + / -2sec, + / -3sec, + / -4sec, or + / -5sec. In one example, the temperature may be maintained above a threshold of about 255°C for a period greater than about 15 seconds. In some examples, the maximum temperature applied during the thermocompression bonding of the metal core ball 106 and the metal core ball 108 may be about 235°C, about 245°C, about 255°C, about 265°C, or about 275°C.

[0059] In some examples, temperature may be applied simultaneously with pressure to bond the fusible coating 205 ( Figure 2F ) and fusible coating 215 ( Figure 2F ), thereby providing fusible material 109 extending between inner terminal 206 and inner terminal 216. Pressure may be applied in a compressive direction (e.g., compressing substrate 200 toward substrate 210) while maintaining alignment of metal core balls 106 and metal core balls 108. In some examples, a pressure of about 300 Newtons (N), about 320N, about 360N, or about 380N may be applied. As used herein with reference to force or pressure, about may mean + / -5%, + / -10%, + / -15%, + / -20%, or + / -25%. In some examples, the pressure applied during bonding may be determined based on the number of vertical interconnects 107 to be formed by melting the aligned metal core balls on substrate 200 and substrate 210.

[0060] Figure 2GA More specifically, the metal core ball 106 is coupled to the metal core ball 108. Figure 2G Area A. Figure 2GA In the example of FIG. 1 , the fusible coating 205 ( Figure 2F ) and a fusible coating 215 ( Figure 2F ) may be reflowed to form a vertical interconnect 107 including an upper metal core ball 106, a lower metal core ball 108, and a fusible material 109. The vertical interconnect 107 may include an upper metal core ball 106 having a diameter D1, a lower metal core ball 108 having a diameter D2, and a fusible material 109 having a width W1.

[0061] exist Figure 2GA In the depicted example of , diameter D1 and diameter D2 are equal. In other examples, diameter D1 may be greater than diameter D2, or diameter D1 may be less than diameter D2. Selecting metal core balls 106 and 108 with diameter D1 less than (or greater than) diameter D2 may tend to increase space for sliding or misalignment. Selecting metal core balls with smaller diameters D1 and D2 tends to reduce the height and volume of fusible material 109 in vertical interconnects 107. Selecting metal core balls with larger diameters D1 and D2 tends to increase the height and volume of fusible material 109 in vertical interconnects 107. In some examples, the reduced volume of fusible material 109 may reduce the width or footprint of vertical interconnects 107.

[0062] In some examples, vertical interconnect 107 may have sidewalls 228. When fusible coating 205 and fusible coating 215 reflow into fusible material 109, sidewalls 228 may be formed under surface tension. Fusible material 109 may have an elliptical geometry or a substantially convex geometry. Fusible material 109 of vertical interconnect 107 may be coupled to internal terminal 206 and internal terminal 216.

[0063] In some examples, the fusible material 109 may have a maximum width W1 in an area surrounding a point between the center of the metal core ball 106 and the center of the metal core ball 108. In some examples, the maximum width W1 of the fusible material 109 may occur at a height of about D2 from the redistribution structure 114, or at a height of about half the height H1 from the redistribution structure 114. The maximum width W1 tends to be greater than the diameter D1 and greater than the diameter D2. The fusible material 109 may have a maximum width W1 in an area surrounding the contact point of the metal core ball 106 and the metal core ball 108. The sidewall 228 may have a substantially convex geometry at an area disposed around or surrounding the contact point between the metal core ball 106 and the metal core ball 108.

[0064] In a certain example, the metal core ball 106 may be separated from the metal core ball 108 by the fusible material, and the width W1 may occur at a region disposed around or enclosing a gap between the metal core ball 106 and the metal core ball 108 .

[0065] In some examples, the upper metal core ball 106 may be in contact with the lower metal core ball 108 in the vertical interconnect 107. In some examples, the upper metal core ball 106 may be separated from the lower metal core ball 108 by the fusible material 109 after bonding. In some examples, the metal core balls 106, 108 may be separated from the internal terminals 206, 216 by the fusible material 109 after bonding. In some examples, the metal core balls 106, 108 may be in contact with the internal terminals 206, 216 after bonding.

[0066] In some examples, a portion 221 of the inner dielectric layer 208 covers a portion of the inner terminal 206. The portion 221 of the inner dielectric layer 208 may overhang a portion of the inner terminal 206. A portion of the metal core ball 106 may extend into the opening 223 and may be above the underside of the portion 221 of the inner dielectric layer 208. The inner terminal 206 may be recessed relative to the inner dielectric layer 208. The fusible material 109 may completely or partially fill the opening 223 defined by the inner dielectric layer 208 above the inner terminal 206. Although in Figure 2GA In the example of FIG. 2 , the internal terminal 206 is recessed, but in other examples, the internal terminal 206 can be coplanar with the internal dielectric layer 208 .

[0067] In some examples, a portion 224 of the inner dielectric layer 218 covers a portion of the inner terminal 216. The portion 224 of the inner dielectric layer 218 may overhang a portion of the inner terminal 216. A portion of the metal core ball 108 may extend into the opening 225 and may be below the upper side of the portion 224 of the inner dielectric layer 218. The inner terminal 216 may be recessed relative to the inner dielectric layer 218. The fusible material 109 may completely or partially fill the opening 225. The fusible material 109 may cover the portion 224 of the inner dielectric layer 218 above the inner terminal 216. Although in Figure 2GA In the example of FIG. 2 , the internal terminal 216 is recessed, but in other examples, the internal terminal 216 can be coplanar with the internal dielectric layer 218 .

[0068] In some examples, the height H1 may be the height of the vertical interconnect 107 between the inner surface of the substrate 200 and the inner surface of the substrate 210. In examples including gaps between the metal core balls 106 and 108 or between the metal core balls 106, 108 and the internal terminals 206, 216, the height H1 may be greater than the sum of the diameter D1 and the diameter D2. The increased height H1 tends to enable the electronic device 100 to accommodate thicker electronic components 102 between the redistribution structures 104 and the redistribution structures 114. The height H1 of the vertical interconnect 107 may be controlled by selecting the metal core balls 106, 108 having the desired diameters D1 and D2. In some examples, the internal terminal 206 contacts the metal core ball 106, the metal core ball 106 contacts the metal core ball 108, and the metal core ball 108 contacts the internal terminal 216.

[0069] In an example where the metal core balls 106 and 108 are stacked directly on the center in the direction of the height H1, and the metal core balls 106 and 108 contact each other and contact the adjacent internal terminals 206, 216, the height H1 may be approximately the sum of the diameter D1 and the diameter D2 minus the depth of the opening 223 and the depth of the opening 225 that exposes the internal terminals 206, 216. In an example where the metal core balls 106 and 108 are stacked off-center, and the metal core balls 106 and 108 contact each other and contact the adjacent internal terminals 206, 216, the height H1 may be less than the sum of the diameter D1 and the diameter D2. The lateral offset of the metal core ball 106 relative to the metal core ball 108 may reduce the height H1 by an amount based on the lateral offset. In some examples, the metal core balls 106 and 108 of the vertical interconnect 107 tend to maintain a minimum height H1 based on fixed diameters D1 and D2.

[0070] In one example, a metal core ball 106 having a diameter D1 equal to 180 μm and a metal core ball 108 having a diameter D2 equal to 180 μm can accommodate a die thickness of 280 μm. The term die thickness refers to the thickness of the electronic component 102 ( Figure 2G ) is measured in the direction of height H1. Increasing the die thickness of electronic component 102 tends to improve the thermal performance of electronic device 100. In some examples, electronic component 102 may have a height from redistribution structure 114 that is greater than diameter D2 of metal core ball 108. In some examples, electronic component 102 may have a height from redistribution structure 114 that is less than the sum of diameter D1 and diameter D2.

[0071] exist Figure 2GA In an example of , the metal core ball 106 may be in direct contact with the inner terminal 206 and the metal core ball 108. The metal core ball 108 may be in direct contact with the inner terminal 206. The diameter D1 may be equal to the diameter D2.

[0072] Figure 2GB More specifically, the metal core ball 106 is coupled to the metal core ball 108. Figure 2G Area B. Figure 2GB The features in the instance of Figure 2GA The features in the examples are similar or identical. Figure 2GBIn an example of the present invention, the upper metal core ball 106 may directly contact the lower metal core ball 108. The upper metal core ball 106 may be separated from the internal terminal 206. The fusible material 109 may be located between the upper metal core ball 106 and the internal terminal 206. The fusible material 109 may couple the upper metal core ball 106 and the internal terminal 206. The lower metal core ball 108 may be separated from the internal terminal 216. The fusible material 109 may be located between the lower metal core ball 108 and the internal terminal 216. The fusible material 109 may couple the lower metal core ball 108 and the internal terminal 216. The diameter D1 of the upper metal core ball 106 may be smaller than the diameter D2 of the lower metal core ball 108.

[0073] exist Figure 2GC In the example of FIG. 1 , it is described in more detail after the metal core ball 106 is coupled to the metal core ball 108. Figure 2G The upper metal core ball 106 may be separated from the lower metal core ball 108 by a gap, wherein the fusible material 109 fills the gap between the upper metal core ball 106 and the lower metal core ball 108. The upper metal core ball 106 may directly contact the internal terminal 206. The lower metal core ball 108 may directly contact the internal terminal 216. The diameter D1 of the upper metal core ball 106 may be greater than the diameter D2 of the lower metal core ball 108. Figure 2GC Other features in the examples may be related to Figure 2GA and Figure 2GB are similar or identical to the examples.

[0074] Figure 2GD More specifically, the metal core ball 106 is coupled to the metal core ball 108. Figure 2G area D. Figure 2GD The features in the instance of Figure 2GA to Figure 2GC The examples are similar or identical. Figure 2GD In the example of the embodiment of the present invention, the upper metal core ball 106 may be separated from the inner terminal 206 by a gap, the lower metal core ball 108 may be separated from the inner terminal 216 by a gap, and the upper metal core ball 106 may be separated from the lower metal core ball 108 by a gap. The gaps between the inner terminal 206, the upper metal core ball 106, the lower metal core ball 108, and the inner terminal 216 may be filled with the fusible material 109. The diameter D1 of the upper metal core ball 106 may be equal to the diameter D2 of the lower metal core ball 108.

[0075] Although Figure 2GA to Figure 2GD Various examples of spacing configurations and diameters D1 and D2 are depicted. It is contemplated and understood that vertical interconnects 107 in the same electronic device may all have the same or similar configurations. It is further contemplated and understood that vertical interconnects 107 in the same electronic device may have configurations including Figure 2GA , Figure 2GB , Figure 2GC , Figure 2GDConfigurations of any combination of features depicted in or generally described herein.

[0076] Figure 2H A cross-sectional view of the electronic device 100 is shown in a post-manufacturing stage. Figure 2H In the example of FIG. 1 , the encapsulant 122 may be provided to cover the inner side of the substrate 200 , the inner side of the substrate 210 , the electronic component 102 , and the vertical interconnects 107 .

[0077] In some examples, the encapsulant 122 may include or be referred to as a body, an encapsulation body, or a molding. For example, the encapsulant 122 may include an epoxy molding compound, a resin, a filler-reinforced polymer, a B-stage pressed film, or a gel. The encapsulant 122 may be formed by compression molding, transfer molding, liquid body molding, vacuum lamination, paste printing, or film-assisted molding.

[0078] Fig.2I A cross-sectional view of the electronic device 100 is shown in a post-manufacturing stage. Fig.2I In some examples, the lower redistribution structure 114 may be released from the carrier 211 to expose the outer side (e.g., the side oriented away from the electronic component 102) of the redistribution structure 114 for further processing. The external interconnect 116 may be disposed on the outer side of the redistribution structure 114. Before the external interconnect 116 is disposed on the redistribution structure 114, the carrier 211 may be separated from the redistribution structure 114. In some examples, the carrier 211 may be separated from the outer side of the redistribution structure 114 after removing or reducing the adhesion of the temporary bonding layer inserted between the carrier 211 and the redistribution structure 114 by applying heat, light, a chemical solution, or a physical external force. The temporary bonding layer of the carrier 211 may be separated from the redistribution structure 114 while remaining attached to the carrier 211. The carrier 211 may be removed to expose the outer side of the redistribution structure 114.

[0079] In some examples, the external interconnect 116 may be coupled to the external terminal 217 of the redistribution structure 114. In some examples, the external interconnect 116 may include tin (NS), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. For example, the external interconnect 116 may be formed by a reflow process after forming a conductive material including solder on the external terminal 217 by a ball drop process. The external interconnect 116 may include or be referred to as a conductive ball (e.g., a solder ball), a conductive pillar (e.g., a copper pillar), or a conductive pillar having a solder cap formed on the copper pillar. In some examples, the external interconnect 116 may be arranged in a ball grid array or a pad grid array outside the redistribution structure 114. In some examples, the size of external interconnect 116 may be in the range of about 25 μm to 500 μm. In some examples, external interconnect 116 may be referred to as an external input / output terminal of electronic device 100.

[0080] In some examples, the external interconnect 116 can be electrically connected to the electronic component 102 through the redistribution structure 114, the vertical interconnect 107, or the redistribution structure 104. In some examples, additional electronic components 118, 120 (e.g., a die, a chip, a passive component (e.g., an LSC, a DTC), etc.) can be coupled to the redistribution structure 114. For example, the additional electronic components 118, 120 can be coupled to the external terminals 217. The electronic component 102 and the external interconnect 116 can be electrically coupled to the electronic components 118, 120 through the redistribution structure 114. The electronic component 102, the external interconnect 116, or the electronic components 118, 120 can be coupled to the redistribution structure 104 through the redistribution structure 114 and the vertical interconnect 107. In some examples, the additional electronic components (e.g., a die, a chip, a passive component, a package, etc.) can be coupled to the external terminals 207 or the internal terminals 206 of the redistribution structure 114.

[0081] In some examples, singulation along the saw streets S may be performed to separate the redistribution structures 104, 114 and the encapsulant 122 into individual electronic devices 100. The electronic device 100 may include the redistribution structures 104, 114, the electronic component 102, the underfill 222, the metal core balls 106 and 108, the encapsulant 122, and the external interconnect 116. In some examples, the electronic device 100 may also include the electronic components 118, 120.

[0082] View now Figure 3 and Figure 3A , showing an example electronic device 300. Figure 3A Show in more detail Figure 3 Area A of the electronic device 300. Figure 3 In the example of , the electronic device 300 can have a structure and processing steps similar to those described above for the electronic device 100. The electronic device 300 can include a plurality of vertical interconnects 107 adjacent to one or more lateral sides of the electronic component 102. Each vertical interconnect 107 can include a metal core ball 106, a metal core ball 108, and a fusible material 109. The bottom filler 222 can fill the volume between the electronic component 102 and the redistribution structure 114. The encapsulant 122 can fill the volume between the redistribution structure 114 and the redistribution structure 104. In Figure 3A In the example of FIG. 1 , the metal core ball 106 and the metal core ball 108 are depicted as being spaced apart or having a gap from each other and from the internal terminals 206 and 216 . In other examples, the metal core ball 108 and the metal core ball 106 may be in direct contact with each other or with the internal terminals 206 or 216 .

[0083] In some examples, the spacing P1 between adjacent internal terminals coupled to adjacent vertical interconnects 107 can be about 0.20 mm, about 0.21 mm, about 0.22 mm, about 0.23 mm, about 0.24 mm, about 0.25 mm, about 0.26 mm, about 0.27 mm, about 0.28 mm, or about 0.29 mm. The spacing P1 of vertical interconnects 107 including metal core balls 106 and metal core balls 108 tends to be similar to vertical interconnects including a single metal core ball. The spacing P1 can therefore be maintained while increasing the height H1 to accommodate a larger die thickness relative to a single metal core ball interconnect. In various examples, the spacing P1 can be less than the height H1. In an example where both diameters D1 and D2 are 180 μm, H1 can be about 360 μm and the spacing P1 can be about 270 μm.

[0084] Various example devices and methods may include vertical interconnects with multiple metal core balls. The height of the vertical interconnect with multiple metal core balls can be increased relative to the height of the vertical interconnect with a single metal core ball while maintaining a similar footprint. The vertical interconnect with stacked metal core balls therefore tends to increase the available vertical space to accommodate thicker electronic components, and maintains the same or similar interconnect spacing relative to the vertical interconnect with a single metal core ball. By being able to use thicker electronic components, the vertical interconnect described above tends to improve thermal performance in electronic devices. In some examples, the manufacturing method can be simplified because the vertical interconnect with multiple metal core balls tends to reduce the use of artificial stretching steps sometimes used for vertical interconnects with a single metal core ball. The vertical interconnect with multiple metal core balls can also control the solder volume and the height of the interconnect by selecting the diameter of the upper metal core ball and the lower metal core ball. The bonding strength can be improved by selecting a metal core ball coated with a desired volume of fusible material.

[0085] The present disclosure includes references to certain examples, however, it will be appreciated by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, modifications may be made to the disclosed examples without departing from the scope of the present disclosure. Therefore, it is intended that the present disclosure is not limited to the disclosed examples, but that the present disclosure will include all examples within the scope of the appended claims.

Claims

1. An electronic device, characterized in that: Include: a first substrate; an electronic component disposed over one side of the first substrate; a vertical interconnect coupled to the side of the first substrate, the vertical interconnect comprising: a first metal core ball proximate to the first substrate; a second metal core ball disposed above the first metal core ball and away from the first substrate; and a fusible material coupling the first metal core ball to the second metal core ball, wherein the fusible material is coupled to the first substrate; and A second substrate is disposed over the electronic component and the vertical interconnect, wherein the fusible material of the vertical interconnect is coupled to the second substrate.

2. The electronic device according to claim 1, characterized in that: The diameter of the first metal core ball is greater than the diameter of the second metal core ball.

3. The electronic device according to claim 1, characterized in that: The sidewalls of the vertical interconnect include a substantially convex geometry in a region surrounding a point between the first metal core ball and the second metal core ball.

4. The electronic device according to claim 1, characterized in that: A height of the electronic component measured from the side of the first substrate is greater than a diameter of the first metal core ball.

5. The electronic device according to claim 1, characterized in that: The first substrate comprises: internal terminals; and A dielectric structure defines an opening above the inner terminal, wherein the fusible material extends through the opening to the inner terminal.

6. The electronic device according to claim 5, characterized in that: The fusible material extends from the opening onto a portion of the dielectric structure adjacent the opening.

7. The electronic device according to claim 1, characterized in that: The first metal core ball contacts the second metal core ball.

8. The electronic device according to claim 1, characterized in that: Further included is a second vertical interconnect coupled to the first substrate and disposed laterally to the electronic component, wherein the second vertical interconnect includes a third metal core ball proximate to the first substrate and a fourth metal core ball distal to the first substrate.

9. An electronic device, characterized in that: Include: a first internal terminal; a fusible material coupled to the first internal terminal; a first metal core ball proximate to the first inner terminal and coupled to the fusible material; a second metal core ball remote from the first inner terminal and coupled to the fusible material; and A second inner terminal is coupled to the fusible material and is proximate to the second metal core ball.

10. The electronic device according to claim 9, characterized in that: The sidewall of the fusible material includes a substantially convex geometry in a region surrounding a point between the first metal core ball and the second metal core ball.

11. The electronic device according to claim 9, characterized in that: Further included is an electronic component adjacent to the first metal core ball, wherein a height of the electronic component is greater than a height of the first metal core ball.

12. The electronic device according to claim 9, characterized in that: Further included is a dielectric structure defining an opening over the first inner terminal, wherein the fusible material extends through the opening to the first inner terminal.

13. The electronic device according to claim 12, characterized in that: The fusible material extends from the opening onto a portion of the dielectric structure adjacent the opening.

14. The electronic device according to claim 9, characterized in that: The first metal core ball contacts the second metal core ball.

15. A method for manufacturing an electronic device, characterized in that: Include: providing a first substrate; disposing a first metal core ball on the first substrate; providing a second substrate; disposing a second metal core ball on one side of the second substrate; disposing an electronic component on the side of the second substrate; and The first metal core ball is coupled to the second metal core ball with a fusible material.

16. The method according to claim 15, characterized in that The fusible material includes a substantially convex geometry in a region surrounding a point between the first metal core ball and the second metal core ball.

17. The method according to claim 15, characterized in that The diameter of the first metal core ball is greater than the diameter of the second metal core ball.

18. The method according to claim 15, characterized in that Further comprising disposing an encapsulant between the first substrate and the second substrate.

19. The method according to claim 15, characterized in that Coupling the first metal core ball to the second metal core ball further includes applying a temperature greater than about 220° C. for a period greater than about 15 seconds.

20. The method according to claim 15, characterized in that Coupling the first metal core ball to the second metal core ball further includes applying a temperature of about 255°C.

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